Light-emitting chip, light-emitting device, and measurement device

Abstract

This light-emitting device is provided with: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when switched to an on-state, cause the light-emitting elements to emit light or increase the intensity of light emitted from the light-emitting elements; a drive unit that is provided on the substrate and drives the plurality of thyristors individually for transition to the on-state; and a reference potential terminal that supplies a predetermined reference potential to the drive unit, wherein a region of the drive unit that is connected to the reference potential terminal is electrically separated from the side surface of the substrate.

Description

Light-emitting chip, light-emitting device, and measuring device

[0001] The present disclosure relates to a light-emitting chip, a light-emitting device, and a measurement device.

[0002] Patent Document 1 describes a light emitting device having a semiconductor substrate, a light emitting element section formed on the semiconductor substrate and having a plurality of light emitting elements that emit light, a signal line formed on the semiconductor substrate for transmitting a signal to the light emitting element, and an oxide film formed along the signal line between the signal line and the semiconductor substrate. Patent Document 2 describes a light emitting section that uses transistor coupling.

[0003] Japanese Patent Publication No. 2023-42123 Japanese Patent Publication No. 2023-112937

[0004] In a light-emitting chip in which a light-emitting element and a driver that transmits signals to the light-emitting element are configured on a semiconductor substrate, leakage current from the light-emitting element may flow from the substrate, particularly via the dicing surface on the outer periphery of the substrate, to a terminal that supplies a reference potential to the driver. In this case, the light-emitting element that has once emitted light remains in an on state, resulting in erroneous lighting. Embodiments of the present disclosure relate to suppressing erroneous lighting compared to a configuration in which leakage current from the light-emitting element can flow to a terminal that supplies a reference potential to the driver.

[0005] (1) According to one aspect of the present disclosure, there is provided a light-emitting device comprising: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that are turned on to cause each of the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driver provided on the substrate and that individually drives the plurality of thyristors to transition to an on state; and a reference potential terminal that supplies a predetermined reference potential to the driver, wherein an area of ​​the driver connected to the reference potential terminal is electrically isolated from a side surface of the substrate. (2) According to another aspect of the present disclosure, there is provided a light-emitting chip comprising: a semiconductor substrate; a plurality of light-emitting elements provided on a surface side of the substrate; a plurality of thyristors that are turned on to cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a reference potential terminal that supplies a predetermined reference potential to the driver; and a separator that suppresses current flow between the reference potential terminal and the substrate. (3) In (2), the isolation portion may prevent the driver from extending to the outer periphery of the substrate. (4) In (2), the isolation portion may prevent a current path from being formed between the light-emitting element and the reference potential terminal via a side surface of the substrate. (5) In (2), the thyristor may be stacked on the light-emitting element provided on the substrate, and the driver may be stacked on a structure equivalent to the light-emitting element provided on the substrate. (6) In (5), the light-emitting element, the thyristor, and the driver may be formed by a semiconductor laminate in which a plurality of semiconductor layers of different conductivity types are stacked, and the isolation portion may be a groove provided in the semiconductor laminate and / or a region in which insulating ions are implanted into the semiconductor laminate. (7) In (6), the light-emitting element and the structure may have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, and the groove or the region into which the insulating ions are injected may extend from the surface side of the substrate to at least the side of the p-type semiconductor layer and the n-type semiconductor layer constituting the diode structure that is farther from the substrate side.(8) In (6), the light-emitting element may have a current confinement layer, which is a region that is oxidized to make it difficult for current to flow, and the depth of the groove may reach the current confinement layer. (9) In (5), the reference potential may be applied to a side of a diode structure, in which a p-type semiconductor layer serving as the anode of the structure and an n-type semiconductor layer serving as the cathode are stacked, that is, farther from the substrate. (10) In (6), the groove and / or the region into which insulating ions have been implanted may be provided so as to surround the drive unit. (11) In (2), the drive unit may sequentially transition the on-states of the plurality of thyristors. (12) According to another aspect of the present disclosure, there is provided a light-emitting chip including a semiconductor substrate, a plurality of light-emitting elements provided on the surface side of the substrate, a plurality of thyristors stacked on the light-emitting elements and configured to cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements when turned on, a reference potential terminal provided on a structure equivalent to the light-emitting elements and configured to supply a predetermined reference potential, and a separator that prevents a current path from being formed between the reference potential terminal and the light-emitting elements via the side of the substrate. (13) According to another aspect of the present disclosure, there is provided a light-emitting device including the light-emitting chip according to any one of (2) to (12), and a driver having one end set to a ground potential and the other end connected to the substrate of the light-emitting chip, and transitioning to an on state at a predetermined timing to pass a current to the light-emitting elements for light emission. (14) According to another aspect of the present disclosure, there is provided a measurement device including the light-emitting device according to (13), and an acquisition unit that acquires information about an object based on light reflected from the object by the light from the light-emitting device.

[0006] According to (1), (2), and (12), erroneous lighting can be suppressed compared to a configuration in which leakage current from the light-emitting element can flow to the reference potential terminal of the driver. According to (3), the side surface of the light-emitting chip is less susceptible to damage caused by dicing compared to a configuration in which the driver extends to the outer periphery of the substrate. According to (4), damage caused by dicing is tolerated. According to (5), the light-emitting elements of the light-emitting chip can be arranged at a higher density compared to a configuration in which thyristors are not stacked on the light-emitting elements. According to (6), the driver and the dicing surface can be electrically isolated. According to (7), the effectiveness of electrically isolating the driver and the dicing surface can be enhanced. According to (8), the isolation portion can be formed using the same process as the formation of the current blocking portion. According to (9), electrical isolation can be achieved by a pn junction. According to (10), the reference potential and the substrate potential can be more reliably isolated compared to a configuration in which the driver is not surrounded. According to (11), lighting control of the light-emitting element is easier compared to a configuration in which the on-states are not sequentially transitioned. According to (13), the light emitting element can be operated at a higher speed than in high side driving. According to (14), a measuring device capable of three-dimensional measurement is provided.

[0007] FIG. 1 is a diagram illustrating an example of a measurement device to which the first embodiment is applied. FIG. 2 is an equivalent circuit diagram illustrating a light source device to which the first embodiment is applied. FIG. 3 is an example of a planar layout diagram and a cross-sectional view of a light-emitting chip to which the first embodiment is applied, where (a) is an example of a planar layout diagram of the light-emitting chip, and (b) is an example of a cross-sectional view taken along line IIIB-IIIB in (a). FIG. 4 is an example of an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked. FIG. 5 is a diagram illustrating leakage current in a light source device to which the first embodiment is applied, where (a) is a cross-sectional view when a light-emitting chip without a groove is used, and (b) is a cross-sectional view when a light-emitting chip with a groove is used. FIG. 6 is an example of a planar layout diagram and a cross-sectional view of a light-emitting chip according to a modification of the first embodiment, where (a) is an example of a planar layout diagram of the light-emitting chip, and (b) is an example of a cross-sectional view taken along line VIB-VIB in (a). FIG. 7 is an equivalent circuit diagram illustrating a light source device to which the second embodiment is applied. FIG. 8 is an equivalent circuit diagram illustrating a light source device to which the third embodiment is applied. 9 is a diagram explaining the operation of a light-emitting chip to which embodiment 3 is applied, where (a) is an equivalent circuit diagram and (b) is a cross-sectional view of a portion of a transfer thyristor and a coupling transistor. FIG. 10 is an example of a planar layout diagram and a cross-sectional view of a light-emitting chip to which embodiment 3 is applied, where (a) is an example of a planar layout diagram of the light-emitting chip and (b) is an example of a cross-sectional view taken along line XB-XB in (a). FIG. 11 is an equivalent circuit diagram explaining a light source device to which embodiment 4 is applied. FIG. 12 is a diagram explaining leakage current in a light source device to which embodiment 4 is applied, where (a) is a cross-sectional view when a light-emitting chip without a groove is used and (b) is a cross-sectional view when a light-emitting chip with a groove is used.

[0008] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Here, a case will be described in which a light source device 1 including a light-emitting chip 10, which is an example of a light-emitting device, is applied to a measurement device that measures the three-dimensional shape (hereinafter referred to as 3D shape) of a measurement object.

[0009] [Embodiment 1] (Measuring Device 100) FIG. 1 is a diagram showing an example of a measuring device 100 to which embodiment 1 is applied. The measuring device 100 of embodiment 1 measures the three-dimensional shape of an object to be measured. The measuring device 100 is a device that measures the 3D shape based on the so-called ToF (Time of Flight) method, which uses the time of flight of light. The measuring device 100 includes a light source device 1 including a light-emitting chip 10 and a control unit 110, and a three-dimensional sensor (hereinafter referred to as a 3D sensor) 5. The ToF method measures the time from when light is emitted from the light source device 1 to when the light is reflected by the object to be measured and received by the 3D sensor 5. The distance to the object to be measured is calculated from the time acquired from the 3D sensor 5, and the 3D shape of the object to be measured is identified. Measuring a 3D shape may be referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0010] The light source device 1 emits light toward the object to be measured. The 3D sensor 5 acquires the light (reflected light) reflected by the object to be measured. The 3D sensor 5 outputs information (distance information) regarding the distance to the object to be measured based on the time from when the light is emitted to when the reflected light is received, measured using the ToF method. The measurement device 100 may also include a measurement control unit 200. The measurement control unit 200 is configured as a computer including a CPU, ROM, RAM, etc., and identifies the 3D shape of the object to be measured based on the distance information acquired from the 3D sensor 5. The measurement control unit 200 is an example of an acquisition unit.

[0011] The measurement device 100 can be applied to recognizing a measurement object from a specified 3D shape. For example, the measurement device 100 is installed in a portable information processing device and used to recognize the face of a user attempting to access the device. That is, the measurement device 100 acquires the 3D shape of the face of the accessing user, identifies whether or not the access is permitted, and allows use of the device (portable information processing device) only if the user is recognized as being authorized to access the device. The measurement device 100 can also be applied to cases where the 3D shape of a measurement object is continuously measured, such as in augmented reality (AR). The measurement object is an example of a target object, and the measurement device 100 is an example of a measurement device.

[0012] (Light Source Device 1) Fig. 2 is an equivalent circuit diagram illustrating the light source device 1 to which the first embodiment is applied. In Fig. 2, the right direction of the paper surface is defined as the +x direction. The light source device 1 shown in Fig. 2 includes a light-emitting chip 10 and a control unit 110.

[0013] (Control Unit 110) The control unit 110 includes a transfer signal generating unit 120, a lighting signal generating unit 140, a reference potential supplying unit 160, and a power supply potential supplying unit 170. The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially switch the multiple transfer thyristors T in the transfer unit 12 (described later) to an ON state. The lighting signal generating unit 140 generates a lighting signal φI that supplies a current that lights up (emits light) multiple VCSELs (described later). The reference potential supplying unit 160 supplies a reference potential Vst to the transfer unit 12. The power supply potential supplying unit 170 supplies a power supply potential Vga. The current that lights up (emits light) the VCSELs may be referred to as a light-emitting current.

[0014] (Light-emitting chip 10) The light-emitting chip 10 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting chip 10 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 10 includes a Vsub terminal. The Vsub terminal is a back electrode 91 (see FIG. 3(b) described later) provided on the back surface of the substrate 80. In FIG. 2, the terminal of the element connected to the substrate 80 (which is the same as the Vsub terminal) is indicated by a triangular symbol.

[0015] The light-emitting unit 11 includes a vertical-cavity surface-emitting laser (VCSEL). Hereinafter, the vertical-cavity surface-emitting laser (VCSEL) will be referred to as a VCSEL. In the example shown in FIG. 2, six VCSELs, VCSEL1 to VCSEL6, are included (referred to as VCSELs when no distinction is made). The light-emitting unit 11 also includes six setting thyristors S1 to S6 (referred to as setting thyristor S when no distinction is made). The anodes of the VCSELs are connected to the cathodes of the setting thyristors S. In other words, the setting thyristors S and VCSELs with the same number are connected in series. Additionally, as shown in FIG. 3B (described later), the setting thyristors S are stacked on the VCSELs formed on the substrate 80. Hereinafter, the setting thyristors S may be referred to as thyristors. In the first embodiment, each VCSEL is an example of a light-emitting element. Furthermore, each setting thyristor S is an example of a thyristor.

[0016] The transfer unit 12 includes six transfer thyristors T1 to T6 (referred to as transfer thyristors T when not distinguished) and six lower diodes UD1 to UD6 (referred to as lower diodes UD when not distinguished). The transfer thyristors T1 to T6 and the lower diodes UD1 to UD6 are connected in series with the transfer thyristor T and lower diode UD of the same number. Additionally, as shown in FIG. 3B (described later), the transfer thyristor T is stacked on the lower diode UD formed on the substrate 80. As described later, the lower diodes UD1 to UD6 have an integrated structure without being separated. The lower diodes UD1 to UD6 do not operate. In FIG. 2, the lower diodes UD1 to UD6 are indicated by dashed lines.

[0017] The transfer unit 12 also pairs the transfer thyristors T1 to T6 in numerical order, and includes coupling diodes D1 to D5 (referred to as coupling diode D when no distinction is made) between each pair. The transfer unit 12 also includes power supply line resistors Rg1 to Rg6 (referred to as power supply line resistor Rg when no distinction is made).

[0018] The transfer unit 12 also includes one start diode SD and current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 (described later) is supplied and a second transfer signal line 73 to which a second transfer signal φ2 (described later) is supplied.

[0019] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting unit 11 and the transfer thyristors T1 to T6 of the transfer unit 12 are arranged in numerical order from one side (-x direction side, left side in FIG. 2) to the other side (+x direction side, right side in FIG. 2) in the light-emitting chip 10. Furthermore, the lower diodes UD1 to UD6, coupling diodes D1 to D5, and power supply line resistors Rg1 to Rg6 are arranged in numerical order from one side (-x direction side, left side in FIG. 2) to the other side (+x direction side, right side in FIG. 2) in the light-emitting chip 10.

[0020] In the first embodiment, the number of VCSELs and setting thyristors S in the light-emitting unit 11, the number of transfer thyristors T, lower diodes UD, and power line resistances Rg in the transfer unit 12 are six each. The number of coupling diodes D is five, which is one less than the number of transfer thyristors T. The numbers of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistances Rg, and coupling diodes D are not limited to the above and may be any predetermined number. The number of transfer thyristors T may also be greater than the number of VCSELs.

[0021] The VCSEL, lower diode UD, coupling diode D, and start diode SD are two-terminal semiconductor elements having an anode terminal (anode) and a cathode terminal (cathode). The thyristors (setting thyristor S, transfer thyristor T) are three-terminal semiconductor elements having an anode terminal (anode), a gate terminal (gate), and a cathode terminal (cathode). Note that, hereinafter, terminals may be abbreviated.

[0022] The light-emitting chip 10 of the first embodiment is made of, for example, a III-V group compound semiconductor such as GaAs, AlGaAs, or AlAs. The light-emitting chip 10 is a so-called monolithic integrated circuit made of a semiconductor laminate in which multiple semiconductor layers of different conductivity types are stacked by epitaxial growth on a semiconductor substrate 80. In addition, the light-emitting chip 10 is obtained by dicing a semiconductor wafer on which multiple light-emitting chips 10 are collectively manufactured.

[0023] Next, the electrical connection of each element in the light-emitting chip 10 will be described. The cathodes of the VCSEL and the lower diode UD are connected to the substrate 80 (common cathode). These cathodes are supplied with a substrate potential Vsub via a back electrode 91 (see FIG. 3B), which is a Vsub terminal provided on the back surface of the substrate 80. The anodes of the VCSELs are connected to the cathodes of the setting thyristors S.

[0024] The anodes of the lower diodes UD are connected to the cathodes of the transfer thyristors T. The cathodes of the transfer thyristors T (the same as the anodes of the lower diodes UD) are connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to this Vst terminal from a reference potential supply unit 160. The Vst terminal may be a reference potential terminal 340 shown in FIGS. 3A and 3B, which will be described later. The reference potential terminal 340 is a terminal that supplies a reference potential to the transfer unit 12.

[0025] Along the arrangement of the transfer thyristors T, the anodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current-limiting resistor R1. A first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generating unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the anodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current-limiting resistor R2. A second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generating unit 120 of the control unit 110.

[0026] The anodes of the setting thyristors S are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. A light-up signal φI is supplied to the φI terminal from the light-up signal generating unit 140 of the control unit 110 via a current limiting resistor RI provided outside the light-emitting chip 10. The light-up signal φI supplies a current for lighting the VCSEL.

[0027] The gates Gt1 to Gt6 (written as gate Gt when not distinguished) of the transfer thyristors T1 to T6 are connected one-to-one to the gates Gs1 to Gs6 (written as gate Gs when not distinguished) of the setting thyristors S1 to S6 having the same numbers. Therefore, the gates Gt1 to Gt6 and the gates Gs1 to Gs6 having the same numbers are electrically at the same potential. Therefore, for example, the gate is written as gate Gt1 (gate Gs1) to indicate that the potential is the same.

[0028] Coupling diodes D1 to D5 are connected between pairs of gates Gt1 to Gt6 of the transfer thyristors T1 to T6, arranged in numerical order. That is, the coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6, respectively. The coupling diode D1 is connected in the direction in which current flows from the gate Gt2 to the gate Gt1. The same applies to the other coupling diodes D2 to D5.

[0029] The gates Gt (gates Gs) of the transfer thyristors T are connected to a power supply line 71 via power supply line resistors Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to a Vga terminal. A power supply potential Vga is supplied to the Vga terminal from a power supply potential supply unit 170 of the control unit 110.

[0030] The gate Gt1 of the transfer thyristor T is connected to the anode of the start diode SD. On the other hand, the cathode of the start diode SD is connected to the second transfer signal line 73.

[0031] 3A and 3B are an example of a planar layout diagram and a cross-sectional view of the light-emitting chip 10 to which the first embodiment is applied. FIG. 3A is an example of a planar layout diagram of the light-emitting chip 10, and FIG. 3B is an example of a cross-sectional view taken along line IIIB-IIIB in FIG. 3A. Note that a protective layer (protective layer 90 in FIG. 4 described later) and a light-shielding layer (light-shielding layer 95 in FIG. 4 described later) are omitted in FIGS. 3A and 3B. Also, the connection wirings shown in FIG. 3A are omitted in FIG. 3B. FIG. 3A illustrates VCSELs 1 to 4, setting thyristors S1 to S4, and transfer thyristors T1 to T4 for the VCSELs 1 to 6, setting thyristors S1 to S6, and transfer thyristors T1 to T6 shown in FIG. 2. 3B shows a cross section of the setting thyristor S1, VCSEL1, transfer thyristor T1, lower diode UD1, coupling diode D1, and power supply line resistance Rg1.

[0032] First, the cross-sectional structure of the light-emitting chip 10 will be described with reference to FIG. 3B. The light-emitting chip 10 includes an n-type cathode layer 81, a light-emitting layer 82, and a p-type anode layer 83, which are sequentially disposed on an n-type substrate 80 (substrate 80) and constitute the VCSEL and lower diode UD. The n-type cathode layer 81 and the p-type anode layer 83 are configured with a distributed Bragg reflector (DBR) (hereinafter referred to as a DBR layer) in which multiple semiconductor layers having different refractive indices are stacked. Therefore, hereinafter, the n-type cathode layer 81 will be referred to as an n-cathode (DBR) layer 81. Similarly, the p-type anode layer 83 will be referred to as a p-anode (DBR) layer 83.

[0033] In the light-emitting chip 10, a tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84) is provided on a p-anode (DBR) layer 83. Furthermore, in the light-emitting chip 10, an n-type cathode layer 85 (n-cathode layer 85), a p-type gate layer 86 (p-gate layer 86), an n-type gate layer 87 (n-gate layer 87), and a p-type anode layer 88 (p-anode layer 88) that constitute the setting thyristor S, the transfer thyristor T, the coupling diode D, and the power line resistance Rg are provided in this order on the tunnel junction layer 84. Hereinafter, the notation in parentheses described above will be used. The same applies to other cases.

[0034] As shown in Figures 3A and 3B, elements such as the VCSEL, lower diode UD, setting thyristor S, transfer thyristor T, and coupling diode D are composed of multiple islands separated by etching away portions of each of the above layers. The islands are sometimes referred to as mesas, and the etching process for forming the islands (mesas) is sometimes referred to as mesa etching. In the light-emitting chip 10, these islands are connected to wiring such as the power supply line 71, first transfer signal line 72, second transfer signal line 73, reference potential line 74, and light-up signal line 75 via through-holes (shown as black circles in Figure 3A) provided in a protective layer (protective layer 90 in Figure 4, which will be described later). In the following description, the protective layer and through-holes will not be described.

[0035] As shown in FIG. 3B, a back surface electrode 91 serving as a Vsub terminal is provided on the back surface of the substrate 80 .

[0036] Here, the notation of the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 corresponds to the functions (operations) when configuring the VCSEL and the lower diode UD. That is, the n-cathode (DBR) layer 81 functions as a cathode, and the p-anode (DBR) layer 83 functions as an anode.

[0037] The notations of the n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 correspond to the functions (operations) when configuring the setting thyristor S and the transfer thyristor T. That is, the n-cathode layer 85 functions as a cathode, the p-gate layer 86 and n-gate layer 87 function as gates, and the p-anode layer 88 functions as an anode. When the above-mentioned layers configure the coupling diode D and the power supply line resistance Rg, they have different functions as will be described later.

[0038] As will be described below, the multiple islands included in the light-emitting chip 10 include those that do not include some of the n-cathode (DBR) layer 81, the light-emitting layer 82, the p-anode (DBR) layer 83, the tunnel junction layer 84, the n-cathode layer 85, the p-gate layer 86, the n-gate layer 87, and the p-anode layer 88. For example, islands 301 and 302, which will be described later, do not include part of the p-anode layer 88.

[0039] The substrate 80, the back electrode 91, and the n-cathode (DBR) layer 81 are at the same potential, and therefore may be collectively referred to as the substrate 80. In this specification, the substrate 80 may include the back electrode 91 and the n-cathode (DBR) layer 81.

[0040] Next, an example of a planar layout of the light-emitting chip 10 will be described with reference to FIG. 3A. The island 301 is provided with a VCSEL1 and a setting thyristor S1. The island 302 is provided with a transfer thyristor T1 and a coupling diode D1. The island 303 is provided with a power supply line resistor Rg1. The island 304 is provided with a start diode SD. The island 305 is provided with a current limiting resistor R1, and the island 306 is provided with a current limiting resistor R2.

[0041] The light-emitting chip 10 has a plurality of islands formed in parallel, each of which is similar to the islands 301, 302, and 303. These islands are provided with VCSEL2 to VCSEL6, setting thyristors S2 to S6, lower diodes UD2 to UD6, transfer thyristors T2 to T6, coupling diodes D2 to D5, etc., similar to the islands 301, 302, and 303. The islands 302 to 306 and islands similar to the islands 302 and 303 are provided on the island 300.

[0042] Here, islands 300 to 306 will be described in detail with reference to FIGS. 3A and 3B. As shown in FIG. 3B, island 301 is separated from other islands by removing the p-anode layer 88, n-gate layer 87, p-gate layer 86, n-cathode layer 85, tunnel junction layer 84, p-anode (DBR) layer 83, and light-emitting layer 82 in the thickness direction by mesa etching. It is sufficient that only a portion of the light-emitting layer 82 is removed in the thickness direction. Furthermore, part or all of the n-cathode (DBR) layer 81 may be removed. The VCSEL 1 provided in island 301 is composed of the n-cathode (DBR) layer 81, light-emitting layer 82, and p-anode (DBR) layer 83. The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 stacked via a tunnel junction layer 84 stacked on a p-anode (DBR) layer 83 of the VCSEL 1.

[0043] As shown in FIG. 3B , the p-anode (DBR) layer 83 of the VCSEL includes a current confinement layer (current confinement layer 83a in FIG. 4 , which will be described later) that confines current, as indicated by the black dots. The current confinement layer is formed by oxidizing a portion of the semiconductor layer constituting the p-anode (DBR) layer 83 exposed by mesa etching, forming a current blocking portion β through which current does not easily flow. Meanwhile, the central portion of the semiconductor layer constituting the p-anode (DBR) layer 83, where the portion is not oxidized, forms a current passing portion α through which current easily flows. Providing the current blocking portion β reduces power consumption for non-radiative recombination. Providing the current blocking portion β reduces power consumption and improves light extraction efficiency. Light extraction efficiency is the amount of light that can be extracted per unit of power. To expose the current confinement layer, the depth of the mesa etching that separates the islands 301 is preferably such that a portion of the light-emitting layer 82 is removed in the thickness direction. In the island 301, the setting thyristor S1 (the p-anode layer 88, the n-gate layer 87, the p-gate layer 86, the n-cathode layer 85, and the tunnel junction 84) in the light-emitting portion may be removed. In this case, the setting thyristor S1 has a cylindrical shape. This prevents the light emitted by the VCSEL 1 from being absorbed by the setting thyristor S1, resulting in a decrease in the amount of light.

[0044] 3B, the island 301 will be described. The setting thyristor S1 has a p-type ohmic electrode 321 (p ohmic electrode 321) provided on the region 311 of the p anode layer 88 as its anode terminal. Also, an n-type ohmic electrode 331 (n ohmic electrode 331) provided on the n gate layer 87 exposed by removing the p anode layer 88 as its gate Gs1 terminal.

[0045] The island 300 is separated from the island 301 and islands similar to the island 301 by removing the p anode layer 88, n gate layer 87, p gate layer 86, n cathode layer 85, tunnel junction layer 84, p anode (DBR) layer 83, and light emitting layer 82 in the thickness direction by mesa etching. Islands 302 to 306, and islands similar to the islands 302 and 303, are provided on the island 300. The islands 302 to 306 will be described below.

[0046] The islands 302 to 306 are separated from the island 300 by removing the p-anode layer 88, n-gate layer 87, p-gate layer 86, n-cathode layer 85, and tunnel junction layer 84 by mesa etching. In the island 300, the p-anode (DBR) layer 83, light-emitting layer 82, and n-cathode (DBR) layer 81 remain below the islands 302 to 306. The remaining p-anode (DBR) layer 83, light-emitting layer 82, and n-cathode (DBR) layer 81 of the island 300 constitute the lower diodes UD1 to UD6. In other words, the lower diodes UD1 to UD6 are not separated but integrated. The lower diodes UD1 to UD6 are composed of the n-cathode (DBR) layer 81, light-emitting layer 82, and p-anode (DBR) layer 83, similar to the VCSEL light-emitting element. Therefore, the lower diode UD is a structure in this embodiment and is equivalent to a light emitting element. The VCSEL and the lower diode UD have a diode structure with a pn junction.

[0047] It should be noted that in the mesa etching of the islands 302 to 306, the n-cathode layer 85 and the tunnel junction layer 84 do not have to be removed. The p-anode (DBR) layer 83 and the n-cathode layer 85 are stacked with the tunnel junction layer 84 interposed between them. Therefore, the p-anode (DBR) layer 83 and the n-cathode layer 85 have the same potential, so the tunnel junction layer 84 and the n-cathode layer 85 do not have to be removed and can be left. In the following description, it is assumed that the p-anode (DBR) layer 83 is exposed.

[0048] The transfer thyristor T1 provided in the island 302, like the setting thyristor S1, is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88. A p-ohmic electrode 323 provided on a region 313 of the p-anode layer 88 serves as the anode terminal. An n-ohmic electrode 332 provided on the n-gate layer 87 exposed by removing the p-anode layer 88 serves as the terminal of the gate Gt1. Similarly, the coupling diode D1 provided in the island 302 is composed of an n-gate layer 87 and a p-anode layer 88. A p-ohmic electrode 324 provided on a region 314 of the p-anode layer 88 serves as the anode terminal. An n-ohmic electrode 332 provided on the n-gate layer 87 exposed by removing the p-anode layer 88 serves as the cathode terminal. Here, the cathode terminal of the coupling diode D is the same as the terminal of the gate Gt1.

[0049] The power supply line resistance Rg1 provided in the island 303 is composed of the p anode layer 88. That is, the power supply line resistance Rg1 is provided with the p anode layer 88 between the p ohmic electrode 333 and the p ohmic electrode 334 provided on the p anode layer 88 as a resistor.

[0050] Although not shown in FIG. 3B , the start diode SD provided in the island 304 is composed of an n-gate layer 87 and a p-anode layer 88. That is, the start diode SD uses a p-ohmic electrode 325 provided on a region 315 of the p-anode layer 88 as its anode terminal. Furthermore, the start diode SD uses an n-ohmic electrode 335 provided on the n-gate layer 87 exposed by removing the p-anode layer 88 as its cathode terminal (see FIG. 3A ). The current limiting resistors R1 provided in the island 305 and R2 provided in the island 306 are provided in the same manner as the power line resistor Rg1 provided in the island 303. Each uses the p-anode layer 88 between two p-ohmic electrodes (unnumbered) as its resistor (see FIG. 3A ).

[0051] An island 302 provided with a transfer thyristor T1 and a coupling diode D1, an island 303 provided with a power supply line resistance Rg1, an island similar to the islands 302 and 303, an island 304 provided with a start diode SD, and islands 305 and 306 provided with current limiting resistors R1 and R2 constitute a transfer unit 12. The transfer unit 12 is provided in the island 300.

[0052] The island 300 is provided with a groove 350 that surrounds the islands 302 to 306 and islands similar to the islands 302 and 303. The groove 350 is formed by removing the p-anode (DBR) layer 83 by mesa etching in a portion of the island 300 where the p-anode (DBR) layer 83 is exposed. The groove 350 is formed by removing at least the p-anode (DBR) layer 83, but may be removed to reach the light-emitting layer 82 below the p-anode (DBR) layer 83, or may be removed further to reach the n-cathode (DBR) layer 81. In other words, the groove 350 may have the same depth as the mesa etching that separates the island 301. Therefore, the groove 350 may be formed during the mesa etching that separates the island 301. In other words, the mesa etching that separates the island 301 and the mesa etching that forms the groove 350 can be performed in the same process. This eliminates the need for a separate mesa etching process for forming the groove 350. Additionally, the groove 350 extends from at least the surface side of the substrate 80 to the side (e.g., the p-anode (DBR) layer 83) of the p-type semiconductor layer (e.g., the p-anode (DBR) layer 83) and the n-type semiconductor layer (e.g., the n-cathode (DBR) layer 81) that constitute the diode structure, farther from the substrate 80 side. This allows electrical isolation by a pn junction between the p-type semiconductor layer and the n-type semiconductor layer that constitute the diode structure. The groove 350 will be described later.

[0053] Next, the connection relationships between the elements will be described with reference to Fig. 3(a). The light-on signal line 75 has a trunk 75a and multiple branch portions 75b. The trunk 75a is provided so as to extend in the column direction of the setting thyristors S / VCSEL. The branch portions 75b branch off from the trunk 75a and are connected to the p-ohmic electrode 321, which is the anode terminal of the setting thyristor S1 provided in the island 301. The anode terminals of the other setting thyristors S are connected in the same manner. The light-on signal line 75 is connected to the φI terminal.

[0054] The first transfer signal line 72 is connected to a p-ohmic electrode 323, which is the anode terminal of the transfer thyristor T1 provided in the island 302. The anode terminals of other odd-numbered transfer thyristors T provided in islands similar to the island 302 are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current-limiting resistor R1 provided in the island 305. On the other hand, the second transfer signal line 73 is connected to p-ohmic electrodes (without reference numerals) which are the anode terminals of even-numbered transfer thyristors T provided in islands without reference numerals. The second transfer signal line 73 is connected to the φ2 terminal via a current-limiting resistor R2 provided in the island 306.

[0055] The power supply line 71 is connected to a p-ohmic electrode 334, which is one terminal of a power supply line resistor Rg1 provided on the island 303. One terminal of another power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vga terminal.

[0056] The n-ohmic electrode 331 (gate terminal Gs1) of the setting thyristor S1 provided on the island 301 is connected to the n-ohmic electrode 332 (gate terminal Gt1) of the island 302 by a connection wiring 76.

[0057] The n-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 (the other terminal of the power supply line resistance Rg1) of the island 303 by a connection wiring 77. The p-ohmic electrode 324 (anode terminal of the coupling diode D1) provided on the island 302 is connected to the n-ohmic electrode (no reference numeral) that is the gate terminal Gt2 of the adjacent transfer thyristor T2 by a connection wiring 79. Although the description will be omitted here, the same applies to the other VCSELs, setting thyristors S, transfer thyristors T, coupling diodes D, etc.

[0058] The n-ohmic electrode 332 (gate terminal Gt1) of the island 302 is connected to the p-ohmic electrode 325 (cathode terminal of the start diode SD) provided on the island 304 by a connection wiring 78. The n-ohmic electrode 335 (cathode terminal of the start diode SD) is connected to a second transfer signal line 73.

[0059] In the island 300, a p-ohmic electrode 340 is provided on the p-anode (DBR) layer 83 surrounded by the groove 350. The p-ohmic electrode 340 is connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to the Vst terminal. Note that the reference potential line 74 and the Vst terminal may be omitted, and the p-ohmic electrode 340 may serve as the Vst terminal or the reference potential terminal 340. Hereinafter, the Vst terminal will be referred to as the reference potential terminal 340. The reference potential terminal 340 is an example of a reference potential terminal. The p-anode (DBR) layer 83 provided with the reference potential terminal 340 is provided continuously below the transfer section 12. The p-anode (DBR) layer 83 is set to a potential (reference potential Vst) that serves as a reference for the operation of the transfer section 12 by the reference potential terminal 340. In addition, the transfer unit 12 is provided in an area surrounded by the groove 350, and operates based on the reference potential Vst supplied to the reference potential terminal 340. If the n-cathode layer 85 and the tunnel junction layer 84 are not removed in the mesa etching of the islands 302 to 306, the p-ohmic electrode 340 may be used as an n-ohmic electrode.

[0060] (Stacked Structure of Setting Thyristor S and VCSEL) FIG. 4 is an example of an enlarged cross-sectional view of an island 301 in which the setting thyristor S and the VCSEL are stacked, and is a cross-sectional view of the light-emitting chip 10 taken along line IV-IV in FIG. 3A. Note that FIG. 4 corresponds to a cross-section of the island in which the setting thyristor S and the VCSEL are stacked, as viewed from the -y direction in FIG. 3A. FIG. 4 also shows an island 301 in which the VCSEL1 and the setting thyristor S1 are stacked, and an island (without reference numerals) in which the VCSEL2 and the setting thyristor S2 are stacked. On the right side of FIG. 4, VCSEL1 and VCSEL2 are not distinguished from each other and are referred to as VCSEL. Similarly, the setting thyristor S1 and the setting thyristor S2 are not distinguished from each other and are referred to as the setting thyristor S. As described above, the setting thyristor S is stacked on the VCSEL via the tunnel junction layer 84. That is, the setting thyristor S and the VCSEL are connected in series. Note that "on the VCSEL" does not only refer to a state in which the setting thyristor S is in direct contact with the VCSEL, but also includes a state in which the setting thyristor S is located above the VCSEL without being in direct contact with the VCSEL. The same applies to similar expressions such as "on the substrate."

[0061] 4, the VCSEL is composed of a semiconductor laminate in which an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83 are epitaxially grown in this order on an n-type substrate 80. The n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 are DBR layers in which multiple high-refractive-index layers and low-refractive-index layers are alternately stacked. The n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 are configured to reflect light emitted from the VCSEL.

[0062] The p-anode (DBR) layer 83 also includes a current confinement layer 83a. In this example, the current confinement layer 83a is provided on the side of the p-anode (DBR) layer 83 facing the light-emitting layer 82. The current confinement layer 83a is composed of a current passing portion α and a current blocking portion β. As shown in FIG. 4 , the current passing portion α is provided in the center of the VCSEL, and the current blocking portion β is provided in the peripheral portion of the VCSEL. In other words, the portion of the current confinement layer 83a indicated by the thick solid line is the current blocking portion β, and the portion sandwiched between the two thick solid lines where the current confinement layer 83a is not provided is the current passing portion α. ​​The current blocking portion β does not need to completely block the flow of current; it is sufficient if it can concentrate the current in the current passing portion α. ​​In other words, it is sufficient if the current blocking portion β is more difficult to pass than the current passing portion α. ​​The current confinement layer 83a may also be provided in the n-cathode (DBR) layer 81. The mesa etching for separating the islands 301 is performed to a depth that exposes the side surfaces of the current confinement layer 83 a. When the groove 350 is formed simultaneously with the mesa etching for separating the islands 301, the groove 350 also has a depth that exposes the side surfaces of the current confinement layer 83 a.

[0063] The light-emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. Note that the light-emitting layer 82 may be an intrinsic (i) type layer (i layer) to which no impurities are added. The light-emitting layer 82 may also have a structure other than a quantum well structure, such as a quantum wire or a quantum dot.

[0064] The tunnel junction layer 84 is an n-type layer doped with a high concentration of n-type impurities (dopants). ＋＋ layer and a p-type impurity-doped p-type ＋＋ The tunnel junction layer 84 is a junction between the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S, and current flows due to the tunnel effect even when reverse bias is applied. The tunnel junction layer 84 prevents the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S from being reverse biased, making it difficult for current to flow. Current flows due to the tunnel effect even when reverse bias is applied.

[0065] The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which are stacked on a tunnel junction layer 84. That is, it has a four-layer pnpn structure.

[0066] These semiconductor layers are formed by stacking p-type semiconductor layers (p-gate layer 86, p-anode layer 88) and n-type semiconductor layers (n-cathode layer 85, n-gate layer 87) made of, for example, GaAs, AlGaAs, or AlAs on the substrate 80. The semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Hereinafter, the stacked semiconductor layers will be referred to as a semiconductor stack. Note that the configurations of the substrate 80, the n-cathode (DBR) layer 81, light-emitting layer 82, and p-anode (DBR) layer 83 that constitute the VCSEL, and the n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 that constitute the setting thyristor S will be described in more detail later.

[0067] The p ohmic electrode 321 is made of, for example, Au (AuZn) containing Zn, which easily makes ohmic contact with p-type semiconductor layers such as the p anode layer 88. The n ohmic electrode 331 (see FIG. 3B) is made of, for example, Au (AuGe) containing Ge, which easily makes ohmic contact with n-type semiconductor layers such as the n gate layer 87. The back electrode 91, like the n ohmic electrode 331, is made of, for example, AuGe.

[0068] In the above, the n-ohmic electrode 331 is provided on the n-gate layer 87 to serve as the gate Gs of the setting thyristor S, but the p-ohmic electrode may be provided on the p-gate layer 86 to serve as the gate Gs of the setting thyristor S.

[0069] The light-emitting chip 10 is also provided with a protective layer 90 made of a light-transmitting insulating material, which is provided so as to cover the surface and side surfaces of the island. The protective layer 90 is made of, for example, SiO ２, SiON, SiN, etc. Furthermore, the light-emitting chip 10 is provided with a light-shielding layer 95 for preventing light emitted from the setting thyristor S from leaking out from between the islands to the surface of the light-emitting chip 10. The light-shielding layer 95 may be the wiring described above.

[0070] (Thyristor) Next, the basic operation of the thyristor (transfer thyristor T, setting thyristor S) will be described. As described above, the thyristor has a pnpn structure in which an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 are stacked, and is a semiconductor element having three terminals: an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate). Here, the forward voltage (built-in potential) Vd of the pn junction formed by a p-type semiconductor layer and an n-type semiconductor layer will be described as 1.5 V as an example.

[0071] In the following description, as an example, the substrate potential Vsub supplied to the rear electrode 91 (see FIG. 3B) which is the Vsub terminal and the reference potential Vst supplied to the Vst terminal (reference potential terminal 340) will be described as a low-level potential (hereinafter referred to as "L") of 0 V, and the power supply potential Vga supplied to the Vga terminal will be described as a high-level potential (hereinafter referred to as "H") of 5 V. Therefore, they may be written as "H" (5 V) and "L" (0 V). "L" (0 V) is the ground potential GND. The ground potential GND will be written as the ground potential GND (0 V).

[0072] First, let us explain the operation of a single thyristor. Here, the cathode of the thyristor is assumed to be 0 V. A thyristor in the off state, where no current flows between the anode and cathode, transitions to the on state (turns on) when a potential higher than the threshold voltage is applied to the anode. Here, the threshold voltage of a thyristor is the gate potential plus the forward voltage Vd (1.5 V) of the pn junction. If the gate potential is 1.5 V, the thyristor turns on when the anode potential exceeds 3 V. In the on state, the gate of the thyristor reaches a potential close to the potential of the cathode terminal. Here, since the cathode is 0 V, the gate is assumed to be 0 V. Furthermore, the anode of a thyristor in the on state reaches a potential close to the potential obtained by adding the forward voltage Vd (1.5 V) of the pn junction to the cathode potential. Here, since the cathode is 0 V, the anode of a thyristor in the on state reaches a potential close to 1.5 V. The potential of the anode is set in relation to the power source that supplies current to the thyristor in the ON state.

[0073] A thyristor in the ON state transitions to the OFF state (turns off) when the anode potential becomes lower than the potential required to maintain the ON state (a potential close to the above-mentioned 1.5 V). On the other hand, if a potential higher than the potential required to maintain the ON state is continuously applied to the anode of a thyristor in the ON state and a current sufficient to maintain the ON state (maintenance current) is supplied, the thyristor will maintain the ON state.

[0074] Next, the operation of the thyristor S and the VCSEL stacked together will be described. Here, the substrate potential Vsub is set to "L" (0 V), so the cathode of the VCSEL is at 0 V. As described above, if the potential of the light-up signal φI is greater than the threshold voltage, the thyristor S turns on. At this time, since the VCSEL is connected in series, the anode of the thyristor S is higher by the forward voltage Vd (1.5 V) of the VCSEL, resulting in a potential close to 3.0 V. The difference between the anode potential and the light-up signal φI potential is applied to the current-limiting resistor RI (see FIG. 2 ). A current corresponding to the voltage drop across the current-limiting resistor RI flows through the turned-on thyristor S and the VCSEL, causing the VCSEL to light up. On the other hand, if the potential of the light-up signal φI is smaller than the threshold voltage, the thyristor S does not turn on and remains off. A thyristor in the on state can be maintained in the on state by supplying a current equal to or greater than the current required to maintain the on state (holding current).On the other hand, a thyristor will transition to the off state (turn off) by supplying a current equal to or less than the holding current.

[0075] The voltages shown above are merely examples, and will be changed depending on the emission wavelength and light intensity of the VCSEL. In this case, the potential ("H") of the lighting signal φI can be adjusted. In the above, the setting thyristor S is described as controlling the lighting or non-lighting (lighting control) of the VCSEL, but it may also be used as an element that increases the light intensity of a VCSEL that is already lit by turning on the setting thyristor S.

[0076] (Operation of Light Source Device 1) Next, the operation of the light source device 1 will be described. The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 2 and 3A) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 2 and 3A) are signals having two potentials, "H" (5 V) and "L" (0 V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, periods T(1) and T(2)). A set of transfer signals, the first transfer signal φ1 and the second transfer signal φ2, shifts the on-state of the transfer thyristor T in numerical order, thereby designating the VCSEL having the same number as the on-state transfer thyristor T as the target of lighting control. As described above, when the transfer thyristor T is turned on, the gate Gt of the transfer thyristor T becomes 0 V. Then, the gate Gs of the setting thyristor S is connected to the gate Gt of the transfer thyristor T, and therefore becomes 0 V. In other words, the threshold voltage of the setting thyristor S becomes 1.5 V. Note that the gate Gt of the transfer thyristor T on the right of the on-state transfer thyristor T increases in voltage by the voltage drop across the coupling diode D and the parasitic resistance (not shown) connected in series with the coupling diode D, and becomes 1.8 V. In other words, the threshold voltage of the setting thyristor S on the right becomes 3.3 V. The setting thyristor S on its right has a higher threshold voltage. Furthermore, the gate Gt on the left of the on-state transfer thyristor T becomes 5 V, and the threshold voltage becomes 6.5 V. In this way, the threshold voltages of the setting thyristors S other than those with the same number as the on-state transfer thyristor T are all 3.3 V or higher.

[0077] The light-up signal φI supplied to the φI terminal (see FIGS. 2 and 3(a)) is a signal having two potentials, "H" (5 V) and "L" (0 V). When the light-up signal φI transitions from "L" to "H," the setting thyristor S corresponding to the VCSEL designated by the transfer signal as the target for lighting is turned on, and the VCSEL is lighted. When this setting thyristor S is turned on, the anode voltage becomes 3 V as described above, and the voltage of the light-up signal line 75 also becomes 3 V. Therefore, setting thyristors S other than the setting thyristor S corresponding to the designated VCSEL are not turned on.

[0078] That is, when the transfer thyristor T is turned on, it designates the VCSEL that is the target of lighting control, and the lighting signal φI of “H” (5 V) turns on the setting thyristor S connected in series to the VCSEL that is the target of lighting control, and lights up the VCSEL. That is, in the light-emitting chip 10, the on state of the transfer thyristor T is transferred, and the VCSELs are sequentially lit. When the transfer thyristor T is turned on, the gate Gt changes, and the potential of the gate Gs of the setting thyristor S connected to the gate Gt changes, turning on the setting thyristor S. Here, a signal that is transmitted from the gate Gt of the transfer thyristor T to the gate Gs of the setting thyristor S and turns on the setting thyristor S is referred to as an on signal. By sequentially transitioning the on state, lighting control of the VCSELs is facilitated. Note that the lighting signal φI of “L” (0 V) maintains the setting thyristor S in the off state and maintains the VCSEL in the non-light state. That is, the light-up signal φI sets whether the VCSEL is turned on or off.

[0079] The light source device 1 of the first embodiment includes a plurality of elements (transfer thyristors T1 to T6, setting thyristors S1 to S6, and VCSEL1 to VCSEL6), and the elements that are turned on among the plurality of elements are successively switched on. Specifically, in the light source device 1 of the first embodiment, the control unit 110 (see FIG. 2 ) controls the lighting of the plurality of transfer thyristors T1 to T6 in the transfer unit 12 of the light-emitting chip 10, and the plurality of transfer thyristors T1 to T6 are individually switched on. When the transfer thyristors T1 to T6 are switched on, a VCSEL that is the target of the lighting control is designated, and the plurality of setting thyristors S1 to S6 in the light-emitting unit 11 are individually switched on. When each setting thyristor S is switched on, the VCSEL corresponding to that setting thyristor S is individually lit. In the light source device 1 of the first embodiment, the transfer unit 12 of the light-emitting chip 10 is an example of a drive unit that individually drives the plurality of setting thyristors S to switch them to the on state. In the light-emitting chip 10 of the first embodiment, the portion of the light-emitting layer 82 of each VCSEL that actually emits light when supplied with current is the light-emitting region of each VCSEL.

[0080] In the light-emitting chip 10 of the first embodiment, when the setting thyristor S receives an ON signal, it enters a state in which a current can be supplied to the corresponding VCSEL. Then, when the setting thyristor S enters an ON state and a current of a magnitude necessary for the VCSEL to emit light is supplied, the VCSEL lights up. However, depending on the configuration of the light-emitting chip 10 and the control by the control unit 110, after an ON signal is supplied to the setting thyristor S and a current is supplied to the corresponding VCSEL, the ON signal to the setting thyristor S may be stopped while the VCSEL remains in an emission-enabled state. Even in such a case, the setting thyristor S enters an ON state and a current of a magnitude necessary for the VCSEL to emit light is supplied to the VCSEL, thereby causing the VCSEL to emit light. In the first embodiment, "the thyristor (setting thyristor S) enters an ON state, causing the light-emitting element (VCSEL) to emit light" means that the setting thyristor S enters an ON state, causing the corresponding VCSEL to emit light by supplying a current. In addition, after an ON signal is supplied to the setting thyristor S to make the VCSEL capable of emitting light by supplying a current, when the VCSEL is actually emitting light due to the current being supplied to the VCSEL, the supply of the ON signal to the setting thyristor S may be continued or stopped.

[0081] 5(a) and 5(b) are diagrams illustrating leakage current in the light source device 1 to which the first embodiment is applied. FIG. 5(a) is a cross-sectional view when a light-emitting chip 10' without a groove 350 is used, and FIG. 5(b) is a cross-sectional view when a light-emitting chip 10 having a groove 350 is used. The horizontal direction of the drawings is the +y direction shown in FIG. 3(a). The cross-sectional view shown in FIG. 5(b) is the same as FIG. 3(b).

[0082] A case where the light-emitting chip 10′ shown in FIG. 5A is used will be described. When the setting thyristor S is turned on and a current flows through the series-connected setting thyristor S and VCSEL, the current flows from the p-ohmic electrode 321 to the substrate 80 and the back electrode 91. The side surface of the light-emitting chip 10 is damaged when the semiconductor wafer is diced to separate it into chips. The side surface P of the light-emitting chip 10 (the rightmost portion in FIG. 5A) is an example of a dicing surface. When the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 of the island 300 are exposed on the side surface P, which is the dicing surface, the p-n junction between the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 is damaged by dicing. If the p-n junction is damaged, it cannot be maintained and a short circuit may occur. In other words, the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 are no longer electrically isolated by the pn junction, and current can flow through a path via the side surface P, which is the damaged dicing surface. More specifically, the current flowing from the p-ohmic electrode 321 to the setting thyristor S and the VCSEL flows as leakage current through the inside of the substrate 80 to the side surface P of the light-emitting chip 10, as shown by the leakage current path 360 indicated by the arrow in FIG. 5A . The leakage current then flows along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83. The leakage current that has flowed along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83 flows to the reference potential terminal 340, to which the reference potential Vst is supplied to the transfer unit 12. The region of the transfer unit 12 connected to the reference potential terminal 340 and the substrate potential Vsub supplied to the substrate 80 are no longer electrically isolated. The region of the transfer unit 12 connected to the reference potential terminal 340 is the region of the p anode (DBR) layer 83 connected to the reference potential terminal 340 of the transfer unit 12, and is a continuous region in the island 300. If a current continues to flow to the reference potential terminal 340, there is a risk that a current will continue to flow from the p ohmic electrode 321 to the setting thyristor S and the VCSEL. If the setting thyristor S connected to the VCSEL that has emitted light remains on, the setting thyristor S may not turn off, resulting in erroneous lighting.

[0083] Next, a case where the light-emitting chip 10 shown in FIG. 5B is used will be described. As shown in FIG. 5B, in the light-emitting chip 10 having the groove 350 to which the first embodiment is applied, the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface P of the light-emitting chip 10 are electrically separated by the groove 350. Even if the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 of the island 300 are exposed in the light-emitting chip 10, the current flowing from the p-ohmic electrode 321 to the setting thyristor S and the VCSEL tends to flow as leakage current through the inside of the substrate 80, via the side surface P of the light-emitting chip 10, and from the p-anode (DBR) layer 83 to the reference potential terminal 340, as shown by the leakage current path 360 indicated by the dashed arrow in FIG. 5B. However, the presence of the groove 350 separating the p anode (DBR) layer 83 prevents leakage current from flowing through the p anode (DBR) layer 83 to the reference potential terminal 340. In other words, the formation of a leakage current path 360 via the side surface of the substrate 80 between the VCSEL light-emitting element and the reference potential terminal 340 is prevented. The groove 350 prevents the transfer unit 12 from extending to the outer periphery of the substrate 80 of the light-emitting chip 10. The leakage current path 360 is indicated by a dashed line to indicate that it is prevented. The groove 350 reduces the risk of damage caused by dicing on the side surface P, which is the dicing surface of the light-emitting chip 10. Furthermore, damage caused by dicing on the side surface P, which is the dicing surface of the light-emitting chip 10, is tolerated. To provide the groove 350, the light-emitting chip 10 may be slightly larger in area. Here, the transfer unit 12 is provided on the structure, and the p-anode (DBR) layer 83 and n-cathode (DBR) layer 81 of the structure form a p-n junction, and this p-n junction also separates the substrate potential Vsub of the substrate 80 (including the back electrode 91 and n-cathode (DBR) layer 81) from a reference potential terminal 340 that supplies a reference potential Vst to the transfer unit 12. Furthermore, since the function of the transfer unit 12 is completed on the structure, the original function of the transfer unit 12 does not require it to be an island. However, because the side surface of the light-emitting chip 10 is damaged and the separation by the p-n junction is insufficient, it is separated by a groove 350. The groove 350 is an example of a separation unit.

[0084] 6(a) and 6(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip 20 according to a modified example of the first embodiment. FIG. 6(a) is an example of a planar layout diagram of the light-emitting chip 20, and FIG. 6(b) is an example of a cross-sectional view taken along line VIB-VIB in FIG. 6(a). The light-emitting chip 20 is similar to the light-emitting chip 10 shown in FIGS. 3(a) and 3(b), except for the island 300. Therefore, the light-emitting chip 20 will be described with reference to the island 300, which is a different part from the light-emitting chip 10.

[0085] In the light-emitting chip 10 shown in FIG. 3A, the groove 350 is provided in the island 300 so as to surround the transfer unit 12 (see FIG. 3A). By providing the groove 350 so as to surround the transfer unit 12, the reference potential Vst and the substrate potential Vsub can be reliably separated. The groove 350 only needs to prevent leakage current that flows along the side surface of the light-emitting chip 10 to the p-anode (DBR) layer 83 from flowing through the p-anode (DBR) layer 83 to the reference potential terminal 340 of the transfer unit 12. In the light-emitting chip 20 shown in FIGS. 6A and 6B, the groove 350 is provided along the outer periphery of the light-emitting chip 10. In the light-emitting chip 20, the portion along the outer periphery of the light-emitting chip 20 is formed as the groove 350 by mesa etching down to the p-anode (DBR) layer 83. Note that the periphery of the island 301 is also removed by mesa etching until the p-anode (DBR) layer 83 is exposed. Therefore, the periphery of the island 301 can also be considered as a groove 350 .

[0086] Furthermore, the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the light-emitting chip 10 may be electrically isolated by a region in which insulating ions are implanted into the semiconductor layer constituting the transfer unit 12. The region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the light-emitting chip 10 may be electrically isolated by both a groove and insulating ions. The region implanted with insulating ions becomes an insulating region, which can electrically isolate the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the substrate 80. The insulating ions are H for III-V group compound semiconductors such as GaAs, AlGaAs, and AlAs. ＋When the insulating ions electrically separate the region of the transfer unit 12 connected to the reference potential terminal 340 from the side surface P of the light-emitting chip 10, the insulating ions may be implanted to surround the transfer unit 12, as in the case where the groove 350 is formed in the light-emitting chip 10 shown in FIG. 3A, or may be implanted along the periphery of the light-emitting chip 20, as in the case where the groove 350 is formed along the periphery of the light-emitting chip 20 shown in FIG. 6A. The insulating ions are implanted to separate at least the p anode (DBR) layer 83, and may be implanted deeper. The region into which the insulating ions are implanted is another example of a separation unit. Note that the separation unit may be formed partially as a groove and partially by implantation of insulating ions. Alternatively, the separation unit may simply be formed to prevent the leakage current path 360 from forming in a region where the leakage current path 360 is likely to form even without surrounding the region.

[0087] As described above, it is sufficient that the separation portion such as the groove 350 prevents the p anode (DBR) layer 83 located below the transfer portion 12 connected to the reference potential terminal 340 from extending to the outer periphery of the light-emitting chip 10.

[0088] [Embodiment 2] In embodiment 1, a common-cathode light-emitting chip 10 has been described. In embodiment 2, a common-anode light-emitting chip 30 will be described. The measurement device 100 is the same as in embodiment 1. FIG. 7 is an equivalent circuit diagram illustrating a light source device 2 to which embodiment 2 is applied. In FIG. 7, the right direction on the paper is the +x direction. Note that parts having the same functions as those in the light source device 1 to which embodiment 1 is applied are given the same reference numerals and will not be described. The light source device 2 shown in FIG. 7 includes a light-emitting chip 30 and a control unit 110.

[0089] (Control Unit 110) The control unit 110 includes a transfer signal generating unit 120, a lighting signal generating unit 140, a reference potential supplying unit 160, and a power supply potential supplying unit 170. The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially transition the multiple transfer thyristors T in the transfer unit 12 to an ON state. The lighting signal generating unit 140 generates a lighting signal φI that supplies a current that lights (emits light) the multiple VCSELs. The reference potential supplying unit 160 supplies a reference potential Vst to the transfer unit 12. The power supply potential supplying unit 170 supplies a power supply potential Vga. These have the same functions as those of the light source device 1, but the first transfer signal φ1, the second transfer signal φ2, the lighting signal φI, the reference potential Vst, and the power supply potential Vga have the same absolute values ​​but opposite signs. In other words, they are negative potentials with respect to the ground potential GND (0 V).

[0090] (Light-emitting chip 30) The light-emitting chip 30 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting chip 30 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 30 includes a Vsub terminal. The Vsub terminal is a back electrode 91 provided on the back surface of the substrate 80. In FIG. 7 , the terminal of the element connected to the substrate 80 (which is the same as the Vsub terminal) is indicated by the symbol △.

[0091] The light-emitting unit 11 includes a vertical cavity surface-emitting laser (VCSEL). In the example shown in Fig. 7, six VCSELs, VCSEL1 to VCSEL6, are included. The light-emitting unit 11 also includes six setting thyristors S1 to S6. The cathodes of the VCSELs and the anodes of the setting thyristors S are connected.

[0092] The transfer unit 12 includes six transfer thyristors T1 to T6 and six lower diodes UD1 to UD6. The transfer thyristors T1 to T6 and the lower diodes UD1 to UD6 are connected in series with the transfer thyristor T and lower diode UD of the same number. Additionally, similar to the light-emitting chip 10 shown in FIG. 3(b), the transfer thyristor T is stacked on the lower diode UD formed on the substrate 80. The lower diodes UD1 to UD6 are not separated but are integrated into one structure. The lower diodes UD1 to UD6 do not operate. In FIG. 7, the lower diodes UD1 to UD6 are indicated by dashed lines.

[0093] The transfer unit 12 pairs the transfer thyristors T1 to T6 in numerical order, and includes coupling diodes D1 to D5 between each pair. The transfer unit 12 also includes power line resistors Rg1 to Rg6.

[0094] The transfer unit 12 includes one start diode SD. The transfer unit 12 also includes current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 (described later) is supplied and a second transfer signal line 73 to which a second transfer signal φ2 (described later) is supplied.

[0095] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting unit 11, the transfer thyristors T1 to T6 of the transfer unit 12, the lower diodes UD1 to UD6, the coupling diodes D1 to D5, and the power supply line resistors Rg1 to Rg6 are arranged in numerical order in the light-emitting chip 30 from one side (the -x direction side, the left side in Figure 7) to the other side (the +x direction side, the right side in Figure 7).

[0096] In the second embodiment, similarly to the first embodiment, the number of VCSELs, setting thyristors S in the light-emitting unit 11, and the number of transfer thyristors T, lower diodes UD, and power line resistances Rg in the transfer unit 12 are six each. The number of coupling diodes D is five, which is one less than the number of transfer thyristors T. The numbers of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistances Rg, and coupling diodes D are not limited to the above and may be any predetermined number. The number of transfer thyristors T may also be greater than the number of VCSELs.

[0097] Next, the electrical connections of the elements in the light-emitting chip 30 will be described.

[0098] The anodes of the VCSEL and the lower diode UD are connected to the substrate 80 (anode common). A substrate potential Vsub is supplied to these anodes via a back electrode 91 (see FIG. 3B ), which is a Vsub terminal provided on the back surface of the substrate 80. The cathodes of the VCSELs are connected to the anodes of the setting thyristors S. The cathodes of the lower diodes UD are connected to the anodes of the transfer thyristors T. The anodes of the transfer thyristors T (the same as the cathodes of the lower diodes UD) are connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to this Vst terminal from a reference potential supply unit 160. The Vst terminal may be the reference potential terminal 340 shown in FIGS. 3A and 3B.

[0099] Along the arrangement of the transfer thyristors T, the anodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current-limiting resistor R1. A first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generating unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the anodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current-limiting resistor R2. A second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generating unit 120 of the control unit 110.

[0100] The cathodes of the setting thyristors S are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. A light-up signal φI is supplied to this φI terminal from the light-up signal generating unit 140 of the control unit 110 via a current limiting resistor RI provided outside the light-emitting chip 30. The light-up signal φI supplies a current for lighting the VCSEL.

[0101] The gates Gt1 to Gt6 of the transfer thyristors T1 to T6 are connected one-to-one to the gates Gs1 to Gs6 of the setting thyristors S1 to S6 having the same numbers. Therefore, the gates Gt1 to Gt6 and the gates Gs1 to Gs6 having the same numbers are electrically at the same potential.

[0102] Coupling diodes D1 to D5 are connected between pairs of gates Gt1 to Gt6 of the transfer thyristors T1 to T6, which are arranged in numerical order. That is, the coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6, respectively. The coupling diode D1 is connected in the direction in which current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D5.

[0103] The gates Gt (gates Gs) of the transfer thyristors T are connected to a power supply line 71 via power supply line resistors Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to a Vga terminal. A power supply potential Vga is supplied to the Vga terminal from a power supply potential supply unit 170 of the control unit 110.

[0104] The gate Gt1 of the transfer thyristor T is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0105] The planar layout and cross section of the light-emitting chip 30 are the same as those of embodiment 1 shown in Figures 3(a) and 3(b). The light-emitting chip 10 shown in Figure 3(b) uses a semiconductor laminate in which an n-cathode (DBR) layer 81, a light-emitting layer 82, a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 are stacked in this order on an n-type substrate 80. The light-emitting chip 30 uses a semiconductor laminate in which a p-anode (DBR) layer, a light-emitting layer, an n-cathode (DBR) layer, a tunnel junction layer, a p-anode layer, an n-gate layer, a p-gate layer, and an n-cathode layer are stacked in this order on a p-type substrate. In other words, n and p are in an inverted relationship.

[0106] As described above, by making the signal supplied from the control unit 110 negative, the light-emitting chip 30 operates in the same manner as the light-emitting chip 10. The same applies to the groove 350.

[0107] In the light-emitting chips 10, 20, and 30 shown in the first and second embodiments, two adjacent transfer thyristors T in the transfer unit 12 are coupled by a coupling diode D. In the light-emitting chip 40 shown in the third embodiment, two adjacent transfer thyristors T in the transfer unit 12 are connected by a coupling transistor Q. The measuring device 100 is the same as that in the first embodiment.

[0108] (Light Source Device 3) Figure 8 is an equivalent circuit diagram illustrating a light source device 3 to which embodiment 3 is applied. In Figure 8, the right direction on the paper surface is the +x direction. The light source device 3 shown in Figure 8 includes a light-emitting chip 40 and a control unit 110. The light-emitting chip 40 is a common cathode, similar to the light-emitting chip 10 of embodiment 1. The control unit 110 has the same configuration as the control unit 110 of the light source device 1 of embodiment 1, and is therefore referred to as the control unit 110.

[0109] (Light-Emitting Chip 40) The light-emitting chip 40 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting unit 11 and the transfer unit 12 in the light-emitting chip 40 have the same functions as those in the light-emitting chip 10. Therefore, the light-emitting chip 40 will also be referred to as the light-emitting unit 11 and the transfer unit 12. Like the light-emitting chip 10 of embodiment 1, the light-emitting chip 40 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 40 also includes a Vsub terminal. Like the light-emitting chip 10, the Vsub terminal is a back electrode 91 (see FIG. 10(b) described later) provided on the back surface of the substrate 80. In FIG. 8, the terminals of the elements connected to the substrate 80 (which is the same as the Vsub terminal) are indicated by the symbol ▽. These terminals have the same configuration as the light-emitting chip 10. The terminals excluding the Vsub terminal are connected to the control unit 110, like the light source device 1 of embodiment 1. In FIG. 8, resistors are indicated by rectangles.

[0110] The light-emitting unit 11 includes a plurality of VCSELs and setting thyristors S connected in series, similar to the light-emitting chip 10 of the first embodiment. Six VCSELs (VCSEL1 to VCSEL6) and six setting thyristors S (setting thyristors S1 to S6) are shown in FIG. 8. The anodes of the VCSELs and the cathodes of the setting thyristors S with the same number are connected. The six VCSELs and six setting thyristors S are arranged from one side (the −x direction side) to the other side (the +x direction side).

[0111] The transfer unit 12 includes a plurality of transfer thyristors T, coupling transistors Q, power supply line resistances Rg, current limiting resistances RL, and coupling resistances Rc. FIG. 8 shows six transfer thyristors T (transfer thyristors T1 to T6) and six coupling transistors Q (coupling transistors Q1 to Q6). The transfer unit 12 includes six power supply line resistances Rg, six current limiting resistances RL, and six coupling resistances Rc, but these are not numbered. One transfer thyristor T, coupling transistor Q, power supply line resistance Rg, current limiting resistance RL, and coupling resistance Rc form a transfer unit 12a. The six transfer units 12a are arranged from one side (the −x direction side) to the other side (the +x direction side). The transfer unit 12 includes a power supply line resistance Rg and a start resistance Rs at one end (the −x direction side). The transfer unit 12 also includes current limiting resistances R1 and R2.

[0112] In the transfer unit 12a, a setting thyristor S and a coupling transistor Q are connected. The coupling transistor Q in the transfer unit 12a is connected to the setting thyristor S of the light-emitting unit 11. The setting thyristors S1 to S6 are connected to the coupling transistors Q1 to Q6 of the same number. The coupling transistors Q1 to Q6 are connected to the setting thyristors S1 to S6 of the same number. Although six transfer thyristors T, coupling transistors Q, setting thyristors S, and VCSELs are shown in FIG. 8, other numbers may be used.

[0113] Although not shown in Fig. 8, the transfer unit 12 includes a lower diode UD having a structure similar to that of a VCSEL, similar to the light-emitting chip 10 of the first embodiment shown in Fig. 2. The lower diode UD does not operate in the same manner as the light-emitting chip 10.

[0114] In the light-emitting chip 40, the Vga terminal is connected to a power supply line 71, the Vst terminal is connected to a reference potential line 74, the φ1 terminal is connected to a first transfer signal line 72, the φ2 terminal is connected to a second transfer signal line 73, and the φI terminal is connected to a light-up signal line 75. The Vsub terminal is grounded to the ground potential GND (0 V).

[0115] (Operations of the Transfer Thyristor T, the Coupling Transistor Q, the VCSEL, and the Setting Thyristor S) Here, the basic operation of the light-emitting chip 40 will be described. The transfer thyristor T and the setting thyristor S are thyristors with an npnp structure. The thyristors include an n-type cathode K (hereinafter referred to as cathode K, and the same applies below), a p-type gate Gp (p-gate Gp), an n-type gate Gn (n-gate Gn), and a p-type anode A (anode A). The setting thyristor S does not use the p-gate Gp for control, so it is not shown. In the light-emitting chip 10 of the first embodiment, the gate of the transfer thyristor T is referred to as gate Gt, and the gate of the setting thyristor S is referred to as gate Gs. In the light-emitting chip 40, the p-type gate Gp (p-gate Gp) is used, so the gates are divided into the p-type gate Gp (p-gate Gp) and the n-type gate Gn (n-gate Gn). In the light-emitting chip 10, the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S correspond to the n-gate Gn.

[0116] The coupling transistor Q is a multi-collector npn bipolar transistor and includes an n-type emitter E (emitter E), a p-type base B (base B), and n-type collectors Cf and Cs (collector Cf and Cs).

[0117] The above symbols are used without distinction between thyristors and coupling transistors. The same applies to bipolar transistors that make up thyristors, which will be described later. However, as will be described later, a thyristor is made up of a combination of a single-collector npn bipolar transistor and a single-collector pnp bipolar transistor (see FIG. 9(a)). Therefore, the symbols are written as emitter E, base B, and collector C. Hereinafter, even when symbols are not attached to the figures, the symbols are used: anode A, cathode K, n-gate Gn, p-gate Gp, emitter E, base B, and collector C.

[0118] The transfer thyristor T, the coupling transistor Q, the setting thyristor S, and the VCSEL are made of a III-V group compound semiconductor, such as GaAs. As described above, the forward voltage (diffusion potential) Vd of the junction of this compound semiconductor is set to 1.5 V. The saturation voltage Vc of the bipolar transistor made of the compound semiconductor is set to 0.3 V. The power supply potential Vga is set to 5 V ("H" (5 V)). The first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI are signals whose L level is 0 V ("L" (0 V)) and whose H level is 5 V ("H" (5 V)). The ground potential GND is set to the ground potential GND (0 V).

[0119] 9A and 9B are diagrams illustrating the operation of the light-emitting chip 40 to which the third embodiment is applied. Fig. 9A is an equivalent circuit diagram, and Fig. 9B is a cross-sectional view of the transfer thyristor T1 and the coupling transistor Q1. Fig. 9A also shows the transfer thyristor T2.

[0120] 9A, the transfer thyristor T1 is configured by a combination of an npn bipolar transistor Tr1 (hereinafter referred to as npn transistor Tr1) and a pnp bipolar transistor Tr2 (hereinafter referred to as pnp transistor Tr2). The base B of the npn transistor Tr1 is connected to the collector C of the pnp transistor Tr2, and the collector C of the npn transistor Tr1 is connected to the base B of the pnp transistor Tr2. The emitter E of the npn transistor Tr1 is the cathode K of the transfer thyristor T1, the collector C of the npn transistor Tr1 (the base B of the pnp transistor Tr2) is the n gate Gn of the transfer thyristor T1, the collector C of the pnp transistor Tr2 (the base B of the npn transistor Tr1) is the p gate Gp of the transfer thyristor T1, and the emitter E of the pnp transistor Tr2 is the anode A of the transfer thyristor T1.

[0121] The emitter E of the npn transistor Tr1, which is the cathode K of the transfer thyristor T1, is connected to a reference potential line 74 connected to a Vst terminal to which a reference potential Vst is supplied. The emitter E of the pnp transistor Tr2, which is the anode A of the transfer thyristor T1, is connected to a first transfer signal line 72. The n gate Gn is connected to a connection point between the series-connected start resistor Rs and power supply line resistor Rg. The other end of the start resistor Rs (the end not at the connection point) is connected to a second transfer signal line 73. The other end of the power supply line resistor Rg (the end not at the connection point) is connected to a power supply line 71. The first transfer signal line 72 is connected to a φ1 terminal and is supplied with a first transfer signal φ1. The second transfer signal line 73 is connected to a φ2 terminal and is supplied with a second transfer signal φ2. The power supply line 71 is connected to a Vga terminal and is supplied with a power supply potential Vga.

[0122] The coupling transistor Q1, which is an npn transistor, has a base B connected to the p-gate Gp of the transfer thyristor T1 (the base B of the npn transistor Tr1 and the collector C of the pnp transistor Tr2), and an emitter E connected to the reference potential line 74. The collector Cf of the coupling transistor Q1 is connected to the power supply line 71 via a coupling resistor Rc and a power supply line resistor Rg connected in series. The connection point between the coupling resistor Rc and the power supply line resistor Rg is connected to the n-gate Gn of the transfer thyristor T2.

[0123] The npn transistor Tr1 in the transfer thyristor T1 and the coupling transistor Q1 form a current mirror circuit. A current proportional to the current flowing through the npn transistor Tr1 flows through the coupling transistor Q1.

[0124] The collector Cs of the coupling transistor Q1 is connected to the n-gate Gn of the setting thyristor S1 and is also connected via a current limiting resistor RL to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal and is supplied with a light-up signal φI.

[0125] As described above, the VCSEL1 and the setting thyristor S1 are connected in series. The anode A of the VCSEL1 and the cathode K of the setting thyristor S1 are connected. The anode A of the setting thyristor S1 is connected to the light-on signal line 75. The cathode K of the VCSEL1 is connected to the substrate 80 at the substrate potential Vsub.

[0126] The anode A of the transfer thyristor T2 is connected to the second transfer signal line 73. As shown in Fig. 8 , the anode A of the odd-numbered transfer thyristors T is connected to the first transfer signal line 72, and the anode A of the even-numbered transfer thyristors T is connected to the second transfer signal line 73. Except for the connection relationship of the transfer thyristors T with the first transfer signal line 72 and the second transfer signal line 73, the connection relationship of the transfer thyristors T numbered 2 or more, the coupling transistors, the setting thyristors S, and the VCSELs is the same as that of the transfer thyristor T1, the coupling transistor Q1, the setting thyristor S1, and the VCSEL1.

[0127] (Operation of Transfer Thyristor T) The operation of the transfer thyristors T1 and T2 will be described. The power supply potential Vga (power supply line 71) is set to 5 V. The reference potential Vst (reference potential line 74) is set to the ground potential GND (0 V). The first transfer signal φ1, the second transfer signal φ2, and the light-up signal φI are set to "L" (0 V). At this time, the npn transistor Tr1 and the pnp transistor Tr2 constituting the transfer thyristor T1 are in the off state. The n gate Gn of the transfer thyristor T1 is connected to the connection point between the start resistor Rs and the power supply line resistance Rg connected in series. The other end of the start resistor Rs (the side not at the connection point) is connected to the second transfer signal line 73 at "L" (0 V), and the other end of the power supply line resistance Rg (the side not at the connection point) is connected to the 5 V power supply line 71. Therefore, the n gate Gn has a voltage obtained by dividing the voltage difference (5 V) between the start resistor Rs and the power supply line resistance Rg. If the resistance ratio between the start resistor Rs and the power supply line resistor Rg is 1:5, for example, the n-gate Gn will be 0.83 V. This state will be referred to as the initial state.

[0128] Here, the first transfer signal φ1 (first transfer signal line 72) is shifted from "L" (0 V) to "H" (5 V). The emitter E of the pnp transistor Tr2 of the transfer thyristor T1 becomes "H" (5 V). The voltage difference (4.17 V) between the emitter E ("H" (5 V)) and the base B (p-gate Gp) (0.83 V) becomes equal to or greater than the forward voltage Vd (1.5 V). Because a forward bias is applied between the emitter E and the base B, the pnp transistor Tr2 shifts from the OFF state to the ON state. Then, the collector C of the pnp transistor Tr2 (the base B of the npn transistor Tr1) becomes 4.7 V, which is the emitter E ("H" (5 V)) minus the saturation voltage Vc (0.3 V). The voltage difference (4.7 V) between the emitter E (0 V) and base B (4.7 V) of the npn transistor Tr1 becomes equal to or greater than the forward voltage Vd (1.5 V). Because a forward bias is applied between the emitter E and base B, the npn transistor Tr1 transitions from an off state to an on state. Because the npn transistor Tr1 and the pnp transistor Tr2 in the transfer thyristor T1 transition to an on state, the transfer thyristor T1 transitions from an off state to an on state (turns on).

[0129] In the initial state, when the first transfer signal φ1 transitions from “L” (0 V) to “H” (5 V), the transfer thyristor T1 turns on and transitions from the OFF state to the ON state.

[0130] When the transfer thyristor T1 is turned on, the n-gate Gn of the transfer thyristor T1 becomes 0.3 V, which is the saturation voltage Vc. The anode A becomes a voltage determined by the sum of the forward voltage Vd and the saturation voltage Vc (Vd+Vc) and the voltage drop due to the internal resistance of the transfer thyristor T. Here, it is assumed that the anode A becomes 1.9 V. In other words, when the transfer thyristor T1 is turned on, the first transfer signal line 72 shifts from 5 V to 1.9 V. The p-gate Gp of the transfer thyristor T1 becomes 1.6 V.

[0131] As described above, the transfer thyristor T1 turns on when the voltage of the n gate Gn becomes lower than the voltage of the anode A by the forward voltage Vd (1.5 V) or more. The transfer thyristor T1 turns off when the voltage of the first transfer signal line 72 (the voltage between the anode A and the cathode K) becomes less than 1.9 V. For example, when the anode A becomes "L" (0 V), the voltage difference between the anode A and the cathode K becomes 0 V, and the transfer thyristor T1 turns off. On the other hand, if the voltage of the first transfer signal line 72 (the voltage difference between the anode A and the cathode K) is 1.9 V or more, the on state of the transfer thyristor T1 is maintained. Therefore, 1.9 V is referred to as the holding voltage. Even if the holding voltage is applied, if a current for maintaining the transfer thyristor T1 in the on state does not flow, the on state of the transfer thyristor T1 is not maintained. The current that maintains the on state is referred to as the holding current.

[0132] Next, the operation of the coupling transistor Q1 will be described. When the transfer thyristor T1 is in the off state, the npn transistor Tr1 is in the off state. Therefore, the coupling transistor Q1 is also in the off state. The emitter E of the coupling transistor Q1 is connected to the reference potential line 74. Since the reference potential Vst is set to the ground potential GND (0 V), the reference potential line 74 is also at the ground potential GND (0 V). Therefore, the emitter E is at the ground potential GND (0 V). The collector Cf is at the power supply potential Vga (5 V) via the power supply line resistance Rg and the coupling resistance Rc, which are connected in series. Furthermore, the collector Cs is at the potential (0 V) of the lighting signal φI ("L" (0 V)) via the current limiting resistance RL.

[0133] When the transfer thyristor T1 turns on, that is, when the npn transistor Tr1 enters the on state, the p-gate Gp of the transfer thyristor T1 becomes 1.6 V, as described above. Then, because the base B of the coupling transistor Q1 is connected to the p-gate Gp of the transfer thyristor T1, the voltage between the emitter E and base B becomes equal to or higher than the forward voltage Vd (1.5 V), that is, a forward bias occurs. The coupling transistor Q1 transitions from the off state to the on state. The collector Cf becomes the saturation voltage Vc (0.3 V) (the collector Cs will be described later). The connection point between the power supply line resistance Rg and the coupling resistance Rc (the n-gate Gn of the transfer thyristor T2) becomes a voltage obtained by dividing the voltage difference (4.7 V) between the power supply voltage (5 V) of the power supply line 71 and the voltage (0.3 V) of the collector Cf by the power supply line resistance Rg and the coupling resistance Rc. If the resistance ratio between the power supply line resistance Rg and the coupling resistance Rc is 5:1, for example, the connection point between the power supply line resistance Rg and the coupling resistance Rc (the n-gate Gn of the transfer thyristor T2) becomes 1.08V.

[0134] The anode A of the transfer thyristor T2 is connected to the second transfer signal line 73 to which the second transfer signal φ2 is supplied. Because the second transfer signal φ2 is "L" (0 V), the transfer thyristor T2 does not turn on. However, when the second transfer signal φ2 shifts from "L" (0 V) to "H" (5 V), the anode A of the transfer thyristor T2 becomes "H" (5 V), and the voltage difference (3.92 V) with the n gate Gn (1.08 V) becomes equal to or greater than the forward voltage Vd (1.5 V), that is, a forward bias is applied between the n gate Gn and the anode A, and the transfer thyristor T2 turns on. In this way, the transfer thyristor T shifts its on state sequentially according to the first transfer signal φ1 and the second transfer signal φ2.

[0135] Next, the operation of the setting thyristor S1 and VCSEL1 will be described. When the coupling transistor Q1 is turned on, the collector Cs becomes equal to the saturation voltage Vc (0.3 V), as does the collector Cf. The n-gate Gn of the setting thyristor S1 is connected to the collector Cs of the coupling transistor Q1, and therefore becomes 0.3 V. At this point, the light-up signal φI transitions from "L" (0 V) to "H" (5 V). The anode A of the setting thyristor S1 is connected to the light-up signal line 75 to which the light-up signal φI is supplied. The anode A of the setting thyristor S1 becomes "H" (5 V). The cathode K of VCSEL1 is connected to the substrate 80 (Vsub terminal) which is set to the ground potential GND (0 V). Therefore, when the lighting signal φI transitions from "L" (0 V) to "H" (5 V), "H" (5 V) is applied to the series connection of the setting thyristor S1 and the VCSEL, and at the same time, a voltage difference (4.7 V) occurs between the anode A and gate Gn of the setting thyristor S1, and a forward bias is applied between the anode A and gate Gn. This turns on the setting thyristor S1, causing a current to flow through the VCSEL1 and lighting it up.

[0136] That is, the initial state is a state in which the power supply line 71 is set to the power supply potential Vga (5 V), the reference potential Vst and the substrate potential Vsub of the reference potential line 74 are set to the ground potential GND (0 V), and the first transfer signal φ1 and the second transfer signal φ2 are “L” (0 V). In the initial state, the transfer thyristor T1 is in a state in which it can transition to an ON state. Here, when the first transfer signal φ1 (first transfer signal line 72) transitions from “L” (0 V) to “H” (5 V), the transfer thyristor T1 turns on and transitions from an OFF state to an ON state. When the transfer thyristor T1 turns on, the coupling transistor Q1 transitions from an OFF state to an ON state. Here, when the light-up signal φI (light-up signal line 75) transitions from “L” (0 V) to “H” (5 V), a forward bias is applied between the anode A and gate Gn of the setting thyristor S, and VCSEL1 is turned on. Furthermore, when the coupling transistor Q1 is turned on, the transfer thyristor T2 is able to transition to the on state. Then, when the second transfer signal φ2 (second transfer signal 73) transitions from "L" (0 V) to "H" (5 V), the transfer thyristor T2 is turned on. Note that when the first transfer signal φ1 (first transfer signal line 73) transitions from "H" (5 V) to "L" (0 V), the cathode K and anode A of the transfer thyristor T1 become 0 V, and the transfer thyristor T1 is turned off. The other transfer thyristors T, coupling transistors Q, setting thyristors S, and VCSELs operate in the same manner.

[0137] As shown in FIG. 9B , the light-emitting chip 40 is configured with a semiconductor laminate in which multiple semiconductor layers are stacked (see FIG. 10B , which will be described later). The semiconductor laminate is similar to the semiconductor laminate of the light-emitting chip 10. FIG. 9B shows a portion in which a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which constitute the transfer thyristor T1 and the coupling transistor Q1, are stacked. The transfer thyristor T1 is configured with the n-cathode layer 85 as the cathode K, the p-gate layer 86 as the p-gate Gp, the n-gate layer 87 as the n-gate Gn, and the p-anode layer 88 as the anode A. On the other hand, the coupling transistor Q1 is configured with the n-cathode layer 85 as the emitter E, the p-gate layer 86 as the base B, and the n-gate layer 87 as the collectors Cf and Cs. The p-anode (DBR) layer 83 is connected to a Vst terminal (reference potential terminal 341) that supplies a reference potential Vst of the transfer unit 12. The p-anode (DBR) layer 83, the tunnel junction layer 84, and the n-cathode layer 85 are at the same potential.

[0138] Here, the cathode K of the transfer thyristor T1 and the emitter E of the coupling transistor Q1 are electrically connected via an n-cathode layer 85. Similarly, the p-gate Gp of the transfer thyristor T1 and the base B of the coupling transistor Q1 are electrically connected via a p-gate layer 86. The n-gate Gn of the transfer thyristor T1 and the collectors Cf and Cs of the coupling transistor Q1 are both formed of an n-gate layer 87 but are separated from each other. The same applies to the other transfer thyristors T and coupling transistors Q.

[0139] 10(a) and 10(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip 40 to which the third embodiment is applied. FIG. 10(a) is an example of a planar layout diagram of the light-emitting chip 40, and FIG. 10(b) is an example of a cross-sectional view taken along line XB-XB of FIG. 10(a). In FIGS. 10(a) and 10(b), the protective layer (protective layer 90 of FIG. 4) and the light-shielding layer (light-shielding layer 95 of FIG. 4) are omitted. In FIG. 10(b), the connection wirings shown in FIG. 10(a) are omitted. In FIG. 10(a), the transfer thyristors T1 to T4, the coupling transistors Q1 to Q4, the setting thyristors S1 to S4, and the VCSELs 1 to 4 shown in FIG. 8 are mainly shown. FIG. 10B shows a cross section of the setting thyristor S1, VCSEL1, transfer thyristor T1, coupling transistor Q1, coupling resistor Rc connected to coupling transistor Q1, and power supply line resistor Rg.

[0140] 10(b), the light-emitting chip 40 is configured by stacking an n-cathode (DBR) layer 81, a light-emitting layer 82, a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 on an n-type substrate 80. Elements such as the transfer thyristor T, the coupling transistor Q, the setting thyristor S, and the VCSEL are configured on a plurality of islands separated by removing some of the semiconductor layers by etching. Below, the islands (islands 300, 361 to 367) will be described, focusing on the island 361 where the setting thyristor S1 and the VCSEL1 are provided, and the island 362 where the transfer thyristor T1 and the coupling transistor Q1 are provided.

[0141] The island 300 is the part where the transfer section 12 (see Figure 8) such as the transfer thyristor T1 and the coupling transistor Q1 is provided, similar to the light-emitting chip 10, and the n-cathode (DBR) layer 81, the light-emitting layer 82, and the p-anode (DBR) layer 83 remain on the substrate 80 without being removed.

[0142] The VCSEL1 and the setting thyristor S1 are stacked on the island 361. The transfer thyristor T1 and the coupling transistor Q1 shown in FIG. 9B are provided on the island 362. The current limiting resistor RL is provided on the island 363, and the power supply line resistor Rg and the coupling resistor Rc are provided on the island 364. The power supply line resistor Rg and the start resistor Rs are provided on the island 365. The current limiting resistor R1 is provided on the island 366, and the current limiting resistor R2 is provided on the island 367.

[0143] The planar layout and cross section of the light-emitting chip 40 will be described below with reference to FIGS. 10A and 10B. Around the island 361, the p-anode layer 88, n-gate layer 87, p-gate layer 86, n-cathode layer 85, tunnel junction layer 84, and p-anode (DBR) layer 83 have been removed by etching. A p-ohmic electrode 381 that easily makes ohmic contact with the p-type semiconductor layer is provided on the p-anode layer 88. An n-ohmic electrode 391 that easily makes ohmic contact with the n-type semiconductor layer is provided on the n-gate layer 87 that is exposed by removing the p-anode layer 88. In the VCSEL 1, the n-cathode (DBR) layer 81 is referred to as the cathode K (see FIG. 9A), the light-emitting layer 82 is referred to as the light-emitting layer, and the p-anode (DBR) layer 83 is referred to as the anode A. The setting thyristor S1 has the n-cathode layer 85 as the cathode K, the p-gate layer 86 as the p-gate Gp, the n-gate layer 87 as the n-gate Gn, and the p-anode layer 88 as the anode A. The n-ohmic electrode 391 is an electrode of the n-gate Gn of the setting thyristor S1 (n-gate Gn electrode). The n-ohmic electrode 391 may be referred to as the n-gate Gn.

[0144] 10B, the VCSEL1 is provided on a substrate 80, and the setting thyristor S1 is provided on the VCSEL1 via a tunnel junction layer 84. The tunnel junction layer 84 prevents a reverse bias between the p-anode (DBR) layer 83 of the VCSEL1 and the n-cathode layer 85 of the setting thyristor S1, which would make it difficult for a current to flow.

[0145] The island 361 is cylindrical except for the portion where the n-ohmic electrode 391 is provided. The p-ohmic electrode 381 is provided in a circular ring shape on the p-anode layer 88 of the cylindrical island 361. A portion of the semiconductor layer constituting the p-anode (DBR) layer 83 exposed by etching is oxidized from the exposed portion, forming a circular current blocking portion β through which current does not easily flow. On the other hand, the unoxidized central portion forms a current passing portion α through which current easily flows. The current passing portion α and the current blocking portion β are the same as those of the light-emitting chip 10.

[0146] Around the island 362, the p-anode layer 88, the n-gate layer 87, the p-gate layer 86, the n-cathode layer 85, and the tunnel junction layer 84 are removed by etching (see FIG. 9B ). A p-ohmic electrode 382 is provided on the p-anode layer 88. The p-ohmic electrode 382 is an electrode (anode A electrode) connected to the anode A of the transfer thyristor T1, and is connected to the first transfer signal line 72 to which the first transfer signal φ1 is supplied. N-ohmic electrodes 392, 393, and 394 are provided on the n-gate layer 87 exposed by removing the p-anode layer 88. The n-ohmic electrodes 392 and 394 are electrodes (collector Cf and Cs electrodes) connected to the collectors Cs and Cf of the coupling transistor Q1. Note that the n-gate layer 87 between the p-ohmic electrode 382 and the n-ohmic electrodes 392 and 394 is removed (see FIG. 9B ). The n-ohmic electrode 393 is an electrode (n-gate Gn electrode) connected to the n-gate Gn of the transfer thyristor T1.

[0147] Around the periphery of the island 364, the p anode layer 88, n gate layer 87, p gate layer 86, n cathode layer 85, and tunnel junction layer 84 are removed by etching. Three n ohmic electrodes 397, 398, and 399 are provided on the n gate layer 87 exposed by removing the p anode layer 88. The n gate layer 87 between the n ohmic electrodes 397 and 398 is a coupling resistance Rc, and the n gate layer 87 between the n ohmic electrodes 398 and 399 is a power supply line resistance Rg.

[0148] 10B is configured similarly to the island 364, and has two n-ohmic electrodes 395 and 396 provided on the exposed n-gate layer 87. The n-gate layer 87 between the two n-ohmic electrodes 395 and 396 is a current-limiting resistor RL.

[0149] An island 365 not shown in Fig. 10B has the same configuration as the island 364, and is provided with a start resistor Rs and a power supply line resistor Rg. Islands 366 and 367 not shown in Fig. 10B have the same configuration as the island 363, and are provided with current limiting resistors R1 and R2.

[0150] A p-ohmic electrode 341 is provided on the exposed p-anode (DBR) layer 83 of the island 300. In the light-emitting chip 40, a portion along the periphery of the light-emitting chip 40 is removed by mesa etching down to the p-anode (DBR) layer 83 to form a groove 350. The periphery of the island 361 is also removed by mesa etching until the p-anode (DBR) layer 83 is exposed. Therefore, the periphery of the island 361 can also be considered to be the groove 350. This groove 350 is similar to that of the light-emitting chip 20 shown in FIG. 6. The transfer unit 12 of the light-emitting chip 40 is surrounded by the groove 350. A back electrode 91 is provided on the back surface of the n-type substrate 80.

[0151] Next, the connection relationships will be described. Note that in FIG. 10A, the wiring used for the connections (power supply line 71, first transfer signal line 72, second transfer signal line 73, reference potential line 74, and light-up signal line 75) are indicated by solid lines. A p-ohmic electrode 381, which is the anode A electrode of the setting thyristor S1 of the island 361, is connected to the light-up signal line 75 to which the light-up signal φI is supplied. An n-ohmic electrode 391, which is the n-gate Gn electrode of the setting thyristor S1 of the island 361, is connected to an n-ohmic electrode 392, which is the collector Cs electrode of the coupling transistor Q1 of the island 362. The n-ohmic electrode 392 is connected to an n-ohmic electrode 396 of a current limiting resistor RL provided in the island 363. An n-ohmic electrode 395 of the island 363 is connected to the light-up signal line 75.

[0152] A p-ohmic electrode 382, ​​which is the anode A electrode of the transfer thyristor T1 of the island 362, is connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal to which a first transfer signal φ1 is supplied, via a current limiting resistor R1 provided in the island 366. An n-ohmic electrode 393, which is the n-gate Gn electrode of the transfer thyristor T1 of the island 362, is connected to an n-ohmic electrode (without symbol) that is the connection point between the power supply line resistor Rg and the start resistor Rs provided in the island 365. An n-ohmic electrode 394, which is the collector Cf electrode of the coupling transistor Q1 of the island 362, is connected to one n-ohmic electrode 397 of the coupling resistor Rc of the island 364.

[0153] The other n-ohmic electrode 398 of the coupling resistance Rc of the island 364 is connected to an n-ohmic electrode (no symbol) that is the n-gate Gn electrode of the transfer thyristor T2. The other n-ohmic electrode 399 of the power supply line resistance Rg of the island 364 is connected to the power supply line 71 to which the power supply potential Vga is supplied.

[0154] One n-ohmic electrode (no symbol) of the start resistance Rs of the island 365 is connected to the second transfer signal line 73. The other n-ohmic electrode (no symbol) of the power supply line resistance Rg of the island 365 is connected to the power supply line 71. The second transfer signal line 73 is connected to the φ2 terminal to which the second transfer signal φ2 is supplied via a current limiting resistance R2 provided in the island 367.

[0155] The first transfer signal line 72 is connected to the p-ohmic electrode which is the anode A electrode of the odd-numbered transfer thyristor T, and the second transfer signal line 73 is connected to the p-ohmic electrode which is the anode A electrode of the even-numbered transfer thyristor T.

[0156] The other transfer thyristors T, coupling transistors Q, setting thyristors S, and VCSELs are configured similarly to the transfer thyristor T1, coupling transistor Q1, setting thyristor S1, and VCSEL1.

[0157] The p ohmic electrode 341 of the exposed p anode (DBR) layer 83 of the island 300 is connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to the Vst terminal. Note that the reference potential line 74 and the Vst terminal may be omitted, and the p ohmic electrode 341 may serve as the Vst terminal or the reference potential terminal 341. Hereinafter, the Vst terminal will be referred to as the reference potential terminal 341. The reference potential terminal 341 is another example of a reference potential terminal. A back surface electrode 91 on the back surface of the n-type substrate 80 is a Vsub terminal to which a substrate potential Vsub is supplied.

[0158] The transfer unit 12, which includes the transfer thyristor T, the coupling transistor Q, and the like, is provided on a lower diode UD, which is configured with a p-anode (DBR) layer 83, a light-emitting layer 82, and an n-cathode (DBR) layer 81, similar to a VCSEL, which is a light-emitting element. The lower diode UD is referred to as a structure equivalent to the light-emitting element. The p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 of the equivalent structure form a p-n junction. This p-n junction electrically isolates the substrate potential Vsub of the substrate 80 (including the back electrode 91 and the n-cathode (DBR) layer 81) from a reference potential terminal 341 that supplies a reference potential Vst to the transfer unit 12.

[0159] As described above, the light-emitting chip 40 is provided on the substrate 80 made of a single semiconductor. Although a common-cathode type circuit is shown in the third embodiment, a common-anode type circuit may also be used. While a common-cathode type uses an n-type substrate, a common-anode type uses a p-type substrate, with the n-type and p-type being reversed from the third embodiment.

[0160] [Embodiment 4] In Embodiments 1, 2, and 3, the light-emitting chips 10, 20, 30, and 40 have been described. In Embodiment 4, a method for operating the light-emitting chips 10, 20, 30, and 40 will be described. The light-emitting chip 20 is a modified version of the light-emitting chip 10. The light-emitting chip 30 is the light-emitting chip 10 with the polarity reversed. The light-emitting chip 30 can be operated by reversing the polarity of the potential in the light-emitting chip 10. The light-emitting chip 40 is the light-emitting chip 10 in which the element (coupling element) that couples two adjacent transfer thyristors T is changed from a diode to a transistor, and can be operated in the same manner as the light-emitting chip 10. A method for operating the light-emitting chip 10 will be described below.

[0161] In the equivalent circuit diagram of the light source device 1 in FIG. 2 , the substrate potential Vsub and the reference potential Vst are set to the ground potential GND (0 V), and the power supply potential Vga is set to “H” (5 V). The first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI are set to signals having “H” (5 V) and “L” (0 V). Then, a voltage of up to 5 V (equivalent to “H” (5 V)) is applied to the series connection of the VCSEL and the setting thyristor S. Similarly, a voltage of up to 5 V (equivalent to “H” (5 V)) is also applied to the transfer thyristor T. As described above, the transfer thyristor T operates in the same manner as the setting thyristor S. Therefore, the voltage applied to the transfer thyristor T may be 5 V or less. If the reference potential Vst is set to, for example, 1 V, the voltage applied to the transfer thyristor T is reduced to 4 V. This prevents an excessive voltage (overvoltage) from being applied to the transfer thyristor T.

[0162] The reference potential Vst is applied to a reference potential terminal 340 shown in FIG. 3B. The reference potential terminal 340 is connected to the p-anode (DBR) layer 83 of the transfer section 12. The n-cathode (DBR) layer 81 is located below the p-anode (DBR) layer 83 via the light-emitting layer 82. The p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 form a pn junction. The n-cathode (DBR) layer 81 is at a substrate potential Vsub via an n-type substrate 80 and a back electrode 91. When the substrate potential Vsub is set to the ground potential GND (0 V) and the reference potential Vst is set to 1 V, the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 are in a forward bias state. However, the 1 V set as the reference potential Vst is less than the forward voltage Vd (1.5 V) of the p-n junction, and no current flows between the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81. Even if leakage current occurs at the side surface P, which is the dicing surface of the light-emitting chip 10, the groove 350 where the p-anode (DBR) layer 83 is removed prevents the leakage current from flowing via the side surface P of the light-emitting chip 10 to the reference potential terminal 340 of the transfer unit 12. As described above, current flow from the n-cathode (DBR) layer 81 to the p-anode (DBR) layer 83 of the transfer unit 12 via the p-n junction is also prevented. Note that if the voltage applied to the reference potential Vst is equal to or greater than the forward voltage Vd (1.5 V) of the p-n junction, current will flow from the n-cathode (DBR) layer 81 to the p-anode (DBR) layer 83 of the transfer unit 12. The voltage applied to the reference potential Vst is preferably less than the forward voltage Vd (1.5 V) of the pn junction.

[0163] Next, a method for operating the light-emitting chip 10 by low-side driving will be described. Low-side driving is a configuration in which an element such as a MOS transistor is positioned downstream of the current path of a light-emitting element. Low-side driving is recommended when it is desired to operate the light-emitting element at a higher speed.

[0164] FIG. 11 is an equivalent circuit diagram illustrating a light source device 4 to which embodiment 4 is applied. In FIG. 11, the right direction of the paper is the +x direction. The measurement device 100 using the light source device 4 is the same as that of embodiment 1. The light source device 4 shown in FIG. 11 includes a light-emitting chip 10 and a control unit 111. The light-emitting chip 10 is the light-emitting chip 10 described in embodiment 1. The control unit 111 is partially different from the control unit 110 described in embodiment 1. Below, the different parts will be described, and similar parts will be given the same symbols and will not be described again.

[0165] (Control Unit 111) The control unit 111 includes a transfer signal generating unit 120, a lighting signal generating unit 140, a power supply potential supplying unit 170, a driver unit 180, and a light-emitting potential supplying unit 190. The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially switch a plurality of transfer thyristors T in the transfer unit 12 (described later) to an ON state. The lighting signal generating unit 140 generates a lighting signal φI that turns on (emits) a plurality of VCSELs (described later). The power supply potential supplying unit 170 supplies a power supply potential Vga. The driver unit 180 controls the light-emitting current in response to the lighting signal φI. The light-emitting potential supplying unit 190 supplies a light-emitting potential VLD.

[0166] The driver unit 180 includes a driver Drv. The driver Drv uses, for example, an NMOS transistor as a driver element. The driver Drv is turned on / off by a lighting signal φI applied to the gate of the NMOS transistor. The source of the NMOS transistor is grounded and is at the ground potential GND (0 V). The drain is connected to the Vsub terminal of the light-emitting chip 10 via a current-limiting resistor RI. When the driver Drv is turned on, it supplies the ground potential GND (0 V) to the Vsub terminal of the light-emitting chip 10. The lighting signal φI is a signal that transitions between "H" (5 V) and "L" (0 V). "H" (5 V) turns on the driver Drv, and "L" (0 V) turns off the driver Drv. The source is one end of the driver Drv, and the drain is the other end of the driver Drv.

[0167] The light-emitting potential supply unit 190 supplies a light-emitting potential VLD to the φI terminal of the light-emitting chip 10. The light-emitting potential VLD is, for example, 5 V ("H" (5 V)). That is, in the light source device 4, the φI terminal of the light-emitting chip 10 is supplied with the light-emitting potential VLD, rather than with the lighting signal φI. The VCSEL and the setting thyristor S are connected in series. The light-emitting potential VLD is applied to the anode of the setting thyristor S.

[0168] The Vst terminal that supplies the reference potential Vst is grounded to the ground potential GND (0 V).

[0169] The operation of the light source device 4 will be described. The lighting signal φI is set to "L" (0 V). The driver Drv is off, and the Vsub terminal is not at the ground potential GND (0 V). The operation of the transfer unit 12 of the light-emitting chip 10 is the same as in the first embodiment. When the transfer thyristor T is turned on, the gate Gt of the transfer thyristor T becomes "L" (0 V). The gate Gs of the setting thyristor S connected to the gate Gt of the transfer thyristor T also becomes "L" (0 V). This causes the threshold voltage of the setting thyristor S to become 1.5 V. At this time, the driver Drv is off, so no current flows through the VCSEL and setting thyristor S connected in series. Here, when the lighting signal φI becomes "H" (5 V), the driver Drv turns on. The Sub terminal becomes the ground potential GND (0 V). Then, the setting thyristor S is turned on, and the VCSEL connected in series to the setting thyristor S is turned on.

[0170] 12(a) and 12(b) are diagrams illustrating leakage current in a light source device 4 to which the fourth embodiment is applied. FIG. 12(a) is a cross-sectional view illustrating a case where a light-emitting chip 10' without a groove 350 is used, and FIG. 12(b) is a cross-sectional view illustrating a case where a light-emitting chip 10 having a groove 350 is used. The horizontal direction of the drawings is the +y direction shown in FIG. 3(a). The cross-sectional view shown in FIG. 12(a) is the same as the cross-sectional view shown in FIG. 5(a). The cross-sectional view shown in FIG. 12(b) is the same as the cross-sectional view shown in FIG. 5(b). The case where the light-emitting chip 10' shown in FIG. 12(a) is used will be described. Note that FIG. 12(a) shows a state in which the driver Drv has been switched from on to off (denoted as "off" in FIG. 12(a)). In the light source device 4, the substrate 80 (rear electrode 91) of the light-emitting chip 10' is grounded (GND (0V)) via the driver Drv. When the driver Drv is on (the lighting signal φI is “H” (5 V)), the setting thyristor S is turned on, and a current flows through the series-connected setting thyristor S and the VCSEL. The current flows from the p-ohmic electrode 321 to the substrate 80 and back surface electrode 91, and then to ground (GND (0 V)) via the driver Drv.

[0171] At this time, if the side surface of the light-emitting chip 10′ is damaged by dicing, the current will flow through the inside of the substrate 80 to the side surface P of the light-emitting chip 10, and then flow along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83 of the transfer unit 12. The p-anode (DBR) layer 83 of the transfer unit 12 is grounded (GND (0 V)) via the reference potential terminal 340. In addition, when the driver Drv is on, a leakage current path (leakage current path 360) is formed, which flows from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80 to ground (GND (0 V)) via the driver Drv, and from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10′ to the reference potential terminal 340 at the ground potential GND (0 V).

[0172] Here, when the driver Drv is transitioned from on to off, the current path that flows from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, and then to ground (GND (0 V)) via the driver Drv, is interrupted. However, the leakage current path 360 that flows from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10, and to the reference potential terminal 340 at the ground potential GND (0 V), is not interrupted and continues to flow. In other words, if the leakage current can maintain the lighting of the VCSEL, the VCSEL continues to light. Even if the leakage current cannot maintain the lighting of the VCSEL, if the setting thyristor S can maintain the on state, when other VCSELs are turned on, the VCSEL connected to the setting thyristor S that is maintained in the on state will light up along with the other VCSELs. In other words, erroneous lighting occurs.

[0173] Next, a case where the light-emitting chip 10 shown in Fig. 12(b) is used will be described. Fig. 12(b) shows a state in which the driver Drv has been transitioned from on to off (denoted as off in Fig. 12(b)). When the light-emitting chip 10 having the groove 350 is used, when the driver Drv is on, the path from the p-ohmic electrode 321, which is the light-emitting potential VLD, via the setting thyristor S, the VCSEL, and the substrate 80, and then via the driver Drv to ground (GND (0 V)) is the same as that of the light-emitting chip 10'. However, unlike the case shown in FIG. 12A , a leakage current path 360 that attempts to flow from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10, and to the reference potential terminal 340 at the ground potential GND (0 V), is blocked by the groove 350 and does not reach the p-anode (DBR) layer 83 of the transfer unit 12 that is set to the ground potential GND (0 V) by the reference potential terminal 340. In a light-emitting chip 10 having the groove 350, even if the side surface P of the light-emitting chip 10 is damaged by dicing, the groove 350 provided in the island 300 prevents the leakage current path 360 from being formed. Therefore, the leakage current path 360 is indicated by a dashed line. The lit VCSEL is turned off by turning off the driver Drv. The setting thyristor S is prevented from remaining in the on state.

[0174] The p-anode (DBR) layer 83 and n-cathode (DBR) layer 81 of the transfer unit 12 form a p-n junction as described above. The p-anode (DBR) layer 83 is at ground potential GND (0 V) via the reference potential terminal 340. On the other hand, the n-cathode (DBR) layer 81 is at the same potential as the substrate 80 (including the back electrode 91) and is grounded (GND (0 V)) via the driver Drv. By passing through the driver Drv, the n-cathode (DBR) layer 81 is at least at a positive potential. The p-n junction between the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 is in a reverse bias state. In addition, the region to which the reference potential terminal 340 of the transfer unit 12 is connected (the p-anode (DBR) layer 83 of the island 300) is electrically isolated from the substrate 80 (including the back electrode 91).

[0175] By using the light-emitting chip 10 in which the groove 350 is provided in the island 300 in which the transfer unit 12 is provided, the formation of the leakage current path 360 is suppressed in the light source device 4 that drives the light-emitting chip 10 on the low side, thereby suppressing erroneous lighting.

[0176] As described above, the reference potential terminal 340 described in the first and second embodiments and the reference potential terminal 341 described in the third embodiment may be set to a potential other than the ground potential GND (0 V).

[0177] In the above first to fourth embodiments, the transfer unit 12 has been described as an example of a drive unit. In the transfer units 12 shown in FIGS. 2, 7, and 8, a coupling diode D is used. In the transfer unit 12 shown in FIG. 8, a coupling transistor Q is used. These coupling elements are not limited to the coupling diode D and the coupling transistor Q, and other elements such as resistors and thyristors may also be used. Although the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S are directly connected, a configuration in which the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S are connected via a diode, a resistor, or the like may also be used.

[0178] In the above-described first to fourth embodiments, the transfer unit 12 that shifts the ON state of the transfer elements in the arranged order is used as an example of a drive unit, but the drive unit does not have to shift the ON state in the arranged order. The drive unit may be one that individually specifies the light-emitting elements to be controlled to light up.

[0179] By providing a separation section that prevents the driver section from extending to the periphery of the light-emitting chip, the substrate potential Vsub supplied to the light-emitting element can be made different from the reference potential Vst of the driver section provided on the structure equivalent to the light-emitting element. The separation section is effective when configuring circuits that use different reference potentials on a single semiconductor substrate.

[0180] (Note) (((1))) A light emitting device comprising: a substrate; a plurality of light emitting elements provided on the substrate; a plurality of thyristors that cause each of the light emitting elements to emit light or increase the amount of light emitted by the light emitting elements when turned on; a drive unit that is provided on the substrate and drives the plurality of thyristors individually to transition them to an on state; and a reference potential terminal that supplies a predetermined reference potential to the drive unit, wherein an area of ​​the drive unit connected to the reference potential terminal is electrically isolated from a side surface of the substrate. (((2))) A light emitting chip comprising: a semiconductor substrate; a plurality of light emitting elements and a plurality of thyristors that are provided on a surface side of the substrate and that cause the light emitting elements to emit light or increase the amount of light emitted by the light emitting elements when turned on; a drive unit that is provided on the surface side of the substrate and drives the plurality of thyristors individually to transition them to an on state; a reference potential terminal that supplies a predetermined reference potential to the drive unit; and a separation unit that suppresses the flow of current between the reference potential terminal and the substrate. (((3))) The light-emitting chip according to (((2))), wherein the separating portion prevents the driving portion from being formed to extend to the outer periphery of the substrate. (((4))) The light-emitting chip according to ((2))), wherein the separating portion prevents a current path from being formed between the light-emitting element and the reference potential terminal, passing through a side surface of the substrate. (((5))) The light-emitting chip according to (((2))), wherein the thyristor is stacked on the light-emitting element provided on the substrate, and the driving portion is stacked on a structure equivalent to the light-emitting element, provided on the substrate. (((6))) The light-emitting chip according to (((5))), wherein the light-emitting element, the thyristor, and the driving portion are formed by a semiconductor laminate in which a plurality of semiconductor layers of different conductivity types are stacked, and the separating portion is a groove provided in the semiconductor laminate and / or a region in which insulating ions are implanted into the semiconductor laminate.(((7))) The light-emitting chip according to ((6))), wherein the light-emitting element and the structure have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, and the groove or the region into which the insulating ions are implanted extends from the surface side of the substrate to at least the side of the p-type semiconductor layer and the n-type semiconductor layer constituting the diode structure, which is far from the substrate side. (((8))) The light-emitting chip according to ((6))) or (((7))), wherein the light-emitting element has a current confinement layer which is a region through which current does not easily flow due to oxidation, and the depth of the groove reaches the current confinement layer. ((9))) The light-emitting chip according to (((5))), wherein the reference potential is applied to the side of the diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode of the structure are stacked, which is far from the substrate. (((10))) The light-emitting chip according to (((6))), wherein the groove and / or the region into which insulating ions have been implanted is provided so as to surround the drive unit. (((11))) The light-emitting chip according to ((2))), wherein the drive unit sequentially transitions the on states of the plurality of thyristors. (((12))) A light-emitting chip comprising: a semiconductor substrate; a plurality of light-emitting elements provided on a surface side of the substrate; a plurality of thyristors stacked on the light-emitting elements and causing the light-emitting elements to emit light or increasing the amount of light emitted by the light-emitting elements when turned on; a reference potential terminal provided on a structure equivalent to the light-emitting elements and supplied with a predetermined reference potential; and a separation section that prevents a current path from being formed between the reference potential terminal and the light-emitting elements via a side surface of the substrate. (((13))) A light emitting device comprising: a light emitting chip according to any one of (((2))) to (((12))); and a driver having one end set to ground potential and the other end connected to the substrate of the light emitting chip, and transitioning to an on state at a predetermined timing to pass a current for light emission to the light emitting element. (((14))) A measurement device comprising: the light emitting device according to (((13))); and an acquisition unit that acquires information about an object based on light from the light emitting device reflected by the object.

[0181] The light-emitting device according to (((1))) and the light-emitting chips according to (((2))) and (((12))) can suppress erroneous lighting compared to a configuration in which leakage current from the light-emitting element can flow to the reference potential terminal of the drive unit. The light-emitting chip according to ((3))) is less susceptible to damage caused by dicing of the side surface of the light-emitting chip compared to a configuration in which the drive unit extends to the outer periphery of the substrate. The light-emitting chip according to ((4))) tolerates damage caused by dicing. The light-emitting chip according to ((5))) allows light-emitting elements of the light-emitting chip to be arranged at a higher density compared to a configuration in which thyristors are not stacked on the light-emitting elements. The light-emitting chip according to ((6))) can electrically isolate the drive unit from the dicing surface. The light-emitting chip according to ((7))) can enhance the effect of electrically isolating the drive unit from the dicing surface. The light-emitting chip according to ((8))) allows the isolation portion to be formed in the same process as the formation of the current blocking portion. According to the light-emitting chip of (((9))), electrical isolation is achieved by the pn junction. According to the light-emitting chip of (((10))), the reference potential and the substrate potential can be isolated more reliably than when the driving unit is not surrounded. According to the light-emitting chip of (((11))), lighting control of the light-emitting element is easier than when the on-state is not transitioned sequentially. According to the light-emitting device of (((13))), the light-emitting element can be operated at a higher speed than with high-side driving. According to the measuring device of (((14))), a measuring device capable of three-dimensional measurement is provided.

[0182] This application is based on a Japanese patent application filed on January 24, 2024 (Patent Application No. 2024-009051) and a Japanese patent application filed on December 23, 2024 (Patent Application No. 2024-226415).

Claims

1. A light-emitting device comprising: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driver provided on the substrate that drives the plurality of thyristors individually to transition them to the on state; and a reference potential terminal that supplies a predetermined reference potential to the driver, wherein an area of the driver connected to the reference potential terminal is electrically isolated from a side surface of the substrate.

2. A light-emitting chip comprising: a semiconductor substrate; a plurality of light-emitting elements provided on the surface side of the substrate; and a plurality of thyristors that cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements when turned on; a drive unit provided on the surface side of the substrate that individually drives the plurality of thyristors to transition them to the on state; a reference potential terminal that supplies a predetermined reference potential to the drive unit; and a separation unit that suppresses the flow of current between the reference potential terminal and the substrate.

3. The light-emitting chip according to claim 2, wherein the separating portion prevents the driving portion from extending to the outer periphery of the substrate.

4. The light-emitting chip according to claim 2, wherein the separating portion prevents a current path from being formed between the light-emitting element and the reference potential terminal through the side surface of the substrate.

5. The light-emitting chip according to claim 2, wherein the thyristor is stacked on the light-emitting element provided on the substrate, and the driving unit is stacked on a structure equivalent to the light-emitting element provided on the substrate.

6. The light-emitting chip according to claim 5, wherein the light-emitting element, the thyristor, and the driving unit are composed of a semiconductor laminate in which multiple semiconductor layers of different conductivity types are stacked, and the separation unit is a groove provided in the semiconductor laminate or a region in which insulating ions are implanted into the semiconductor laminate.

7. The light-emitting chip according to claim 6, wherein the light-emitting element and the structure have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, and the groove or the region into which the insulating ions are injected extends from the surface side of the substrate to at least the side of the p-type semiconductor layer and n-type semiconductor layer constituting the diode structure that is farthest from the substrate side.

8. The light-emitting chip according to claim 6 or 7, wherein the light-emitting element has a current confinement layer, which is a region that is oxidized to make it difficult for current to flow, and the depth of the groove is deep enough to reach the current confinement layer.

9. The light-emitting chip described in claim 5, wherein the reference potential is applied to the side of a diode structure farther from the substrate, in which a p-type semiconductor layer serving as the anode of the structure and an n-type semiconductor layer serving as the cathode are stacked.

10. The light-emitting chip according to claim 6, wherein the groove and / or the region into which insulating ions are implanted is provided so as to surround the driving section.

11. The light-emitting chip according to claim 2, wherein the driving unit sequentially shifts the ON states of the plurality of thyristors.

12. A light-emitting chip comprising: a semiconductor substrate; a plurality of light-emitting elements provided on the surface side of the substrate; a plurality of thyristors stacked on the light-emitting elements and turning on to cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a reference potential terminal provided on a structure equivalent to the light-emitting elements and to which a predetermined reference potential is supplied; and a separation section that prevents a current path from being formed between the reference potential terminal and the light-emitting elements that passes through the side of the substrate.

13. A light-emitting device comprising: a light-emitting chip according to any one of claims 2 to 12; and a driver having one end set to ground potential and the other end connected to the substrate of said light-emitting chip, which transitions to an ON state at a predetermined timing to pass a current for light emission to said light-emitting element.

14. A measuring device comprising: the light emitting device according to claim 13; and an acquisition unit that acquires information about an object based on light emitted from the light emitting device and reflected by the object.

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