Circuit board and semiconductor package comprising same

Abstract

According to an embodiment, the circuit board may comprise: an insulating layer including a through hole penetrating the upper surface and lower surface thereof; a wiring layer disposed on the upper surface of the insulating layer; and a via electrode extending from the wiring layer so as to be disposed inside the through hole of the insulating layer and to overlap the insulating layer in the horizontal direction. The via electrode may include a first via region having a width decreasing from the upper surface of the insulating layer toward the lower surface of the insulating layer, and a second via region connected to the first via region and having a width decreasing from the upper surface of the insulating layer toward the lower surface of the insulating layer. The height of the first via region may be different from the height of the second via region.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005]

[0006] Meanwhile, in a circuit board, the via electrode has a slope in which the width gradually increases or decreases along the vertical direction, and this sloped structure of the via electrode causes an increase in stress according to the heat cycle, which may cause cracks to occur.

[0007] Accordingly, conventional technologies have attempted to utilize vertical via electrode structures to improve stress-resistance. However, vertical via electrodes suffer from a problem in that, due to poor plating processability, the via hole may not be completely filled with conductive material during the plating process, resulting in voids occurring within the via hole.

[0008] One of the technical challenges of the present invention is to provide a circuit board and a semiconductor package including the same that can maintain rigidity against stress within a via hole, while having excellent plating processability within the via hole and solving the problem of voids occurring within the via hole.

[0009] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0010] A circuit board according to an embodiment may include an insulating layer including a through hole penetrating an upper surface and a lower surface, a wiring layer disposed on an upper surface of the insulating layer, and a via electrode extending from the wiring layer and disposed inside the through hole of the insulating layer and overlapping the insulating layer in a horizontal direction.

[0011] The above via electrode may include a first via region whose width decreases from the upper surface to the lower surface of the insulating layer, and a second via region connected to the first via region and whose width decreases from the upper surface to the lower surface.

[0012] The height of the first via area may be different from the height of the second via area.

[0013] The height of the first via region may be smaller than the height of the second via region.

[0014] The first slope angle of the first via region may be different from the second slope angle of the second via region.

[0015] The first slope angle of the first via region may be smaller than the second slope angle of the second via region.

[0016] The second slope angle of the second via region may be closer to vertical than the first slope angle of the first via region.

[0017] The first via region has a via extension that extends horizontally and does not vertically overlap with the second via region, and a horizontal extension width of the via extension may be different from a thickness of the insulating layer.

[0018] The horizontal extension width of the above via extension may be smaller than the thickness of the above insulating layer.

[0019] The extension width of the above via extension may be in the range of 20% to 80% of the thickness of the first insulating layer.

[0020] The height of the first via region may be smaller than the thickness of the first insulating layer.

[0021] The extension width of the above via extension may be thinner than the thickness of the wiring layer.

[0022] A semiconductor package according to an embodiment may include any one of the circuit boards described above.

[0023] According to a circuit board and a semiconductor package including the same according to an embodiment, while maintaining rigidity against stress within a via hole, the plating process within the via hole is excellent, and the physical reliability and electrical reliability of the via electrode can be improved.

[0024] For example, according to an embodiment, since the via hole has a double slope, the processability of the plating process performed after forming the through hole can be improved, thereby solving the problem of voids occurring inside the via hole, and the physical reliability and electrical reliability of the via electrode can be improved by improving the rigidity of the via electrode against stress.

[0025] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0026] Fig. 1 is a cross-sectional view of a circuit board (200) according to an embodiment.

[0027] FIG. 2 is a detailed view of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 1.

[0028] FIGS. 3A to 3C are detailed drawings of a second area (A2) among the first areas (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2.

[0029] FIG. 4 is an electron microscope photograph of an area corresponding to a first area (A1) of a circuit board (200) according to an embodiment.

[0030] Fig. 5 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0031] Fig. 6 is a drawing showing a semiconductor package according to the second embodiment.

[0032] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0033] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0034] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0035] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0036] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0037] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0038] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0039] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0040] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0041] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0042] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0043] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0044]

[0045] (Example)

[0046] Hereinafter, a circuit board and a semiconductor package according to an embodiment will be specifically described. Here, a circuit board may refer to a board before electronic components are mounted. In addition, a circuit board may refer to an auxiliary board (e.g., an interposer) connected to another board on which electronic components are mounted. In addition, a semiconductor package may refer to a package in which electronic components are mounted on a circuit board. In this case, the product group to which the circuit board of the embodiment is applied may include, but is not limited to, FC-BGA (Flip Chip-Ball Grid Array) or FC-CSP (Flip Chip-Chip Scale Package).

[0047]

[0048] Fig. 1 is a cross-sectional view of a circuit board (200) according to an embodiment.

[0049] Referring to FIG. 1, the circuit board (200) of the embodiment includes a build-up insulator (210), a build-up wiring body (250), and a protective layer (280). The build-up structure may be referred to as a build-up structure including the build-up insulator (210), the build-up wiring body (250), and the protective layer (280), but is not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components, a main board, etc. The main features of each component will be described below.

[0050] First, the build-up insulator (210) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies. For example, the build-up insulator (210) may include, but is not limited to, a first insulating layer (211), a second insulating layer (212), and a third insulating layer (213).

[0051] Additionally, one of the insulating layers of the build-up insulator (210) may be a core layer. For example, the first insulating layer (211) located at the center of the build-up insulator (210) may be a core layer, but is not limited thereto.

[0052] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and enhance its reliability.

[0053] The core layer may include a reinforcing member, such as glass fiber, extending horizontally and a resin covering the reinforcing member, and the mechanical strength may be adjusted depending on the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer.

[0054] According to another embodiment, the core layer may be formed of glass. When formed of glass, the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. Furthermore, the core layer may have the advantage of being able to thin the circuit board due to its higher mechanical rigidity than a resin containing glass fiber. The core layer may be freely selected and used with any material that can secure mechanical rigidity, without being limited to the above-described materials, taking into consideration yield, price, etc.

[0055] In addition, the build-up insulator (210) may include an upper build-up insulator disposed on the upper surface of the core layer and a lower build-up insulator disposed on the lower surface of the core layer. For example, the build-up insulator (210) may include a first insulating layer (211) which is the core layer, a second insulating layer (212) which is the upper build-up insulator disposed on the upper surface of the core layer, and a third insulating layer (213) which is the lower build-up insulator disposed on the lower surface of the core layer.

[0056] The upper build-up insulator and the lower build-up insulator each have a function to place a wiring layer or via electrode of the build-up wiring body, secure insulation between circuits, and control impedance or insertion loss by the circuit. Considering the dielectric constant, mechanical rigidity, and fairness, the insulating layer of the build-up insulator (210) includes an insulating layer including at least one of a thermosetting resin, a photocurable resin, and an optically isotropic film.

[0057] For example, the insulating layer of the build-up insulator (210) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0058] Also, for example, the insulating layer of the build-up insulator (210) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0059] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0060] Additionally, the insulating layer of the build-up insulator (210) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0061] Additionally, the insulation layer of the build-up insulator (210) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0062]

[0063] Next, the build-up wiring body (250) of the circuit board (200) includes a wiring layer (250w) arranged on the surface of each insulating layer and a via electrode (250v) for vertically connecting each wiring layer (250w). The wiring layer (250w) may be referred to as a circuit pattern layer, a metal wiring, or a wiring portion. The via electrode (250v) may be referred to as a through-hole electrode, a via, or a via portion.

[0064] The via electrode (250v) includes first to third via electrodes (251v, 252v, 253v) formed in through holes penetrating the first to third insulating layers (211, 212, 213), respectively. The via electrode (250v) can electrically connect between wiring layers (250w) arranged on different layers.

[0065] Through-holes can be formed by any of the following methods: mechanical processing, laser processing, or chemical processing. When formed mechanically, methods such as milling, drilling, and routing can be used. When formed by laser processing, UV or CO2 lasers can be used. Chemical processing can utilize chemicals such as aminosilanes and ketones.

[0066] The via electrode (250v) can be formed by forming a through hole penetrating the first insulating layer (211), the second insulating layer (212), and the third insulating layer (213), and filling the inside of the formed through hole with a conductive material. Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the first via electrode (251v), the second via electrode (252v), and the third via electrode (253v). The metal material forming the via electrode (250v) can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). Additionally, the conductive material filling can be accomplished by using one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0067]

[0068] Next, the embodiment includes a wiring layer (250w) electrically connected to a via electrode (250v). For example, the wiring layer (250w) includes a first wiring layer (251w) disposed on a first insulating layer (211), a second wiring layer (252w) disposed on a second insulating layer (212), a third wiring layer (253w) disposed under the first insulating layer (211), and a fourth wiring layer (254w) disposed under the third insulating layer (213).

[0069] The wiring layer (250w) includes pads and / or traces (or connection patterns) for connecting to via electrodes (250v) and / or semiconductor devices and / or capacitors. The traces may be long signal wiring lines connecting between multiple pads.

[0070] At this time, the pad of the wiring layer (250w) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that makes contact with a via electrode and may include a side extension portion for alignment margin.

[0071] The wiring layer (250w) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the wiring layer (250w) may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. The wiring layer (250w) may be formed by a method such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for a circuit board.

[0072]

[0073] Next, the circuit board according to the embodiment includes a protective layer (280) disposed on a wiring layer (250w) of the uppermost or lowermost insulating layer. For example, the protective layer (280) may include a first protective layer (281) disposed on a second wiring layer (252w) and a second protective layer (282) disposed under a fourth wiring layer (254w).

[0074] The protective layer (280) can prevent problems such as oxidation or peeling of the build-up structure due to moisture penetration, etc. In addition, the protective layer can be formed of a material with low wettability to solder to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing the problem of bridging and short circuits between adjacent solders.

[0075] The protective layer (280) includes an insulating material, and the protective layer (280) includes various materials that can be applied and then cured by heating to protect the surfaces of the insulating layers and the surfaces of the wiring layers. For example, the protective layer (280) may be a resist layer, and more specifically, the protective layer (280) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (280) includes an epoxy acrylate series resin. More specifically, the protective layer (280) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the protective layer (280) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0076]

[0077] Next, FIG. 2 is a detailed view of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 1, and FIGS. 3a to 3c are detailed views of a second area (A2) of the first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2.

[0078] FIG. 4 is an electron microscope photograph of an area corresponding to a first area (A1) of a circuit board (200) according to an embodiment.

[0079] As described above, one of the technical challenges of the embodiment is to provide a circuit board and a semiconductor package including the same that can maintain rigidity against stress within a via hole, have excellent plating processability within the via hole, and solve the problem of voids occurring within the via hole.

[0080] The technical features of a circuit board (200) according to an embodiment for solving the technical problems of the following embodiments will be described in detail with reference to FIGS. 2 to 4.

[0081] The circuit board (200) of the embodiment includes an insulating layer including a through hole penetrating the upper surface and the lower surface, a wiring layer disposed on the upper surface of the insulating layer, and a via electrode extending from the wiring layer and disposed inside the through hole of the insulating layer and overlapping the insulating layer in a horizontal direction.

[0082] For example, referring to FIGS. 2 and 3A, the circuit board (200) of the embodiment includes a first insulating layer (211) including a first through hole (VH1) penetrating the upper surface and the lower surface, a first wiring layer (251w) disposed on the upper surface of the first insulating layer (211), and a first via electrode (251v) extending from the first wiring layer (251w) and disposed inside the first through hole (VH1) of the first insulating layer (211) and overlapping the first insulating layer (211) in a horizontal direction.

[0083] The first via electrode (251v) includes a first via region (251v1) whose width decreases from the upper surface to the lower surface of the first insulating layer (211) and a second via region (251v2) whose width decreases from the upper surface to the lower surface and is connected to the first via region (251v1). The point where the first wiring layer (251w) and the first via region (251v1) meet may be referred to as a first node (n1), and the point where the first via region (251v1) and the second via region (251v2) meet may be referred to as a second node (n2) (see FIG. 3a).

[0084] Hereinafter, a process for forming a first via electrode (251v) will be described with reference to FIGS. 3A and 4. In the embodiment, when forming a first through-hole (VH1) by controlling CO2 Laser drilling conditions for a first insulating layer (211) in a circuit board manufacturing process, a first via electrode (251v) can be formed by a plating process or the like after forming a taper at the top of the first through-hole (VH1) as shown in the upper image of the first through-hole (VH1) (see FIG. 4). Through this, the first via electrode (251v) includes a first via region (251v1) whose width decreases from the upper surface to the lower surface of the first insulating layer (211) and a second via region (251v2) whose width decreases from the upper surface to the lower surface while being connected to the first via region (251v1).

[0085] For example, according to an embodiment, when CO2 laser drilling is performed while a protective layer (not shown) is provided on the first insulating layer (211), the laser energy absorption characteristics of the protective layer and the first insulating layer (211) can be utilized to form a first through hole (VH1) having a two-stage inclination angle, for example, a first inclination angle (θ1) and a second inclination angle (θ2). Afterwards, a first via electrode (251v) including a first via region (251v1) whose width decreases from the upper surface to the lower surface of the first insulating layer (211) and a second via region (251v2) connected to the first via region (251v1) and whose width decreases from the upper surface to the lower surface can be formed through a plating process or the like.

[0086] According to a circuit board and a semiconductor package including the same according to an embodiment, while maintaining rigidity against stress within a via hole, the plating process within the via hole is excellent, and the physical reliability and electrical reliability of the via electrode can be improved.

[0087] For example, according to an embodiment, since the via hole has a double slope, the processability of the plating process performed after forming the through hole can be improved, thereby solving the problem of voids occurring inside the via hole, and the physical reliability and electrical reliability of the via electrode can be improved by improving the rigidity of the via electrode against stress.

[0088]

[0089] Continuing with reference to FIGS. 3A and 4, the first height (H1) of the first via region (251v1) of the first via electrode (251v) and the second height (H2) of the second via region (251v2) may be different. The first height (H1) of the first via region (251v1) may be the distance between horizontal lines passing through the first node (n1) and the second node (n2), respectively. The second height (H2) of the second via region (251v2) may be the distance between the bottom surface of the first insulating layer (211) and the horizontal lines passing through the second node (n2), respectively.

[0090] For example, the first height (H1) of the first via area (251v1) may be smaller than the second height (H2) of the second via area (251v2), thereby maintaining rigidity against stress within the via hole, while improving the plating processability within the via hole and improving the physical reliability and electrical reliability of the via electrode.

[0091] For example, the first height (H1) of the first via region (251v1) may be in a range of about 10% to about 30% of the second height (H2) of the second via region (251v2). When the first height (H1) of the first via region (251v1) is less than 10% of the second height (H2) of the second via region (251v2), the distribution of the inclined region of the first via region (251v1) is low, which may deteriorate the plating processability and thus voids may be formed in the via electrode. When it exceeds 30%, the distribution of the inclined region is too high, which may excessively increase the area through which stress is transmitted, and thus the effect of improving the rigidity may be low.

[0092]

[0093] Next, referring to FIG. 3b and FIG. 4 together, the first via electrode (251v) includes a first via region (251v1) having a width that decreases from the upper surface to the lower surface of the first insulating layer (211) and having a first inclination angle (θ1), and a second via region (251v2) connected to the first via region (251v1) and having a second inclination angle (θ2) different from the first inclination angle (θ1).

[0094] The first slope angle (θ1) of the first via area (251v1) may be the slope angle between a horizontal line passing through the second node (n2) and a straight line connecting the second node (n2) and the first node (n1). The second slope angle (θ2) of the second via area (251v2) may be the slope angle between a horizontal line passing through the bottom surface of the first insulating layer (211) and a straight line passing through the lower end edge of the second via area (251v2) and the second node (n2).

[0095] For example, the first inclination angle (θ1) of the first via area (251v1) may be smaller than the second inclination angle (θ2) of the second via area (251v2), thereby maintaining rigidity against stress within the via hole, while improving the plating processability within the via hole and improving the physical reliability and electrical reliability of the via electrode.

[0096] For example, the second slope angle (θ2) of the second via area (251v2) may be closer to vertical than the first slope angle (θ1) of the first via area (251v1). For example, the first slope angle (θ1) of the first via area (251v1) may be in a range of about 20% to about 50% of the second slope angle (θ2) of the second via area (251v2). When the first slope angle (θ1) of the first via area (251v1) is less than 20% of the second slope angle (θ2) of the second via area (251v2), the distribution of vertical via areas may increase, which may lower the plating processability, and when it exceeds 50%, the distribution of slope areas may increase, which may increase stress, which may lower the rigidity.

[0097]

[0098] Next, referring to FIG. 3c and FIG. 4 together, the first via region (251v1) has a via extension (VP) that extends horizontally and does not vertically overlap with the second via region (251v2), and the extension width (PW) of the via extension (VP) may be different from the thickness (T) of the first insulating layer (211). For example, the extension width (PW) of the via extension (VP) may be smaller than the thickness (T) of the first insulating layer (211), thereby maintaining rigidity against stress within the via hole while improving the plating processability within the via hole and improving the physical reliability and electrical reliability of the via electrode.

[0099] For example, the extension width (PW) of the via extension (VP) may range from about 20% to 80% of the thickness (T) of the first insulating layer (211). If the extension width (PW) of the via extension (VP) is less than 20% of the thickness (T) of the first insulating layer (211), the distribution of the inclined region may be low, which may deteriorate the plating processability and thus may result in voids being formed in the via electrode. On the other hand, if it exceeds 80%, the distribution of the inclined region may be too high, which may excessively increase the area through which stress is transmitted, thereby reducing the effect of improving the rigidity.

[0100]

[0101] According to a circuit board and a semiconductor package including the same according to an embodiment, while maintaining rigidity against stress within a via hole, the plating process within the via hole is excellent, and the physical reliability and electrical reliability of the via electrode can be improved.

[0102] For example, according to an embodiment, since the via hole has a double slope, the processability of the plating process performed after forming the through hole can be improved, thereby solving the problem of voids occurring inside the via hole, and the physical reliability and electrical reliability of the via electrode can be improved by improving the rigidity of the via electrode against stress.

[0103]

[0104] Next, a semiconductor package including a circuit board according to an embodiment will be described.

[0105] FIG. 5 is a cross-sectional view showing a semiconductor package according to the first embodiment, and the semiconductor package may include the circuit board (200) of FIG. 1.

[0106] Referring to FIG. 5, the semiconductor package includes a first connection portion (291) and may also include a chip (310) or element (310) disposed on the first connection portion (291).

[0107] Specifically, the second wiring layer (252w) arranged on the uppermost side of the circuit board includes a pad. The pad of the second wiring layer (252w) vertically overlaps with an opening of the first protective layer (281). The first connection portion (291) is arranged on the pad of the second wiring layer (252w) that vertically overlaps with the opening of the first protective layer (281).

[0108] The first connecting portion (291) may have a spherical shape. For example, the cross-section of the first connecting portion (291) may have a circular shape or a semicircular shape. The first connecting portion (291) may be a solder ball, but is not limited thereto.

[0109] The semiconductor package may include a chip (310) or a device (310) disposed on the first connection portion (291). The chip (310) may be a processor chip. For example, the chip (310) may be an application processor (AP) chip of any one of a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0110] At this time, the bottom of the chip (310) may include a terminal (320), and the terminal (320) may be electrically connected to the second wiring layer (252w) of the circuit board through the first connection portion (291).

[0111] Meanwhile, the semiconductor package of the first embodiment may include a plurality of chips arranged and spaced apart from each other in the horizontal direction on a single circuit board. For example, the chip (310) may include a first chip and a second chip that are spaced apart from each other. The first chip and the second chip may be different types of application processor (AP) chips.

[0112] Meanwhile, the semiconductor package may include a second connection portion (292). The second connection portion (292) may be disposed on a lower surface of the fourth wiring layer (254w). For example, the fourth wiring layer (254w) includes at least one pad. And, the pad of the fourth wiring layer (254w) may vertically overlap with an opening of the second protection layer (282). And, the second connection portion (292) may be disposed under the pad of the fourth wiring layer (254w) that vertically overlaps with the opening of the second protection layer (282). The second connection portion (292) may be a solder ball, but is not limited thereto. The second connection portion (292) may be for connecting the semiconductor package and a main board (or motherboard) of an external device.

[0113]

[0114] Next, FIG. 6 is a drawing showing a semiconductor package according to the second embodiment.

[0115] Referring to FIG. 6, the semiconductor package according to the second embodiment further includes an external substrate (410) attached on the semiconductor package of FIG. 5. The external substrate (410) may be an interposer, but is not limited thereto.

[0116] The external substrate (410) includes a plurality of insulating layers (not shown). The external substrate (410) includes a circuit layer (450) disposed on the plurality of insulating layers. The external substrate (410) may be a substrate connecting a semiconductor package on which an AP chip is disposed and a semiconductor package on which a memory chip is disposed. To this end, the circuit layer of the external substrate (410) may be designed to correspond to the terminal specifications of the AP chip and the terminal specifications of the memory chip. Specifically, the width or pitch of the circuit layer of the circuit board on which the AP chip is disposed may be different from the width or pitch of the circuit layer of the circuit board on which the memory chip is disposed. Accordingly, the external substrate (410) may be disposed between a plurality of circuit boards having the same difference in width or pitch as that to electrically connect them therebetween.

[0117] For this purpose, the semiconductor package further includes a third connection portion (293).

[0118] The third connection portion (293) may be disposed on the second wiring layer (252w). Specifically, the second wiring layer (252w) may include a first pad on which the chip (310) is disposed, and a second pad connected to the external substrate (410). In addition, the third connection portion (293) may be disposed on the second pad. At this time, the uppermost portion of the third connection portion (293) may be positioned higher than the upper end of the chip (310). Through this, the embodiment can prevent the chip (310) from being damaged when coupled with the external substrate (410).

[0119] Additionally, the semiconductor package may include a first molding layer (270). The first molding layer (270) may mold the first connection portion (291), the chip (310), and the third connection portion (293). Meanwhile, although not illustrated in FIG. 6, a memory substrate (not illustrated) may be placed on the external substrate (410).

[0120]

[0121] An electronic device including a semiconductor package of the embodiment will be described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to the semiconductor package of the embodiment. Various components may be mounted on the semiconductor package.

[0122] For example, a semiconductor package may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

[0123] For example, a semiconductor package may contain at least one of various types of passive and active components.

[0124] At this time, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited to this, and it is obvious that the electronic device may be any other electronic device that processes data.

[0125] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integrity or technical interoperability with each other.

[0126] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0127]

[0128] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0129] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. An insulating layer including a through hole penetrating the upper and lower surfaces; A wiring layer disposed on the upper surface of the insulating layer; and It includes a via electrode extending from the above wiring layer, positioned inside the through hole of the above insulating layer, and overlapping the above insulating layer in a horizontal direction, The above via electrode is, A first via region having a width that decreases from the upper surface of the insulating layer toward the lower surface, and a second via region connected to the first via region and having a width that decreases from the upper surface toward the lower surface, The height of the first via area is different from the height of the second via area, A circuit board, wherein the first slope angle of the first via region is different from the second slope angle of the second via region.

2. In paragraph 1, A circuit board, wherein the height of the first via area is smaller than the height of the second via area.

3. In paragraph 1, The first slope angle of the above first via area is A circuit board having a second slope angle smaller than that of the second via area.

4. In paragraph 1, A circuit board wherein the second slope angle of the second via area is closer to vertical than the first slope angle of the first via area.

5. In paragraph 1, The above first via area is, It has a via extension that extends horizontally and does not vertically overlap with the second via area, A circuit board in which the horizontal extension width of the above via extension is different from the thickness of the above insulating layer.

6. In paragraph 5, A circuit board wherein the horizontal extension width of the above via extension is smaller than the thickness of the above insulating layer.

7. In paragraph 6, A circuit board, wherein the extension width of the above via extension is in the range of 20% to 80% of the thickness of the first insulating layer.

8. In paragraph 6, A circuit board, wherein the height of the first via region is smaller than the thickness of the first insulating layer.

9. In paragraph 6, A circuit board in which the extension width of the above via extension is thinner than the thickness of the wiring layer.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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