Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment of the present invention comprises: an insulating layer including a reinforcing member; and an electronic element disposed on or under the insulating layer, wherein the electronic element can be vertically spaced a first separation distance (D1) of 2 μm or greater apart from the reinforcing member of the insulating layer.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005]

[0006] Recently, research is being conducted on technologies that embed electronic components that consume, store, and release power supplied to the motherboard of electronic devices into package substrates. For example, various passive components such as capacitors, inductors, and resistors are required to operate active components such as memory, APs, or RF semiconductors. Furthermore, package substrate technologies that embed electronic components such as DTCs (Deep Trench Capacitors) to achieve high capacity and high performance due to the high integration and multi-functionality of semiconductor packages are in demand.

[0007] Meanwhile, in order to minimize the form factor of the package substrate, a substrate technology is required in which thin electronic components are embedded in a thin core substrate. However, there is a limit to the technology for embedding electronic components such as DTC in a thin substrate in the core substrate that can currently be embedded.

[0008] In particular, when embedding electronic components in a substrate, there is a problem of reduced reliability when the glass fabric provided in the insulating layer of the substrate comes into contact with the electronic components, so there is a technical problem that makes it difficult to reliably embed electronic components in the substrate.

[0009] One of the technical challenges of the embodiment is to solve the problem of reduced reliability of glass fabric provided in the insulating layer of the substrate when the electronic device is embedded in the substrate and comes into contact with the electronic device.

[0010] For example, when glass fibers and electronic components come into contact, migration defects may occur, which may reduce electrical reliability, and delamination may occur, which may reduce structural reliability.

[0011] A circuit board according to an embodiment includes an insulating layer having a reinforcing member and an electronic element disposed on or under the insulating layer, wherein the electronic element can be vertically spaced apart from the reinforcing member of the insulating layer by a first separation distance (D1) of 2 μm or more.

[0012] Electronic components may be arranged on a core layer having a cavity.

[0013] The electronic element may be spaced apart from the second reinforcing member provided in the core layer by a second distance that is greater than the first distance horizontally.

[0014] The core layer may include a first insulating layer that fills a cavity in which electronic components are placed.

[0015] The resin of the first insulating layer filling the cavity may include the same material as the resin of the insulating layer.

[0016] The reinforcing member of the insulating layer may be spaced vertically from the electronic element by 3㎛ or more.

[0017] The reinforcing member of the insulating layer may be spaced vertically from the electronic element by 10㎛ or less.

[0018] The thickness of the above electronic device may be less than or equal to the thickness of the core layer.

[0019] The first separation distance may be in the range of 2 / 100 to 6 / 100 of the thickness of the electronic component.

[0020] A semiconductor package according to an embodiment may include any one circuit board.

[0021] According to the embodiment, there is a technical effect that enables reliably embedding electronic components in a substrate.

[0022] For example, the embodiment can prevent electrical reliability by preventing migration by spacing out a reinforcing member such as glass fiber provided in an insulating layer from an electronic element by 2㎛ or more, thereby preventing contact between the glass fiber and the electronic element, and can improve structural reliability by preventing delamination between layers.

[0023] Figure 1a is a cross-sectional view of a circuit board (100) according to an embodiment.

[0024] FIG. 1b is a first detailed view of a circuit board (100) according to the embodiment illustrated in FIG. 1a.

[0025] FIG. 1c is a second detailed view of a circuit board (100) according to the embodiment illustrated in FIG. 1a.

[0026] FIG. 2a is an enlarged view of a first area (A1) of a circuit board (100) according to the embodiment illustrated in FIG. 1c.

[0027] Figure 2b is an electron microscope photograph corresponding to the first region (A1) of Figure 2a.

[0028] Figures 3a to 3f are cross-sectional views of a manufacturing process of a circuit board (100) according to an embodiment.

[0029] Fig. 4 is a cross-sectional view showing a semiconductor package (200) according to an embodiment.

[0030] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0031] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0032] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0033] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0034] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0035] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0036] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0037] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0038] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0039] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0040] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0041] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0042]

[0043] (Example)

[0044] FIG. 1a is a cross-sectional view of a circuit board (100) according to an embodiment, FIG. 1b is a first detailed view of the circuit board (100) according to the embodiment illustrated in FIG. 1a, and FIG. 1c is a second detailed view of the circuit board (100) according to the embodiment illustrated in FIG. 1a.

[0045]

[0046] Referring to FIG. 1A, a circuit board (100) according to an embodiment includes a core portion (110), a lower build-up structure (120), and an upper build-up structure (130). The core portion (110), the lower build-up structure (120), and the upper build-up structure (130) may be referred to as a 'build-up structure' and may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0047] The core portion (110) includes a core layer (111), a first build-up wiring body (112), and a first insulating layer (113). In addition, the lower build-up structure (120) includes a second insulating layer (121) and a lower build-up wiring body (122), and the upper build-up structure (130) includes a third insulating layer (131) and an upper build-up wiring body (132). The second insulating layer (121) may be referred to as a 'lower build-up insulator', and the third insulating layer (131) may be referred to as an 'upper build-up insulator'.

[0048] In addition, the circuit board (100) according to the embodiment includes an electronic element (170) disposed in at least one of the core portion (110), the lower build-up structure (120), or the upper build-up structure (130). For example, the circuit board (100) according to the embodiment includes an electronic element (170) embedded in the core portion (110), but the embodiment is not limited thereto. The electronic element (170) may be a passive element such as a capacitor, an inductor, or a resistor, but is not limited thereto.

[0049]

[0050] Next, FIG. 1b is a first detailed view of a circuit board (100) according to the embodiment illustrated in FIG. 1a, and specifically, FIG. 1b is a detailed view of a core portion (110) of the circuit board (100) according to the embodiment illustrated in FIG. 1a.

[0051] Referring to FIG. 1b, the core portion (110) includes a core layer (111), a first insulating layer (113), and a first build-up wiring body (112).

[0052] The core layer (111) of the core portion (110) includes a first through hole (not shown) penetrating the upper and lower surfaces and a cavity (111C) (see FIG. 3a). The cavity may be referred to as an opening.

[0053] The core layer (111) may include a reinforcing member such as glass fiber extending in a horizontal direction and a resin covering the reinforcing member, and the mechanical strength may be adjusted according to the density of the reinforcing member. For example, the core layer (111) includes a first reinforcing member (111G1) and a first resin (111R1). The first reinforcing members (111G1) of the core layer (111) may be stacked in multiple layers spaced apart from each other in the vertical direction and provided within the first resin (111R1).

[0054]

[0055] Next, the core portion (110) includes a first build-up wiring body (112) arranged on the core layer (111).

[0056] The first build-up wiring body (112) includes a first via portion (112V) arranged in a through hole of the core layer (111), and a first wiring portion (112W) electrically connected to the first via portion (112V) and arranged above or below the core layer (111). The 'via portion' may be referred to as a through electrode, a via, or a via electrode. The 'wiring portion' may be referred to as a metal wiring, a wiring layer, or a wiring pattern layer.

[0057] The first via (112V) may be any one material selected from conductive metal materials such as copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).

[0058] The first wiring portion (112W) includes a pad or trace (or connection pattern) for connecting to the first via portion (112V) or the electronic component (170). The trace may be a long signal wiring line connecting between a plurality of pads. The first wiring portion (112W) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn).

[0059]

[0060] Next, the core portion (110) includes a first insulating layer (113) that fills a cavity (111C) of the core layer (111) in which an electronic element (170) is arranged. The first insulating layer (113) may be, but is not limited to, a thermosetting material. For example, the first insulating layer (113) may include, but is not limited to, a thermosetting resin. The resin of the first insulating layer (113) may include, but is not limited to, the same material as the resin of the second insulating layer (121) or the third insulating layer (131) adjacent to the first insulating layer (113).

[0061]

[0062] Next, FIG. 1c is a second detailed view of a circuit board (100) according to the embodiment illustrated in FIG. 1b, for example, FIG. 1c is a detailed view of a lower build-up structure (120) and an upper build-up structure (130) of the circuit board (100) according to the embodiment illustrated in FIG. 1b.

[0063] Referring to FIG. 1c, the lower build-up structure (120) includes a second insulating layer (121) and a lower build-up wiring body (122). In addition, the upper build-up structure (130) includes a third insulating layer (131) and an upper build-up wiring body (132). The second insulating layer (121) may be referred to as a 'lower build-up insulator', and the third insulating layer (131) may be referred to as an 'upper build-up insulator'.

[0064]

[0065] First, the second insulating layer (121) and the third insulating layer (131) include a single or multiple laminated insulating layers and provide insulating properties between the built-up wiring bodies. For example, the second insulating layer (121) may include, but is not limited to, a 2-1 insulating layer (121a), a 2-2 insulating layer (121b), and a 2-3 insulating layer (121c). In addition, the third insulating layer (131) may include, but is not limited to, a 3-1 insulating layer (131a), a 3-2 insulating layer (131b), and a 3-2 insulating layer (131b).

[0066] The second insulating layer (121) and the third insulating layer (131) have a function for arranging a wiring section or a via section of a build-up wiring body, and a function for securing insulation between circuits and controlling impedance or insertion loss by the circuit, and include an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0067] For example, at least one of the insulating layers of the second insulating layer (121) and the third insulating layer (131) may include prepreg (PPG), thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board.

[0068] For example, the 2-1 insulating layer (121a) of the 2nd insulating layer (121) or the 3-1 insulating layer (131a) of the 3rd insulating layer (131) may include prepreg (PPG), and may have a structure in which an epoxy resin or the like is impregnated into a glass fiber layer in the form of a fabric sheet, such as a glass fabric.

[0069] In addition, at least one of the insulating layers of the second insulating layer (121) and the third insulating layer (131) may be a thermosetting material, and may include, for example, one or more of Ajinomoto Build-up Film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0070] In addition, at least one of the insulating layers of the second insulating layer (121) and the third insulating layer (131) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0071] In addition, at least one of the insulating layers of the second insulating layer (121) and the third insulating layer (131) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0072]

[0073] Continuing with reference to FIG. 1c, the lower build-up wiring body (122) includes a second via portion (122V) arranged in a through hole of the second insulating layer (121), and a second wiring portion (122W) electrically connected to the second via portion (122V) and arranged on or under the insulating layer of the second insulating layer (121).

[0074] Additionally, the upper build-up wiring body (132) includes a third via portion (132V) arranged in a through hole of the third insulating layer (131), and a third wiring portion (132W) electrically connected to the third via portion (132V) and arranged on or under the insulating layer of the third insulating layer (131).

[0075] For example, the second via portion (122V) of the lower build-up wiring body (122) may include, but is not limited to, a second-first via portion (122Va), a second-second via portion (122Vb), and a second-third via portion (122Vc) which are respectively arranged in the through holes of the second-first insulating layer (121a), the second-second insulating layer (121b), and the second-third insulating layer (121c).

[0076] In addition, the second wiring section (122W) of the lower build-up wiring body (122) is electrically connected to the 2-1 via section (122Va), the 2-2 via section (122Vb), and the 2-3 via section (122Vc), respectively, and includes the 2-1 wiring section (122Wa), the 2-2 wiring section (122Wb), and the 2-3 wiring section (122Wc) which are respectively arranged above or below the 2-1 insulating layer (121a), the 2-2 insulating layer (121b), and the 2-3 insulating layer (121c).

[0077]

[0078] In addition, the third via portion (132V) of the upper build-up wiring body (132) may include, but is not limited to, a third-first via portion (132Va), a third-second via portion (132Vb), and a third-third via portion (132Vc) which are respectively arranged in the through holes of the third-first insulating layer (131a), the third-second insulating layer (131b), and the third-third insulating layer (131c).

[0079] In addition, the third wiring section (132W) of the upper build-up wiring body (132) is electrically connected to the third-first via section (132Va), the third-second via section (132Vb), and the third-third via section (132Vc), respectively, and includes the third-first wiring section (132Wa), the third-second wiring section (132Wb), and the third-third wiring section (132Wc) which are respectively arranged above or below the third-first insulating layer (131a), the third-second insulating layer (131b), and the third-third insulating layer (131c).

[0080]

[0081] The second via portion (122V) and the third via portion (132V) may be any one material selected from among conductive metal materials such as copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).

[0082] In addition, the second wiring portion (122W) and the third wiring portion (132W) each include pads or traces (or connection patterns) for connecting to the second via portion (122V), the third via portion (132V) or the electronic component (170). The traces may be long signal wiring lines connecting between a plurality of pads. The second wiring portion (122W) and the third wiring portion (132W) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn).

[0083]

[0084] Next, FIG. 2a is an enlarged view of a first area (A1) of a circuit board (100) according to the embodiment illustrated in FIG. 1c, and FIG. 2b is an electron microscope photograph corresponding to the first area (A1) of FIG. 2a.

[0085]

[0086] One of the technical challenges of the present invention is to address the issue of reduced reliability when embedded with electronic components within a substrate, due to the glass fabric provided in the substrate's insulating layer coming into contact with the electronic components. For example, contact between the glass fabric and the electronic components can result in migration defects, which can degrade electrical reliability, and delamination, which can degrade structural reliability.

[0087]

[0088] Referring to FIGS. 2a and 2b, a circuit board (100) according to an embodiment for solving a technical problem can prevent contact between glass fiber and electronic elements by spacing a reinforcing member such as glass fiber provided in an insulating layer by 2 μm or more from electronic elements (170), thereby preventing migration and improving electrical reliability, and can prevent delamination and thereby improving structural reliability.

[0089] For example, a circuit board (100) according to an embodiment may include a core layer (111) having a first reinforcing member (111G1) and a cavity (111C) that penetrates the upper and lower surfaces, an electronic element (170) disposed in a portion of the cavity (111C) of the core layer (111), a first insulating layer (113) that fills the cavity (111C) of the core layer (111) in which the electronic element (170) is disposed, and a second insulating layer (121) that includes a second reinforcing member (121G2) and is disposed on the lower surface of the core layer (111).

[0090] The second reinforcing member (121G2) at a position vertically overlapping with the electronic element (170) may be spaced apart from the electronic element (170) by a first separation distance (D1) of 2 μm or more. In addition, the second reinforcing member (121G2) may be spaced apart vertically from the electronic element (170) by 3 μm or more. In addition, the second reinforcing member (121G2) may be spaced apart vertically from the electronic element (170) by 10 μm or less. When the second reinforcing member (121G2) is spaced apart vertically from the electronic element (170) by more than 10 μm, it may be difficult for the second reinforcing member (121G2) to be positioned at the center of the second insulating layer (121), making it difficult to contribute to maintaining strength, which may cause warping of the substrate. In the embodiment, the vertical direction may mean the top (top) or bottom (bottom) of each component, and the horizontal direction may mean a direction perpendicular to the vertical direction.

[0091] In an embodiment, the electronic device (170) may have a device body (170a) and a device pad (170b).

[0092] The thickness (T1) of the electronic element (170) may be less than or equal to the thickness of the core layer (111). For example, the electronic element (170) may have a thin thickness of about 60 μm or less, and the first distance (D1) at which the second reinforcing member (121G2) is spaced apart from the electronic element (170) may be in the range of about 2 / 100 to 6 / 100 of the thickness (T1) of the electronic element (170), but is not limited thereto.

[0093] Additionally, in the embodiment, the cavity side wall of the core layer (111) is spaced apart from the electronic element (170) in the horizontal direction by a second separation distance (D2), and the second separation distance (D2) may be greater than the first separation distance (D1).

[0094] For example, the cavity side wall of the core layer (111) may be spaced apart from the electronic element (170) in the horizontal direction by a second separation distance (D2) of more than about 10 ㎛, but is not limited thereto. In addition, the cavity side wall of the core layer (111) may be spaced apart from the electronic element (170) in the horizontal direction by a second separation distance (D2) of more than about 10 ㎛ and less than about 50 ㎛, but is not limited thereto.

[0095] In an embodiment, when the cavity side wall of the core layer (111) is spaced apart from the electronic element (170) by 10 µm or less in the horizontal direction, the electronic element (170) may come into contact with the first reinforcing member (111G1) such as glass fiber of the core layer when mounting the electronic element (170). On the other hand, in an embodiment, when the cavity side wall of the core layer (111) is spaced apart from the electronic element (170) by more than 50 µm in the horizontal direction, it may be difficult to precisely fill the cavity with resin, which may result in the generation of voids.

[0096]

[0097] Next, the manufacturing process of the circuit board (100) according to the embodiment will be described with reference to FIGS. 3a to 3f.

[0098] Referring to FIG. 3a, a first build-up wiring body (112) is formed on a core layer (111), a cavity (111C) is formed, and then an adhesive layer (210) such as polyimide is adhered, and then an electronic element (170) can be mounted on the adhesive layer (210) of the cavity (111C).

[0099] The electronic device (170) may have a device body (170a) and a device pad (170b), and the device pad (170b) may be mounted on an adhesive layer (210).

[0100] The core layer (111) includes a first reinforcing member (111G1) and a first resin (111R1), and the first reinforcing members (111G1) may be provided in the first resin (111R1) by being stacked in multiple layers spaced apart from each other along the vertical direction.

[0101] The first build-up wiring body (112) includes a first via portion (112V) arranged in a through hole of the core layer (111), and a first wiring portion (112W) electrically connected to the first via portion (112V) and arranged above or below the core layer (111).

[0102] The first via portion (112V) can be formed in the through hole of the core layer (111) by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0103] The first wiring section (112W) can be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0104] The through hole of the core layer (111) can be formed by any one of mechanical processing, laser processing, or chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When the through hole is formed by laser processing, a UV or CO2 laser method can be used, and for chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0105] Next, referring to FIGS. 3b and 3c, a first insulating layer (113) that fills the cavity (111C) can be formed by laminating the lower build-up material layer (120M) and then performing a heating and pressurizing process. In FIG. 3c, the adhesive layer (210) is removed after the first insulating layer (113) is formed.

[0106] The lower build-up material layer (120M) includes a second preliminary insulating layer (121A) and a second-first wiring portion (122Wa). The second preliminary insulating layer (121A) includes a second resin (121R2) and a second reinforcing member (121G2), and a portion of the second resin (121R2) may fill the cavity (111C) of the core layer (111) through a heating and pressurizing process to form a first insulating layer (113). Accordingly, the boundary between the first insulating layer (113) and the second-first insulating layer (121a) within the cavity (111C) of the core layer (111) may be substantially indistinguishable, but is not limited thereto.

[0107] Next, referring to FIG. 3d, after laminating the upper build-up material layer (not shown), a heating and pressurizing process is performed to form the 3-1 insulating layer (131a) and the 3-1 build-up wiring body (132Wa).

[0108] Next, as shown in FIG. 3e, subsequent processes may be performed to sequentially form a lower build-up structure (120) and an upper build-up structure (130), thereby forming a circuit board (100) according to the embodiment.

[0109] Next, as shown in FIG. 3f, a protective layer (140) can be formed on the circuit board (100) according to the embodiment. For example, a first protective layer (141) and a second protective layer (142) can be formed on the lower build-up structure (120) and the upper build-up structure (130), respectively.

[0110] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure due to moisture penetration, etc. The protective layer can be formed of a material with low wettability to solder to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing the problem of bridging and short circuits between adjacent solders.

[0111] The protective layer (140) includes an insulating material, and the protective layer (140) includes various materials that can be applied and then cured by heating to protect the surfaces of the insulating layers and the wiring layer. The protective layer (140) may be a resist layer, and for example, the protective layer (140) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (140) includes an epoxy acrylate series resin. In detail, the protective layer (140) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0112]

[0113] Next, Fig. 4 is a cross-sectional view showing a semiconductor package (200) according to an embodiment.

[0114] Referring to FIG. 4, a semiconductor package (200) according to an embodiment includes a first connection portion (291) and may also include a chip (310) or element (310) placed on the first connection portion (291).

[0115] Specifically, the 3-3 wiring layer (132Wc) positioned on the top of the circuit board includes a pad. The first connection portion (291) is positioned on the pad of the 3-3 wiring layer (132Wc).

[0116] The first connecting portion (291) may have a spherical shape. For example, the cross-section of the first connecting portion (291) may have a circular shape or a semicircular shape. The first connecting portion (291) may be a solder ball, but is not limited thereto.

[0117] The chip (310) may be a processor chip. For example, the chip (310) may be an application processor (AP) chip of any one of a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. At this time, a terminal (320) may be included on the lower surface of the chip (310), and the terminal (320) may be electrically connected to the 3-3 wiring layer (132Wc) of the circuit board through the first connection portion (291).

[0118] Meanwhile, the semiconductor package may include a second connection portion (292). The second connection portion (292) may be disposed on the lower surface of the 2-3 wiring layer (122Wc). For example, the 2-3 wiring layer (122Wc) includes at least one pad. In addition, the second connection portion (292) may be disposed under the pad of the 2-3 wiring layer (122Wc). The second connection portion (292) may be a solder ball, but is not limited thereto. The second connection portion (292) may be for connecting the semiconductor package and a main board (or motherboard) of an external device.

[0119]

[0120] -Electronic devices-

[0121] An electronic device to which the semiconductor package of the embodiment is applied will be described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor elements may be mounted in the semiconductor package.

[0122] Semiconductor devices include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into a single chip. Semiconductor devices may be logic chips, memory chips, etc. Logic chips may be central processors (CPUs), graphics processors (GPUs), etc. For example, logic chips may be application processor (AP) chips that include at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set that includes a specific combination of the above.

[0123] The memory chip may be a stacked memory such as HBM. In addition, the memory chip includes memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0124] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0125] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0126]

[0127] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0128] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0129] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0130] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. An insulating layer having a reinforcing member; and An electronic element disposed on or under the insulating layer; The above electronic components, A circuit board, which is spaced vertically from the reinforcing member of the insulating layer by a first separation distance (D1) of 2㎛ or more.

2. In paragraph 1, A circuit board in which the above electronic components are arranged on a core layer having a cavity.

3. In paragraph 2, The above electronic components, A circuit board, which is horizontally spaced apart from a second reinforcing member provided on the core layer by a second distance greater than the first distance.

4. In paragraph 2, The above core layer is, A circuit board comprising a first insulating layer filling the cavity in which the electronic component is placed.

5. In paragraph 4, A circuit board, wherein the resin of the first insulating layer filling the cavity includes the same material as the resin of the insulating layer.

6. In paragraph 1, A circuit board in which the reinforcing member of the insulating layer is spaced vertically from the electronic element by 3㎛ or more.

7. In paragraph 6, A circuit board in which the reinforcing member of the insulating layer is spaced vertically from the electronic element by 10㎛ or less.

8. In paragraph 2, A circuit board wherein the thickness of the electronic component is less than or equal to the thickness of the core layer.

9. In paragraph 1, A circuit board, wherein the first separation distance is in the range of 2 / 100 to 6 / 100 of the thickness of the electronic element.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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