Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment of the present invention comprises: an insulating layer; a pad disposed on the insulating layer; and a surface treatment layer disposed on the pad, wherein the pad includes a first region overlapping the surface treatment layer and a second region not overlapping the surface treatment layer, and comprises a protective layer disposed on the second region, and the protective layer may be spaced apart from the surface treatment layer.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005] Meanwhile, Fig. 1 is a cross-sectional view showing a portion of a circuit board being internally studied. Referring to Fig. 1, a pad (135) is placed on an insulating layer (115), and a surface treatment layer (150) may be placed on the pad (135). Meanwhile, the surface treatment layer (150) is formed with a uniform surface to minimize electrical resistance, and a connection part such as a solder for connection to an external chip or substrate is placed through an open area (140H) of a protective layer (140).

[0006] However, when a protective layer (140) is placed on a surface treatment layer (150) with low roughness, there is a problem that the adhesive strength of the protective layer (140) is weak and thus lifts off from the surface treatment layer (150), and when the lifting area increases, there is a problem that the protective layer (140) is peeled off. Accordingly, there is a problem that the pad (135) of the circuit board is oxidized or the positional accuracy of the solder is significantly reduced, resulting in a decrease in electrical and structural reliability.

[0007] One of the technical challenges of the embodiment is to prevent lifting and peeling of the protective layer.

[0008] Additionally, one of the technical challenges of the embodiment is to improve the signal transmission speed of the circuit board.

[0009] In addition, one of the technical challenges of the embodiment is to prevent detachment of connecting parts such as solder and to improve positioning accuracy.

[0010] Additionally, one of the technical challenges of the embodiment is to improve the adhesion between the protective layer and the pad.

[0011] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0012] A circuit board according to an embodiment comprises: an insulating layer; a pad disposed on the insulating layer; and

[0013] A surface treatment layer disposed on the pad; wherein the pad includes a first region overlapping the surface treatment layer and a second region not overlapping the surface treatment layer, and includes a protective layer disposed on the second region, wherein the protective layer can be spaced apart from the surface treatment layer.

[0014] Additionally, in an embodiment, the side surface of the protective layer may vertically overlap with the second region.

[0015] Additionally, in the embodiment, the surface treatment layer includes a first surface treatment layer and a second surface treatment layer disposed on the first surface treatment layer, and the second surface treatment layer may include Au.

[0016] Additionally, in the embodiment, the horizontal width of the upper surface of the first region may be the same as the horizontal width of the lower surface of the surface treatment layer.

[0017] Additionally, in an embodiment, the horizontal width of the lower surface of the pad may be greater than the horizontal width of the lower surface of the surface treatment layer.

[0018] Additionally, in the embodiment, the upper surface of the second region may be flat.

[0019] Additionally, in the embodiment, the height of the upper surface of the second region may be lower than the height of the upper surface of the first region.

[0020] Additionally, in the embodiment, the upper surface of the second region may include a concave portion that is concave from the upper surface of the pad to the lower surface.

[0021] Additionally, in the embodiment, the upper surface of the second region may include a slope.

[0022] The circuit board according to the embodiment has a technical effect of preventing lifting and peeling of a protective layer disposed on the outermost layer of the circuit board.

[0023] For example, the embodiment can prevent lifting and peeling of the protective layer by having the protective layer cover the second area of ​​the pad and be spaced apart from the surface treatment layer.

[0024] Additionally, the embodiment has a technical effect that can improve signal transmission speed.

[0025] For example, since the protective layer is disposed spaced apart from the surface treatment layer, the upper surface of the surface treatment layer is not covered by the protective layer, so that the contact area with the connection part increases, and thus the signal transmission speed can be improved.

[0026] Additionally, the embodiment has a technical effect that can improve the adhesion between the protective layer and the pad.

[0027] For example, the embodiment may improve the adhesion between the pad and the protective layer by forming the roughness of the second region of the pad to be greater than the roughness of the first region.

[0028] In addition, for example, the embodiment forms a film through surface treatment in the second open area of ​​the protective layer, and the film is in contact with the protective layer and the pad, thereby improving the fixing strength of the protective layer and the pad.

[0029] In addition, the embodiment has a technical effect capable of preventing detachment of a connecting portion placed on a pad.

[0030] For example, the embodiment may be such that the connecting portion is in contact with not only the upper surface of the second surface treatment layer but also the side surface thereof, and the side surface of the second surface treatment layer may perform an anchor function to prevent detachment of the connecting portion.

[0031] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0032] Figure 1 is a cross-sectional view showing a portion of a circuit board being studied internally.

[0033] Figure 2 is a cross-sectional view of a circuit board (100) according to the first embodiment.

[0034] FIG. 3 is a drawing showing in detail one area (A1) of FIG. 2 according to an embodiment.

[0035] FIG. 4 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to the second embodiment.

[0036] FIG. 5 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to the third embodiment.

[0037] FIG. 6 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to the fourth embodiment.

[0038] Fig. 7 is a drawing of a semiconductor package (101) according to an embodiment.

[0039] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0040] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0041] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0042] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0043] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0044] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0045] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0046] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0047] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0048] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0049] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0050]

[0051] (Example)

[0052] FIG. 2 is a cross-sectional view of a circuit board (100) according to a first embodiment. Referring to FIG. 2, the circuit board (100) according to the embodiment may include a build-up insulating portion (110), a build-up wiring portion (118), and a protective layer (140). The build-up insulating portion (110), the build-up wiring portion (118), and the protective layer (140) may be referred to as a build-up structure, but are not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0053] The build-up insulation (110) includes a single or multiple laminated insulation layers and provides insulation properties between the build-up wiring sections. The build-up insulation (110) may be referred to as a build-up insulator. The build-up insulation (110) may include, but is not limited to, a first insulation layer (111), a second insulation layer (112), and a third insulation layer (113).

[0054] One of the build-up insulation parts (110) may be a core layer. The second insulation layer (112) located at the center of the build-up insulation part (110) may be a core layer, but is not limited thereto.

[0055] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and enhance its reliability.

[0056] The core layer may include a reinforcing member such as glass fiber extending horizontally and a resin covering the reinforcing member, and the mechanical rigidity may be controlled according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0057] The build-up insulation (110) may include an upper build-up insulation disposed on the upper surface of the core layer and a lower build-up insulation disposed on the lower surface of the core layer. For example, the build-up insulation (110) may include a second insulation layer (112) which is the core layer, a first insulation layer (111) which is the upper build-up insulation disposed on the upper surface of the core layer, and a third insulation layer (113) which is the lower build-up insulation disposed on the lower surface of the core layer.

[0058] The upper build-up insulation part and the lower build-up insulation part each have a function to place a wiring layer or via electrode of the build-up wiring part, secure insulation between circuits, and control impedance or insertion loss due to the circuit, and may include an insulation layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0059] For example, the insulation layer of the build-up insulation (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0060] Also, for example, the insulation layer of the build-up insulation portion (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0061] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0062] Additionally, the insulating layer of the build-up insulation (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0063] Additionally, the insulation layer of the build-up insulation portion (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0064]

[0065] Next, the build-up wiring section (118) of the circuit board (100) includes a wiring layer (130) arranged on the surface of each insulating layer and a via electrode (120) for vertically connecting each wiring layer (130). The wiring layer (130) may have the function of transmitting signals and / or power to semiconductor elements arranged on the circuit board (100) and may have an impedance matching function. The wiring layer (130) may be referred to as a wiring pattern layer, a metal wiring, or a wiring section.

[0066] The via electrode (120) may include a plurality of first via electrodes (121), second via electrodes (122), and third via electrodes (123) formed in through holes penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113), respectively. The via electrode (120) may electrically connect between wiring layers (130) arranged in different layers.

[0067] The via electrode (120) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material. Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the via electrode (120). The metal material forming the via electrode (120) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0068]

[0069] Next, the circuit board (100) according to the embodiment may include a wiring layer (130) electrically connected to a via electrode (120). The wiring layer (130) may include pads and / or traces (or connection patterns) for connecting to the via electrode (120) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads.

[0070] At this time, the pad of the wiring layer (130) may include a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0071]

[0072] The wiring layer (130) may include, but is not limited to, a first wiring layer (131) disposed on a first insulating layer (111) and electrically connected to the upper surface of a first via electrode (121), a second wiring layer (132) disposed on a second insulating layer (112) and electrically connected to the lower surface of the first via electrode (121), a third wiring layer (133) electrically connected to the lower surface of the second via electrode (122), and a fourth wiring layer (134) electrically connected to the lower surface of the third via electrode (123).

[0073] The wiring layer (130) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0074] In addition, any one of the above-described build-up wiring sections (118) may have an ETS (Embedded Trace Substrate) structure. The ETS structure may also be referred to as a buried structure. The ETS structure may be advantageous for miniaturization compared to a build-up wiring section having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0075] In addition, the build-up wiring portion (118) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring portion (118) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0076]

[0077] Next, the circuit board (100) according to the embodiment may include a protective layer (140) disposed on the uppermost or lowermost insulating layer. For example, the protective layer (140) may include a first protective layer (141) disposed on the first insulating layer (111) and a second protective layer (142) disposed under the third insulating layer (113).

[0078] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer (140) is formed of a material with low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridge short circuits between adjacent solders.

[0079] In addition, the protective layer (140) includes an insulating material, and may include various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. In addition, the protective layer (140) may also be a resist layer, and for example, the protective layer (140) may include an epoxy acrylate series resin. In detail, the protective layer (140) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0080] Additionally, a surface treatment layer (150) may be disposed on the first wiring layer (131). The surface treatment layer (150) can improve the wear resistance, heat resistance, and corrosion resistance of the pad (135), and can reduce electrical resistance by increasing flatness compared to the pad (135) and improve electrical conductivity by using a material with high electrical conductivity.

[0081] Although FIG. 2 shows that the surface treatment layer (150) is disposed only on the first wiring layer (131), the surface treatment layer (150) may also be disposed under the fourth wiring layer (134).

[0082]

[0083] FIG. 3 is a drawing showing a detailed area (A1) of FIG. 2. Referring to FIG. 3, a pad (135) may be arranged on an upper surface of an insulating layer (115). The insulating layer (115) of FIG. 3 may be the first insulating layer (111) of FIG. 2, and may be an insulating layer positioned at the uppermost or lowermost side of the circuit board (100). In addition, a via electrode (not shown) may be arranged within the insulating layer (115), and the via electrode may be electrically connected to the pad (135). In addition, the pad (135) may be a first wiring layer (131), and may be a wiring layer (130) arranged on the outermost layer of the circuit board (100).

[0084] Additionally, the surface treatment layer (150) may include a first surface treatment layer (152) and a second surface treatment layer (154) disposed on the first surface treatment layer (152). The first surface treatment layer (152) may be in contact with the upper surface of the pad (135). Additionally, the second surface treatment layer (154) may be in contact with the upper surface of the first surface treatment layer (152).

[0085] Additionally, the surface treatment layer (150) may include a different material from the pad (135). Additionally, the second surface treatment layer (154) may include a different material from the first surface treatment layer (152).

[0086] In addition, the second surface treatment layer (154) may include a material having a higher electrical conductivity than the pad (135). In addition, the roughness of the surface of the second surface treatment layer (154) may be lower than the roughness of the pad (135). Accordingly, the embodiment has a technical effect in that a connection part for connection with an external chip or substrate is connected to the second surface treatment layer (154), thereby improving the signal transmission speed and reducing signal noise.

[0087] For example, in the embodiment, the first surface treatment layer (152) may include Ni. In addition, the second surface treatment layer (154) may include Au. The first surface treatment layer (152) may prevent the material of the second surface treatment layer (154) from diffusing into the pad (135) and may function as a barrier metal layer. In addition, the second surface treatment layer (154) may have excellent wettability with solder, thereby improving solderability.

[0088] Additionally, the horizontal width of the surface treatment layer (150) may be smaller than the horizontal width of the pad (135). The pad (135) may include a first region (135-1) that vertically overlaps the surface treatment layer (150) and a second region (135-2) that does not vertically overlap. Additionally, the horizontal widths of the first surface treatment layer (152) and the second surface treatment layer (154) may be the same, but are not limited thereto.

[0089] Additionally, the central axis of the surface treatment layer (150) may be the same as the central axis of the pad (135). Additionally, the central axis of the surface treatment layer (150) may be different from the central axis of the pad (135).

[0090] Additionally, a protective layer (140) may be disposed on the insulating layer (115). Additionally, the protective layer (140) may be disposed to cover a portion of the pad (135). The protective layer (140) may include an open area (140H) that exposes the surface treatment layer (150).

[0091] Meanwhile, the protective layer (140) may not vertically overlap with the surface treatment layer (150). In addition, the protective layer (140) may be disposed spaced apart from the surface treatment layer (150). The protective layer (140) may be disposed to contact the upper surface of the second region (135-2) of the pad (135). Accordingly, the open region (140H) of the protective layer (140) may include a first open region (140H1) that vertically overlaps with the surface treatment layer (150) and a second open region (140H2) that does not vertically overlap with the surface treatment layer (150). The upper surface of the second surface treatment layer (154) may be exposed in the first open region (140H1) of the protective layer (140).

[0092] Accordingly, the embodiment has a technical effect of preventing lifting and peeling due to reduced adhesive strength between the protective layer (140) and the second surface treatment layer (154) as the protective layer (140) does not come into contact with the upper surface of the second surface treatment layer (154).

[0093] In addition, the embodiment has a technical effect that the signal transmission speed can be improved because the surface of the second surface treatment layer (154) is not covered by the protective layer (140) as the protective layer (140) does not vertically overlap with the second surface treatment layer (154), thereby improving the contact area with the connection part.

[0094] Meanwhile, in FIG. 3, a portion of the upper surface of the pad (135) is shown to be exposed by the second open area (140H2) of the protective layer (140), but surface treatment may be performed to form a film within the second open area (140H2) to prevent oxidation of the exposed pad (135). The film may include an insulating material. For example, in the embodiment, an OSP (Organic Solderability Preservative) process may be performed on the pad (135) exposed in the second open area (140H2) so that an organic material covers the exposed surface of the pad (135) to prevent oxidation of the pad (135). The height of the film formed by the surface treatment may be lower than the height of the upper surface of the second surface treatment layer (154).

[0095] Accordingly, the pad (135) can be protected by the surface treatment while the side surface of the second surface treatment layer (154) can be exposed by the second open area (140H2) of the protective layer (140). Therefore, when a connection part such as a solder is placed on the second surface treatment layer (154), the signal transmission speed can be improved by making contact with not only the upper surface but also the side surface of the surface treatment layer (150), and there is a technical effect that the side surface of the second surface treatment layer (154) can perform an anchor function to prevent detachment of the connection part.

[0096]

[0097] FIG. 4 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to a second embodiment. Referring to FIG. 4, a pad (135) may be disposed on an insulating layer (115), and a surface treatment layer (150) may be disposed on the pad (135). The pad (135) may include a first area (135-1) that vertically overlaps the surface treatment layer (150) and a second-second area (135-2b) that does not vertically overlap the surface treatment layer (150). The second-second area (135-2b) may not be in contact with the first surface treatment layer (152).

[0098] Meanwhile, the second-second region (135-2b) of the pad (135) may include a concave portion that is concave from the upper surface to the lower surface of the pad (135). In addition, the upper surface of the second-second region (135-2b) may include a curved surface. In addition, the upper surface of the second-second region (135-2b) may have a rougher surface than the upper surface of the first region (135-1). The concave portion may be formed by partially etching the second-second region (135-2b) of the pad (135), but is not limited thereto.

[0099] In addition, a protective layer (140) may be disposed on the insulating layer (115), and the protective layer (140) may be disposed on a portion of the pad (135). In detail, the protective layer (140) may be disposed to be in contact with the 2-2 region (135-2b) of the pad (135), and may be disposed spaced apart from the surface treatment layer (150). The side surface of the protective layer (140) may vertically overlap with the 2-2 region (135-2b) of the pad (135). In addition, the protective layer (140) may be disposed to cover the concave portion.

[0100] Accordingly, in the second embodiment, the protective layer (140) is arranged to cover the concave portion of the pad (135), and since the concave portion is formed to have a greater roughness than the upper surface of the first region (135-1), the adhesive strength with the protective layer (140) is further improved, thereby providing a technical effect of preventing the lifting phenomenon and peeling of the protective layer (140).

[0101]

[0102] FIG. 5 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to a third embodiment. Referring to FIG. 5, a pad (135) may be placed on an insulating layer (115), and a surface treatment layer (150) may be placed on the pad (135). The pad (135) may include a first area (135-1) that vertically overlaps the surface treatment layer (150) and a second-third area (135-2c) that does not vertically overlap the surface treatment layer (150).

[0103] Meanwhile, the 2-3 region (135-2c) may include a slope. The vertical thickness of the 2-3 region (135-2c) may decrease toward both ends of the pad (135). In addition, the roughness of the upper surface of the 2-3 region (135-2c) may be greater than the roughness of the upper surface of the 1st region (135-1). Although one end of the 2-3 region (135-2c) is shown in contact with the insulating layer (115) in FIG. 5, one end of the 2-3 region (135-2c) may have a predetermined height from the insulating layer (115).

[0104] Additionally, a protective layer (140) may be disposed on the insulating layer (115). The protective layer (140) may be disposed to cover the second-third region (135-2c) of the pad (135). Additionally, the protective layer (140) may be disposed spaced apart from the surface treatment layer (150). The protective layer (140) may not vertically overlap the first region (135-1) of the pad (135) and the surface treatment layer (150).

[0105] Accordingly, the third embodiment has a technical effect in that the protective layer (140) is arranged so that it does not come into contact with the surface treatment layer, but comes into contact with the 2-3 area (135-2c) of the pad (135) having an inclined surface, thereby improving the adhesive strength between the protective layer (140) and the pad (135), thereby preventing the lifting phenomenon and peeling of the protective layer (140).

[0106] In addition, the embodiment may perform a surface treatment process in which a film is formed on the upper surface of the 2-3 region (135-2c) of the pad (135) within the second open region (140H2) of the protective layer (140). The film is formed between the inclined surface of the 2-3 region (135-2c) and the side surface of the protective layer (140), so that the adhesive strength can be improved, and the adhesive strength between the protective layer (140) and the pad (135) can be further improved. In addition, the film prevents the exposure of the pad (135) to prevent oxidation, and is formed lower than the second surface treatment layer (154), so that the connecting portion can be in contact with not only the upper surface but also the side surface of the second surface treatment layer (154), thereby providing a technical effect in which the fixing strength of the connecting portion can be improved.

[0107]

[0108] FIG. 6 is a drawing showing one area (A1) of the circuit board (100) of FIG. 2 according to a fourth embodiment. Referring to FIG. 6, the pad (135) may include a first area (135-1) that is in contact with the surface treatment layer (150) and a second-fourth area (135-2d) that is not in contact with the surface treatment layer (150). In addition, the protective layer (140) may be disposed on the second-fourth area (135-2d) of the pad (135) and may not vertically overlap with the first area (135-1).

[0109] Meanwhile, a step may be formed between the first region (135-1) and the second-fourth region (135-2d) of the pad (135). The second-fourth region (135-2d) of the pad (135) may be positioned lower than the first region (135-1). In addition, the thickness of the second-fourth region (135-2d) may be smaller than the thickness of the first region (135-1).

[0110] The roughness of the upper surface of the 2-4 region (135-2d) may be greater than the roughness of the upper surface of the first region (135-1). Accordingly, in the embodiment, the protective layer (140) is in contact with the upper surface of the 2-4 region (135-2d) having a large roughness, and thus the adhesive strength is improved, thereby preventing the lifting and peeling of the protective layer (140). In addition, when a film is formed through surface treatment on the upper surface of the 2-4 region (135-2d) of the exposed pad (135), the film can improve the fixing strength by being in contact with the side surface of the first region (135-1), the upper surface of the 2-4 region (135-2d), and the side surface of the protective layer (140), and thus the adhesive strength of the protective layer (140) and the pad (135) can be further improved.

[0111]

[0112] Fig. 7 is a drawing of a semiconductor package (101) according to an embodiment. The semiconductor package (101) of the embodiment may include a circuit board having a build-up structure of the first to fourth embodiments.

[0113] Referring to FIG. 7, a semiconductor package (101) according to an embodiment may include a circuit board and a chip (200) disposed on the circuit board. In detail, the circuit board is disposed on a first wiring layer (131) disposed on the outermost layer of a build-up insulating member (110), and may include a first protective layer (141) disposed spaced apart from a side of a surface treatment layer (150). The first protective layer (141) does not vertically overlap with the surface treatment layer (150) and is disposed spaced apart from the surface treatment layer (150) by a predetermined distance, thereby having a technical effect of preventing the first protective layer (141) from being lifted off and peeled off due to a decrease in adhesive strength between the first protective layer (141) and the surface treatment layer (150).

[0114] Additionally, a film (157) may be formed on the upper surface of the first wiring layer (131) exposed between the surface treatment layer (150) and the first protective layer (141) through a surface treatment process. The film (157) may be formed lower than the second surface treatment layer (154).

[0115] Additionally, a connection portion (190) may be placed on the exposed surface treatment layer (150). The connection portion (190) may have a spherical shape. Additionally, the cross-section of the connection portion (190) may have a circular shape or a semicircular shape. The connection portion (190) may be a solder ball, but is not limited thereto.

[0116] Accordingly, the embodiment has a technical effect in that the first protective layer (141) is disposed spaced apart from the surface treatment layer (150), so that the upper and side surfaces of the second surface treatment layer (154) are exposed, and the connection portion (190) is in contact with not only the upper surface but also the side surface of the second surface treatment layer (154), thereby increasing the contact area and improving the signal transmission speed and reducing signal noise, and the second surface treatment layer (154) performs an anchor function to prevent the connection portion (190) from coming off and improve the positioning precision.

[0117] In addition, the circuit board may further include a bonding portion on the first protective layer (141). The bonding portion is positioned on the upper surface of the first protective layer (141) to perform thermal compression bonding with the semiconductor element, and may be used when the pitch of the pad of the semiconductor element becomes fine and it is difficult to implement with conventional solder bonding.

[0118] In addition, a chip (200) or a component may be included on the connection portion (190) of the circuit board. The chip (200) may be a processor chip. For example, the chip (200) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (205) may be included on the bottom surface of the chip (200), and the terminals (205) may be included in multiple numbers. The terminal (205) of the chip (200) may be electrically connected to the connection portion (190) of the circuit board.

[0119] Meanwhile, the semiconductor package (101) of the embodiment may include a plurality of chips that are horizontally spaced apart from each other and arranged on a single circuit board. For example, the chip (200) may also include a first chip and a second chip. The first chip and the second chip may be different types of application processor (AP) chips.

[0120] Additionally, the connection portion located at the bottom of the semiconductor package (101) of the embodiment may be for connecting a main board (or motherboard) of an external device.

[0121] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0122] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0123] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0124] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Insulating layer; a pad disposed on the insulating layer; and A surface treatment layer disposed on the above pad; The pad includes a first region overlapping the surface treatment layer and a second region not overlapping the surface treatment layer, Including a protective layer disposed on the second region, A circuit board, wherein the protective layer is separated from the surface treatment layer.

2. In paragraph 1, A circuit board, wherein the side surface of the protective layer vertically overlaps the second region.

3. In paragraph 1, The surface treatment layer includes a first surface treatment layer and a second surface treatment layer disposed on the first surface treatment layer, A circuit board, wherein the second surface treatment layer comprises Au.

4. In paragraph 1, A circuit board in which the horizontal width of the upper surface of the first region is the same as the horizontal width of the lower surface of the surface treatment layer.

5. In paragraph 1, A circuit board in which the horizontal width of the lower surface of the above pad is greater than the horizontal width of the lower surface of the above surface treatment layer.

6. In paragraph 1, The upper surface of the second region is a flat circuit board.

7. In paragraph 6, A circuit board, wherein the height of the upper surface of the second region is lower than the height of the upper surface of the first region.

8. In paragraph 1, A circuit board, wherein the upper surface of the second region includes a concave portion that is concave from the upper surface of the pad to the lower surface.

9. In paragraph 1, A circuit board, wherein the upper surface of the second region includes an inclined surface.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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