Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a core layer including an upper surface and a lower surface; an upper electrode layer disposed on the upper surface of the core layer; a lower electrode layer disposed on the lower surface of the core layer; and a core via electrode disposed on the lower surface of the lower electrode layer and extending through the core layer to the upper surface of the upper electrode layer, wherein the core via electrode may comprise a through-portion overlapping the core layer in the horizontal direction, the upper electrode layer may comprise an upper through-hole having the same width as the through-portion, and the lower electrode layer may comprise a lower through-hole having a width smaller than that of the through-portion.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of electronic components on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single electronic component, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple electronic components across multiple substrates have recently been developed. These semiconductor packages feature a structure in which multiple electronic components are interconnected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the electronic components and enabling high-speed signal transmission through short signal transmission paths between the components.

[0004] Meanwhile, a circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, a circuit board may mean that a mounting position of each electronic component is predetermined for mounting at least one electronic component, and a build-up wiring body connected to the electronic component is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The electronic component is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005]

[0006] Conventionally, miniaturization of circuit boards has required miniaturization of build-up wiring. However, even if the wiring layers of the build-up wiring can be formed small, it has been difficult to form small-diameter via electrodes in the core layer.

[0007] For example, the annular ring, which indicates the margin of pad size compared to via opening, must be processed to have an appropriate value. However, even if the size of the wiring layer is reduced, it is difficult to process a small-diameter via electrode in the core layer, which poses a problem in that the reliability of the circuit board cannot be guaranteed.

[0008] One of the technical tasks of the present invention is to provide a circuit board having a small-diameter via electrode in a core layer and a package board including the same.

[0009] In addition, a circuit board and a package board including the same can be provided, which can secure reliability while increasing the density of the wiring layer by reducing the pitch between core via electrodes, the pitch between upper electrode layers, and the pitch between lower electrode layers.

[0010] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0011] A circuit board according to an embodiment includes a core layer including an upper surface and a lower surface, an upper electrode layer disposed on an upper surface of the core layer, a lower electrode layer disposed on a lower surface of the core layer, and a core via electrode disposed on a lower surface of the lower electrode layer and extending through the core layer to an upper surface of the upper electrode layer, wherein the core via electrode includes a through portion that overlaps the core layer in a horizontal direction, and the upper electrode layer may include an upper through hole having a width equal to a width of the through portion, and the lower electrode layer may include a lower through hole having a width smaller than a width of the through portion.

[0012] Additionally, the core via electrode may include a first layer having different crystal grains and a second layer disposed on the first layer.

[0013] Additionally, the crystal grains of the first layer may be smaller than the crystal grains of the second layer.

[0014] Additionally, the lower electrode layer may include a protrusion that vertically overlaps the penetration portion.

[0015] Additionally, the first layer can be in contact with the protrusion.

[0016] Additionally, the width between the upper electrode layers may be 25 μm or less.

[0017] Additionally, the width between the lower electrode layers may be 5 μm or less.

[0018] Additionally, the diameter of the upper electrode layer and the lower electrode layer may be 60 μm or less.

[0019] Additionally, the present invention may include a package substrate including the circuit substrate described above.

[0020] The circuit board of the embodiment of the invention has a horizontal width of a core via electrode formed on a core layer of 25 ㎛ or less, and an electrode layer of 60 ㎛ or less, thereby securing a large number of wiring layer patterns.

[0021] In addition, even if the wiring layer pattern is secured in large numbers and the density is increased, reliability can be secured because the pitch between adjacent upper electrode layers, the pitch between adjacent lower electrode layers, and the pitch between adjacent core via electrodes have appropriate intervals.

[0022] In the circuit board of the embodiment, the horizontal width of the core via electrode may be the same from the second surface to the first surface of the core layer. In another example, the horizontal width of the core via electrode may gradually decrease from the second surface to the first surface of the core layer. This varies depending on the manufacturing method of the core via electrode according to the embodiment, and the core layer according to the embodiment may be formed through two processing steps. In the embodiment, a small-diameter core via electrode can be implemented by using a top-hat mode beam or / and a Gaussian mode beam. In addition, the problem of an electrical short circuit due to a lower through hole of the core via electrode not being formed or an electrode layer not being formed through two processing steps can be prevented.

[0023] Figure 1 illustrates a circuit board according to a first embodiment of the present invention.

[0024] Figure 2 is an enlarged view of area A of Figure 1.

[0025] Fig. 3 illustrates a method for manufacturing a core layer via electrode of a circuit board according to the first embodiment.

[0026] Figure 4 illustrates a circuit board according to the second embodiment.

[0027] Figure 5 is an enlarged view of area B of Figure 4.

[0028] Fig. 6 illustrates a method for manufacturing a core layer via electrode of a circuit board according to a second embodiment.

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0032] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0033] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0034] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0035] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0036] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0037] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0038] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0039] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0040]

[0041] -Semiconductor package-

[0042] Before describing the embodiment, a semiconductor package including the circuit board of the embodiment will be briefly described. The semiconductor package includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various electronic components may be mounted on the semiconductor package.

[0043] Electronic components include active components and / or passive components. Active components may be semiconductor chips in the form of integrated circuits (ICs) with hundreds to millions of components integrated into a single chip. Electronic components may be logic chips, memory chips, etc. Logic chips may be central processors (CPUs), graphics processors (GPUs), etc. For example, logic chips may be application processor (AP) chips that include at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set that includes a specific combination of the aforementioned components.

[0044] The memory chip may be a stacked memory such as HBM. In addition, the memory chip includes memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0045] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0046] Additionally, the semiconductor package may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited thereto, and it is obvious that the semiconductor package may be any other electronic device that processes data.

[0047]

[0048] -Circuit board-

[0049] Below, a circuit board according to an embodiment is described.

[0050] Figure 1 illustrates a circuit board according to a first embodiment of the present invention.

[0051] Referring to FIG. 1, a circuit board (10) according to the first embodiment includes a build-up structure (100) including a build-up insulator (110), a build-up wiring body (120), and a protective layer (140). The build-up structure (100) can function as a laminated circuit for connecting to electronic components / main boards, etc.

[0052] The build-up structure (100) may include a build-up insulator (110). The build-up insulator (110) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies (120). The build-up insulator (110) may include, but is not limited to, a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113).

[0053] One of the insulating layers of the build-up insulator (110) may be a core layer. For example, the first insulating layer (111) may be a core layer. The core layer may function to secure the overall mechanical rigidity of the circuit board and suppress warpage. Since it can suppress both warpage occurring during the process and warpage occurring during the operation of the product, the core layer may improve the yield of the circuit board and enhance the reliability of the circuit board.

[0054] The core layer (111) may include a reinforcing member such as glass fiber extending in the horizontal direction and a resin covering the same, and the mechanical rigidity may be adjusted according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided in the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0055] The build-up insulator (110) may include an upper build-up insulator disposed on the upper surface of the core layer (111) and a lower build-up insulator disposed on the lower surface of the core layer (111). For example, the build-up insulator (110) may include a second insulating layer (112), which is an upper build-up insulator disposed on the upper surface of the core layer (111), and a third insulating layer (113), which is a lower build-up insulator disposed on the lower surface of the core layer (111).

[0056] The upper build-up insulator (112) and the lower build-up insulator (113) each have a function of arranging a wiring layer or via electrode of the build-up wiring body (120) and a function of securing insulation between circuits and controlling impedance or insertion loss by the circuit, and include an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film in consideration of dielectric constant, mechanical rigidity, and processability.

[0057] For example, the insulating layer of the build-up insulator (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0058] Also, for example, the insulating layer of the build-up insulator (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0059] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0060] Additionally, the insulating layer of the build-up insulator (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0061] In addition, the insulation layer of the build-up insulator (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with epoxy resin or the like.

[0062]

[0063] The build-up wiring body (120) includes a wiring layer (121) arranged on the surface of each insulating layer and a via electrode (122) for vertically connecting each wiring layer (121). The wiring layer (121) can have the function of transmitting signals and / or power to electronic devices arranged on a circuit board and can perform an impedance matching function. The wiring layer (121) may be referred to as a wiring pattern layer, a metal wiring, or a wiring portion. The via electrode (122) may be referred to as a through electrode, a via, or a via portion.

[0064]

[0065] Any one of the build-up wiring bodies (120) may have an ETS (Embedded Trace Substrate) structure. For example, the build-up wiring body arranged on the upper surface of the circuit board (10) may have an ETS structure. For example, the build-up wiring body arranged on the upper surface of the circuit board (10) may be arranged in a recess provided on the upper surface of the uppermost second insulating layer (112). The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in an electronic device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through an electronic device, thereby minimizing signal transmission loss.

[0066] In addition, the build-up wiring body (120) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring body (120) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0067]

[0068] The wiring layer (121) of the circuit board (10) according to the embodiment includes pads and / or traces (or connection patterns) for connecting to via electrodes (122) and / or electronic components and / or capacitors. The traces may be long signal wiring lines connecting between a plurality of pads.

[0069] At this time, the pad (123) of the wiring layer (121) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or a semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a side extension portion for an alignment margin. The wiring layer (121) may be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0070]

[0071] A circuit board (10) according to an embodiment includes a protective layer (140) disposed on a wiring layer (121, 124, 125) of an uppermost or lowermost insulating layer. For example, the protective layer (140) may include a first protective layer (141) disposed on the uppermost insulating layer and a second protective layer (142) disposed under the lowermost insulating layer.

[0072] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure (100) due to external moisture or contaminants. The protective layer can be formed of a material with low wettability to solder to prevent short circuits between adjacent solders when connecting the build-up structure (100) to an electronic component or main board, thereby preventing bridging and short circuits between adjacent solders.

[0073] The protective layer (140) includes an insulating material, and the protective layer (140) includes various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The protective layer (140) may be a resist layer, and for example, the protective layer (140) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (140) includes an epoxy acrylate series resin. In detail, the protective layer (140) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0074]

[0075] Fig. 2 is an enlarged view of area A of Fig. 1, and Fig. 3 illustrates a method for manufacturing a core layer via electrode of a circuit board according to the first embodiment.

[0076] Referring to FIGS. 1 to 3, a via electrode (122) of a circuit board (10) according to the first embodiment can electrically connect wiring layers (121) arranged on different layers. The via electrode (122) can include a first via electrode (122a) penetrating a core layer (111) and a second via electrode (122b) penetrating a second insulating layer (112) and a third insulating layer (113). The first via electrode (122a) can be referred to as a core via electrode.

[0077] The core via electrode (122a) penetrating the core layer (111) may include an intermediate member (not shown). The intermediate member may be provided to fill a portion of the through hole penetrating the core layer (111). The intermediate member may also be referred to as a hole plugging member. The intermediate member may include an insulating material provided in the through hole of the core layer. For example, the intermediate member may include a paste of an insulating ink material. For example, the intermediate member may include a plugging ink. However, the embodiment is not limited thereto. For example, the intermediate member may include a conductive material. Specifically, the intermediate member may include a conductive paste containing a conductive metal powder.

[0078] Additionally, the core layer may be provided with reinforcing fibers. Through this, the embodiment can further enhance the rigidity of the circuit board.

[0079] The vertical thickness of the core layer may be greater than the vertical thickness of the build-up insulation layer disposed above and / or below the core layer. For example, the vertical thickness of the core layer may be at least three times, at least four times, at least five times, at least seven times, or at least ten times the vertical thickness of the build-up insulation layer.

[0080] As semiconductor packages have recently become more high-performance, the number of insulating layers in semiconductor package substrates has also increased. For example, the number of insulating layers in a semiconductor package substrate may be 10 or more, 12 or more, 16 or more, or 20 or more. Specifically, if the build-up insulating layers are laminated in multiple layers, as illustrated, the stresses in each insulating layer may cause warpage in the semiconductor package substrate. If the semiconductor package substrate warps, it may be difficult to form the through-electrodes included in the semiconductor package substrate in the correct position. Furthermore, if the semiconductor package substrate warps, problems such as misalignment of the semiconductor devices during the process of mounting the semiconductor devices on the semiconductor package substrate may occur. Therefore, to prevent warpage of the semiconductor package substrate, the vertical thickness of the core layer may be 200 μm or more. Accordingly, to increase the physical rigidity of the semiconductor package substrate and improve the warpage characteristics of the semiconductor package substrate during the packaging process, the core layer may have a vertical thickness of 200 μm or more. Additionally, if the core layer thickness becomes too thick, the process of forming a through hole in the core layer becomes difficult, and the electrical characteristics, such as signals and / or power applied to the semiconductor element, may deteriorate. Furthermore, it may become difficult to slim down the semiconductor package, which may make it difficult to manufacture a small volume electronic device. Therefore, it is appropriate to have the vertical thickness of the core layer be 1200㎛ or less.

[0081] However, the embodiment is not limited thereto. For example, the core layer may have a multilayer structure, and when the core layer has a multilayer structure, the total thickness of the core layer of the multilayer structure may have a thickness within the above-described range, and the thickness of each layer of the core layer of the multilayer structure may be 30 um to 50 um.

[0082]

[0083] The wiring layer (121) according to the first embodiment may include a lower electrode layer (121a) disposed on the lower surface (S1) of the core layer (111) and an upper electrode layer (121b) disposed on the upper surface (S2) of the core layer (111). The lower electrode layer (121a) and the upper electrode layer (121b) may be connected by the core via electrode (122a).

[0084] The core via electrode (122a) may penetrate the core layer (111) and have a penetration portion (TH) that overlaps the core layer (111) in a horizontal direction.

[0085] The core via electrode (122a) may include a first core via electrode (122a1) forming a first layer of the through-hole (TH) and a second core via electrode (122a2) forming a second layer of the through-hole (TH). The first core via electrode (122a1) may be formed of a chemical copper having small crystal grains, and the second core via electrode (122a2) may be formed of an electroplated layer having larger crystal grains than the crystal grains of the first core via electrode (122a1).

[0086] The first core via electrode (122a1) is arranged on the inner surface (S3) of the core layer (111) and can be in contact with the lower electrode layer (121a) and the upper electrode layer (121b).

[0087] The lower electrode layer (121a) may include a first lower electrode layer (121a1), a second lower electrode layer (121a2), and a third lower electrode layer (121a3). The first lower electrode layer (121a1) is a copper foil layer disposed on the first surface (S1) of the core layer (111). The first lower electrode layer (121a1) may be in contact with the first core via electrode (122a1). The second lower electrode layer (121a2) may be formed of chemical copper, and may be connected to the first core via electrode (122a1) or formed integrally with it during a process. The first lower electrode layer (121a1) and the second lower electrode layer (121a2) may form a lower through hole (BVH). The third lower electrode layer (121a3) is formed as an electroplated layer growing from the second lower electrode layer (121a2), and may be connected to the second core via electrode (122a2) or formed integrally with it during the process. The third lower electrode layer (121a3) may penetrate the lower through hole (BVH). The first lower electrode layer (121a1) and the second lower electrode layer (121a2) may have a protrusion (121a-1) that protrudes so as to vertically overlap with the through portion (TH) of the core via electrode.

[0088] The upper electrode layer (121b) may include a first upper electrode layer (121b1), a second upper electrode layer (121b2), and a third upper electrode layer (121b3). The first upper electrode layer (121b1) is a copper foil layer disposed on the second surface (S2) of the core layer (111). The first upper electrode layer (121b1) may be in contact with the first core via electrode (122a1). The second upper electrode layer (121b2) may be formed of chemical copper, and may be connected to the first core via electrode (122a1) or formed integrally with it during a process. The first upper electrode layer (121b1) and the second upper electrode layer (121b2) may form an upper through hole (TVH). The third upper electrode layer (121b3) is formed as an electroplated layer growing from the second upper electrode layer (121b2), and may be connected to the second core via electrode (122a2) or formed integrally with it during the process. The third upper electrode layer (121b3) may penetrate the upper through hole (TVH).

[0089]

[0090] Referring to FIG. 3, after the first lower electrode layer (121a1) and the first upper electrode layer (121b1) are formed on the first surface (S1) and the second surface (S2) of the core layer (111), a process of forming a through-hole (TH) may be performed. First, the first processing may be performed in the direction of the second surface (S2). At this time, the beam used for the first processing may be a beam in the top-hat mode. Since the beam in the top-hat mode has the same energy density at both the center and the edge, the width of the upper through-hole (TVH) formed in the upper electrode layer (121b1) and the through-hole (TH) of the core layer may have the same diameter. That is, the horizontal width of the through-hole (TH) of the core via electrode (122a) may be constant. Since the beam in top-hat mode has a property of spreading its energy widely, a bottom penetration hole (BVH) may not be formed or may be formed minutely in the central region.

[0091] Thereafter, a second processing may be performed on the second surface (S2) to expand the lower through hole (BVH). At this time, a Gaussian mode beam may be used as the beam used in the second processing. Since the Gaussian mode beam can form a deep and narrow via, the diameter (L2) of the lower through hole (BVH) can be adjusted. That is, the problem of the lower through hole (BVH) of the core via electrode not being properly formed through the second processing and thus not being electrically connected can be prevented. In an embodiment, the diameter (L2) of the lower through hole may be smaller than the diameter (L1) of the upper through hole. As a result, the first lower electrode layer (121a1) may have a protrusion (121a-1) that vertically overlaps the through portion (TH). The protrusion (121a-1) may have an inclined structure due to the Gaussian mode beam used in the second processing.

[0092] According to the first embodiment, the diameter (L2) of the lower through hole may have a range of 4 μm to 6 μm. Preferably, the diameter (L2) of the lower through hole may have 5 μm. In addition, the diameter (L1) of the upper through hole (TVH) may have a range of 20 μm to 25 μm. Preferably, the diameter (L1) of the upper through hole may have 25 μm. The diameter of the through portion (TH) according to the first embodiment may be the same as the diameter (L1) of the upper through hole.

[0093] After the through-hole (TH), the upper through-hole (TVH) and the lower through-hole (BVH) according to the first embodiment are formed, the second lower electrode layer (121a2), the first upper electrode layer (121b2) and the first core via electrode (122a1) may be formed, and the third lower electrode layer (121a3), the third upper electrode layer (121b3) and the second core via electrode (122a2) may be formed sequentially. At this time, the diameter (D2) of the lower and upper electrode layers (121a, 121b) may have 60 µm or less. For example, the diameter (D2) of the lower and upper electrode layers (121a, 121b) may have 40 µm to 60 µm. In addition, the width (D3) between the second lower electrode layers (121a2) may have 5 µm or less. For example, the width (D3) between the second lower electrode layers (121a2) may have a range of 3 µm to 5 µm. In addition, the width (D4) between the second upper electrode layers (121b2) may have a range of 25 µm or less. For example, the width (D4) between the second upper electrode layers (121b2) may have a range of 20 µm to 25 µm. The width (D4) between the second upper electrode layers (121b2) may be greater than or equal to the width of the through-hole (TH). The diameter (D2) of the upper and lower electrode layers (121a, 121b) described above may have a range that satisfies the width of the through-hole (TH) of the core via electrode and an appropriate annual ring. If the width of the through-hole (TH) is 25 µm or more, the margin of the upper and lower electrode layers may be reduced, which may cause problems such as via shift. According to an embodiment, by having the diameter between the lower and upper electrode layers and the width of the penetration portion of the core via electrode as described above, the pitch between adjacent upper electrode layers, the pitch between adjacent lower electrode layers, and the pitch between adjacent core via electrodes are at appropriate intervals while achieving high density, so that interference between adjacent wiring bodies may not occur.

[0094] Fig. 4 illustrates a circuit board according to a second embodiment, Fig. 5 is an enlarged view of area B of Fig. 4, and Fig. 6 illustrates a method for manufacturing a core layer via electrode of a circuit board according to the second embodiment.

[0095] Referring to FIGS. 4 to 6, the circuit board (10) according to the second embodiment differs only in the configuration of the core via electrode (122a), and the other configurations may be the same.

[0096] The core via electrode (122a) according to the second embodiment may have a width of the penetration portion (TH) that becomes smaller as it goes from the second surface (S2) of the core layer (111) to the first surface (S1). That is, the penetration portion (TH) of the core layer (111) according to the second embodiment may have an inclined inner surface (S3).

[0097] The width (D3) between the lower electrode layers (121a) may be smaller than the width (D5) between the upper electrode layers (121b).

[0098]

[0099] Referring to FIG. 6, after the first lower electrode layer (121a1) and the first upper electrode layer (121b1) are formed on the first surface (S1) and the second surface (S2) of the core layer (111), a process of forming a through-hole (TH) may be performed. First, a first processing may be performed in the direction of the second surface (S2). At this time, a Gaussian mode beam may be used as the beam used in the first processing. Since the Gaussian mode beam forms a deep and narrow via, through the first processing, the diameter of the through-hole (TH) of the core layer (111) may become narrower from the second surface (S2) to the first surface (S1). The lower through-hole (BVH) may be formed as a fine via in the central region.

[0100] Thereafter, a second processing may be performed on the second surface (S2) to expand the lower through hole (BVH). At this time, the beam used in the second processing may be a Gaussian mode beam. Since the Gaussian mode beam can form a deep and narrow via, the diameter (L2) of the lower through hole (BVH) can be adjusted. That is, the problem of the lower through hole (BVH) of the core via electrode not being properly formed through the second processing and thus not being electrically connected can be prevented. In an embodiment, the diameter (L2) of the lower through hole may be smaller than the diameter (L1) of the upper through hole. As a result, the first lower electrode layer (121a1) may have a protrusion (121a-1) that vertically overlaps the through portion (TH). The protrusion (121a-1) may have an inclined structure due to the Gaussian mode beam used in the second processing. The diameter (L4) of the lower through hole (BVH) may be smaller than the diameter at the lowest part of the through portion (TH) of the core layer (111).

[0101] According to the second embodiment, after the through-hole (TH), the upper through-hole (TVH) and the lower through-hole (BVH) are formed, the second lower electrode layer (121a2), the first upper electrode layer (121b2) and the first core via electrode (122a1) are formed, and the third lower electrode layer (121a3), the third upper electrode layer (121b3) and the second core via electrode (122a2) may be sequentially formed. At this time, the diameter (D2) of the lower and upper electrode layers (121a, 121b) may have 60 µm or less. For example, the diameter (D2) of the lower and upper electrode layers (121a, 121b) may have 40 µm to 60 µm. In addition, the width (D3) between the second lower electrode layers (121a2) may have 5 µm or less. For example, the width (D3) between the second lower electrode layers (121a2) may have a range of 3 µm to 5 µm. In addition, the width (D4) between the second upper electrode layers (121b2) may have a range of 25 µm or less. For example, the width (D4) between the second upper electrode layers (121b2) may have a range of 20 µm to 25 µm. The width (D4) between the second upper electrode layers (121b2) may be greater than or equal to the width of the through-hole (TH). The diameter (D2) of the upper and lower electrode layers (121a, 121b) described above may have a range that satisfies the width of the through-hole (TH) of the core via electrode and an appropriate annual ring. If the width of the through-hole (TH) is 25 µm or more, the margin of the upper and lower electrode layers may be reduced, which may cause problems such as via shift. According to an embodiment, by having the diameter between the lower and upper electrode layers and the width of the penetration portion of the core via electrode as described above, the pitch between adjacent upper electrode layers, the pitch between adjacent lower electrode layers, and the pitch between adjacent core via electrodes are at appropriate intervals while achieving high density, so that interference between adjacent wiring bodies may not occur.

[0102]

[0103] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0104] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0105]

[0106] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer including the upper and lower surfaces; An upper electrode layer disposed on the upper surface of the core layer; A lower electrode layer disposed on the lower surface of the core layer; It includes a core via electrode disposed on the lower surface of the lower electrode layer and extending through the core layer to the upper surface of the upper electrode layer, The above core via electrode includes a penetration portion that overlaps the core layer in a horizontal direction, The upper electrode layer includes an upper through hole having a width equal to the width of the through portion. A circuit board including a lower through hole having a width smaller than the width of the penetration portion, wherein the lower electrode layer is above.

2. In paragraph 1, The above core via electrode is a circuit board including a first layer having different crystal grains and a second layer disposed on the first layer.

3. In paragraph 2, A circuit board wherein the crystal grains of the first layer are smaller than those of the second layer.

4. In paragraph 3, A circuit board wherein the lower electrode layer includes a protrusion vertically overlapping the penetration portion.

5. In paragraph 4, The above first layer is a circuit board in contact with the above protrusion.

6. In paragraph 1, A circuit board having a width between the upper electrode layers of 25㎛ or less.

7. In paragraph 1, A circuit board having a width between the lower electrode layers of 5㎛ or less.

8. In paragraph 1, A circuit board wherein the diameter of the upper electrode layer and the lower electrode layer is 60㎛ or less.

9. In paragraph 1, A circuit board in which the lower width of the above penetration portion is equal to or smaller than the upper width of the above penetration portion.

10. A package substrate comprising a circuit board according to any one of claims 1 to 9.

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