Array substrate and display panel

Abstract

Disclosed in embodiments of the present invention are an array substrate and a display panel. The array substrate comprises a substrate, a first conductor part located on one side of the substrate, a second conductor part, and an active layer, wherein the active layer comprises a first doped part, a second doped part, and a channel part, the second doped part is located on the side of the first doped part distant from the substrate, the channel part is connected between the first doped part and the second doped part, the first conductor part is in contact with the first doped part, and the second conductor part is in contact with the second doped part.

Description

Array substrate and display panel Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] With the widespread application of display technology in mobile phones, televisions, computers, virtual reality (VR) displays, and augmented reality (AR) displays, there is an increasing demand for display products with higher resolution and higher pixel density. Thin-film transistors (TFTs) are a common switching element in the array substrate of display panels. In the active layer of a TFT, the doped portions that contact the source and drain electrodes are located horizontally at both ends of the channel. The effective conductive channel length of the active layer is typically determined by the horizontal length of the channel between the source and drain electrodes. This makes it difficult to reduce the size of the TFT, resulting in difficulty in increasing the pixel density (PPI) of the display panel.

[0003] Therefore, an array substrate and a display panel are urgently needed to solve the above technical problems. SUMMARY OF THE INVENTION

[0004] The present invention provides an array substrate and a display panel, which can alleviate the technical problem that the thin film transistors of the current array substrate are difficult to reduce in horizontal dimension, resulting in a limited improvement in the pixel density of the display panel.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present invention provides an array substrate, comprising:

[0007] substrate;

[0008] a first conductor portion, located on one side of the substrate;

[0009] a second conductor portion, located on a side of the first conductor portion away from the substrate;

[0010] an active layer comprising a first doping portion, a second doping portion, and a channel portion, wherein the second doping portion is located on a side of the first doping portion away from the substrate, and the channel portion is connected between the first doping portion and the second doping portion;

[0011] The first conductor portion is in contact with the first doped portion, and the second conductor portion is in contact with the second doped portion.

[0012] The present invention further provides a display panel, comprising an array substrate, wherein the array substrate comprises:

[0013] substrate;

[0014] a first conductor portion, located on one side of the substrate;

[0015] a second conductor portion, located on a side of the first conductor portion away from the substrate;

[0016] an active layer comprising a first doping portion, a second doping portion, and a channel portion, wherein the second doping portion is located on a side of the first doping portion away from the substrate, and the channel portion is connected between the first doping portion and the second doping portion;

[0017] The first conductor portion is in contact with the first doped portion, and the second conductor portion is in contact with the second doped portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a schematic structural diagram of a first structure of an array substrate provided by an embodiment of the present invention;

[0019] FIG2 is a schematic structural diagram of a second structure of an array substrate provided by an embodiment of the present invention;

[0020] FIG3 is a schematic structural diagram of a third structure of an array substrate provided by an embodiment of the present invention;

[0021] FIG4 is a schematic structural diagram of a fourth structure of an array substrate provided by an embodiment of the present invention;

[0022] FIG5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0023] 6a to 6h are schematic flow charts of a method for manufacturing an array substrate according to an embodiment of the present invention;

[0024] FIG7 is a schematic diagram of a first structure of a display panel provided by an embodiment of the present invention;

[0025] FIG8 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present invention. Modes for Carrying Out the Invention

[0026] The present application provides an array substrate and a display panel. To make the purpose, technical solutions, and effects of the present application more clear and explicit, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0027] Currently, since the conductive channel length of the thin film transistor in the array substrate is determined by the horizontal length of the channel between the source and the drain, it is difficult to reduce the size of the thin film transistor, and there is a technical problem that the pixel density of the display panel is limited.

[0028] Referring to FIG. 1 to FIG. 4 , an embodiment of the present invention provides an array substrate 100 , including:

[0029] substrate 101;

[0030] A first conductor portion 102 is located on one side of the substrate 101;

[0031] The second conductor portion 103 is located on a side of the first conductor portion 102 away from the substrate 101;

[0032] The active layer 104 includes a first doped portion 105, a second doped portion 106, and a channel portion 107. The second doped portion 106 is located on a side of the first doped portion 105 away from the substrate 101. The channel portion 107 is connected between the first doped portion 105 and the second doped portion 106.

[0033] The first conductor portion 102 is in contact with the first doped portion 105 , and the second conductor portion 103 is in contact with the second doped portion 106 .

[0034] In the embodiment of the present invention, the first doping portion 105 and the second doping portion 106 of the active layer 104 are arranged in different layers, and the channel portion 107 is connected between the two. This reduces the length of the channel portion 107 of the active layer 104 in a direction parallel to the substrate 101, reduces the size of the thin film transistor in the array substrate 100, and is beneficial to improving the pixel density of the display panel having the array substrate 100.

[0035] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0036] Referring to FIG. 1 to FIG. 4 , in this embodiment, the orthographic projection of the first doped portion 105 on the substrate 101 and the orthographic projection of the second doped portion 106 on the substrate 101 at least partially overlap.

[0037] In this embodiment, the first conductor portion 102 is one of the source and the drain of the array substrate 100 , and the second conductor portion 103 is the other of the source and the drain of the array substrate 100 .

[0038] In some embodiments, the first conductor portion 102 is a source, and the second conductor portion 103 is a drain.

[0039] 1 to 4 , in some embodiments, the orthographic projection of the first doped portion 105 on the substrate 101 and the orthographic projection of the second doped portion 106 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101. Alternatively, the orthographic projection of an end of the first doped portion 105 away from the channel portion 107 on the substrate 101 and the orthographic projection of an end of the second doped portion 106 away from the channel portion 107 on the substrate 101 are respectively located on opposite sides of the orthographic projection of the channel portion 107 on the substrate 101.

[0040] 1 to 4 , in some embodiments, the first conductor portion 102 is located on a side of the first doped portion 105 away from the first channel portion 107 . The second conductor portion 103 is located on a side of the first doped portion 105 away from the first channel portion 107 .

[0041] In some embodiments, the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 may be located on either side of the orthographic projection of the channel portion 107 on the substrate 101. Alternatively, referring to Figures 1 to 4 , the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101.

[0042] When the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101, the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 at least partially overlap.

[0043] Referring to FIG. 1 to FIG. 4 , in some embodiments, the array substrate 100 further includes a gate 108 . The gate 108 is located between the first conductor portion 102 and the second conductor portion 103 .

[0044] In some embodiments, the gate 108 is located on a side of the channel portion 107 away from the first doped portion 105 , that is, the orthographic projection of the gate 108 on the substrate 101 and the orthographic projection of the first conductor portion 102 on the substrate 101 are respectively located on both sides of the orthographic projection of the channel portion 107 on the substrate 101 .

[0045] Alternatively, the gate 108 is located on a side of the channel portion 107 away from the second doped portion 106 , that is, the orthographic projection of the gate 108 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are respectively located on both sides of the orthographic projection of the channel portion 107 on the substrate 101 .

[0046] Alternatively, referring to Figures 1 and 2, when the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101, the gate 108 is located on a side of the channel portion 107 away from the first doped portion 105, and the gate 108 is located on a side of the channel portion 107 away from the second doped portion 106.

[0047] The first conductor portion 102, the second conductor portion 103, the active layer 104, and the gate 108 constitute a thin film transistor of the array substrate 100. Compared to a thin film transistor in which the channel portion 107 extends parallel to the substrate 101, when the orthographic projection of the first conductor portion 102 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the conductor portions on the substrate 101, and the gate 108 is located on the side of the channel portion 107 away from the first doped portion 105, and the gate 108 is located on the side of the channel portion 107 away from the second doped portion 106, the width of the thin film transistor in the direction parallel to the substrate 101 can be reduced by 3 to 4 microns, which is beneficial for improving the pixel density of a display panel using the array substrate 100.

[0048] In some embodiments, when the gate 108 is located on a side of the channel portion 107 away from the second doped portion 106, the second conductor portion 103 and the gate 108 can be formed in the same process, and the thickness of the second conductor portion 103 is equal to the thickness of the gate 108. This helps simplify the manufacturing process and reduce the manufacturing cost of the array substrate 100. It is understood that when the ratio of the thickness of the second conductor portion 103 to the thickness of the gate 108 is within the range of 95:100 to 105:100, the thickness of the second conductor portion 103 can be equal to the thickness of the gate 108. The thickness of the second conductor portion 103 is greater than the thickness of the first conductor portion 102, and the thickness of the gate 108 is greater than the thickness of the first conductor portion 102.

[0049] In some embodiments, when the gate 108 is located on a side of the channel portion 107 away from the first doping portion 105, and the gate 108 is located on a side of the channel portion 107 away from the second doping portion 106, the thickness of the gate 108 is greater than or equal to 400 nanometers, and the thickness of the gate 108 is less than or equal to 600 nanometers, for example, it can be 420 nanometers, 450 nanometers, 480 nanometers, 500 nanometers, 520 nanometers, 550 nanometers, 580 nanometers, etc.

[0050] Please refer to Figures 1 to 4. In some embodiments, the array substrate 100 further includes a gate insulating layer 109 located between the first conductor portion 102 and the second conductor portion 103. The thickness of the gate insulating layer 109 is greater than or equal to 200 nanometers, and the thickness of the gate insulating layer 109 is less than or equal to 500 nanometers. For example, the thickness can be 220 nanometers, 240 nanometers, 250 nanometers, 260 nanometers, 280 nanometers, 300 nanometers, 320 nanometers, 340 nanometers, 350 nanometers, 360 nanometers, 380 nanometers, 400 nanometers, 420 nanometers, 440 nanometers, 450 nanometers, 460 nanometers, 480 nanometers, etc.

[0051] In some embodiments, the material of the gate insulating layer 109 can be selected from silicon oxide (eg, silicon dioxide, etc.).

[0052] In some embodiments, when the gate 108 is located on a side of the channel portion 107 away from the second conductor portion 103 , the gate insulation layer 109 includes a first opening, the gate 108 is located in the first opening, and the depth of the first opening is less than or equal to the thickness of the gate insulation layer 109 .

[0053] In some embodiments, when the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the conductor portion on the substrate 101, the gate 108 is located on the side of the channel portion 107 away from the first doped portion 105, and the gate 108 is located on the side of the channel portion 107 away from the second doped portion 106, the first opening can penetrate the gate insulating layer 109, and the thickness of the gate 108 can be greater than the depth of the first opening.

[0054] 1 to 4 , in some embodiments, the array substrate 100 further includes a buffer layer 110 located between the substrate 101 and the first conductor portion 102. When the thickness of the gate electrode 108 is greater than the depth of the first opening, the buffer layer 110 includes a second opening, the first opening is connected to the first opening, and the gate electrode 108 is located within the first opening and the second opening.

[0055] In some embodiments, the material of the buffer layer 110 may be selected from silicon oxide and / or silicon nitride.

[0056] 1 to 4 , in some embodiments, the buffer layer 110 includes a first buffer sublayer 111 and a second buffer sublayer 112. The second buffer sublayer 112 is located on a side of the first buffer sublayer 111 away from the substrate 101. The material of the first buffer sublayer 111 can be selected from silicon nitride. The thickness of the first buffer sublayer 111 is greater than or equal to 30 nanometers. The thickness of the first buffer sublayer 111 is less than or equal to 70 nanometers, for example, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, etc.

[0057] The material of the second buffer sublayer 112 can be selected from silicon oxide, the thickness of the second buffer sublayer 112 can be greater than or equal to 200 nanometers, and the thickness of the second buffer sublayer 112 can be less than or equal to 400 nanometers, for example, it can be 220 nanometers, 250 nanometers, 280 nanometers, 300 nanometers, 320 nanometers, 350 nanometers, 380 nanometers, etc.

[0058] In some embodiments, the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101, that is, the orthographic projection of the gate 108 on the substrate 101 and the orthographic projection of the first conductor portion 102 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101.

[0059] Alternatively, the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the second conductor portion 103 on the substrate 101, that is, the orthographic projection of the gate 108 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the channel portion 107 on the substrate 101.

[0060] Alternatively, referring to Figures 3 and 4, when the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the conductor portions on the substrate 101, the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101, and the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the second conductor portion 103 on the substrate 101.

[0061] Compared to a thin film transistor in which the channel portion 107 extends in a direction parallel to the substrate 101, when the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the second conductor portion 103 on the substrate 101 are located on the same side of the orthographic projection of the conductor portions on the substrate 101, and the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101, and the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the second conductor portion 103 on the substrate 101, it is beneficial to further reduce the size of the thin film transistor, and the width of the thin film transistor in the direction parallel to the substrate 101 can be reduced by 9 microns to 10 microns, which is beneficial to further improve the pixel density of a display panel using the array substrate 100.

[0062] In some embodiments, the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101, and when the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the second conductor portion 103 on the substrate 101, the thickness of the gate 108 is greater than or equal to 100 nanometers, and the thickness of the gate 108 is less than or equal to 200 nanometers, for example, can be 120 nanometers, 140 nanometers, 150 nanometers, 160 nanometers, 180 nanometers, 190 nanometers, etc.

[0063] In some embodiments, when the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101, and the orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the second conductor portion 103 on the substrate 101, the gate insulation layer 109 includes a first gate insulation sublayer and a second gate insulation sublayer, the first gate insulation sublayer is located between the gate 108 and the first conductor portion 102, and the second gate insulation sublayer is located between the second gate 108 and the second conductor portion 103.

[0064] Referring to Figures 1 to 4, in some embodiments, the active layer 104 further includes a third doping portion 115 located between the first doping portion 105 and the channel portion 107, the first doping portion 105 and the third doping portion 115 have a first doping element, and the concentration of the first doping element in the first doping portion 105 is greater than the concentration of the first doping element in the third doping portion 115.

[0065] In some embodiments, the material of the first doping part 105 and the third doping part 115 is polycrystalline silicon having the first doping element. The first doping element can be selected from N-type doping elements, such as phosphorus. The first doping part 105 and the third doping part 115 can be formed by blue laser annealing technology. During this process, amorphous silicon is transformed into polycrystalline silicon, and the N-type doping element in the first doping part 105 diffuses into the third doping part 115, thereby forming the first doping part 105 and the third doping part 115 with different doping element concentrations. While eliminating the original ion implantation step of forming the doping part, it is beneficial to reduce the edge electric field gradient of the first conductor part 102, reduce the leakage current and avoid the hot carrier effect, and improve the off-state current tail problem of the thin film transistor in the array substrate 100.

[0066] Referring to Figures 1 to 4, in some embodiments, the active layer 104 further includes a fourth doping portion 116 located between the second doping portion 106 and the channel portion 107, the second doping portion 106 and the fourth doping portion 116 have a second doping element, and the concentration of the second doping element in the second doping portion 106 is greater than the concentration of the second doping element in the fourth doping portion 116.

[0067] In some embodiments, the material of the second doping portion 106 and the fourth doping portion 116 is polycrystalline silicon having the second doping element. The second doping element can be selected from N-type doping elements, such as phosphorus. The second doping portion 106 and the fourth doping portion 116 can be formed by blue laser annealing technology. During this process, amorphous silicon is transformed into polycrystalline silicon, and the N-type doping element in the second doping portion 106 diffuses into the fourth doping portion 116, thereby forming the second doping portion 106 and the fourth doping portion 116 with different doping element concentrations. While eliminating the original ion implantation step of forming the doping portion, it is beneficial to reduce the edge electric field gradient of the second conductor portion 103, reduce leakage current generation and avoid hot carrier effects, and improve the off-state current tail problem of the thin film transistor in the array substrate 100.

[0068] In some embodiments, the first doping portion 105 and the second doping portion 106 may be formed simultaneously.

[0069] In some embodiments, the channel portion 107 may be made of undoped polysilicon, such as undoped low-temperature polysilicon. The channel portion 107 may be formed using a blue laser annealing technique. The channel portion 107, the first doped portion 105, and the second doped portion 106 may be formed simultaneously. The channel portion 107 is directly connected between the third doped portion 115 and the fourth doped portion 116.

[0070] In some embodiments, the gate insulating layer 109 includes a through hole, and the channel portion 107 is located in the through hole and connects the first doped portion 105 and the second doped portion 106 .

[0071] 1 and 3 , in some embodiments, the first doped portion 105 is disposed in the same layer as the first conductor portion 102 . An end surface of the first doped portion 105 close to the first conductor portion 102 contacts an end surface of the first conductor portion 102 close to the first doped portion 105 .

[0072] Referring to Figures 2 and 4, in some embodiments, the first doped portion 105 includes a first overlapping sub-portion 113, which contacts the first conductor portion 102 and is located on a side of the first conductor portion 102 away from the substrate 101. The first doped portion 105 may include only the first overlapping sub-portion 113, which contacts the first conductor portion 102 on a side closer to the substrate 101. Alternatively, the first doped portion 105 further includes a first non-overlapping sub-portion, which together with the first overlapping sub-portion 113 constitute the first doped portion 105, and the first non-overlapping sub-portion is disposed on the same layer as the first conductor portion 102.

[0073] Referring to Figures 1 to 4, in some embodiments, the array substrate 100 includes a first conductor layer 117, the first conductor portion is located in the first conductor layer 117, and the array substrate 100 includes a first region 118 and a second region 119. The first region 118 is located on a side of the second region 119 close to the first doped portion 105. The first conductor layer 117 in the second region 119 includes at least two stacked metal layers, and the number of metal layers in the first conductor layer 117 in the first region 118 is less than the number of metal layers in the first conductor layer 117 in the second region 119.

[0074] In some embodiments, the metal layer of the first conductor layer 117 in the second region 119 may include materials such as Mo, Ti, Cu, Al, and ITO. For example, the first conductor layer 117 in the second region 119 may be composed of three metal layers formed of Mo, Ti, and Cu, respectively; or the first conductor layer 117 in the second region 119 may be composed of three metal layers formed of Mo, Al, and Mo, respectively.

[0075] The metal layer of the first conductor layer 117 in the first region 118 may include materials such as Mo, Ti, and ITO. Compared to the first conductor layer 117 in the second region 119, the metal layer of the first conductor layer 117 in the first region 118 contains fewer metal materials, such as Cu and Al. For example, the first conductor layer 117 in the first region 118 may be composed of two metal layers, each composed of Mo and Ti. Alternatively, the first conductor layer 117 in the first region 118 may be composed of a single or two metal layers composed of Mo.

[0076] When the first doping portion 105, the second doping portion 106 and the channel portion 107 are formed by blue laser annealing technology, the blue laser causes damage to metal materials such as Cu and Al. Therefore, the metal layer formed by metal materials such as Cu and Al in the first conductor layer 117 in the first region 118 closer to the first doping portion 105 is removed, which is beneficial to improving the product quality of the thin film transistor of the array substrate 100.

[0077] In some embodiments, the width of the orthographic projection of the first region 118 on the substrate is greater than or equal to 30 microns, and the width of the orthographic projection of the first region 118 on the substrate is less than or equal to 50 microns. For example, the width of the orthographic projection of the first region 118 on the substrate 101 can be 32 microns, 35 microns, 38 microns, 40 microns, 42 microns, 45 microns, 48 ​​microns, etc. By providing the first region 118, the metal layer formed of metal materials such as Cu and Al in the first conductor layer 117 closer to the first doped portion 105 is removed, which helps improve the product quality of the thin film transistors of the array substrate 100.

[0078] In some embodiments, the first conductor portion 102 is at least partially located within the first region 118 .

[0079] In some embodiments, when the first doped portion 105 includes the first overlapping sub-portion 113, the first conductor portion 102 includes a first contact sub-portion that contacts the first overlapping sub-portion 113, and the orthographic projection of the first overlapping sub-portion 113 on the substrate 101 coincides with the orthographic projection of the first contact sub-portion on the substrate 101. The first contact sub-portion is located within the first region 118.

[0080] In some embodiments, the width of the orthographic projection of the first conductor portion 102 on the substrate 101 is greater than or equal to 5 microns, and the width of the orthographic projection of the first conductor portion 102 on the substrate 101 is less than or equal to 6 microns, for example, it can be 5.2 microns, 5.4 microns, 5.5 microns, 5.6 microns, 5.8 microns, etc.

[0081] In some embodiments, the width of the orthographic projection of the first doped portion 105 on the substrate 101 is greater than or equal to 2 microns, and the width of the orthographic projection of the first conductor portion 102 on the substrate 101 is less than or equal to 3 microns, for example, it can be 2.2 microns, 2.4 microns, 2.5 microns, 2.6 microns, 2.8 microns, etc.

[0082] In some embodiments, the sum of the widths of the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the first doped portion 105 on the substrate 101 is greater than or equal to 7 microns, and the sum of the widths of the orthographic projection of the first conductor portion 102 on the substrate 101 and the orthographic projection of the first doped portion 105 on the substrate 101 is less than or equal to 9 microns, for example, can be 7.2 microns, 7.4 microns, 7.5 microns, 7.6 microns, 7.8 microns, 8 microns, 8.2 microns, 8.4 microns, 8.5 microns, 8.6 microns, 8.8 microns, etc.

[0083] In some embodiments, the thickness of the first conductor portion 102 is greater than or equal to 50 nanometers, and the thickness of the first conductor portion 102 is less than or equal to 100 nanometers. For example, the thickness can be 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, 80 nanometers, 85 nanometers, 90 nanometers, 95 nanometers, etc.

[0084] Referring to Figures 1 to 4, in some embodiments, the array substrate 100 further includes a first routing portion 120 disposed on the same layer as the first conductor portion 102. The material of the first routing portion 120 is the same as that of the first conductor portion 102, and the first routing portion 120 and the first conductor portion 102 can be formed in the same manufacturing process. The thickness of the first routing portion 120 is the same as that of the first conductor portion 102. It is understood that when the ratio of the thickness of the first conductor portion 102 to the thickness of the first routing portion 120 is within a range of 95:100 to 105:100, the thickness of the first conductor portion 102 can be the same as that of the first routing portion 120.

[0085] In some embodiments, the thickness of the first doping portion 105 is greater than or equal to 20 nanometers, and the thickness of the first doping portion 105 is less than or equal to 50 nanometers, for example, it can be 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, etc.

[0086] 1 and 3 , in some embodiments, the second doped portion 106 is disposed in the same layer as the second conductor portion 103 . An end surface of the second doped portion 106 close to the second conductor portion 103 contacts an end surface of the second conductor portion 103 close to the second doped portion 106 .

[0087] 2 and 4 , in some embodiments, the second conductor portion 103 includes a second overlapping sub-portion 114, which contacts the second doped portion 106 and is located on a side of the second doped portion 106 away from the substrate 101. The second conductor portion 103 also includes a second non-overlapping sub-portion, which together with the second overlapping sub-portion 114 constitute the second conductor portion 103, and the second non-overlapping sub-portion and the second doped portion 106 are disposed on the same layer.

[0088] In some embodiments, the array substrate includes a second conductor layer, and the second conductor portion 103 is located in the second conductor layer. The second conductor layer may include at least two stacked metal layers. The metal layer of the second conductor layer may include materials such as Mo, Ti, Cu, Al, and ITO. For example, the second conductor layer may be composed of three metal layers formed of Mo, Ti, and Cu, respectively, or the second conductor layer may be composed of three metal layers formed of Mo, Al, and Mo, respectively.

[0089] The second conductor layer is formed after the second doped portion 106 is formed, that is, the second conductor portion 103 is formed after the blue laser annealing process. Therefore, the second conductor layer does not need to have a region with reduced metal materials, such as Cu, Al, etc.

[0090] In some embodiments, the second doped portion 106 includes a second contact sub-portion, the second contact sub-portion contacts the second overlapping sub-portion 114, and the orthographic projection of the second contact sub-portion on the substrate 101 coincides with the orthographic projection of the second overlapping sub-portion 114 on the substrate 101. The second doped portion 106 may include only the second contact sub-portion. Alternatively, the second doped portion 106 further includes a second non-contact sub-portion, the orthographic projection of the second non-contact sub-portion on the substrate 101 being located outside the orthographic projection of the second overlapping sub-portion 114 on the substrate 101.

[0091] In some embodiments, the thickness of the second conductor portion 103 is greater than or equal to 400 nanometers, and the thickness of the second conductor portion 103 is less than or equal to 600 nanometers. For example, the thickness can be 420 nanometers, 450 nanometers, 480 nanometers, 500 nanometers, 520 nanometers, 550 nanometers, 580 nanometers, etc.

[0092] In some embodiments, the array substrate 100 further includes a second routing portion disposed on the same layer as the second conductor portion 103. The second routing portion is made of the same material as the second conductor portion 103, and the second routing portion and the second conductor portion 103 can be formed in the same manufacturing process. The thickness of the second routing portion is the same as the thickness of the second conductor portion 103. It is understood that when the ratio of the thickness of the second conductor portion 103 to the thickness of the second routing portion is within a range of 95:100 to 105:100, the thickness of the second conductor portion 103 can be the same as the thickness of the second routing portion.

[0093] In some embodiments, the thickness of the second doping portion 106 is greater than or equal to 20 nanometers, and the thickness of the second doping portion 106 is less than or equal to 50 nanometers, for example, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, etc.

[0094] In some embodiments, the substrate 101 may be a rigid substrate, such as a glass substrate; or the substrate 101 may be a flexible substrate, such as a polyimide substrate. When the substrate 101 is a flexible substrate, the substrate 101 may be formed of multiple sub-substrates made of the same material, such as polyimide, with adjacent sub-substrates bonded together by adhesive sub-layers.

[0095] The array substrate 100 provided in this embodiment reduces the length of the channel portion 107 of the active layer 104 in a direction parallel to the substrate 101 by arranging the first doping portion 105 and the second doping portion 106 of the active layer 104 in different layers, and connects the channel portion 107 therebetween, thereby reducing the size of the thin film transistors in the array substrate 100, and facilitating improving the pixel density of the display panel having the array substrate 100.

[0096] Referring to FIG. 5 and FIG. 6 a to FIG. 6 h , the present embodiment further provides a method for manufacturing an array substrate, including:

[0097] S100 , providing a substrate 101 .

[0098] S200 , forming a first conductor portion 102 on one side of the substrate 101 .

[0099] S300 , forming an active layer 104 on one side of the substrate 101 , wherein the active layer 104 and the first conductor portion 102 are located on the same side of the substrate 101 .

[0100] S400 , forming a second conductor portion 103 on a side of the first conductor portion 102 away from the substrate 101 .

[0101] The active layer 104 includes a first doped portion 105, a second doped portion 106 and a channel portion 107. The second doped portion 106 is located on a side of the first doped portion 105 away from the substrate 101. The channel portion 107 is connected between the first doped portion 105 and the second doped portion 106. The first conductor portion 102 is in contact with the first doped portion 105, and the second conductor portion 103 is in contact with the second doped portion 106.

[0102] Please refer to FIG. 6 a . In some embodiments, after step S100 and before step S200 , the process further includes:

[0103] S500 , forming a buffer layer 110 on one side of the substrate 101 .

[0104] The buffer layer 110 is located between the first conductor portion 102 and the substrate 101 . That is, the first conductor portion 102 is formed on a side of the buffer layer 110 away from the substrate 101 .

[0105] In some embodiments, step S500 includes:

[0106] S510 , forming a first buffer sublayer 111 on one side of the substrate 101 .

[0107] S520 , forming a second buffer sublayer 112 on a side of the first buffer sublayer 111 away from the substrate 101 .

[0108] The thickness and material of the first buffer sublayer 111 and the second buffer sublayer 112 have been described in detail in the aforementioned array substrate and will not be repeated here.

[0109] Referring to FIG. 6b , in some embodiments, step S200 includes:

[0110] S210 , forming a first conductive material layer on one side of the substrate 101 .

[0111] In some embodiments, the first conductive material layer may be formed by stacking at least two metal material layers.

[0112] S220 , patterning the first conductor material layer to form a first conductor layer 117 , where the first conductor layer 117 includes the first conductor portion 102 .

[0113] In some embodiments, the array substrate includes a first area 118 and a second area 119, the first area 118 is located on a side of the second area 119 close to the first doped portion 105, the first conductor layer 117 in the second area 119 includes at least two stacked metal layers, and when the number of metal layers in the first conductor layer 117 in the first area 118 is less than the number of metal layers in the first conductor layer 117 in the second area 119, step S220 includes:

[0114] S221 , forming a first photoresist layer on a side of the first conductive material layer away from the substrate 101 .

[0115] S222 , patterning the first photoresist layer to form a first photoresist region, a second photoresist region, and a third photoresist region.

[0116] The photoresist in the first photoresist region is removed, and the thickness of the photoresist in the second photoresist region is smaller than the thickness of the photoresist in the third photoresist region.

[0117] S223 , removing the first conductive material layer in an area corresponding to the first photoresist area.

[0118] S224 , removing the photoresist in the second photoresist region.

[0119] S225 , removing at least one metal material layer in the first conductive material layer in the region corresponding to the second photoresist region to form the first conductive layer 117 in the first region 118 .

[0120] In some embodiments, the metal material layer of the first conductor layer 117 removed in the first region 118 may be a Cu or Al material layer.

[0121] S226 , removing the photoresist in the third photoresist region to form the first conductive layer 117 in the second region.

[0122] The first conductor portion 102 is at least partially located in the first region 118 .

[0123] The structure, thickness, material, etc. of the first conductor portion 102 have been described in detail in the aforementioned array substrate and will not be repeated here.

[0124] Referring to FIG. 6 c to FIG. 6 f , in some embodiments, step S300 includes:

[0125] S310 , forming a first doping material layer 121 at one end of the first conductor portion 102 along a direction parallel to the substrate 101 .

[0126] S320 , forming a gate insulating layer 109 on a side of the first conductor portion 102 away from the substrate 101 , wherein the gate insulating layer 109 includes a through hole.

[0127] S330 , forming a channel material layer 122 in the through hole, wherein the channel material layer 122 is connected to one end of the first doping material layer 121 .

[0128] S340 , forming a second doping material layer 123 on a side of the insulating material layer away from the substrate 101 , wherein the channel material layer 122 is connected to one end of the second doping material layer 123 .

[0129] S350 , performing blue laser annealing technology on the first doping material layer 121 , the second doping material layer 123 , and the channel material layer 122 to form the first doping portion 105 , the second doping portion 106 , the third doping portion 115 , the fourth doping portion 116 and the channel portion 107 .

[0130] Through blue laser annealing technology, the first doping element in the first doping material layer 121 diffuses into the channel material layer 122 connected to one end of the first doping material layer 121, and the second doping element in the second doping material layer 123 diffuses into the channel material layer 122 connected to one end of the second doping material layer 123, so that the end of the first channel material layer 122 connected to the first doping material layer 121 at least partially becomes the third doping part 115, and the end of the second channel material layer 122 connected to the second doping material layer 123 at least partially becomes the fourth doping part 116.

[0131] In some embodiments, the thickness of the channel material layer 122 is greater than or equal to 200 nanometers, and the thickness of the channel material layer 122 is less than or equal to 500 nanometers. For example, it can be 220 nanometers, 250 nanometers, 280 nanometers, 300 nanometers, 320 nanometers, 350 nanometers, 380 nanometers, 400 nanometers, 420 nanometers, 450 nanometers, 480 nanometers, etc.

[0132] In some embodiments, the thickness of the channel material layer 122 is greater than or equal to the thickness of the gate insulation layer 109 .

[0133] In some embodiments, the thickness of the channel material layer 122 is equal to the sum of the thickness of the gate insulation layer 109 and the thickness of the second doping material layer 123 .

[0134] The structures and materials of the first doping portion 105 , the second doping portion 106 , the third doping portion 115 , the fourth doping portion 116 and the channel portion 107 have been described in the aforementioned array substrate and will not be repeated here.

[0135] Referring to FIG. 6g to FIG. 6h , in some embodiments, the method for manufacturing the array substrate further includes:

[0136] S600 , forming a gate 108 on a side of the channel portion 107 away from the first conductor portion 102 and / or the second conductor portion 103 .

[0137] In some embodiments, step S600 is performed after step S300 and before step S400, and step S600 includes:

[0138] S610 , forming a first opening in the gate insulating layer 109 , where the first opening is located on a side of the channel portion 107 away from the first conductor portion 102 and / or the second conductor portion 103 .

[0139] S620 , forming the gate 108 in the first opening.

[0140] In some embodiments, the thickness of the gate 108 is greater than the thickness of the gate insulating layer 109 , and step S16 includes:

[0141] S630, forming a first opening in the gate insulating layer 109 and forming a second opening in the second buffer sublayer 112, wherein the first opening and the second opening are located on a side of the channel portion 107 away from the first conductor portion 102 and / or the second conductor portion 103, and the first opening is connected to the second opening.

[0142] S640 , forming the gate 108 in the first opening and the second opening.

[0143] In some embodiments, step S16 is performed together with step S320. Specifically, step S320 includes:

[0144] S321 . Form a first gate insulating sublayer on a side of the first conductor portion 102 away from the substrate 101 .

[0145] S322 , forming a second gate insulating sublayer on a side of the first gate insulating sublayer away from the substrate 101 .

[0146] S333 , forming a through hole penetrating the first gate insulating sublayer and the second gate insulating sublayer.

[0147] After step S321 and before step S322, step S600 includes:

[0148] S650 , forming a gate 108 on a side of the first gate insulating sublayer away from the substrate 101 .

[0149] The orthographic projection of the gate 108 on the substrate 101 at least partially overlaps with the orthographic projection of the first conductor portion 102 on the substrate 101 and / or the orthographic projection of the second conductor portion 103 on the substrate 101 .

[0150] The second gate insulating sublayer covers the gate 108 .

[0151] The manufacturing method of the array substrate provided by an embodiment of the present invention reduces the length of the channel portion 107 of the active layer 104 in a direction parallel to the substrate 101 by arranging the first doping portion 105 and the second doping portion 106 of the active layer 104 in different layers and connecting the channel portion 107 therebetween, thereby reducing the size of the thin film transistors in the array substrate, which is beneficial to improving the pixel density of the display panel having the array substrate.

[0152] Referring to FIG. 7 and FIG. 8 , an embodiment of the present invention further provides a display panel 10 , including the array substrate 100 as described above.

[0153] The specific structure of the array substrate 100 can be found in any of the above-mentioned embodiments and drawings of the array substrate, and will not be described in detail here.

[0154] In some embodiments, the display panel 10 may be a liquid crystal display panel or a self-luminous display panel.

[0155] Referring to FIG. 7 , when the display panel 10 is a liquid crystal display panel, the display panel 10 further includes a color filter substrate 12 disposed opposite the array substrate 100, a liquid crystal layer 13 located between the color filter substrate 12 and the array substrate 100, a first polarizer layer 14 located on a side of the array substrate 100 away from the color filter substrate 12, and a second polarizer layer 15 located on a side of the color filter substrate 12 away from the array substrate 100. When the display panel 10 is a liquid crystal display panel, the display panel 10 further includes a backlight assembly 16. The backlight assembly 16 is located on a side of the first polarizer layer 14 away from the array substrate 100, or on a side of the second polarizer layer 15 away from the color filter substrate 12.

[0156] Referring to FIG. 8 , when the display panel 10 is a self-luminous display panel, the display panel 10 further includes a light-emitting device layer 22 located on a side of the array substrate 100 away from the substrate 101. The light-emitting device layer 22 includes a plurality of light-emitting devices. These light-emitting devices may include OLED (Organic Light-Emitting Diode) materials, or may include Micro LEDs or Mini LEDs, without specific limitations herein. When the display panel 10 is a self-luminous display panel, the display panel 10 further includes an encapsulation layer 23 located on a side of the light-emitting device layer 22 away from the array substrate 100. The encapsulation layer 23 may include a first inorganic encapsulation sublayer, a first organic encapsulation sublayer, and a second inorganic encapsulation sublayer. When the display panel 10 is a self-luminous display panel, the display panel 10 further includes a cover layer 24 located on a side of the encapsulation layer 23 away from the array substrate 100. When the display panel 10 is a self-luminous display panel, the display panel 10 further includes a polarizing layer 25 located between the encapsulation layer 23 and the cover layer 24.

[0157] The display panel 10 can be applied to display terminals such as mobile phones, tablets, televisions, computers, virtual reality display devices, and augmented reality display devices.

[0158] An embodiment of the present invention discloses an array substrate and a display panel; the array substrate includes a substrate, a first conductor portion located on one side of the substrate, a second conductor portion located on a side of the first conductor portion away from the substrate, and an active layer, the active layer includes a first doped portion, a second doped portion and a channel portion, the second doped portion is located on a side of the first doped portion away from the substrate, the channel portion is connected between the first doped portion and the second doped portion, the first conductor portion is in contact with the first doped portion, and the second conductor portion is in contact with the second doped portion. The present invention reduces the length of the channel portion of the active layer in a direction parallel to the substrate by arranging the first doped portion and the second doped portion of the active layer in different layers and connecting the channel portion between the two, thereby reducing the size of the thin film transistors in the array substrate, which is beneficial to improving the pixel density of the display panel having the array substrate.

[0159] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. An array substrate, wherein: include: substrate; a first conductor portion, located on one side of the substrate; a second conductor portion, located on a side of the first conductor portion away from the substrate; an active layer comprising a first doping portion, a second doping portion, and a channel portion, wherein the second doping portion is located on a side of the first doping portion away from the substrate, and the channel portion is connected between the first doping portion and the second doping portion; The first conductor portion is in contact with the first doped portion, and the second conductor portion is in contact with the second doped portion.

2. The array substrate according to claim 1, wherein: The orthographic projection of the first doped portion on the substrate at least partially overlaps with the orthographic projection of the second doped portion on the substrate, and the orthographic projection of the first conductor portion on the substrate at least partially overlaps with the orthographic projection of the second conductor portion on the substrate.

3. The array substrate according to claim 2, wherein: The array substrate further includes a gate located between the first conductor portion and the second conductor portion, the gate located on a side of the channel portion away from the first doping portion, and the gate located on a side of the channel portion away from the second doping portion.

4. The array substrate according to claim 3, wherein: The gate is located on a side of the channel portion away from the second doped portion, and a thickness of the second conductor portion is equal to a thickness of the gate.

5. The array substrate according to claim 4, wherein: The thickness of the gate is greater than or equal to 400 nanometers, and the thickness of the gate is less than or equal to 600 nanometers.

6. The array substrate according to claim 2, wherein: The array substrate further includes a gate located between the first conductor portion and the second conductor portion, an orthographic projection of the gate on the substrate at least partially overlapping with an orthographic projection of the first conductor portion on the substrate, and an orthographic projection of the gate on the substrate at least partially overlapping with an orthographic projection of the second conductor portion on the substrate.

7. The array substrate according to claim 6, wherein: The thickness of the gate is greater than or equal to 100 nanometers, and the thickness of the gate is less than or equal to 200 nanometers.

8. The array substrate according to claim 1, wherein: The first doped portion and the first conductor portion are provided in the same layer.

9. The array substrate according to claim 1, wherein: The first doping portion includes a first overlapping sub-portion, the first overlapping sub-portion is in contact with the first conductor portion, and the first overlapping sub-portion is located on a side of the first conductor portion away from the substrate.

10. The array substrate according to claim 1, wherein: The array substrate includes a first conductor layer, the first conductor portion is located in the first conductor layer, the array substrate includes a first area and a second area, the first area is located on a side of the second area close to the first doped portion; The first conductor layer in the second area includes at least two stacked metal layers, and the number of metal layers in the first conductor layer in the first area is less than the number of metal layers in the second area.

11. The array substrate according to claim 10, wherein: The width of the orthographic projection of the first region on the substrate is greater than or equal to 30 micrometers, and the width of the orthographic projection of the first region on the substrate is less than or equal to 50 micrometers.

12. The array substrate according to claim 1, wherein: The second doped portion and the second conductor portion are provided in the same layer.

13. The array substrate according to claim 1, wherein: The second conductor portion includes a second overlapping sub-portion, the second overlapping sub-portion is in contact with the second doped portion, and the second overlapping sub-portion is located on a side of the second doped portion away from the substrate.

14. The array substrate according to claim 1, wherein: The active layer further includes a third doping portion located between the first doping portion and the channel portion, the first doping portion and the third doping portion having a first doping element, and a concentration of the first doping element in the first doping portion is greater than a concentration of the first doping element in the third doping portion; The active layer further includes a fourth doping portion located between the second doping portion and the channel portion, the second doping portion and the fourth doping portion have a second doping element, and a concentration of the second doping element in the second doping portion is greater than a concentration of the second doping element in the fourth doping portion.

15. The array substrate according to claim 1, wherein: The first conductor portion is one of a source electrode and a drain electrode of the array substrate, and the second conductor portion is the other of the source electrode and the drain electrode of the array substrate.

16. A display panel, wherein: The array substrate includes: substrate; a first conductor portion, located on one side of the substrate; a second conductor portion, located on a side of the first conductor portion away from the substrate; an active layer comprising a first doping portion, a second doping portion, and a channel portion, wherein the second doping portion is located on a side of the first doping portion away from the substrate, and the channel portion is connected between the first doping portion and the second doping portion; The first conductor portion is in contact with the first doped portion, and the second conductor portion is in contact with the second doped portion.

17. The display panel according to claim 16, wherein: The orthographic projection of the first doped portion on the substrate at least partially overlaps with the orthographic projection of the second doped portion on the substrate, and the orthographic projection of the first conductor portion on the substrate at least partially overlaps with the orthographic projection of the second conductor portion on the substrate.

18. The display panel according to claim 17, wherein: The array substrate further includes a gate located between the first conductor portion and the second conductor portion, the gate located on a side of the channel portion away from the first doping portion, and the gate located on a side of the channel portion away from the second doping portion.

19. The display panel according to claim 17, wherein: The array substrate further includes a gate located between the first conductor portion and the second conductor portion, an orthographic projection of the gate on the substrate at least partially overlapping with an orthographic projection of the first conductor portion on the substrate, and an orthographic projection of the gate on the substrate at least partially overlapping with an orthographic projection of the second conductor portion on the substrate.

20. The display panel according to claim 16, wherein The array substrate includes a first conductor layer, the first conductor portion is located in the first conductor layer, the array substrate includes a first area and a second area, the first area is located on a side of the second area close to the first doped portion; The first conductor layer in the second area includes at least two stacked metal layers, and the number of metal layers in the first conductor layer in the first area is less than the number of metal layers in the second area.

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