Memory capacity adjustment method and apparatus, and server, electronic device and storage medium

Abstract

The embodiments of the present application relate to the technical field of computer systems and storage. Provided are a memory capacity adjustment method and apparatus, and a server, an electronic device and a storage medium. The method is applied to a server, wherein the server is provided with at least one central processing unit; the central processing unit is provided with a plurality of memory slots; the memory slots are used for allowing memory banks to be installed and connected therein; the plurality of memory slots are connected to a communication protocol interface of a baseboard management controller by means of at least one expansion chip; the plurality of memory slots and the expansion chip have different protocol addresses; and the plurality of memory slots correspond to pins of the expansion chip on a one-to-one basis. The method comprises: reading memory setting information; on the basis of a target protocol address value, determining a target pin of an expansion chip; on the basis of a state setting value, setting a level state of the target pin; and on the basis of the level state of the target pin, setting a slot voltage of a memory slot corresponding to the target pin, wherein the slot voltage is used for adjusting the usage state of a memory bank. By means of the embodiments of the present application, the memory capacity can be dynamically adjusted.

Description

Memory capacity adjustment method, device, server, electronic device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 30, 2024, with application number 202410129069.8 and titled “Memory Capacity Adjustment Method, Device, Server, Electronic Device and Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer systems and storage technologies, and in particular to a memory capacity adjustment method, a memory capacity adjustment device, a server, an electronic device, and a storage medium. Background Art

[0004] In computer systems, memory is an essential physical device in any computer product. The size of memory in a server affects operational efficiency. Therefore, to improve efficiency, maximum memory configurations are often adopted, with servers in data centers typically configured with maximum memory. However, this configuration wastes memory, increases power consumption, and reduces memory lifespan. Furthermore, when a partial memory error occurs, isolation can only be achieved by physically replacing the entire unit; dynamic isolation of individual memory modules is not possible.

[0005] Summary of the Invention

[0006] In view of the above problems, embodiments of the present application are proposed to provide a memory capacity adjustment method, a memory capacity adjustment device, a server, an electronic device and a storage medium that overcome the above problems or at least partially solve the above problems.

[0007] To solve the above problems, in a first aspect of the present application, an embodiment of the present application discloses a memory capacity adjustment method, which is applied to a server. The server is provided with at least one central processing unit (CPU), and the CPU is provided with multiple memory slots. The memory slots are used to install memory modules. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one with the pins of the expansion chip. The method includes:

[0008] Read memory setting information, which includes target protocol address value and status setting value;

[0009] Determine the target pin of the expansion chip based on the target protocol address value;

[0010] Set the level state of the target pin according to the state setting value;

[0011] The slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0012] Optionally, the state setting value is a polarized value;

[0013] The polarized value is high or low.

[0014] Optionally, determining the target pin of the expansion chip according to the target protocol address value includes:

[0015] After the target protocol address value is obtained, the target pin of the expansion chip is determined according to the matching condition between the target protocol address value and the protocol address corresponding to each pin of the expansion chip.

[0016] Optionally, setting the level state of the target pin according to the state setting value includes:

[0017] Set the level of the target pin of the expansion chip to correspond to the state setting value.

[0018] Optionally, the level state of the target pin is initially in a high level state; and the step of setting the level state of the target pin according to the state setting value includes:

[0019] In response to the state setting value being a preset high level setting value, maintaining the level state of the target pin;

[0020] In response to the state setting value being a preset low level setting value, the level state of the target pin is switched.

[0021] Optionally, the method further comprises:

[0022] Based on the usage status of all memory modules in the entire server, determine the number of memory modules in use and adjust the memory capacity.

[0023] Optionally, the voltage of a single slot represents the usage status of the corresponding memory module.

[0024] Optionally, the slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin, including: based on the level state of the target pin, the level state of the target pin is synchronously adjusted with the slot voltage of the corresponding memory slot, so that the slot voltage of the memory slot corresponding to the target pin is adjusted or maintained in the default state.

[0025] Optionally, the step of setting a slot voltage of a memory slot corresponding to the target pin according to a level state of the target pin includes:

[0026] According to the level state of the target pin, turning on the slot voltage of the memory slot corresponding to the target pin to enable the memory module; and / or;

[0027] According to the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is cut off to shut down the memory module.

[0028] Optionally, a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground wire;

[0029] The steps of conducting the memory slot and the memory module corresponding to the target pin according to the level state of the target pin include:

[0030] In response to the target pin being in a high level state, connecting the target pin and the connection circuit of the memory slot corresponding to the target pin to a voltage terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to a preset power supply, and the slot voltage of the memory slot corresponding to the target pin is turned on;

[0031] Correspondingly, the step of cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0032] In response to the target pin's level state being a low level state, the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the ground terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the preset power ground line, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0033] Optionally, the baseboard management controller controls the memory capacity through a management page or intelligent platform management interface instructions.

[0034] Optionally, the baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to a memory bar or multiple memory slots; and the step of reading memory setting information includes:

[0035] In response to a setting operation on a state setting control;

[0036] Determining a target protocol address value from protocol addresses of a plurality of memory slots according to a setting operation; and determining a state setting value;

[0037] The read status setting value and target protocol address value are memory setting information.

[0038] Optionally, the state setting control is an enable or disable control button.

[0039] Optionally, the step of reading memory setting information includes:

[0040] Reading intelligent platform management interface instructions from the baseboard management controller;

[0041] Parsing the target bytes of the intelligent platform management interface instruction to determine the state setting value and the target protocol address value;

[0042] The read status setting value and target protocol address value are memory setting information.

[0043] Optionally, when the user needs to perform remote control, relevant setting instructions are sent to the baseboard management controller through the intelligent platform management interface.

[0044] Optionally, when there are multiple target protocol address values, the step of determining the target pin of the expansion chip according to the target protocol address value includes:

[0045] Determine whether the target protocol address value is the last target protocol address value;

[0046] In response to the target protocol address value not being the last target protocol address value, the target pin of the expansion chip is determined according to the target protocol address value, and the target protocol address value is updated until the target protocol address value is the last target protocol address value.

[0047] Optionally, the operation of controlling the slot voltage of the memory slot is performed when the server is powered off.

[0048] In a second aspect of the present invention, an embodiment of the present invention discloses a server, wherein the server is provided with at least one central processing unit (CPU), the CPU is provided with multiple memory slots, the memory slots are used to install memory modules, the multiple memory slots are connected to a communication protocol interface of a baseboard management controller (BMC) via at least one expansion chip, the multiple memory slots and the expansion chip have different protocol addresses, and the multiple memory slots correspond one-to-one to pins of the expansion chip.

[0049] The baseboard management controller reads memory setting information, where the memory setting information includes a target protocol address value and a state setting value;

[0050] The baseboard management controller determines the target pin of the expansion chip according to the target protocol address value;

[0051] The central processing unit sets the level state of the target pin according to the state setting value;

[0052] The CPU sets the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0053] In a third aspect of the application, an embodiment of the present application discloses a memory capacity adjustment device, which is applied to a server. The server is provided with at least one central processing unit (CPU), and the CPU is provided with multiple memory slots. The memory slots are used to install memory modules. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one with the pins of the expansion chip. The device includes:

[0054] A reading module is used to read memory setting information, the memory setting information including a target protocol address value and a state setting value;

[0055] The target pin determination module is used to determine the target pin of the expansion chip according to the target protocol address value;

[0056] A first setting module, configured to set a level state of a target pin according to a state setting value;

[0057] The second setting module is used to control the connection state between the memory slot corresponding to the target pin and the memory stick according to the level state of the target pin, so as to adjust the memory capacity.

[0058] In the fourth aspect of the present application, an embodiment of the present application discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the steps of the above memory capacity adjustment method are implemented.

[0059] In the fifth aspect of the present application, an embodiment of the present application discloses a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above memory capacity adjustment method are implemented.

[0060] The embodiments of the present application include the following advantages:

[0061] The embodiment of the present application is provided with a plurality of memory slots through a central processing unit, and the memory slots are used to install memory sticks. The plurality of memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the plurality of memory slots and the expansion chip have different protocol addresses; the plurality of memory slots correspond to the pins of the expansion chip one-to-one; the memory setting information is read, and the memory setting information includes a target protocol address value and a status setting value; the target pin of the expansion chip is determined according to the target protocol address value; the level state of the target pin is set according to the status setting value; the slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin, and the slot voltage is used to adjust the usage state of the memory stick. By physically designing the pins of the expansion chip and the memory slot voltage in the server to be physically linked, the memory slot voltage is controlled by reading and setting the level state value of the pins of the expansion chip, and the usage state of the memory stick is adjusted, thereby controlling the memory capacity of the server and the power consumption of the entire server. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a flowchart of a memory capacity adjustment method according to an embodiment of the present invention;

[0063] FIG2 is a flowchart of another embodiment of a memory capacity adjustment method of the present application;

[0064] FIG3 is a schematic diagram of the structural connection of an application server of a memory capacity adjustment method of the present application;

[0065] FIG4 is a schematic diagram of a structural connection of a slot voltage conduction in a memory capacity adjustment method of the present application;

[0066] FIG5 is a schematic diagram of the structural connection of a slot voltage cutoff of a memory capacity adjustment method of the present application;

[0067] FIG6 is a flowchart of an example of a method for adjusting memory capacity according to the present invention;

[0068] FIG7 is a swim lane diagram 1 of an example of a memory capacity adjustment method of the present application;

[0069] FIG8 is a second swim-lane diagram of an example of a memory capacity adjustment method of the present application;

[0070] FIG9 is a structural block diagram of an embodiment of a memory capacity adjustment device of the present application;

[0071] FIG10 is a structural block diagram of a server embodiment of the present application;

[0072] FIG11 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0073] FIG12 is a structural block diagram of a storage medium provided in an embodiment of the present application. Specific embodiments

[0074] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0075] 1 , a flowchart of an embodiment of a memory capacity adjustment method of the present application is shown. The memory capacity adjustment method is applied to a server. The server is provided with at least one central processing unit (CPU). The CPU is provided with multiple memory slots, each of which is used to install memory modules. The multiple memory slots are connected to a communication protocol interface of a baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one to the pins of the expansion chip. The memory capacity adjustment method may specifically include the following steps:

[0076] Step 101, read memory setting information, the memory setting information includes a target protocol address value and a state setting value;

[0077] In the embodiment of the present application, when the memory capacity needs to be adjusted, memory setting information can be read. The memory setting information includes a target protocol address value and a state setting value. The target protocol address value corresponds to a pin of the expansion chip. The state setting value can be a polarized value, such as a high level or a low level, which is not limited in the embodiment of the present application.

[0078] Step 102, determining the target pin of the expansion chip according to the target protocol address value;

[0079] After obtaining the target protocol address value, firstly, the target pin of the expansion chip is determined according to the matching condition between the target protocol address value and the protocol address corresponding to each pin of the expansion chip.

[0080] Step 103, setting the level state of the target pin according to the state setting value;

[0081] Then, the level of the target pin of the expansion chip can be set to a state corresponding to the state setting value, thereby adjusting the level state of the target pin.

[0082] Step 104 : setting a slot voltage of a memory slot corresponding to the target pin according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0083] Based on the target pin's voltage level, the voltage of the corresponding memory slot can be adjusted synchronously with the target pin's voltage level, either adjusting the voltage or maintaining the default voltage. The voltage of a single slot represents the usage status of a memory module. Therefore, adjusting the voltage of a memory slot also adjusts the usage status of the memory module. Based on the usage status of all memory modules in the server, the number of available memory modules can be determined, allowing for adjustment of memory capacity.

[0084] The embodiment of the present application is provided with a plurality of memory slots through a central processing unit, and the memory slots are used to install memory sticks. The plurality of memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the plurality of memory slots and the expansion chip have different protocol addresses; the plurality of memory slots correspond to the pins of the expansion chip one-to-one; the memory setting information is read, and the memory setting information includes a target protocol address value and a status setting value; the target pin of the expansion chip is determined according to the target protocol address value; the level state of the target pin is set according to the status setting value; the slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin, and the slot voltage is used to adjust the usage state of the memory stick. By physically designing the pins of the expansion chip and the memory slot voltage in the server to be physically linked, the memory slot voltage is controlled by reading and setting the level state value of the pins of the expansion chip, and the usage state of the memory stick is adjusted, thereby controlling the memory capacity of the server and the power consumption of the entire server.

[0085] Referring to Figure 2, a step flow chart of another memory capacity adjustment method embodiment of the present application is shown. The memory capacity adjustment method is applied to a server. The server is provided with at least one central processing unit, and the central processing unit is provided with multiple memory slots. The memory slots are used to install memory sticks. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the multiple memory slots and the expansion chip have different protocol addresses.

[0086] In an embodiment of the present application, the expansion chip can be multiple expansion chips, which are determined according to needs, and the number of pins of each expansion chip is also selected based on actual conditions. This embodiment of the present application is not limited. The expansion chip can be a GPIO (General-purpose input / output) interface expansion chip. The communication protocol can be the I2C (Inter-Integrated Circuit) protocol. The specific connection relationship can be referred to in Figure 3. The server motherboard introduces two GPIO expansion chips with 16 GPIO pins to provide 32 GPIO control pins. Each GPIO control pin is physically connected to the motherboard memory slot; that is, each GPIO control pin is connected to the memory of the corresponding memory slot. The I2C address of the above-mentioned GPIO expansion chip can be physically linked to the I2C bus of the processor and a unique I2C address can be set. A GPIO expansion chip requires a separate I2C address and cannot have the same I2C address as other devices. The GPIO pins of the GPIO expansion chip must be physically designed with the memory voltage of the memory slot, that is, a GPIO high level turns on the voltage input, and a GPIO low level turns off the voltage and turns on the circuit.

[0087] The memory capacity adjustment method may specifically include the following steps:

[0088] Step 201, read memory setting information, the memory setting information includes a target protocol address value and a state setting value;

[0089] In the embodiment of the present application, the memory setting information can be read in different ways, and the pins and setting states that need to be set can be determined based on the target protocol address value and state setting value in the memory setting information.

[0090] In some optional embodiments of the present application, the baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to a memory bar or multiple memory slots; the step of reading memory setting information includes: responding to a setting operation for the status setting control; determining a target protocol address value from the protocol addresses of multiple memory slots based on the setting operation; and determining a status setting value; reading the status setting value and the target protocol address value as memory setting information.

[0091] In the embodiment of the present application, the baseboard management controller may correspond to a management page, which may include a memory bar or memory slot status setting control, for example, an enable or disable control button for the status setting control.

[0092] When a user operates a status setting control, the device can respond to the setting operation on the status setting control. Based on the memory bank or memory slot selected in the setting operation, the protocol address corresponding to the selected memory bank or memory slot is determined from the protocol addresses of the multiple memory slots as the target protocol address value. Furthermore, the status setting value is determined based on the setting content of the setting operation.

[0093] Finally, the state setting value and the target protocol address value are used to determine the memory setting information and read to obtain the memory setting information.

[0094] In other optional embodiments of the present application, the step of reading memory setting information includes: reading an intelligent platform management interface instruction from a baseboard management controller; parsing the target bytes of the intelligent platform management interface instruction to determine a status setting value and a target protocol address value; and reading the status setting value and the target protocol address value as memory setting information.

[0095] In an embodiment of the present application, when a user needs to perform remote control, the relevant setting instructions can be sent to the baseboard management controller through the intelligent platform management interface. Therefore, the intelligent platform management interface instructions can be read from the baseboard management controller. The specific message position in the read intelligent platform management interface instruction is parsed. For example, the command format of the intelligent platform management interface instruction is ipmitool raw 0x32 0x71 0x06 0x00 0x01; wherein, the following two bytes can be parsed. 0x00 represents the first GPIO of the first GPIO expansion chip, 0x01 represents setting it to a high state, i.e., the memory voltage is turned on, and if it is 0x0, it means turning off the memory voltage turn-on function; 0x10 represents the first GPIO of the second GPIO expansion chip, 0x01 represents setting it to a high state, i.e., the memory voltage is turned on, and if it is 0x0, it means turning off the memory voltage turn-on function. The state setting value and the target protocol address value are determined based on the parsed message content; the memory setting information is obtained by reading the state setting value and the target protocol address value.

[0096] Step 202: Determine the target pin of the expansion chip based on the target protocol address value;

[0097] According to the target protocol address value, query the pin of the corresponding expansion chip, which is the target pin of the expansion chip.

[0098] In some optional embodiments of the present application, when there are multiple target protocol address values, the step of determining the target pin of the expansion chip based on the target protocol address value includes: judging whether the target protocol address value is the last target protocol address value; in response to the target protocol address value not being the last target protocol address value, determining the target pin of the expansion chip based on the target protocol address value, and updating the target protocol address value until the target protocol address value is the last target protocol address value.

[0099] In addition, when there are multiple target protocol address values, it is necessary to set multiple memory sticks at the same time. At this time, it is possible to determine whether the target protocol address value is the last target protocol address value. When the target protocol address value is not the last target protocol address value, the step of determining the target pin of the expansion chip based on the target protocol address value can be first performed to determine the target pin of the expansion chip corresponding to the current target protocol address value. Then, the next target protocol address value is updated, and then the target pin of the new expansion chip is determined based on the updated target protocol address value. This cycle is repeated until the target pin of the expansion chip corresponding to the last target protocol address value is also determined, and the target pins of all expansion chips are used as the target pins of the expansion chips that need to be processed.

[0100] Step 203, setting the level state of the target pin according to the state setting value;

[0101] The level state of the target pin can be set according to the state setting value so that the level state of the target pin is consistent with the state setting value. If the state setting value is a high level, the level state of the target pin is set to a high level.

[0102] In some optional embodiments of the present application, the level state of the target pin is initially in a high level state; the step of setting the level state of the target pin according to the state setting value includes: maintaining the level state of the target pin in response to the state setting value being a preset high level setting value; switching the level state of the target pin in response to the state setting value being a preset low level setting value.

[0103] In an embodiment of the present application, the level state of the target pin is initially in a high level state, that is, in a high level state by default. When the state setting value is a preset high level setting value, the level state of the target pin can be maintained in response to the state setting value being the preset high level setting value, so that the level state of the target pin remains in a high level state. When the state setting value is a preset low level setting value, the level state of the target pin can be switched in response to the state setting value being the preset low level setting value, switching the high level state of the target pin to a low level state, so that the level state of the target pin is in a low level state.

[0104] Step 204: Turning on the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin to enable the memory module; and / or;

[0105] Step 205 : Cut off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin, so as to shut down the memory module.

[0106] In an embodiment of the present application, the slot voltage of the memory slot corresponding to the target pin can be turned on based on the level state of the target pin, that is, the slot voltage of the memory slot is set to a high level, thereby enabling the memory stick, which can be used for business processing, that is, increasing the memory capacity. And / or, the slot voltage of the memory slot corresponding to the target pin can be turned off based on the level state of the target pin, that is, the slot voltage of the memory slot is set to a low level, thereby turning off the memory stick, and not using the memory stick as memory available for business processing, that is, reducing the content capacity. Isolation can be achieved by setting the corresponding memory slot voltage, without the need for overall disassembly and replacement, which can improve operation and maintenance efficiency.

[0107] In some optional embodiments of the present application, referring to FIG4 and FIG5 , a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground line;

[0108] The steps of conducting the memory slot and the memory module corresponding to the target pin according to the level state of the target pin include:

[0109] In response to the target pin being in a high level state, connecting the target pin and the connection circuit of the memory slot corresponding to the target pin to a voltage terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to a preset power supply, and the slot voltage of the memory slot corresponding to the target pin is turned on;

[0110] Correspondingly, the step of cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0111] In response to the target pin's level state being a low level state, the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the ground terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the preset power ground line, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0112] Referring to Figure 4, in response to the level state of the target pin being a high level state, the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the voltage end. At this time, the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the preset power supply, the voltage of the memory slot is high level, and the slot voltage of the memory slot corresponding to the target pin is turned on.

[0113] Referring to Figure 5, in response to the level state of the target pin being a low level state, the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the ground terminal. At this time, the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the power ground line, the voltage of the memory slot is low, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0114] In an embodiment of the present application, a central processing unit is provided with multiple memory slots, and the memory slots are used to install memory sticks. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the multiple memory slots and the expansion chip have different protocol addresses; the multiple memory slots correspond one-to-one with the pins of the expansion chip; memory setting information is read, and the memory setting information includes a target protocol address value and a status setting value; based on the target protocol address value, the target pin of the expansion chip is determined; based on the status setting value, the level state of the target pin is set; based on the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is turned on to enable the memory stick; and / or; based on the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is turned off to turn off the memory stick. By physically designing the pins of the expansion chip in the server to be physically linked to the memory slot voltage, the memory slot voltage can be controlled by reading the level status value of the pins of the expansion chip, and the usage status of the memory stick can be adjusted to control the server memory capacity and the power consumption of the entire server. When the memory stick needs to be isolated, isolation can be achieved by setting the corresponding memory slot voltage, without the need for overall disassembly and replacement, which can improve operation and maintenance efficiency. Moreover, the faulty memory stick can be isolated to avoid causing larger server errors, which can improve operation efficiency.

[0115] In order to make the implementation process of the embodiments of the present application more clear to those skilled in the art, the following examples are used to illustrate:

[0116] 6, there is shown a flowchart of a memory capacity adjustment method embodiment of the present application.

[0117] Memory voltage control needs to be performed when the server is powered off. If the server is powered on, there is a risk of server data loss or uncontrollable problems. This is because after the server is powered on, all data runs on the server's memory. If there is a problem with the memory, server failure cannot be predicted.

[0118] Specifically, after the server is shut down, the user can determine the level of the corresponding target pin of the expansion chip that needs to be controlled based on the management webpage of the baseboard management controller or the IPMI (Intelligent Platform Management Interface) command, and then control the corresponding memory slot voltage according to the level of the target pin to control whether the memory stick is enabled, thereby achieving control of the memory capacity.

[0119] For the control process of the baseboard management control management webpage, please refer to Figure 7. The BMC (baseboard management controller) webpage adds a memory bar or memory slot enable or disable control button in the memory management interface. The control button uses the I2C protocol to set the GPIO signal state value of the memory slot voltage physical link to a high or low state through the interface function to enable or disable the memory of the memory slot;

[0120] For the control process of the IPMI command of the baseboard management controller, please refer to Figure 8. The IPMI command on the BMC side can be used to remotely control the memory voltage of the memory slot of the server motherboard out-of-band. The command format is ipmitool raw 0x32 0x71 0x06 0x00 0x01. Among them, the last two bytes, 0x00 represents the first GPIO of the first GPIO expansion chip, 0x01 represents setting it to a high state, that is, the memory voltage is turned on, if it is 0x0, it means the memory voltage turn-on function is turned off; 0x10 represents the first GPIO of the second GPIO expansion chip, 0x01 represents setting it to a high state, that is, the memory voltage is turned on, if it is 0x0, it means the memory voltage turn-on function is turned off; the 16th GPIO signal can be represented by 0x0F.

[0121] The memory is controlled by one of the two methods mentioned above, thereby adjusting the memory capacity.

[0122] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0123] 9 shows a block diagram of an embodiment of a memory capacity adjustment device of the present application. The memory capacity adjustment device is applied to a server. The server is provided with at least one central processing unit (CPU). The CPU is provided with multiple memory slots for installing memory modules. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one to the pins of the expansion chip. The memory capacity adjustment device may specifically include the following modules:

[0124] A reading module 901 is used to read memory setting information, where the memory setting information includes a target protocol address value and a status setting value;

[0125] A target pin determination module 902 is configured to determine a target pin of the expansion chip according to a target protocol address value;

[0126] A first setting module 903 is configured to set the level state of the target pin according to the state setting value;

[0127] The second setting module 904 is configured to control the connection state between the memory slot corresponding to the target pin and the memory module according to the level state of the target pin, so as to adjust the memory capacity.

[0128] In some optional embodiments of the present application, the second setting module 904 includes:

[0129] a conduction setting submodule, configured to conduct the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin, so as to enable the memory stick; and / or;

[0130] The cutoff setting submodule is used to cut off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin, so as to shut down the memory bank.

[0131] In some optional embodiments of the present application, a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground line;

[0132] The conduction setting submodule includes:

[0133] a first response unit, configured to connect the target pin and the connection circuit of the memory slot corresponding to the target pin to a voltage end in response to the target pin being in a high-level state, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to a preset power supply, thereby turning on the slot voltage of the memory slot corresponding to the target pin;

[0134] Correspondingly, the cutoff setting submodule includes:

[0135] The second response unit is used to connect the connection circuit between the target pin and the memory slot corresponding to the target pin to the ground terminal in response to the level state of the target pin being a low level state, so that the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the preset power ground line, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0136] In some optional embodiments of the present application, the baseboard management controller corresponds to a management page; the management page has status setting controls corresponding to a memory bank or multiple memory slots; the reading module 901 includes:

[0137] A second response submodule, configured to respond to a setting operation on the state setting control;

[0138] A setting operation determination submodule, configured to determine a target protocol address value from protocol addresses of a plurality of memory slots according to a setting operation; and to determine a state setting value;

[0139] The first reading submodule is used to read the state setting value and the target protocol address value as memory setting information.

[0140] In some optional embodiments of the present application, the level state of the target pin is initially in a high level state; the first setting module 903 includes:

[0141] a third response submodule, configured to maintain the level state of the target pin in response to the state setting value being a preset high level setting value;

[0142] The fourth response submodule is configured to switch the level state of the target pin in response to the state setting value being a preset low level setting value.

[0143] In some optional embodiments of the present application, the reading module 901 includes:

[0144] The second reading submodule is used to read the intelligent platform management interface instruction from the baseboard management controller;

[0145] The parsing submodule is used to parse the target bytes of the intelligent platform management interface instruction and determine the state setting value and the target protocol address value;

[0146] The third reading submodule is used to read the state setting value and the target protocol address value as memory setting information.

[0147] In some optional embodiments of the present application, when there are multiple target protocol address values, the target pin determination module 902 includes:

[0148] The judgment submodule is used to judge whether the target protocol address value is the last target protocol address value;

[0149] The fifth response submodule is used to determine the target pin of the expansion chip according to the target protocol address value in response to the target protocol address value not being the last target protocol address value, and update the target protocol address value until the target protocol address value is the last target protocol address value.

[0150] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0151] 10 , an embodiment of the present application further provides a server, wherein the server is provided with at least one central processing unit (CPU), the CPU is provided with a plurality of memory slots, the memory slots being used to install memory modules, the plurality of memory slots being connected to a communication protocol interface of a baseboard management controller via at least one expansion chip, the plurality of memory slots and the expansion chip having different protocol addresses; the plurality of memory slots corresponding one-to-one to the pins of the expansion chip;

[0152] The baseboard management controller reads memory setting information, where the memory setting information includes a target protocol address value and a state setting value;

[0153] The baseboard management controller determines the target pin of the expansion chip according to the target protocol address value;

[0154] The central processing unit sets the level state of the target pin according to the state setting value;

[0155] The CPU sets the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0156] Optionally, the step of the central processing unit setting the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0157] The central processing unit turns on the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin to enable the memory module; and / or;

[0158] The central processing unit cuts off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin, so as to shut down the memory module.

[0159] Optionally, a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground wire;

[0160] The steps of the central processing unit turning on the memory slot and the memory module corresponding to the target pin according to the level state of the target pin include:

[0161] In response to the target pin being in a high level state, the central processing unit connects the target pin to a voltage terminal of a connection circuit of a memory slot corresponding to the target pin, so that the target pin is connected to a preset power supply of the connection circuit of the memory slot corresponding to the target pin, and turns on the slot voltage of the memory slot corresponding to the target pin;

[0162] Correspondingly, the step of the central processing unit cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0163] In response to the target pin having a low level state, the central processing unit connects the target pin and the connection circuit of the memory slot corresponding to the target pin to the ground terminal, so that the connection circuit of the target pin and the memory slot corresponding to the target pin is connected to the preset power ground line, thereby cutting off the slot voltage of the memory slot corresponding to the target pin.

[0164] Optionally, the baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to a memory bar or multiple memory slots; and the step of the baseboard management controller reading memory setting information includes:

[0165] The baseboard management controller responds to a setting operation for the state setting control;

[0166] The baseboard management controller determines a target protocol address value from protocol addresses of a plurality of memory slots according to a setting operation; and determines a state setting value;

[0167] The baseboard management controller reads the status setting value and the target protocol address value as memory setting information.

[0168] Optionally, the step of the baseboard management controller reading the memory setting information includes:

[0169] The baseboard management controller reads the intelligent platform management interface instruction from the baseboard management controller;

[0170] The baseboard management controller parses the target bytes of the intelligent platform management interface instruction and determines the state setting value and the target protocol address value;

[0171] The baseboard management controller reads the status setting value and the target protocol address value as memory setting information.

[0172] Optionally, the level state of the target pin is initially in a high level state; and the step of the central processing unit setting the level state of the target pin according to the state setting value includes:

[0173] The central processing unit maintains the level state of the target pin in response to the state setting value being a preset high level setting value;

[0174] In response to the state setting value being a preset low level setting value, the central processing unit switches the level state of the target pin.

[0175] Optionally, when there are multiple target protocol address values, the baseboard management controller determines the target pin of the expansion chip according to the target protocol address value, including:

[0176] The baseboard management controller determines whether the target protocol address value is the last target protocol address value;

[0177] In response to the target protocol address value not being the last target protocol address value, the baseboard management controller determines the target pin of the expansion chip according to the target protocol address value and updates the target protocol address value until the target protocol address value is the last target protocol address value.

[0178] 11 , an embodiment of the present application further provides an electronic device, including:

[0179] Processor 1101 and storage medium 1102, storage medium 1102 stores a computer program executable by processor 1101, when the electronic device is running, processor 1101 executes the computer program to perform a memory capacity adjustment method such as any one of the embodiments of the present application.

[0180] A memory capacity adjustment method is applied to a server. The server is provided with at least one central processing unit (CPU). The CPU is provided with multiple memory slots. The memory slots are used to install memory modules. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one with the pins of the expansion chip. The method includes:

[0181] Read memory setting information, which includes target protocol address value and status setting value;

[0182] Determine the target pin of the expansion chip based on the target protocol address value;

[0183] Set the level state of the target pin according to the state setting value;

[0184] The slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0185] Optionally, the step of setting a slot voltage of a memory slot corresponding to the target pin according to a level state of the target pin includes:

[0186] According to the level state of the target pin, turning on the slot voltage of the memory slot corresponding to the target pin to enable the memory module; and / or;

[0187] According to the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is cut off to shut down the memory module.

[0188] Optionally, a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground wire;

[0189] The steps of conducting the memory slot and the memory module corresponding to the target pin according to the level state of the target pin include:

[0190] In response to the target pin being in a high level state, connecting the target pin and the connection circuit of the memory slot corresponding to the target pin to a voltage terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to a preset power supply, and the slot voltage of the memory slot corresponding to the target pin is turned on;

[0191] Correspondingly, the step of cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0192] In response to the target pin's level state being a low level state, the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the ground terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the preset power ground line, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0193] Optionally, the baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to a memory bar or multiple memory slots; and the step of reading memory setting information includes:

[0194] In response to a setting operation on a state setting control;

[0195] Determining a target protocol address value from protocol addresses of a plurality of memory slots according to a setting operation; and determining a state setting value;

[0196] The read status setting value and target protocol address value are memory setting information.

[0197] Optionally, the level state of the target pin is initially in a high level state; and the step of setting the level state of the target pin according to the state setting value includes:

[0198] In response to the state setting value being a preset high level setting value, maintaining the level state of the target pin;

[0199] In response to the state setting value being a preset low level setting value, the level state of the target pin is switched.

[0200] Optionally, the step of reading memory setting information includes:

[0201] Reading intelligent platform management interface instructions from the baseboard management controller;

[0202] Parsing the target bytes of the intelligent platform management interface instruction to determine the state setting value and the target protocol address value;

[0203] The read status setting value and target protocol address value are memory setting information.

[0204] Optionally, when there are multiple target protocol address values, the step of determining the target pin of the expansion chip according to the target protocol address value includes:

[0205] Determine whether the target protocol address value is the last target protocol address value;

[0206] In response to the target protocol address value not being the last target protocol address value, the target pin of the expansion chip is determined according to the target protocol address value, and the target protocol address value is updated until the target protocol address value is the last target protocol address value.

[0207] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0208] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0209] 12 , an embodiment of the present application further provides a computer non-volatile readable storage medium 1201 , on which a computer program is stored. When the computer program is run by a processor, the memory capacity adjustment method according to any one of the embodiments of the present application is executed.

[0210] A memory capacity adjustment method is applied to a server. The server is provided with at least one central processing unit (CPU). The CPU is provided with multiple memory slots. The memory slots are used to install memory modules. The multiple memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip. The multiple memory slots and the expansion chip have different protocol addresses. The multiple memory slots correspond one-to-one with the pins of the expansion chip. The method includes:

[0211] Read memory setting information, which includes target protocol address value and status setting value;

[0212] Determine the target pin of the expansion chip based on the target protocol address value;

[0213] Set the level state of the target pin according to the state setting value;

[0214] The slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin. The slot voltage is used to adjust the usage state of the memory module.

[0215] Optionally, the step of setting a slot voltage of a memory slot corresponding to the target pin according to a level state of the target pin includes:

[0216] According to the level state of the target pin, turning on the slot voltage of the memory slot corresponding to the target pin to enable the memory module; and / or;

[0217] According to the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is cut off to shut down the memory module.

[0218] Optionally, a voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground wire;

[0219] The steps of conducting the memory slot and the memory module corresponding to the target pin according to the level state of the target pin include:

[0220] In response to the target pin being in a high level state, connecting the target pin and the connection circuit of the memory slot corresponding to the target pin to a voltage terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to a preset power supply, and the slot voltage of the memory slot corresponding to the target pin is turned on;

[0221] Correspondingly, the step of cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes:

[0222] In response to the target pin's level state being a low level state, the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the ground terminal, so that the target pin and the connection circuit of the memory slot corresponding to the target pin are connected to the preset power ground line, and the slot voltage of the memory slot corresponding to the target pin is cut off.

[0223] Optionally, the baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to a memory bar or multiple memory slots; and the step of reading memory setting information includes:

[0224] In response to a setting operation on a state setting control;

[0225] Determining a target protocol address value from protocol addresses of a plurality of memory slots according to a setting operation; and determining a state setting value;

[0226] The read status setting value and target protocol address value are memory setting information.

[0227] Optionally, the level state of the target pin is initially in a high level state; and the step of setting the level state of the target pin according to the state setting value includes:

[0228] In response to the state setting value being a preset high level setting value, maintaining the level state of the target pin;

[0229] In response to the state setting value being a preset low level setting value, the level state of the target pin is switched.

[0230] Optionally, the step of reading memory setting information includes:

[0231] Reading intelligent platform management interface instructions from the baseboard management controller;

[0232] Parsing the target bytes of the intelligent platform management interface instruction to determine the state setting value and the target protocol address value;

[0233] The read status setting value and target protocol address value are memory setting information.

[0234] Optionally, when there are multiple target protocol address values, the step of determining the target pin of the expansion chip according to the target protocol address value includes:

[0235] Determine whether the target protocol address value is the last target protocol address value;

[0236] In response to the target protocol address value not being the last target protocol address value, the target pin of the expansion chip is determined according to the target protocol address value, and the target protocol address value is updated until the target protocol address value is the last target protocol address value.

[0237] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0238] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0239] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0240] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0241] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0242] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0243] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0244] The above is a detailed introduction to a memory capacity adjustment method, a memory capacity adjustment device, a server, an electronic device and a storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory capacity adjustment method, characterized in that: Applied to a server, the server is provided with at least one central processing unit, the central processing unit is provided with multiple memory slots, the memory slots are used to install memory modules, the multiple memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the multiple memory slots and the expansion chip have different protocol addresses; The plurality of memory slots correspond one-to-one to the pins of the expansion chip; the method comprises: Reading memory setting information, wherein the memory setting information includes a target protocol address value and a state setting value; Determining the target pin of the expansion chip according to the target protocol address value; Setting the level state of the target pin according to the state setting value; The slot voltage of the memory slot corresponding to the target pin is set according to the level state of the target pin, and the slot voltage is used to adjust the usage state of the memory module.

2. The method according to claim 1, characterized in that The state setting value is a polarized value; The polarized value is a high level or a low level.

3. The method according to claim 1, characterized in that Determining the target pin of the expansion chip according to the target protocol address value includes: After the target protocol address value is obtained, the target pin of the expansion chip is determined according to the matching condition between the target protocol address value and the protocol address corresponding to each pin of the expansion chip.

4. The method according to claim 1, wherein The step of setting the level state of the target pin according to the state setting value includes: The level of the target pin of the expansion chip is set to correspond to the state setting value.

5. The method according to claim 4, characterized in that The level state of the target pin is initially a high level state; and the step of setting the level state of the target pin according to the state setting value comprises: In response to the state setting value being a preset high level setting value, maintaining the level state of the target pin; In response to the state setting value being a preset low level setting value, the level state of the target pin is switched.

6. The method according to claim 1, characterized in that The method further comprises: Based on the usage status of all the memory bars of the entire server, the number of the memory bars in use is determined, and the memory capacity is adjusted.

7. The method according to claim 1, characterized in that The voltage of a single slot represents the usage status of the corresponding memory module.

8. The method according to claim 1, characterized in that The method of setting the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes: based on the level state of the target pin, synchronously adjusting the level state of the target pin and the slot voltage of the corresponding memory slot, so that the slot voltage of the memory slot corresponding to the target pin is adjusted or maintained in a default state.

9. The method according to claim 8, characterized in that The step of setting the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes: According to the level state of the target pin, turning on the slot voltage of the memory slot corresponding to the target pin to enable the memory stick; and / or; According to the level state of the target pin, the slot voltage of the memory slot corresponding to the target pin is cut off to shut down the memory bank.

10. The method according to claim 9, characterized in that A voltage terminal and a ground terminal are provided between the target pin and the memory slot corresponding to the target pin, the voltage terminal is connected to a preset power supply through a pull-up resistor, and the ground terminal includes a preset power ground line; The step of connecting the memory slot corresponding to the target pin and the memory module according to the level state of the target pin includes: In response to the target pin being in a high level state, connecting the target pin and the connection circuit of the memory slot corresponding to the target pin to the voltage end, so that the connection circuit of the target pin and the memory slot corresponding to the target pin is connected to the preset power supply, and turning on the slot voltage of the memory slot corresponding to the target pin; Correspondingly, the step of cutting off the slot voltage of the memory slot corresponding to the target pin according to the level state of the target pin includes: In response to the level state of the target pin being a low level state, the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the ground terminal, so that the connection circuit between the target pin and the memory slot corresponding to the target pin is connected to the preset power ground line, cutting off the slot voltage of the memory slot corresponding to the target pin.

11. The method according to claim 1, wherein The baseboard management controller controls the memory capacity through a management page or intelligent platform management interface instructions.

12. The method according to claim 11, characterized in that The baseboard management controller corresponds to a management page; the management page has a status setting control corresponding to the memory bar or the plurality of memory slots; The step of reading memory setting information includes: In response to a setting operation on the state setting control; Determining the target protocol address value from the protocol addresses of the plurality of memory slots according to the setting operation; and determining the state setting value; The state setting value and the target protocol address value are read as the memory setting information.

13. The method according to claim 12, characterized in that The state setting control is an enable or disable control button.

14. The method according to claim 11, characterized in that The step of reading memory setting information includes: Reading the intelligent platform management interface instruction from the baseboard management controller; Parsing the target byte of the intelligent platform management interface instruction to determine the state setting value and the target protocol address value; The state setting value and the target protocol address value are read as the memory setting information.

15. The method according to claim 14, characterized in that When the user needs to perform remote control, the user sends relevant setting instructions to the baseboard management controller through the intelligent platform management interface.

16. The method according to claim 1, wherein When there are multiple target protocol address values, the step of determining the target pin of the expansion chip according to the target protocol address value includes: Determining whether the target protocol address value is the last target protocol address value; In response to the target protocol address value not being the last target protocol address value, the target pin of the expansion chip is determined according to the target protocol address value, and the target protocol address value is updated until the target protocol address value is the last target protocol address value.

17. The method according to claim 1, wherein The operation of controlling the slot voltage of the memory slot is performed when the server is powered off.

18. A server, characterized in that: The server is provided with at least one central processing unit, the central processing unit is provided with a plurality of memory slots, the memory slots are used to install memory modules, the plurality of memory slots are connected to the communication protocol interface of the baseboard management controller via at least one expansion chip, the plurality of memory slots and the expansion chip have different protocol addresses; the plurality of memory slots correspond one-to-one with the pins of the expansion chip; The baseboard management controller reads memory setting information, wherein the memory setting information includes a target protocol address value and a state setting value; The baseboard management controller determines the target pin of the expansion chip according to the target protocol address value; The central processing unit sets the level state of the target pin according to the state setting value; The central processing unit sets a slot voltage of a memory slot corresponding to the target pin according to a level state of the target pin, and the slot voltage is used to adjust a usage state of the memory module.

19. A memory capacity adjustment device, characterized in that: Applied to a server, the server is provided with at least one central processing unit, the central processing unit is provided with multiple memory slots, the memory slots are used to install memory modules, the multiple memory slots are connected to the communication protocol interface of the baseboard management controller through at least one expansion chip, and the multiple memory slots and the expansion chip have different protocol addresses; The plurality of memory slots correspond one-to-one to the pins of the expansion chip; the device comprises: A reading module, configured to read memory setting information, wherein the memory setting information includes a target protocol address value and a state setting value; A target pin determination module, configured to determine a target pin of the expansion chip according to the target protocol address value; A first setting module, configured to set the level state of the target pin according to the state setting value; The second setting module is used to control the connection state between the memory slot corresponding to the target pin and the memory stick according to the level state of the target pin, so as to adjust the memory capacity.

20. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the memory capacity adjustment method according to any one of claims 1 to 17 are implemented.

21. A computer-readable non-volatile storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory capacity adjustment method according to any one of claims 1 to 17 are implemented.

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