Memory controller, memory access method, chip, and electronic device

Abstract

Embodiments of the present disclosure provide a memory controller, a memory access method, a chip, and an electronic device. The memory controller comprises: a shared control logic circuit, configured to determine a request command corresponding to a memory access request and send the request command to a final arbiter; a command replicator, configured to, when a command outputted by the final arbiter is a non-replicated request command and meets a preset replication condition, replicate the request command and send a replicated request command to the final arbiter; and the final arbiter, configured to perform final arbitration on the received command, if the command that has passed final arbitration is a non-replicated request command, output the request command and indicate transmission by means of a zeroth virtual channel, and during at least one clock cycle after the output, approve the corresponding replicated request command, output the replicated request command, and indicate transmission by means of a first virtual channel. According to the embodiments of the present disclosure, the zeroth virtual channel and the first virtual channel are coordinatively controlled by means of one set of control logic, thereby reducing the overhead of the memory controller.

Description

Memory controller, memory access method, chip and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202410144118.5 filed on January 31, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a memory controller, a memory access method, a chip, and an electronic device. Background Art

[0003] In order to reduce the problems of bandwidth loss, increased latency, etc. caused by the speed difference between the cache and the hard disk (such as non-volatile memory), memory (such as dynamic random access memory) can be set between the cache and the hard disk to reduce the problems caused by the speed difference between the cache and the hard disk.

[0004] As a key component for managing and controlling memory, a memory controller coordinates, controls, and executes tasks related to memory access operations (such as reads and writes). Memory controller overhead is a key performance metric, and improving memory controllers to reduce this overhead has become a pressing technical challenge for those skilled in the art.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a memory controller, a memory access method, a chip, and an electronic device to reduce the overhead of the memory controller.

[0007] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions.

[0008] In a first aspect, an embodiment of the present disclosure provides a memory controller, wherein data is transmitted between the memory controller and a memory via a memory channel, wherein the memory channel includes a zeroth virtual channel and a first virtual channel; the memory controller includes: a shared control logic circuit, a final arbiter, and a command replicator;

[0009] The shared control logic circuit is shared by the zeroth virtual channel and the first virtual channel, and the shared control logic circuit is configured to determine a request command corresponding to a memory access request and send the request command to a final arbiter;

[0010] The command replicator is configured to, when the command output by the final arbitrator is a non-replicated request command and the request command meets a preset replication condition, replicate the request command to obtain a corresponding replicated request command; and send the replicated request command to the final arbitrator;

[0011] The final arbitrator is configured to perform final arbitration on the command sent to the final arbitrator; if the command passed by the final arbitration is a non-duplicate request command, output the request command and instruct it to be transmitted through the zeroth virtual channel; and at least one clock cycle after outputting the non-duplicate request command, if the command passed by the final arbitration corresponds to a duplicate request command, output the duplicate request command and instruct it to be transmitted through the first virtual channel;

[0012] The non-copied request command comes from the shared control logic circuit, and the copied request command comes from the command copier.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory access method, which is applied to the memory controller described in the first aspect above, wherein data is transmitted between the memory controller and the memory via a memory channel, wherein the memory channel includes a zeroth virtual channel and a first virtual channel; the method includes:

[0014] determining a request command corresponding to the memory access request, wherein the request command corresponding to the memory access request participates in final arbitration;

[0015] and when the command output by the final arbitration is a non-duplicate request command and the request command meets the preset replication condition, replicating the request command to obtain a corresponding replicated request command, wherein the replicated request command participates in the final arbitration;

[0016] Perform final arbitration on the commands participating in the final arbitration; if the command that passes the final arbitration is a non-duplicate request command, output the request command and indicate transmission through the zeroth virtual channel; and, at least one clock cycle after the non-duplicate request command is output, the corresponding duplicate request command passes the final arbitration, output the duplicate request command and indicate transmission through the first virtual channel.

[0017] In a third aspect, an embodiment of the present disclosure provides a chip, comprising: at least one processor core, at least one memory controller, a memory physical layer, and a memory;

[0018] The at least one processor core is connected to the at least one memory controller; the memory physical layer includes at least one memory channel, and the memory channel includes a zeroth virtual channel and a first virtual channel; data is transmitted between the memory controller and the memory via the memory channel;

[0019] Wherein, the memory controller is the memory controller as described in the first aspect above.

[0020] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising the chip as described in the third aspect above, or the memory controller as described in the first aspect above.

[0021] In the embodiment of the present disclosure, the non-copied request command (from the shared control logic circuit) output by the final arbitrator is transmitted through the zeroth virtual channel, and for the non-copied request command output by the final arbitrator that meets the preset copy condition, the command copier can copy the request command; then, the final arbitrator can output the corresponding copied request command and transmit it through the first virtual channel at least one clock cycle after outputting the non-copied request command. It can be seen that when the zeroth virtual channel is set to transmit non-duplicated request commands and the first virtual channel is set to transmit duplicated request commands, the memory controller can collaboratively control the zeroth virtual channel and the first virtual channel; that is, the memory controller can set a common control logic circuit shared by the zeroth virtual channel and the first virtual channel, and use the command duplicator to duplicate request commands, and the final arbitrator transmits the arbitration non-duplicated request commands through the zeroth virtual channel and the arbitration duplicated request commands through the first virtual channel, so that the common control logic circuit can regard the zeroth virtual channel and the first virtual channel as a whole channel for control, so as to realize collaborative control of the zeroth virtual channel and the first virtual channel through a set of control logic inside the memory controller, reduce the number of control logic circuits used by the memory controller, and reduce the overhead of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are merely embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0023] FIG1 is an exemplary diagram of a chip provided in an embodiment of the present disclosure.

[0024] FIG2 is an example diagram of a memory controller provided by an embodiment of the present disclosure.

[0025] FIG3 is a flowchart of a memory access method provided by an embodiment of the present disclosure.

[0026] FIG4A is another example diagram of a memory controller provided in an embodiment of the present disclosure.

[0027] FIG4B is another flowchart of the memory access method provided by an embodiment of the present disclosure.

[0028] FIG4C is another flowchart of the memory access method provided by an embodiment of the present disclosure.

[0029] FIG4D is another flowchart of the memory access method provided by an embodiment of the present disclosure.

[0030] FIG5A is yet another flowchart of a memory access method provided by an embodiment of the present disclosure.

[0031] FIG5B is yet another flowchart of the memory access method provided by an embodiment of the present disclosure.

[0032] FIG5C is another flowchart of the memory access method provided by an embodiment of the present disclosure.

[0033] FIG6 is a flow chart of counting timing parameters of commands according to an embodiment of the present disclosure.

[0034] FIG. 7 is another example diagram of a memory controller provided by an embodiment of the present disclosure.

[0035] FIG8 is a flowchart of determining a request command for a memory access request provided by an embodiment of the present disclosure.

[0036] FIG9 is another example diagram of a memory controller provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0038] The memory controller acts as a bridge between the processor core (such as the CPU core) and the memory. On the one hand, the memory controller can be connected to the system bus through an interface, thereby connecting to the processor core through the system bus. On the other hand, it can be connected to the physical layer through an interface (the physical layer connected to the memory controller can be called the memory physical layer), thereby connecting to the memory through the memory physical layer. In turn, the memory controller can be controlled by the processor core to configure mode registers, perform memory access operations (such as read operations or write operations), and issue control commands (such as memory refresh, precharge, and other control commands).

[0039] To enable data transmission between the memory controller and the memory, the memory physical layer can have multiple memory channels for transmitting data between the memory controller and the memory. Taking HBM3 (High Bandwidth Memory 3, third-generation high-bandwidth memory) technology as an example, in HBM3 technology, the memory controller can be called an HBM3 memory controller, the memory channel can be called an HBM3 channel, and the memory can be called an HBM3 memory. An HBM3 memory (such as a DRAM memory) can support 16 HBM3 channels, and each HBM3 channel can have an independent command interface and data interface. As an example, a DRAM (Dynamic Random Access Memory) die supports 4 HBM3 channels, so a DRAM memory stacked with 4 DRAM dies can support 16 HBM3 channels.

[0040] Memory channels (such as HBM3 channels) can be logically divided into zero-th virtual channels and first virtual channels through virtual channel mode. A memory channel can be divided into at least one zero-th virtual channel and at least one first virtual channel. For example, a memory channel can be logically divided into two virtual channels (one zero-th virtual channel and one first virtual channel). Data transfers supported by the memory channel can be carried out through the divided virtual channels.

[0041] Without including ECC (Error Checking and Correcting) bits, the data length supported by a virtual channel for data transmission (i.e., the amount of data transmitted by a virtual channel through a column command) can be defined as a first data length, and the total data length supported by the virtual channels included in the memory channel for data transmission can be defined as a second data length (for example, the second data length is the total data length supported by the zeroth virtual channel and the first virtual channel included in the memory channel for data transmission). The multiple of the second data length relative to the first data length can correspond to the number of virtual channels divided by a memory channel; for example, if a memory channel is divided into two virtual channels (a zeroth virtual channel and a first virtual channel), the second data length is twice the first data length.

[0042] Taking HBM3 technology as an example, a read or write in HBM3 technology is achieved by continuously operating on 8 columns of data in a specified row, and each column operates on 32 bits of data. In other words, the data bit width of a virtual channel refers to the number of data bus bits that a virtual channel has. For example, in HBM3 technology, the data bit width of a virtual channel is 32 bits. The data length supported by a virtual channel for transmission refers to the amount of data that a virtual channel can transmit through a column command. Since a column command is implemented by continuously operating on 8 columns of data in a specified row, the data length supported by a virtual channel for transmission can be exemplified as 32 bits × 8 = 32 bytes, where 1 byte = 8 bits. Based on this, without including ECC bits, the data length supported by a virtual channel for transmission can be 32 bytes, that is, an example of the first data length can be 32 bytes; when an HBM3 channel is divided into a zeroth virtual channel and a first virtual channel, the second data length is twice the first data length, and the second data length can be 64 bytes.

[0043] It should be noted that since a virtual channel is a logically divided channel of a memory channel (such as an HBM3 channel), a virtual channel is also called a pseudo channel.

[0044] For ease of understanding, FIG1 exemplarily shows an example diagram of a chip provided by an embodiment of the present disclosure. As shown in FIG1 , the chip may include a processor core 110 , a memory controller 120 , a memory physical layer 130 , and a memory 140 .

[0045] Processor core 110 is the computing core of a processor, responsible for data computation and program execution, and includes, but is not limited to, the computing core of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). The number of processor cores 110 may be at least one (or more), and this is not a limitation in the present disclosure.

[0046] The memory controller 120 and the processor core 110 can be connected via a system bus. For example, an interface of the memory controller 120 can be connected to the system bus, thereby connecting to the processor core 110 via the system bus. The system bus may include a command bus and a data bus, so that the memory controller 120 can receive memory access requests from the processor core 110 via the command bus and exchange data with the processor core 110 via the data bus. The number of memory controllers 120 can be at least one (or one or more), and the embodiments of the present disclosure are not limited thereto.

[0047] It should be noted that the processor core can send memory access requests to the memory controller to request memory access operations such as read and write operations. Memory access requests can be divided into read requests and write requests. A read request is a memory access request corresponding to a read operation, requesting that data be read from memory and returned to the processor core. The data read from memory by a read request is called read data, and accordingly, the read data is the memory access data for the read request. A write request is a memory access request corresponding to a write operation, requesting that write data be written to memory. The data to be written to memory by a write request is called write data, and accordingly, the write data is the memory access data for the write request.

[0048] The memory physical layer 130 is responsible for the hardware-level interface and connection between the memory controller 120 and the memory 140, and can provide a physical connection for data transmission between the memory controller 120 and the memory 140. The memory physical layer 130 can have a memory channel 131 for transmitting data between the memory controller and the memory, and the number of memory channels 131 is one or more. By configuring at least one memory channel for a memory controller, a memory controller can control at least one configured memory channel. In one example, HBM3 technology can support configuring 16 HBM3 channels for a memory (such as a DRAM memory), setting at least 16 memory controllers, and a memory controller can control at least one HBM3 channel.

[0049] Memory channels can include a zeroth virtual channel and a first virtual channel. A virtual channel can be considered a logical path divided by a memory channel and used to transfer data between the memory controller and the memory. As shown in Figure 1 , taking a memory channel 131 divided into two virtual channels as an example, a memory channel 131 can include a zeroth virtual channel 0 and a first virtual channel 1. The data length supported by a virtual channel for data transmission can be a first data length (e.g., 32 bytes).

[0050] Memory 140 is responsible for temporarily storing data and programs required for the operation of processor core 110. Memory 140 can be in the form of DRAM (Dynamic Random Access Memory). The technology used by memory 140 is not limited and includes, but is not limited to, HBM3, DDR (Double Data Rate), and other technologies.

[0051] As can be seen, the memory physical layer includes memory channels (e.g., HBM3 channels) controlled by a memory controller (e.g., an HBM3 memory controller). The memory channels are divided into virtual channels 0 and 1. These virtual channels have independent data buses but share a command bus. When a memory controller controls the memory channels, it must configure control logic to control the virtual channels divided by the memory channels.

[0052] One way the memory controller controls virtual channels is:

[0053] Based on transmitting the request command and memory access data of a memory access request through the virtual channel corresponding to the memory access request, the memory controller can set an independent control logic circuit for each virtual channel, thereby achieving independent control of each virtual channel through the independent control logic circuit of each virtual channel. For example, the memory controller can set a zeroth control logic circuit to control the zeroth virtual channel and a first control logic circuit to control the first virtual channel, so that the zeroth virtual channel is controlled by the zeroth control logic circuit, and the first virtual channel is controlled by the first control logic circuit.

[0054] It should be noted that the request command of a memory access request refers to the request command generated by the memory controller based on the memory access request of the processor core, for example, a read command corresponding to a read request, a write command corresponding to a write request, etc. In the case where the memory access request indicates a virtual channel, the request command and memory access data of the memory access request are transmitted through the virtual channel corresponding to the memory access request, which means that the request command and memory access data of the memory access request are transmitted through the virtual channel indicated by the memory access request, and are not transmitted through other virtual channels. It should be further noted that the virtual channel corresponding to the memory access request can be indicated by the virtual channel address of the memory access request (the virtual channel address of the memory access request can be carried in the physical address of the memory access request). If the virtual channel address of the memory access request belongs to the zeroth virtual channel, the memory access request is a memory access request for the zeroth virtual channel; if the virtual channel address of the memory access request belongs to the first virtual channel, the memory access request is a memory access request for the first virtual channel.

[0055] For ease of understanding, taking the virtual channel corresponding to the memory access request sent by the processor core as the zeroth virtual channel as an example, regardless of the data length of the memory access data, the request command and memory access data of the memory access request sent by the processor core are transmitted through the zeroth virtual channel, and will not be transmitted on the first virtual channel; similarly, if the virtual channel corresponding to the memory access request sent by the processor core is the first virtual channel, regardless of the data length of the memory access data, the request command and memory access data of the memory access request sent by the processor core are transmitted through the first virtual channel, and will not be transmitted on the zeroth virtual channel.

[0056] The request command and memory access data based on the memory access request are transmitted on the virtual channel indicated by the memory access request. If the data length of the memory access data is large (for example, the data length of the memory access data is greater than the first data length supported by a virtual channel), the request command and memory access data of the memory access request need to be transmitted multiple times on the virtual channel corresponding to the memory access request.

[0057] For example, take a virtual channel supporting 32-byte data transmission as an example, that is, the single data transmission volume of a single virtual channel of the memory physical layer is 32 bytes (for example, the single data transmission volume supported by a virtual channel of HBM3 technology is 32 bytes). If the memory access data of the memory access request sent by the processor core is large (64 bytes or more), then for the 64-byte memory access request (the memory access request with 64-byte memory data is referred to as the 64-byte memory access request), after determining the virtual channel corresponding to the memory access request, the request command and memory access data of the memory access request are transmitted twice consecutively on the virtual channel corresponding to the memory access request.

[0058] For example, when the memory access request is a write request, the memory controller needs to split the 64-byte write request sent by the processor core into two 32-byte write commands. Each 32-byte write command is used to write 32 bytes of write data to the memory. Therefore, the memory controller continuously transmits the two 32-byte write commands and the corresponding write data to the memory through the virtual channel corresponding to the write request, thereby writing 64 bytes of write data to the memory. For another example, when the memory access request is a read request, the memory controller needs to split the 64-byte read request sent by the processor core into two 32-byte read commands. Each 32-byte read command is used to read 32 bytes of read data from the memory. Therefore, the memory controller continuously transmits the two 32-byte read commands to the memory through the virtual channel corresponding to the read request, and continuously obtains the two 32-byte read data returned from the memory through the virtual channel corresponding to the read request, thereby reading 64 bytes of read data from the memory.

[0059] It should be noted that when HBM3 technology performs reads or writes, it completes the task by performing 8 concurrent reads or writes, 4 times per clock cycle. This allows the zeroth virtual channel and the first virtual channel to have independent data buses. However, when the command bus is shared, the minimum interval between read or write commands transmitted on the same virtual channel is 2 clock cycles. In other words, if a read or write command is transmitted on the zeroth virtual channel in the current clock cycle, the first clock cycle after the current clock cycle cannot transmit a read or write command on the zeroth virtual channel. At least the second clock cycle after the current clock cycle is required to transmit a read or write command on the zeroth virtual channel. Therefore, the first clock cycle after the current clock cycle can transmit a read or write command on the first virtual channel.

[0060] It can be seen that in the above method, the request command and memory access data of the memory access request are transmitted on the virtual channel corresponding to the memory access request, and not on other virtual channels. Therefore, when a memory channel is divided into the zeroth virtual channel and the first virtual channel, the memory controller needs to set an independent control logic circuit for each virtual channel to achieve independent control of each virtual channel.

[0061] However, the memory controller sets up independent control logic circuits for each virtual channel, which results in a large number of control logic circuits in the memory controller (for example, the memory controller needs to set up duplicate control logic circuits for the zeroth virtual channel and the first virtual channel). This leads to high memory controller overhead, such as a large memory controller footprint and high power consumption. In addition, if the memory supports a large number of memory channels and the chip has a large number of memory controllers (for example, HBM3 supports 16 HBM3 channels, one HBM3 channel includes two virtual channels, and the chip supports the setting of at least 16 HBM3 memory controllers), then if each memory controller needs to set up independent control logic circuits for each virtual channel, the chip's overall memory controller overhead will be further increased when there are a large number of memory channels and memory controllers.

[0062] Based on this, the embodiment of the present disclosure provides an improved memory controller design to reduce the memory controller overhead. Different from the way in which the request command and memory access data of the memory access request are transmitted in the virtual channel corresponding to the memory access request, the embodiment of the present disclosure introduces a means of copying the request command, and sets the command transmitted by the zeroth virtual channel as a non-copy request command, and the command transmitted by the first virtual channel as a copy request command, thereby collaboratively controlling the zeroth virtual channel and the first virtual channel, so that the memory controller can internally realize the collaborative control of the zeroth virtual channel and the first virtual channel through a set of control logic, thereby reducing the number of control logic circuits used by the memory controller and reducing the memory controller overhead. It should be noted that, in the case where the memory channel is divided into the zeroth virtual channel and the first virtual channel (the number of the zeroth virtual channel may be one or more, and similarly, the number of the first virtual channel may be one or more), the zeroth virtual channel and the first virtual channel can be adjusted by changing the settings in the memory channel and are not fixed.

[0063] Based on the above ideas, FIG2 exemplarily shows an example diagram of a memory controller provided by an embodiment of the present disclosure. As shown in FIG2 , the memory controller may include: a shared control logic circuit 210 , a command copier 220 and a final arbiter 230 .

[0064] Shared control logic circuit 210 is a control logic circuit shared by virtual channel 0 and virtual channel 1 within the memory controller. In the disclosed embodiment, shared control logic circuit 210 processes memory access requests without distinguishing their virtual channel addresses, thereby determining the corresponding request command for the memory access request sent to the final arbiter for final arbitration. Alternatively, shared control logic circuit 210 may include at least one logic component to process memory access requests.

[0065] As an optional main function of the shared control logic circuit 210 , the shared control logic circuit 210 may be configured to determine a request command corresponding to a memory access request and send the request command to a final arbiter, wherein the memory access request may come from a processor core.

[0066] In the case where the embodiment of the present disclosure introduces a method for copying request commands, a command copier 220 may be provided in the memory controller. Command copier 220 may be configured to: when the command output by the final arbitrator is a non-copied request command and the request command meets a preset copy condition, copy the request command to obtain a corresponding copied request command; and send the copied request command to the final arbitrator.

[0067] That is, the final arbiter 230 is the device that performs final arbitration on commands in the memory controller. The commands sent to the final arbiter 230 for final arbitration can come from at least the request commands provided by the shared control logic circuit 210 and the request commands replicated by the command copier 220. For ease of explanation, in this embodiment of the disclosure, the request commands from the shared control logic circuit are referred to as non-replicated request commands, and the request commands from the command copier are referred to as replicated request commands.

[0068] As an optional implementation, when the command transmitted by the zeroth virtual channel is set to a non-duplicate request command and the command transmitted by the first virtual channel is set to a duplicate request command, the final arbitrator 230 may be configured as follows:

[0069] Final arbitration is performed on the commands sent to the final arbitrator; if the command that passes the final arbitration is a non-duplicate request command (i.e., the request command that passes the final arbitration is from the shared control logic circuit), the request command is output and instructed to be transmitted through the zeroth virtual channel; and, at least one clock cycle after the non-duplicate request command is output, the corresponding duplicate request command is passed by the final arbitration (i.e., the corresponding duplicate request command from the command duplicator is passed by the final arbitration), the duplicate request command is output and instructed to be transmitted through the first virtual channel.

[0070] It can be seen that in the embodiment of the present disclosure, the non-copied request command (from the shared control logic circuit) output by the final arbitrator is transmitted through the zeroth virtual channel, and for the non-copied request command output by the final arbitrator that meets the preset copy condition, the command copier can copy the request command; and then the final arbitrator can output the corresponding copied request command at least one clock cycle after outputting the non-copied request command and transmit it through the first virtual channel. It can be seen that when the zeroth virtual channel is set to transmit non-duplicated request commands and the first virtual channel is set to transmit duplicated request commands, the memory controller can collaboratively control the zeroth virtual channel and the first virtual channel; that is, the memory controller can set a common control logic circuit shared by the zeroth virtual channel and the first virtual channel, and use the command duplicator to duplicate request commands, and the final arbitrator transmits the arbitration non-duplicated request commands through the zeroth virtual channel and the arbitration duplicated request commands through the first virtual channel, so that the common control logic circuit can regard the zeroth virtual channel and the first virtual channel as a whole channel for control, so as to realize collaborative control of the zeroth virtual channel and the first virtual channel through a set of control logic inside the memory controller, reduce the number of control logic circuits used by the memory controller, and reduce the overhead of the memory controller.

[0071] For ease of understanding, based on the structure of the memory controller shown in FIG2 , FIG3 exemplarily shows a flow chart of a memory access method provided by an embodiment of the present disclosure. Combined with FIG2 and FIG3 , the method flow may include the following steps.

[0072] In step S310 , a request command corresponding to the memory access request is determined, wherein the request command corresponding to the memory access request participates in final arbitration.

[0073] In an optional implementation, step S310 may be performed by a shared control logic circuit.

[0074] In an optional implementation, the shared control logic circuit may determine the request command corresponding to the memory access request through initial arbitration. For example, the shared control logic circuit may determine the commands that participate in the initial arbitration for the memory access request based at least on a page hit status of the memory access request, and then determine, from the commands that participate in the initial arbitration, the command that passes the initial arbitration as the request command corresponding to the memory access request.

[0075] It should be noted that the memory may include multiple blocks, and a block may be considered as a data block of a set size in the memory. For example, a block may be an array formed by rows and columns. A row, as part of a memory address (such as a DRAM address), may correspond to a group of storage cells arranged in rows in the memory, also known as a page. For example, the storage cells in the memory are organized together in rows to form a page. The number of storage cells contained in a row in the memory may be fixed (due to the provisions of the memory protocol), and the number of storage cells contained in a row may correspond to the size of the row (referred to as the row size). A column, as another part of a memory address (such as a DRAM address), may correspond to the position of a storage cell in a row when the storage cells are arranged in rows. Therefore, a specific storage cell can be located in the memory through the addresses of the row and column.

[0076] It should be further explained that the memory block has a buffer zone, and data reading and writing in the block must be performed through the buffer zone. However, the buffer zone of the block only loads one row of the block at a time. Therefore, when accessing a row of the block (for example, when reading or writing a row of the block), if the accessed row is not loaded into the buffer zone, it is necessary to write the data in the buffer zone back to the originally loaded row through a precharge operation, and then load the accessed row into the buffer zone through an activation operation before data can be read or written in the accessed row. Therefore, based on the situation of the row being loaded in the block buffer zone, the page hit situation of the memory access request can be divided into page hit, page miss, page conflict, etc.

[0077] As an optional implementation, the disclosed embodiment can generate different commands participating in the initial arbitration for memory access requests based on different page hit situations of the memory access request, such as page hit, page miss, page conflict, etc.; and then determine the command that passes the initial arbitration from the commands participating in the initial arbitration as the request command corresponding to the memory access request, and send it to the final arbitrator for final arbitration.

[0078] In step S311, the command output by the final arbitration is monitored. When the command output by the final arbitration is a non-copied request command and the request command meets the preset copy condition, the request command is copied to obtain a corresponding copied request command, wherein the copied request command participates in the final arbitration.

[0079] In an optional implementation, S311 may be implemented by a command copier.

[0080] In an optional implementation, based on an array of rows and columns formed by blocks in a memory, request commands can be divided into row commands for controlling rows, and column commands for performing memory access operations on columns.

[0081] It should be noted that the two virtual channels (virtual channel 0 and virtual channel 1) divided by the memory channel can share the command bus and address bus, but have independent data buses. Based on the organization of memory blocks in rows and columns, the command bus can include a row command bus (Row Command Interface) and a column command bus (Column Command Interface); wherein the row command bus can transmit row commands, which refers to any command other than read commands and write commands; the column command bus can transmit column commands, which are only for read commands and write commands, such as the column address strobe (CAS) command for reading data and the column strobe command for writing data.

[0082] As an optional implementation, a column command can be used to perform a memory access operation (e.g., a read operation or a write operation) on a column in a row pointed to by a memory access request, including but not limited to any of the following: a column command for a read operation (i.e., a read command), and a column command for a write operation (i.e., a write command). A column command, also known as a column strobe command, is used to select a column in a row to read or write data to the selected column. For example, a column strobe command can select a column in a row of a block, thereby concurrently reading or writing data from a specified starting column and subsequent columns.

[0083] As an optional implementation, the row command can be regarded as any command other than column commands such as read commands and write commands. The row command can be used to control at least the block where the row pointed to by the memory access request is located, including but not limited to any of the following: row activation (Activity, abbreviated as ACT) command, pre-charge (Per Bank Pre-charge, abbreviated as PCHGpb) command, refresh (Refresh) command, RFMab (All Bank Refresh Management, full block refresh management) command, RFMpb (Per Bank Refresh Management, single block refresh management) command, etc.

[0084] It should be noted that the row activation command is also called the Row Address Strobe (RAS) command, which is used to load the row into the buffer of the block. The precharge command is used to precharge the block corresponding to the row; the precharge command can be divided into a single-block precharge (Per Bank Pre-charge, abbreviated as PCHGpb) command, and a full-block precharge (All Banks Pre-charge, abbreviated as PCHGab) command; the single-block precharge command can be a precharge operation on a single block of memory, and the full-block precharge command can be a precharge operation on all blocks of memory. The refresh command is used to refresh the memory to prevent data loss in the memory; for example, for types of memory such as DRAM, due to the existence of charge leakage, it is necessary to refresh regularly to prevent memory data loss. Refresh commands can be divided into All Banks Refresh (REFab) commands and Per Bank Refresh (REFpb) commands; among them, the All Banks Refresh command is a command that controls the refresh operation of all blocks in the memory at the same time, and the Per Bank Refresh command is a command that controls the memory to be refreshed individually by block, for example, each block in the memory receives the refresh command independently; compared with the All Banks Refresh command, the Per Bank Refresh command allows more flexible refresh of a certain block or a part of the blocks in the memory.

[0085] Based on the request commands, they are divided into row commands and column commands. As an optional implementation, since the row command controls the block where the row targeted by the memory access request is located, it involves affecting the page state of the block. Therefore, to maintain the consistency of the page states of the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can copy the non-copied row command output by the final arbiter (i.e., copy the row command output by the final arbiter from the shared control logic circuit). In other words, when the command output by the final arbiter is a non-copied row command, the embodiment of the present disclosure can copy the row command to obtain a corresponding copied row command, thereby ensuring that the zeroth virtual channel (transmitting the non-copied row command) and the first virtual channel (transmitting the copied row command) can transmit the same row command. At the same time, combined with the fact that if the column command output by the final arbiter originates from a memory access request with a first data length (e.g., 32 bytes), the column command does not carry an auto-precharge instruction, thereby maintaining the page states of the zeroth virtual channel and the first virtual channel.

[0086] As an optional implementation, since the column command is a memory access operation that reads or writes the column in the row pointed to by the memory access request, and the data length supported by a single virtual channel for transmitting data is the first data length (for example, 32 bytes), if the command output by the final arbitrator is a non-duplicated column command, and the data length of the memory access request corresponding to the column command is the first data length (for example, 32 bytes), and the virtual channel indicated by the memory access request is the zeroth virtual channel, then since the zeroth virtual channel itself is set to transmit a non-duplicated request command, the embodiment of the present disclosure may not need to copy the column command. If the command output by the final arbitrator is a non-copied column command, and the data length of the memory access request corresponding to the column command is the first data length (for example, 32 bytes), and the virtual channel indicated by the memory access request is the first virtual channel, then since the first virtual channel is set to transmit copied request commands rather than non-copied request commands, the column command output by the final arbitrator needs to be discarded, and the command copier needs to copy the column command to transmit the copied column command through the first virtual channel, thereby meeting the memory access requirements of the memory access request with the first data length (for example, 32 bytes).

[0087] In a further optional implementation, to facilitate distinguishing between column commands output by the final arbiter that need to be discarded and column commands that need to be actually sent to the memory, the final arbiter may mark the output column commands with true or false marking information. If the request command output by the final arbiter is a non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the first virtual channel (which is inconsistent with the setting of the first virtual channel for transmitting the duplicate request command), the final arbiter may mark the output column command with false marking information, so that the column command is not actually sent to the memory, and the corresponding duplicate column command marked as true is sent to the memory instead, thereby satisfying the memory access requirement of the memory access request.

[0088] In addition to marking the column command outputted by the final arbiter as false in the aforementioned circumstances, the outputted column command may be marked as true in all other circumstances. Based on this, the disclosed embodiment can be configured to set conditions for marking column commands as false, so that when the request command outputted by the final arbiter is a column command and satisfies the conditions, the outputted column command is marked as false. The conditions may include: the column command outputted by the final arbiter is a non-replicated column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the first virtual channel. Accordingly, when the request command outputted by the final arbiter is a column command and does not satisfy the aforementioned conditions, the outputted column command is marked as true.

[0089] For example, if the request command output by the final arbitrator is a non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the zeroth virtual channel (consistent with the setting that the zeroth virtual channel transmits non-duplicate request commands), the final arbitrator can annotate the column command with the actual annotation information when output, so that the column command can be truly sent to the memory. For example, if the final arbitrator outputs a non-duplicate column command, the data length of the memory access request corresponding to the column command is 32 bytes, and the virtual channel indicated by the memory access request is the zeroth virtual channel, the final arbitrator can annotate the column command with the actual annotation information when output.

[0090] It should be noted that, in an optional implementation, if the column command output by the final arbitrator is derived from a memory access request of the first data length, the column command does not carry an automatic precharge instruction; for example, if the read command or write command output by the final arbitrator is triggered by a 32-byte memory access request, the read command or write command may not carry an automatic precharge instruction. If the column command output by the final arbitrator is derived from a memory access request of the second data length, the column command may or may not carry an automatic precharge instruction; for example, if the read command or write command output by the final arbitrator is triggered by a 64-byte memory access request, the read command or write command may or may not carry an automatic precharge instruction.

[0091] It should be noted that if the request command output by the final arbiter is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the second data length (e.g., 64 bytes), then regardless of the virtual channel indicated by the memory access request (i.e., regardless of the virtual channel address of the memory access request), the final arbiter may first output a column command marked as authentic, indicating transmission through the zeroth virtual channel, and duplicate the column command via the command duplicator, so that the final arbiter then outputs a duplicate column command marked as authentic, indicating transmission through the first virtual channel, to meet the memory access requirement of the memory access request of the second data length. In other words, if the command output by the final arbiter is a non-duplicate request command, and the request command is a column command marked as authentic originating from a memory access request of the second data length, the command duplicator must duplicate the column command, so that the non-duplicate column command is transmitted through the zeroth virtual channel (the zeroth virtual channel supports data transmission of the first data length) and the corresponding duplicate column command is transmitted through the first virtual channel (the first virtual channel supports data transmission of the first data length), thereby meeting the memory access requirement of the memory access request of the second data length.

[0092] Based on the above description, if the command output by the final arbiter is a non-copied column command (i.e., the column command output by the final arbiter comes from the shared control logic circuit), and the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the zeroth virtual channel, then the column command can be considered a column command for performing a read or write operation corresponding to the memory access request of the first data length, and the column command is transmitted on the zeroth virtual channel that itself transmits non-copied request commands, so the column command does not need to be copied. Therefore, except for the above situation, the command copier can copy the command output by the final arbiter. That is, when the command output by the final arbiter is a non-copied request command, or a column command other than a column command marked as authentic and originating from a memory access request of the first data length, the embodiment of the present disclosure can copy the command output by the final arbiter to obtain the corresponding copied request command. For example, when the command output by the final arbitrator is a non-copied request command, and is a read command or a write command other than a marked real memory access request originating from 32 bytes, the command copier can copy the request command output by the final arbitrator to obtain a corresponding copied request command.

[0093] In step S312, final arbitration is performed on the commands participating in the final arbitration; if the command that passes the final arbitration is a non-duplicate request command, the request command is output and instructed to be transmitted through the zeroth virtual channel; and, at least one clock cycle after the non-duplicate request command is output, the corresponding duplicate request command passes the final arbitration, the duplicate request command is output and instructed to be transmitted through the first virtual channel.

[0094] In an optional implementation, step S312 may be performed by the final arbitrator. In a further optional implementation, the copied command output by the final arbitrator may be deleted from the command copier. For example, the command copier may save the copied command sent to the final arbitrator for final arbitration, and the command copier may delete the copied command output by the final arbitrator from the saved state.

[0095] As an optional implementation, based on the division of request commands into row commands and column commands, FIG4A exemplarily shows another example diagram of the memory controller provided by an embodiment of the present disclosure. In combination with FIG2 and FIG4A , the final arbitrator 230 in the memory controller may include a column command arbitrator 41 and a row command arbitrator 42; wherein, the column command arbitrator can perform final arbitration on the column commands, and the row command arbitrator can perform final arbitration on the row commands.

[0096] The following introduces the optional implementation of the final arbitrator from the perspectives of final arbitration scheduling by column commands and final arbitration scheduling by row commands.

[0097] As an optional implementation, the column command arbiter may be configured to: perform final arbitration on the column commands sent to the final arbiter; if the column command that passes the final arbitration is a non-duplicate column command, output the column command and instruct it to be transmitted through the zeroth virtual channel; and, if a corresponding duplicate column command exists for the output non-duplicate column command, at least one clock cycle after the output of the non-duplicate column command, perform final arbitration on the corresponding duplicate column command, output the duplicate column command and instruct it to be transmitted through the first virtual channel.

[0098] As an optional implementation, the non-replicated column commands output by the column command arbitrator may fall into the following categories:

[0099] Case 1: The non-copy column command originates from a memory access request of the first data length (i.e., the data length of the memory access request corresponding to the non-copy column command is the first data length), and the virtual channel indicated by the memory access request is the zeroth virtual channel (i.e., the virtual channel address of the memory access request belongs to the zeroth virtual channel); for example, the non-copy column command originates from a 32-byte memory access request, and the virtual channel address carried by the physical address of the memory access request belongs to the zeroth virtual channel;

[0100] Case 2: The non-copy column command originates from a memory access request of the first data length, and the virtual channel indicated by the memory access request is the first virtual channel; for example, the non-copy column command originates from a 32-byte memory access request, and the virtual channel address carried by the physical address of the memory access request belongs to the first virtual channel;

[0101] Case three: the non-copy column command originates from a memory access request of the second data length, and the virtual channel indicated by the memory access request is the zeroth virtual channel or the first virtual channel; for example, the non-copy column command originates from a 64-byte memory access request, and the virtual channel address carried by the physical address of the memory access request belongs to the zeroth virtual channel or the first virtual channel; it should be noted that when the data length of the memory access request is the second data length, the embodiment of the present disclosure does not consider the role of the virtual channel address of the memory access request, and therefore when the data length of the memory access request is the second data length, the memory access request of the zeroth virtual channel or the first virtual channel is integrated into case three.

[0102] As an optional implementation, the command copier copies the request command when the command output by the final arbiter is a non-copied request command or a column command other than a column command marked as true and derived from a memory access request of the first data length; and the final arbiter outputting a non-copied column command marked as true and derived from a memory access request of the first data length corresponds to the aforementioned situation one. Therefore, the disclosed embodiment does not perform command replication in situation one, but performs command replication in situations two and three. That is, when the column command arbiter outputs a non-copied column command or a column command other than a column command marked as true and derived from a memory access request of the first data length (i.e., the column command is not marked as true, and the data length of the memory access request corresponding to the column command is not the first data length), the column command is replicated to obtain a corresponding replicated column command.

[0103] In an optional implementation, for case one, FIG4B exemplarily shows another flowchart of the memory access method provided by an embodiment of the present disclosure. Referring to FIG4B , the method flow may be implemented by a column command arbiter, and the method flow may include the following steps.

[0104] In step S410 , the column command arbiter performs final arbitration on the column command sent to the final arbiter.

[0105] The column command sent to the final arbitrator may be a non-duplicate column command (from a shared logic circuit) or a duplicate column command (from a duplicate command device). In an optional implementation, the column command arbitrator may perform final arbitration on the column commands sent to the final arbitrator according to a certain arbitration strategy, for example, an arbitration strategy based on the priority of the command and the order in which it is sent to the final arbitrator. In an optional implementation, since the duplicate request command must have a corresponding non-duplicate request command that has been output by the final arbitrator, the duplicate request command can have the highest priority during the final arbitration to ensure that after the non-duplicate request command is transmitted through the zeroth virtual channel, the corresponding duplicate request command can be transmitted on the first virtual channel immediately, thereby ensuring the state consistency between the zeroth virtual channel and the first virtual channel.

[0106] In step S411, if the column command arbitrator passes the arbitration for the non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the zeroth virtual channel, then in the current cycle clock, the column command output virtual channel address belongs to the zeroth virtual channel and is marked as a real column command.

[0107] In an optional implementation, if the column command arbitrated by the column command arbitrator is a non-duplicate column command, and the memory access request corresponding to the arbitrated non-duplicate column command is 32 bytes, then when the virtual channel address of the memory access request belongs to the zeroth virtual channel (the zeroth virtual channel is set to transmit non-duplicate column commands), the column command arbitrator can output a column command in the current clock cycle, whose virtual channel address belongs to the zeroth virtual channel and is marked as a real column command (this column command does not have an automatic precharge instruction).

[0108] It should be noted that, when the non-duplicated column command arbitrated by the column command arbitrator originates from a memory access request with a first data length (e.g., 32 bytes), and the virtual channel address of the memory access request belongs to the zeroth virtual channel, since the column command arbitrator outputs a virtual channel address belonging to the zeroth virtual channel in the current cycle and marks the real column command, the column command corresponding to the memory access request with the first data length (e.g., 32 bytes) can be sent to the memory through the zeroth virtual channel, thereby transmitting the memory access data of the first data length (e.g., 32 bytes) and satisfying the memory access requirement of the memory access request with the first data length (e.g., 32 bytes); therefore, there is no need for the command duplicator to duplicate the corresponding column command, and there is no need for the first virtual channel to transmit the corresponding duplicated column command.

[0109] Based on this, the embodiment of the present disclosure can set the final arbiter to be occupied by the command duplicator in the next clock cycle, but the final arbitrator does not output the column command to ensure the correctness of the data. That is, when the column command arbitrator outputs a non-duplicated column command, and the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the zeroth virtual channel, the embodiment of the present disclosure can make the final arbiter occupied by the command duplicator in the next clock cycle, but the final arbitrator does not output any column command in the next clock cycle to ensure that the first virtual channel does not transmit the duplicated column command, thereby ensuring the correctness of the data. It can be understood that if the column command arbitrator outputs the corresponding duplicated column command in the next clock cycle and indicates transmission through the first virtual channel, then when the column command is a column command for a read operation, it will result in repeated reading of the read data, increasing meaningless power consumption. In addition, when the column command is a column command for a write operation, it may cause the data written to the memory to be destroyed, resulting in a write error.

[0110] For example, when a column command that passes arbitration comes from a shared logic circuit, the data length of the memory access request corresponding to the column command is 32 bytes, and the virtual channel address of the memory access request belongs to the zeroth virtual channel, the column command arbiter can output a virtual channel address belonging to the zeroth virtual channel in the current clock cycle and mark it as the actual column command (this column command does not include an automatic precharge instruction); and in the next clock cycle, the command replicator can occupy the final arbiter, but the final arbiter (the column command arbiter of the final arbiter) will not output any column command.

[0111] In an optional implementation, for the second situation, FIG4C exemplarily shows another flow chart of the memory access method provided by the embodiment of the present disclosure. Referring to FIG4C , the method flow may include the following steps.

[0112] In step S420 , the column command arbiter performs final arbitration on the column command sent to the final arbiter.

[0113] In step S421, if the column command finally arbitrated and passed is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the first virtual channel, the column command arbiter outputs a column command in the current cycle clock, in which the virtual channel address belongs to the zeroth virtual channel and is marked as false.

[0114] It should be noted that the column command marked as true can be sent to the memory after being output by the final arbitrator; while the column command marked as false needs to be discarded (ie, not sent to the memory) after being output by the final arbitrator.

[0115] In step S422 , the command copier copies the non-copied column command output by the column command arbiter to obtain a corresponding copied column command, and sends the copied column command to the final arbiter.

[0116] When a non-duplicated column command approved by the column command arbitrator originates from a memory access request of a first data length (e.g., 32 bytes), and the virtual channel address of the memory access request belongs to the first virtual channel, the approved non-duplicated column command needs to be transmitted via the set zeroth virtual channel, which is inconsistent with the first virtual channel indicated by the memory access request. Therefore, the column command arbitrator may output a column command in the current clock cycle whose virtual channel address belongs to the zeroth virtual channel and is marked as false, so that the non-duplicated column command output by the column command arbitrator can be discarded based on the false marking information. Simultaneously, the command copier may copy the non-duplicated column command output by the column command arbitrator and send the corresponding copied column command to the final arbitrator, so that the final arbitrator can output the corresponding copied column command marked as authentic in the next clock cycle and indicate that it be transmitted via the first virtual channel, thereby meeting the memory access requirement of the memory access request of the first data length.

[0117] In step S423 , the column command arbiter finally arbitrates the corresponding copied column command in the next clock cycle, and outputs the copied column command with the virtual channel address belonging to the first virtual channel and marked as authentic.

[0118] For example, when the column command that ultimately passes arbitration comes from the shared logic circuit, and the data length of the memory access request corresponding to the column command is 32 bytes, and the virtual channel address of the memory access request belongs to the first virtual channel, the column command arbiter can output a virtual channel address belonging to the zeroth virtual channel in the current clock cycle and mark it as a false column command; thereby, the command copier can copy the column command output by the column command arbiter and send the corresponding copied column command to the column command arbiter; furthermore, the column command arbiter can arbitrate the corresponding copied column command from the command copier in the next clock cycle, output a virtual channel address belonging to the first virtual channel, and mark it as the real copied column command (this column command does not have an automatic precharge instruction), thereby meeting the memory access requirement of 32 bytes.

[0119] As can be seen, for a 32-byte memory access request, the virtual channel address of the memory access request can be used in the disclosed embodiment. That is, the virtual channel address of the 32-byte memory access request determines the virtual channel for actually sending the column command. Furthermore, based on the principle set in the disclosed embodiment that the zeroth virtual channel transmits a non-duplicate request command and the first virtual channel transmits a duplicate request command, when the column command arbiter outputs a non-duplicate column command for a 32-byte memory access request, if the virtual channel address indicated by the memory access request belongs to the first virtual channel (for example, when the shared control logic circuit provides the column command to the column command arbiter, the virtual channel address of the provided column command belongs to the first virtual channel), the column command arbiter can, based on the principle that non-duplicate column commands are transmitted via the zeroth virtual channel, output a non-duplicate column command with a virtual channel belonging to the zeroth virtual channel but marked as false, indicating that the output column command is invalid and must be discarded. Subsequently, the column command arbiter can output a corresponding duplicate column command belonging to the first virtual channel but marked as true, thereby ensuring the memory access requirements of the memory access request and ensuring that the zeroth virtual channel and the first virtual channel transmit commands as set.

[0120] In an optional implementation, for situation three, FIG4D exemplarily shows another flow chart of the memory access method provided by an embodiment of the present disclosure. Referring to FIG4D , the method flow may include the following steps.

[0121] In step S430 , the column command arbiter performs final arbitration on the column command sent to the final arbiter.

[0122] In step S431, if the column command finally passed by arbitration is a non-duplicate column command and the data length of the memory access request corresponding to the column command is the second data length, the column command arbiter outputs a virtual channel address belonging to the zeroth virtual channel in the current cycle clock and marks the column command as a real column command.

[0123] In step S432 , the command copier copies the non-copied column command output by the column command arbiter to obtain a corresponding copied column command, and sends the copied column command to the final arbiter.

[0124] When a non-copied column command arbitrated by the column command arbitrator originates from a memory access request of the second data length (e.g., 64 bytes), the disclosed embodiment does not consider the virtual channel address indicated by the memory access request. Instead, based on the principle that the zeroth virtual channel transmits the non-copied request command and the first virtual channel transmits the copied request command, the present embodiment first outputs a column command with a virtual channel address belonging to the zeroth virtual channel and marked as "true" in the current clock cycle, and the command copier copies the column command output by the column command arbitrator. Furthermore, the column command arbitrator may output the corresponding copied column command (with a virtual channel address belonging to the first virtual channel and marked as "true") in the next clock cycle. This allows the column command arbitrator to output a column command with a virtual channel address belonging to the zeroth virtual channel and marked as "true" in the current clock cycle, and output a corresponding copied column command with a virtual channel address belonging to the first virtual channel and marked as "true" in the next clock cycle, thereby satisfying the memory access requirement of the memory access request of the second data length.

[0125] In step S433 , the column command arbiter arbitrates the corresponding copied column command in the next clock cycle and outputs the copied column command whose virtual channel address belongs to the first virtual channel and is marked as authentic.

[0126] As an optional implementation, the column command arbiter may prohibit the column command from the common control logic circuit from participating in the final arbitration (ie, prohibit the non-replicated column command from participating in the final arbitration) in the next clock cycle.

[0127] For example, when a column command that passes arbitration comes from a shared logic circuit and the data length of the memory access request corresponding to the column command is 64 bytes, the column command arbiter disregards the virtual channel address indicated by the memory access request and instead outputs a column command in the current clock cycle that indicates the virtual channel address belongs to the zeroth virtual channel and is marked as the real column command (this command may include an auto-precharge instruction). The command replicator can then replicate the column command output by the column command arbiter and send the replicated column command to the column command arbiter. Furthermore, the column command arbiter can prohibit the column command from the shared control logic circuit from participating in the final arbitration in the next clock cycle and arbitrate the replicated column command from the command replicator, outputting a column command that indicates the virtual channel address belongs to the first virtual channel and is marked as the real replicated column command (this column command may include an auto-precharge instruction to maintain consistency with the column command transmitted by the zeroth virtual channel and output by the column command arbiter in the previous clock cycle), thereby meeting the memory access requirement of 64 bytes.

[0128] Based on the arbitration scheduling scheme for column commands provided in the embodiments of the present disclosure, as an example, a processing example of a column command (a column command for a read operation or a column command for a write operation) may be as follows:

[0129] When the column command arbiter approves a column command from the shared control logic circuit, if the data length of the memory access request corresponding to the column command is 64 bytes, the column command arbiter may output a virtual channel address belonging to the zeroth virtual channel in the current clock cycle and mark the column command as the real one. The command copier may then copy the column command output by the column command arbiter and send the copied column command to the column command arbiter. Furthermore, in the next clock cycle, the column command arbiter may arbitrate the column command copied by the command copier and output a virtual channel address belonging to the first virtual channel and mark the copied column command as the real one.

[0130] When the column command arbiter arbitrates a column command from the shared control logic circuit, if the data length of the memory access request corresponding to the column command is 32 bytes, and if the virtual channel address of the memory access request belongs to the zeroth virtual channel, the column command arbiter may output a virtual channel address belonging to the zeroth virtual channel in the current clock cycle and mark the column command as the real column command; the command copier does not copy the column command output by the column command arbiter and occupies the final arbiter in the next clock cycle, but the final arbiter does not output any column command in the next clock cycle;

[0131] When the column command arbiter arbitrates a column command from the shared control logic circuit, if the data length of the memory access request corresponding to the column command is 32 bytes, and if the virtual channel address of the memory access request belongs to the first virtual channel, the column command arbiter may output a statement in the current clock cycle indicating that the virtual channel address belongs to the zeroth virtual channel and mark it as a false column command. The command copier can then copy the column command output by the column command arbiter and send the copied column command to the column command arbiter. Furthermore, in the next clock cycle, the column command arbiter arbitrates the column command copied by the command copier and outputs a statement indicating that the virtual channel address belongs to the first virtual channel and marks it as the true copied column command.

[0132] The following describes the row command arbitration and scheduling process. As an optional implementation, the row command arbiter can be configured to: perform final arbitration on the row commands sent to the final arbiter; if the row command that passes the final arbitration is a non-duplicate row command, output the row command and instruct it to be transmitted via the zeroth virtual channel; and, at least one clock cycle after outputting the non-duplicate row command, output the corresponding duplicate row command and instruct it to be transmitted via the first virtual channel.

[0133] It should be noted that since the row command performs precharging, row activation, and other controls on the block where the row is located, and does not involve reading or writing data on the column, in order to ensure the consistency of the page status of the blocks of the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can set the zeroth virtual channel and the first virtual channel to transmit the same row command, that is, the non-replicated row command transmitted through the zeroth virtual channel needs to be replicated, and the corresponding replicated row command needs to be transmitted through the first virtual channel to ensure the consistency of the page status of the zeroth virtual channel and the first virtual channel. Therefore, any non-replicated row command output by the row command arbiter (that is, any row command output by the row command arbiter from the shared control logic circuit) can be replicated by the command copier to obtain the corresponding replicated row command.

[0134] It should be noted that, since the non-copied row commands need to be transmitted through the zeroth virtual channel and the corresponding copied row commands need to be transmitted through the first virtual channel, there is no need for the row commands (non-copied row commands and corresponding copied row commands) to be discarded. Therefore, in an optional implementation, the embodiment of the present disclosure may not mark the row commands (non-copied row commands and corresponding copied row commands) output by the row command arbitrator with true and false marking information.

[0135] In an optional implementation, if the row command that passes the final arbitration is a non-duplicate row command, the row command arbiter can select the row command that participates in the final arbitration based on the clock cycle of the command bus occupied by the output non-duplicate row command, and at least one clock cycle after the output of the non-duplicate row command (for example, select the row command that participates in the final arbitration from the non-duplicate row command sent from the shared control logic circuit and the duplicate row command sent from the duplicate commander), and output the duplicate row command and indicate transmission through the first virtual channel.

[0136] As an optional implementation, different types of commands may occupy different command bus clock cycles. For example, for technologies like HBM3, commands may occupy command bus clock cycles of 0.5 clock cycles, 1 clock cycle, and 1.5 clock cycles. Based on this, in an optional implementation, the clock cycle occupied by a non-replicated row command output by the row command arbiter may be 1.5 clock cycles, 1 clock cycle, or 0.5 clock cycles. The following describes the row command arbitration scheduling method for different clock cycle conditions.

[0137] As an optional implementation, FIG5A exemplarily shows another flowchart of the memory access method provided by an embodiment of the present disclosure. This method flow can be implemented by a row command arbiter. Referring to FIG5A , this method flow can include the following steps.

[0138] In step S510 , if the row command finally passed the arbitration is a non-duplicate row command, the row command arbiter outputs the row command and instructs it to be transmitted through the zeroth virtual channel.

[0139] Correspondingly, the command copier can copy the non-copied row command output by the row command arbiter (i.e., the row command output by the row command arbiter from the shared control logic circuit) to obtain the corresponding copied row command, and send the copied row command to the row command arbiter.

[0140] In step S511, if the output non-copied row command occupies 1.5 clock cycles of the command bus, the row command arbiter selects a row command that does not conflict with the output row command and occupies 0.5 clock cycles of the command bus to participate in the final arbitration in the first clock cycle after the current clock cycle of the output non-copied row command.

[0141] In a further optional implementation, the selected row command that occupies 0.5 clock cycles of the command bus can be output by the row command arbiter 0.5 clock cycles after the first clock cycle, the output row command is copied by the command copier, and the corresponding copied row command can be output by the row command arbiter 0.5 clock cycles after the third clock cycle.

[0142] In step S512 , the row command arbiter prohibits non-duplicate row commands from participating in the final arbitration from the second clock cycle to the third clock cycle after the current clock cycle.

[0143] In the embodiment of the present disclosure, the clock cycle in which the row command arbiter outputs a non-duplicate row command is used as the current clock cycle (set to T0). If the non-duplicate row command output by the row command arbiter at T0 occupies 1.5 clock cycles of the command bus, then in the first clock cycle after T0 (i.e., the next clock cycle after the current clock cycle, set to T1), the row command selected by the row command arbiter to participate in the final arbitration should meet the following conditions: it does not conflict with the non-duplicate row command output by T0, and the clock cycle of the command bus occupied is 0.5 clock cycles, so that the row command participating in the final arbitration at T1 corresponds to the non-duplicate row command output by T0 occupying 1.5 clock cycles of the command bus.

[0144] Furthermore, from the second clock cycle after T0 to the third clock cycle (the second clock cycle after T0 is set to T2, and the third clock cycle after T0 is set to T3), the row command arbiter prohibits non-copied row commands from participating in the final arbitration, that is, the row command arbiter prohibits row commands not from the command copier from participating in the arbitration from T2 to T3 (row commands not from the command copier can be regarded as row commands from the shared control logic circuit).

[0145] In step S513, the row command arbiter outputs the copied row commands in sequence from the second clock cycle to the third clock cycle according to the order in which the copied row commands are sent from the current clock cycle to the first clock cycle, and indicates that the virtual channel address belongs to the first virtual channel.

[0146] Because the non-replicated row command output by the row command arbiter at T0 occupies 1.5 clock cycles of the command bus, the row command arbiter does not output a row command at T1 (the row command output by T0 still occupies the command bus at T1) and must wait to output a row command at T2. Consequently, the row command output by the row command arbiter from T2 to T3 corresponds to the replicated row command sent to the row command arbiter by the command replicator from T0 to T1. Based on this, as an optional implementation, from T2 to T3, the row command arbiter outputs replicated row commands in the order in which the replicated row commands were sent to the row command arbiter from T0 to T1, and instructs the output replicated row commands to be transmitted via the first virtual channel.

[0147] As an optional implementation, FIG5B exemplarily shows another flowchart of the memory access method provided by an embodiment of the present disclosure. The method flow may be implemented by a row command arbiter. Referring to FIG5B , the method flow may include the following steps.

[0148] In step S520 , if the row command finally passed the arbitration is a non-duplicate row command, the row command arbiter outputs the row command and instructs it to be transmitted through the zeroth virtual channel.

[0149] In step S521, if the non-copied row command output by the row command arbiter occupies one clock cycle of the command bus, the non-copied row command is prohibited from participating in the final arbitration in the first clock cycle after the current clock cycle of outputting the non-copied row command.

[0150] In step S522 , the row command arbiter outputs the corresponding copied row command in the first clock cycle after the current clock cycle and indicates that the virtual channel address belongs to the first virtual channel.

[0151] Because the non-duplicated row command output by the row command arbiter at T0 occupies one clock cycle of the command bus, the row command arbiter can output the corresponding duplicated row command at T1 to maintain page state consistency between the zeroth virtual channel and the first virtual channel. Therefore, in the first clock cycle after T0 (i.e., T1), the row command arbiter should prohibit non-duplicated row commands from participating in the final arbitration. That is, the row command arbiter performs final arbitration on the row command from the command copier at T1, and the row command that passes the final arbitration is the duplicated row command corresponding to the row command output at T0. Furthermore, the row command arbiter outputs the corresponding duplicated row command at T1 and indicates that the virtual channel address belongs to the first virtual channel.

[0152] As an optional implementation, FIG5C exemplarily shows another flowchart of the memory access method provided by an embodiment of the present disclosure. This method flow can be implemented by a row command arbiter. Referring to FIG5C , this method flow can include the following steps.

[0153] In step S530 , if the row command finally passed the arbitration is a non-duplicate row command, the row command arbiter outputs the row command and instructs it to be transmitted through the zeroth virtual channel.

[0154] In step S531, if the output non-copied row command occupies 0.5 clock cycles of the command bus, then in the 0.5 clock cycle after the current clock cycle of the output row command, the row command that does not conflict with the output row command and occupies 0.5 clock cycles of the command bus is selected to participate in the final arbitration.

[0155] In step S532 , the row command arbiter prohibits non-copied row commands from participating in arbitration in the first clock cycle after the current clock cycle.

[0156] If the non-copied row command output by the row command arbiter at T0 occupies 0.5 clock cycles of the command bus, the row command arbiter may select a row command to participate in the final arbitration in the 0.5 clock cycle after T0 (i.e., the next 0.5 clock cycles after the current clock cycle, set as T0.5); the row command selected by the row command arbiter to participate in the final arbitration should meet the following conditions: it does not conflict with the non-copied row command output by T0, and the clock cycle of the command bus is 0.5 clock cycles, so that the row command participating in the final arbitration at T0.5 corresponds to the non-copied row command output by T0 occupying 0.5 clock cycles of the command bus.

[0157] Furthermore, at T1 after T0 , the row command arbiter prohibits non-copied row commands from participating in the final arbitration. That is, the row command arbiter prohibits row commands not from the command copier from participating in the arbitration at T1 .

[0158] In a further optional implementation, the selected row command that occupies 0.5 clock cycles of the command bus can be output by the row command arbiter in the first clock cycle, the output row command is copied by the command copier, and the corresponding copied row command can be output by the row command arbiter 0.5 clock cycles after the first clock cycle.

[0159] In step S533, the row command arbiter outputs the copied row commands in sequence in the first clock cycle after the current clock cycle according to the time sequence of the copied row commands being sent in the current clock cycle and indicates that the virtual channel address belongs to the first virtual channel.

[0160] Because the non-duplicate row command output by the row command arbiter at T0 occupies 0.5 clock cycles of the command bus, the row command arbiter can output the duplicate row command at T1. At T1, the row command arbiter can output the duplicate row commands in the order in which the duplicate row commands were input to the row command arbiter at T0, and instruct the output duplicate row commands to be transmitted via the first virtual channel.

[0161] In a further optional implementation, in order to ensure the timing correctness of memory access, the shared control logic circuit may consider the timing parameters of the command output by the final arbitrator when determining the request command sent to the final arbitrator, so as to ensure that the timing of the request command sent to the final arbitrator corresponds to the timing of the command output by the final arbitrator. As an optional implementation, the shared control logic circuit may also be configured to: determine the timing parameters related to memory access (such as recording and detecting various timing parameters used for memory access requests) to ensure the correctness of memory access operations. It should be noted that the timing parameters related to memory access can be various time-related parameters involved in memory access operations, and the timing parameters are designed to ensure the correctness of memory access operations. That is to say, in a computer system, the reading and writing of data in the memory need to be performed within a certain time sequence to ensure correct data exchange and storage.

[0162] In an optional implementation, the shared control logic circuit can determine memory access-related timing parameters based on a timing parameter count. For example, when the final arbitrator outputs a non-replicated command, the shared control logic circuit can sample the command output by the final arbitrator and, based on the timing parameter count, initiate timing parameter counting for the sampled command. As an optional implementation, the timing parameters of the command count can be used by the shared control logic circuit to determine the request command sent to the final arbitrator, so that the timing of the request command sent to the final arbitrator corresponds to the timing of the command output by the final arbitrator, thereby ensuring the correct timing of memory access.

[0163] As an optional implementation, the clock cycle based on the command occupying the command bus may include 0.5 clock cycles, 1 clock cycle, and 1.5 clock cycles; the embodiment of the present disclosure may use the command occupying 1.5 clock cycles of the command bus as the starting point for counting timing parameters as the basis for counting timing parameters.

[0164] In an optional implementation, in order to make the counting basis of the timing parameters more convenient and timely, for commands that occupy 1.5 clock cycles of the command bus, the embodiment of the present disclosure uses the first clock rising edge when the command is output by the final arbitrator as the starting position to count the timing parameters, thereby making the command that occupies 1.5 clock cycles of the command bus one clock cycle earlier than the standard clock cycle.

[0165] It should be noted that under the requirements of memory protocols such as HBM3, the command timing parameter counting starts with the second clock rising edge (that is, the starting point of the standard clock cycle can be regarded as the second clock rising edge of the command output by the final arbitrator). In the embodiment of the present disclosure, for commands that occupy 1.5 clock cycles of the command bus, the timing parameter counting starts with the first clock rising edge of the command output by the final arbitrator, which is equivalent to advancing the start time of the command timing parameter counting by 1 clock cycle.

[0166] That is to say, for commands that occupy 1.5 clock cycles of the command bus, the embodiment of the present disclosure uses the first clock rising edge output by the final arbiter of the command as the starting position for timing (that is, the starting point of timing parameter counting), instead of waiting for one clock cycle to start counting the timing parameters. This can make the timing of commands that occupy 1.5 clock cycles of the command bus more convenient; and, by timing the commands that occupy 1.5 clock cycles of the command bus in advance, the timing update time can be advanced, thereby advancing the time for subsequent screening of commands that do not meet the timing conditions, thereby improving the timeliness of screening commands that do not meet the timing conditions.

[0167] Based on the counting basis of the timing parameters (for commands that occupy 1.5 clock cycles of the command bus, the timing parameter counting starts at the first rising edge of the clock when the command is output by the final arbitrator), as an optional implementation, when the embodiment of the present disclosure samples the non-replicated commands output by the final arbitrator and starts timing parameter counting for the sampled commands, the timing parameter counting basis can be used as the basis to count the timing parameters of the currently sampled command according to the change in the clock cycle of the command bus occupied by the sampled adjacent commands.

[0168] As an optional implementation, the clock cycle of the command bus occupied by a command can be divided into 0.5 clock cycles, 1 clock cycle, and 1.5 clock cycles. The clock cycle of the command bus occupied by sampled adjacent commands (for example, the two non-duplicate commands output by the final arbiter) may vary as follows:

[0169] 1 clock cycle to 1 clock cycle, 0.5 clock cycle to 0.5 clock cycle, 1.5 clock cycles to 1.5 clock cycles, 1 clock cycle to 0.5 clock cycle, 0.5 clock cycle to 1 clock cycle, 1.5 clock cycles to 0.5 clock cycle, 1.5 clock cycles to 1 clock cycle, 0.5 clock cycle to 1.5 clock cycles, 1 clock cycle to 1.5 clock cycles, etc.

[0170] The following describes an optional implementation method for counting timing parameters of sampled commands according to an embodiment of the present disclosure, targeting different situations where the clock cycle changes. As an optional implementation, FIG6 exemplarily illustrates an optional flow chart for counting timing parameters of commands according to an embodiment of the present disclosure. This method flow can be implemented by a shared control logic circuit. Referring to FIG6 , this method flow can include the following steps.

[0171] In step S610 , the clock cycle variation of the command bus occupied by the sampled adjacent commands is determined.

[0172] In step S611, if the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 1 clock cycle to 1 clock cycle, 0.5 clock cycle to 0.5 clock cycle, 1.5 clock cycles to 1.5 clock cycles, 1 clock cycle to 0.5 clock cycle, and 0.5 clock cycle to 1 clock cycle, then based on the counting basis of the timing parameters, the timing parameters of the currently sampled command are counted according to the standard clock cycle.

[0173] For ease of explanation, the clock cycle can be defined as T, so that a command that occupies 0.5T (0.5 clock cycles) of the command bus can be called a 0.5T command, a command that occupies 1T (1 clock cycle) of the command bus can be called a 1T command, and a command that occupies 1.5T (1.5 clock cycles) of the command bus can be called a 1.5T command.

[0174] If the sampled adjacent commands are 1T commands to 1T commands (i.e., the clock cycle of the command bus occupied by the sampled adjacent commands changes from 1 clock cycle to 1 clock cycle), the embodiment of the present disclosure can count the timing parameters of the currently sampled commands according to the standard clock cycle based on the counting basis of the timing parameters described above, for example, according to the standard timing parameters required by memory technologies such as HBM3, such as counting the timing parameters with the second clock rising edge of the command output as the starting position.

[0175] Similarly, for the cases where the sampled adjacent commands are 0.5T command to 0.5T command, 1.5T command to 1.5T command (since the 1.5T command is counted for timing parameters 1T in advance, the timing of the 1.5T command to the 1.5T command can offset each other, thereby maintaining the calculation according to the standard timing parameters to meet the timing requirements), 1T command to 0.5T command, and 0.5T command to 1T command, the embodiment of the present disclosure can count the timing parameters of the currently sampled command according to the standard clock cycle based on the counting basis of the timing parameters described above.

[0176] In step S612, if the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 1.5 clock cycles to 0.5 clock cycles and 1.5 clock cycles to 1 clock cycle, then based on the counting basis of the timing parameters, the currently sampled command is counted according to the standard clock cycle plus 2 clock cycles.

[0177] If the sampled adjacent command is a 1.5T command to a 0.5T command (i.e., the clock cycle of the command bus occupied by the sampled adjacent command changes from 1.5 clock cycles to 0.5 clock cycles), the embodiment of the present disclosure can count the timing parameters of the currently sampled command based on the counting basis of the timing parameters described above, according to the standard clock cycle plus 2 clock cycles, for example, counting according to the standard timing parameters required by memory such as HBM3 plus 2 clock cycles.

[0178] It should be noted that, in the embodiment of the present disclosure, the 1.5T command uses the first rising clock edge of the command output by the final arbiter as the starting point for timing parameter counting, which is one clock cycle earlier than the standard timing parameter. Therefore, for the case of a 1.5T command to a 0.5T command, since the time interval is 1T, the timing parameter counting should be performed by adding one clock cycle to the standard timing parameter. At the same time, based on the arbitration scheduling method for the 1.5T command described above (see FIG. 5A ), if only one clock cycle is added to the standard timing parameter for the case of a 1.5T command to a 0.5T command, the timing parameter count for the case of a 1.5T command to a 1T command transmitted through the first virtual channel will be one clock cycle less than the standard timing parameter. Therefore, to compensate for this, the embodiment of the present disclosure adds two clock cycles to the standard timing parameter for the case of a 1.5T command to a 0.5T command.

[0179] That is, the 1.5T command starts counting according to the first rising edge when it is output by the final arbiter, which is 1T earlier than the second rising edge required by memory protocols such as HBM3. For example, assuming that the time when the 1.5T command is output by the final arbiter is time T0, the timing parameter counting of the 1.5T command starts at time T1. At the same time, according to the solution provided by the embodiment of the present disclosure, if the final arbiter outputs a non-duplicate 1.5T command at time T0 (the virtual channel address belongs to the zeroth virtual channel), then the final arbiter starts outputting a duplicate 1.5T command (the virtual channel address belongs to the first virtual channel) at time T2. An optional implementation method can be specifically shown in Figure 5A. Based on the above situation, assuming that the output interval from the 1.5T command to the 0.5T command is N clock cycles, then at time T(N+1), the arbiter can finally start outputting a non-replicated 0.5T command indicating the zeroth virtual channel. This shows that the 0.5T command is separated from time T1, when the timing parameter counting of the 1.5T command starts, by N clock cycles, and from time T0, when the 1.5T command is output, by N+1 clock cycles.

[0180] At the same time, based on the command copy rules of the embodiment of the present disclosure, the final arbiter must output a corresponding copied 0.5T command indicating the first virtual channel at time T(N+2), and the corresponding copied 1.5T command transmitted through the first virtual channel is output at time T2 (memory protocols such as HBM3 require that the 1.5T command must be output starting from the rising edge of the clock), and the corresponding copied 1.5T command begins timing parameter counting at time T3. That is, for the non-copied 1.5T command and the non-copied 0.5T command, there are corresponding copied commands (i.e., the copied 1.5T command and the copied 0.5T command), and the copied 1.5T command starts timing parameter counting at time T3, and the copied 0.5T command is output by the final arbitrator at time T(N+2). The interval between time T3 and time T(N+2) is N-1 clock cycles, which is less than the timing requirement of the N clock cycle interval. Therefore, the embodiment of the present disclosure uses standard timing parameters plus 2 clock cycles for timing parameter counting for the 1.5T command to the 0.5T command to meet the timing requirements of the corresponding copied command in the first virtual channel.

[0181] Similarly, when the sampled adjacent commands are 1.5T commands to 1T commands, the embodiment of the present disclosure can count the timing parameters of the currently sampled command based on the counting basis of the timing parameters described above, according to the standard clock cycle plus 2 clock cycles.

[0182] In step S613, if the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 0.5 clock cycles to 1.5 clock cycles and 1 clock cycle to 1.5 clock cycles, then based on the counting basis of the timing parameters, the currently sampled command is counted according to the standard clock cycle minus 1 clock cycle.

[0183] If the sampled adjacent command is a 0.5T command to a 1.5T command (i.e., the clock cycle of the command bus occupied by the sampled adjacent command varies from 0.5 clock cycles to 1.5 clock cycles), the embodiment of the present disclosure can count the timing parameters of the currently sampled command based on the counting basis of the timing parameters described above, according to the standard clock cycle minus 1 clock cycle, for example, counting according to the standard timing parameters required by memory such as HBM3 minus 1 clock cycle.

[0184] It should be noted that since the 1.5T command uses the first rising clock edge output by the final arbitrator as the starting point for timing parameter counting, which is one clock cycle earlier than the standard timing parameters, the timing interval from the 0.5T command to the 1.5T command should be considered. The starting point for the timing parameter counting from the 0.5T command to the 1.5T command should be one clock cycle less than the standard timing parameters.

[0185] Similarly, when the sampled adjacent commands are 1T commands to 1.5T commands, the embodiment of the present disclosure can count the currently sampled commands based on the counting basis of the timing parameters described above, according to the standard clock cycle minus 1 clock cycle.

[0186] As an optional implementation, a shared timing check module, common to both the zeroth virtual channel and the first virtual channel, can be provided within the shared control logic circuit to implement the aforementioned process of determining timing parameters related to memory access. For example, the shared control logic circuit can sample the non-duplicate commands output by the final arbiter and initiate timing parameter counting for the sampled commands. By adjusting the timing parameter count in this manner, timing can be achieved for the zeroth virtual channel, thereby meeting the timing requirements for both the zeroth virtual channel and the first virtual channel, thereby simplifying the timing logic.

[0187] The timing parameter counting method provided by the embodiment of the present disclosure can assist the memory controller in the coordinated control of the zeroth virtual channel and the first virtual channel, so that the zeroth virtual channel and the first virtual channel can calibrate the timing and ensure the correctness of the timing, and the timing parameter counting method provided by the embodiment of the present disclosure can simplify the logic of the memory controller in performing timing checks. In other words, the timing parameter counting method of the embodiment of the present disclosure can be combined with the command copy method and the command arbitration scheduling method described above to further achieve the coordinated control of the zeroth virtual channel and the first virtual channel, so that the memory controller can manage and control the zeroth virtual channel and the first virtual channel in the manner of an overall channel, and ensure that the commands transmitted by the zeroth virtual channel and the first virtual channel can meet the timing and page status requirements of their respective virtual channels, thereby ensuring the correctness of memory access.

[0188] Specifically, the embodiment of the present disclosure samples the non-copied commands output by the final arbiter, and based on the counting of the timing parameters, starts timing parameter counting for the sampled commands. At the same time, when counting the timing parameters, the sampled commands are counted according to the changes in the clock cycles of the command bus occupied by the sampled adjacent commands, thereby ensuring the timing correctness of the non-copied commands transmitted on the zeroth virtual channel and maintaining the timing correctness of the copied commands transmitted on the first virtual channel.

[0189] Furthermore, the embodiment of the present disclosure ensures the consistency of the page status of the zeroth virtual channel and the first virtual channel by means of command replication. For example, for row commands (commands other than column commands such as read commands and write commands), the embodiment of the present disclosure ensures that the row commands transmitted by the first virtual channel are consistent with the row commands transmitted by the zeroth virtual channel by replicating the row commands transmitted by the zeroth virtual channel. Therefore, in the case where the row command affects the page status, the embodiment of the present disclosure can ensure that the effects of the row command on the page status of the zeroth virtual channel and the first virtual channel are consistent.

[0190] Moreover, for column commands such as read commands and write commands, for column commands triggered by memory access requests of the second data length (for example, 64 bytes), the embodiment of the present disclosure can transmit the marked real column commands on both the zeroth virtual channel and the first virtual channel (the real column commands transmitted by the first virtual channel can be obtained by copying), and the column commands transmitted by the zeroth virtual channel and the first virtual channel can carry consistent automatic precharge instructions (automatic precharge will affect the page state), thereby ensuring that the column commands triggered by the memory access request of the second data length (for example, 64 bytes) (carrying automatic precharge instructions) have the same impact on the page state of the zeroth virtual channel and the first virtual channel. For column commands triggered by memory access requests of the first data length (for example, 32 bytes), the embodiment of the present disclosure can transmit the marked real column commands on the corresponding virtual channel according to the virtual channel address indicated by the memory access request, and the column commands do not carry automatic precharge instructions, so that the marked real column commands will not affect the page state and guarantee the memory access requirements of the first data length (for example, 32 bytes).

[0191] It can be seen that the solution provided by the embodiment of the present disclosure can realize the coordinated control of the zeroth virtual channel and the first virtual channel through a set of control logic inside the memory controller, reduce the number of control logic circuits used by the memory controller, and reduce the overhead of the memory controller; and, can ensure the correctness of memory access (such as ensuring the consistency of the timing and page status of the zeroth virtual channel and the first virtual channel) while ensuring the memory access requirements of the memory access request.

[0192] In a further optional implementation, the shared control logic circuit may further implement at least one of the following functions: storing request information of memory access requests, recording block information of blocks in the memory, managing memory refresh operations, etc. In an optional implementation, FIG7 exemplarily shows another example diagram of a memory controller provided by an embodiment of the present disclosure. In conjunction with FIG2 , FIG4A , and FIG7 , the shared control logic circuit 210 in the memory controller may include: a shared command queue 710 , a shared page recording module 720 , a shared timing check module 730 , a shared refresh control module 740 , and a shared queue arbiter 750 .

[0193] The shared command queue 710 is a command queue shared by the zeroth virtual channel and the first virtual channel set in the memory controller, and is used to store at least request information of memory access requests. In an optional implementation, the memory controller can perform address decoding processing on the memory access request issued by the processor core to obtain the request information of the memory access request after address decoding processing, so that the request information of the memory access request after address decoding processing can be stored in the shared command queue 710. For example, the memory controller can be provided with an address decoding module, which can perform address decoding processing on the memory access request issued by the processor core and send the request information of the memory access request after address decoding processing to the shared command queue 710 for storage. As an optional implementation, the set bit of the physical address of the memory access request can carry the virtual channel address. For example, the fifth bit (bit 5) of the physical address of the memory access request can carry the virtual channel address. Therefore, when the memory access request is address decoded, the virtual channel address can be determined from the set bit (e.g., bit 5) of the physical address of the memory access request, and the virtual channel to which the virtual channel address belongs is used as the virtual channel corresponding to the memory access request.

[0194] The request information of the memory access request stored in the shared command queue may include the virtual channel address of the memory access request; the virtual channel address of the memory access request is used to indicate whether the column command is marked as true or false when the final arbiter outputs the column command. It should be noted that, in the embodiment of the present disclosure, the virtual channel address of the memory access request may have no other uses other than indicating whether the column command is marked as true or false. In other words, the virtual channel address of the memory access request is not used by other functional modules of the memory controller other than indicating whether the column command is marked as true or false.

[0195] It can be seen that, unlike the method of setting up an independent control logic circuit for each virtual channel, the embodiment of the present disclosure does not need to set up an independent command queue for each virtual channel (for example, there is no need to set up an independent command queue for the zeroth virtual channel, nor is there a need to set up an independent command queue for the first virtual channel). Instead, the request information of the memory access request is uniformly stored in the common command queue 710 without distinguishing the virtual channel address of the memory access request; therefore, the embodiment of the present disclosure can reduce the number of command queues. For example, compared with setting up independent command queues for the zeroth virtual channel and the first virtual channel respectively, the embodiment of the present disclosure can save one command queue, thereby reducing the number of control logics and overhead at the command queue level.

[0196] The shared page recording module 720 is a page recording module shared by the zeroth virtual channel and the first virtual channel set in the memory controller, and is configured to record the block information of the block in the memory. The shared page recording module 720 can record the block information of the block in the memory without paying attention to and using the virtual channel address. As an optional implementation, the block information of the block may include but is not limited to: the address information and page status information of the block. The page status information of the block may include at least: the buffer status of the block; the buffer status of the block records whether the buffer of the block is currently loaded with a row, and when the buffer of the block loads the row of the block, records the loaded row. Optionally, the address information of the block may include: block address, stack ID, row address. For example, the block information of the block may include block address, stack ID, row address, and information on whether the block is loaded with a row. In the embodiment of the present disclosure, the common page recording module does not record the virtual channel address of the memory access request, which can reduce the recording unit of the common page recording module by half, and uses the block address, stack ID and row address as the address information in the block information recorded by the common page recording module, which can reduce the amount of address information recorded by the common page recording module, thereby saving the area occupied by the common page recording module in the memory controller.

[0197] As an optional implementation, after a memory access request enters the memory controller, the memory controller can perform address decoding to query the block information of the block in the shared page record module, compare whether the row accessed by the memory access request is consistent with the target block, and whether the target block is loaded with a row; thereby determining the page hit status such as page hit, miss or conflict for the memory access request.

[0198] As an optional implementation, when the final arbitrator outputs a row command that is not from the command copier, the common page recording module 720 may sample the row command issued by the final arbitrator and update the block information of the block corresponding to the row pointed to by the row command.

[0199] It can be seen that, unlike the method of setting an independent control logic circuit for each virtual channel, the embodiment of the present disclosure does not need to set an independent page recording module for each virtual channel. For example, there is no need to independently set a page recording module for the zeroth virtual channel, nor is there a need to independently set a page recording module for the first virtual channel. Instead, without distinguishing the virtual channel addresses of the memory access requests, a common page recording module shared by the zeroth virtual channel and the first virtual channel is used to record the block information of the blocks in the memory; furthermore, the embodiment of the present disclosure can reduce the number of page recording modules. For example, compared with independently setting page recording modules for the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can save one page recording module, thereby reducing the number of control logics and overhead at the page recording module level.

[0200] The shared timing check module 730 is a timing check module shared by the zeroth virtual channel and the first virtual channel set in the memory controller, and is configured to determine the timing parameters related to memory access (such as recording and detecting various timing parameters used for memory access requests) to ensure the correctness of memory access operations. The shared timing check module can determine the timing parameters related to memory access without paying attention to or using the virtual channel address. For example, when the final arbitrator outputs a non-copied command, the command output by the final arbitrator is sampled and the timing parameter counting of the command is started. The relevant content of the timing parameter counting can be referred to the description of the corresponding part of the previous text and will not be expanded here.

[0201] It can be seen that, unlike the method of setting an independent control logic circuit for each virtual channel, the embodiment of the present disclosure does not need to set an independent timing check module for each virtual channel. For example, there is no need to independently set a timing check module for the zeroth virtual channel, nor is there a need to independently set a timing check module for the first virtual channel. Instead, without distinguishing the virtual channel addresses of the memory access requests, a common timing check module shared by the zeroth virtual channel and the first virtual channel is used to determine the timing parameters related to the memory access; furthermore, the embodiment of the present disclosure can reduce the number of timing check modules. For example, compared with independently setting timing check modules for the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can save one timing check module, thereby reducing the number of control logics and overhead at the level of the timing check modules.

[0202] The shared refresh control module 740 is a refresh control module shared by the zeroth virtual channel and the first virtual channel set in the memory controller, and is configured to manage the refresh operation of the memory, for example, to control the refresh operation of the memory and generate corresponding refresh commands. The shared refresh control module can manage the refresh operation of the memory without paying attention to or using the virtual channel address. It should be noted that the refresh command is used to refresh the memory to prevent the loss of memory data; for example, for types of memory such as DRAM, due to the existence of charge leakage, it is necessary to refresh regularly to prevent the loss of memory data. As an optional implementation, the refresh command can be divided into a full block refresh command and a single block refresh command.

[0203] In a further optional implementation, the shared refresh control module 740 may generate any one of the following commands: a single-block precharge (PCHGpb) command, a full-block precharge (PCHGab) command, a single-block refresh (REFpb) command, a full-block refresh (REFab) command, an RFMab command, and an RFMpb command as needed.

[0204] In a further optional implementation, the shared refresh control module 740 may also be configured to monitor the cumulative number of times a block in the memory is activated.

[0205] In an optional implementation, when the final arbitrator outputs a non-replicated row command, if the row command belongs to any of the single block refresh (REFpb) command, the full block refresh (REFab) command, the RFMab command, and the RFMpb command, the shared refresh control module can sample the row command issued by the final arbitrator and update the status of the row command; as an optional implementation, when the row command is sent to the memory, the status of the row command can indicate information such as the address of the block corresponding to the row indicated by the row command.

[0206] It should be noted that refresh commands must comply with the refresh interval. Therefore, the shared refresh control module needs to sample the non-duplicate row commands issued by the final arbiter to confirm whether the final arbiter has arbitrated to send the refresh command to the memory, so as to maintain the refresh command generation according to the refresh interval. For example, for a single-block refresh (REFpb) command, if the single-block refresh (REFpb) command refreshes a specific block of memory, after issuing the single-block refresh (REFpb) command for that block, a certain refresh interval must be followed before issuing the single-block refresh (REFpb) command for the same block again. Therefore, the shared refresh control module needs to sample the non-duplicate row commands issued by the final arbitrator to confirm whether the final arbitrator sends the single-block refresh (REFpb) command to the memory to ensure that the refreshed block is refreshed after a certain refresh interval. At this time, the shared refresh control module can update the status of the single-block refresh (REFpb) command to ensure that the single-block refresh (REFpb) command sent to the memory can be sent according to the certain refresh interval when refreshing a certain block.

[0207] It can be seen that, unlike the method of setting an independent control logic circuit for each virtual channel, the embodiment of the present disclosure does not need to set an independent refresh control module for each virtual channel. For example, there is no need to independently set a refresh control module for the zeroth virtual channel, nor is there a need to independently set a refresh control module for the first virtual channel. Instead, without distinguishing the virtual channel addresses of memory access requests, the refresh control module shared by the zeroth virtual channel and the first virtual channel is used to be responsible for the memory refresh operation; furthermore, the embodiment of the present disclosure can reduce the number of refresh control modules. For example, compared with independently setting refresh control modules for the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can save one refresh control module, thereby reducing the number of control logics and overhead at the refresh control module level.

[0208] The shared queue arbiter 750 is a queue arbiter shared by the zeroth virtual channel and the first virtual channel in the memory controller. It can determine the request command sent to the final arbiter for final arbitration. As an optional implementation, based on the configuration of the shared page recording module 720, the shared timing check module 730, and the shared refresh control module 740, the shared queue arbiter can determine the request command sent to the final arbiter corresponding to the memory access request based on information provided by at least one of the shared page recording module 720, the shared timing check module 730, and the shared refresh control module 740, as well as the request information of the memory access request stored in the shared command queue 710. The shared page recording module 720 at least provides block information of the blocks in the memory, the shared timing check module 730 at least provides timing parameters for the non-replicated command output by the final arbiter, and the shared refresh control module 740 can at least provide a refresh command (further, the shared refresh control module 740 can also provide precharge commands, RFMab commands, RFMpb commands, etc.).

[0209] As an optional implementation, based on information provided by at least one of the shared page recording module 720, the shared timing check module 730, and the shared refresh control module 740, the shared queue arbiter can determine the command for the memory access request that will participate in the shared queue arbiter's initial arbitration. Furthermore, the shared queue arbiter can determine the request command that will be sent to the final arbiter corresponding to the memory access request from the commands that participated in the initial arbitration. In other words, the shared queue arbiter can determine the request command that will be sent to the final arbiter corresponding to the memory access request through the initial arbitration. Furthermore, when selecting the command that will participate in the initial arbitration, the shared queue arbiter can combine information provided by at least one of the shared page recording module 720, the shared timing check module 730, and the shared refresh control module 740.

[0210] It should be noted that the shared queue arbiter determines the strategy and method for commands participating in the initial arbitration based on at least one of the block information of the block provided by the shared page recording module, the timing parameters provided by the shared timing check module, and the command provided by the shared refresh control module. This strategy and method can be defined and set according to actual circumstances and is not limited by the present embodiment. For example, the page hit status of the memory access request is determined based on the buffer status of the block provided by the shared page recording module; if the timing is consistent with the timing parameters provided by the shared timing check module, different commands participating in the initial arbitration are generated based on different page hit statuses of the memory access request.

[0211] In an optional implementation, the shared queue arbiter can determine the page hit status of the memory access request based on at least the block information of the block recorded by the shared page recording module and the address information in the request information of the memory access request stored in the shared command queue; determine the command for the memory access request to participate in the initial arbitration of the shared queue arbiter based on the page hit status of the memory access request (further, the command for the memory access request to participate in the initial arbitration of the shared queue arbiter can be determined based on the page hit status of the memory access request when the timing is consistent with the timing parameters provided by the shared timing check module); and then, determine the request command corresponding to the memory access request sent to the final arbitrator from the commands participating in the initial arbitration.

[0212] As an optional implementation, FIG8 exemplarily shows an optional flowchart for determining a request command for a memory access request provided in an embodiment of the present disclosure. The process may be implemented by a shared queue arbiter. Referring to FIG8 , the process may include the following steps.

[0213] In step S810 , a page hit status of the memory access request is determined according to the address information of the memory access request.

[0214] In an optional implementation, the block-based page status information includes a buffer status. As an optional implementation method for the shared queue arbiter to determine the page hit status of a memory access request, the shared queue arbiter can query the buffer status of the corresponding block recorded by the shared page recording module based on the address information of the memory access request (for example, based on the address information of the memory access request, determine the block corresponding to the address information, and then query the buffer status of the corresponding block recorded by the shared page recording module), and then determine the page hit status of the memory access request based on the buffer status of the queried block.

[0215] For example, if the buffer status of the queried block indicates that the buffer does not load any row, then the page hit situation of the memory access request is confirmed to be a page miss; if the buffer status of the queried block indicates that the buffer loads a row, and it is determined that the row loaded in the buffer is consistent with the row pointed to by the memory access request, then the page hit situation of the memory access request is confirmed to be a page hit; if the buffer status of the queried block indicates that the buffer loads a row, and it is determined that the row loaded in the buffer is inconsistent with the row pointed to by the memory access request, then the page hit situation of the memory access request is confirmed to be a page conflict.

[0216] In step S811 , if the page hit condition is a page miss, it is determined that the command for the memory access request to participate in the initial arbitration is a row activation command.

[0217] As an optional implementation, if the page hit status of the memory access request is a page miss, since the block's buffer does not load any rows at this time, it is necessary to use a row activation command to load the row pointed to by the memory access request into the block's buffer, and then the column selection command can be used to read or write data in the row pointed to by the memory access request; therefore, when it is determined that the page hit status of the memory access request is a page miss, a row activation command can be generated to participate in the initial arbitration.

[0218] In step S812 , if the page hit condition is a page hit, it is determined that the command of the memory access request participating in the initial arbitration is a column command.

[0219] If the page hit status of the memory access request is determined to be a page hit, since the row pointed to by the memory access request has been loaded into the block's buffer at this time, data can be directly read or written to the row pointed to by the memory access request. Therefore, the embodiment of the present disclosure can generate a read command or a write command based on the command flag of the memory access request (e.g., a read / write flag) and participate in the initial arbitration. For example, if the memory access request is a read request, a read command can be generated and participate in the initial arbitration based on the command flag of the read request being read; if the memory access request is a write request, a write command can be generated and participate in the initial arbitration based on the command flag of the write request being write.

[0220] In one implementation example, based on the memory cells storing data corresponding to the columns of a row of a block, when the row pointed to by a memory access request has been loaded into the buffer of the block, a column strobe command can be used to select a column in the row to read or write data to the selected column. For example, the column strobe command can select a column in a row of a block, thereby concurrently reading or writing data of a specified starting column and subsequent columns. Therefore, when the page hit condition of the memory access request is a page hit, a column strobe command can be generated and participate in initial arbitration. For example, when the page hit condition of the memory access request is a page hit, if the memory access request is a read request, a column strobe command for a read operation (i.e., a read command) can be generated to participate in initial arbitration; if the memory access request is a write request, a column strobe command for a write operation (i.e., a write command) can be generated to participate in transmission arbitration.

[0221] In step S813 , if the page hit condition is a page conflict, it is determined that the command of the memory access request participating in the initial arbitration is a precharge command.

[0222] As an optional implementation, if the page hit of the memory access request is a page conflict, since the row pointed to by the memory access request is inconsistent with the row loaded in the block's buffer, the block needs to be precharged first, and then the row pointed to by the memory access request can be loaded into the block's buffer through a row activation command, and then data can be read and written in the row pointed to by the memory access request through a column selection command; therefore, when it is determined that the page hit of the memory access request is a page conflict, a precharge command can be generated (the precharge command is used to precharge the block corresponding to the row pointed to by the memory access request) and participate in the initial arbitration. The generated precharge command can be a single-block precharge command, and indicates that the precharged block is the block where the row pointed to by the memory access request is located.

[0223] It should be noted that, for the memory access request sent by the processor core, the same memory access request may successively generate a precharge command, a row activation command, and a column strobe command to participate in the initial arbitration. For example, when the page hit situation of a certain memory access request is a page conflict, a precharge command may be generated to participate in the initial arbitration, so that the block where the row pointed to by the memory access request is located can be precharged through the precharge command, but the subsequent page hit situation of the memory access request may become a page miss, so a row activation command may be generated to participate in the initial arbitration, so that the row pointed to by the memory access request is loaded into the buffer of the block; further, when the page hit situation of the memory access request becomes a page hit, a column strobe command may be generated to participate in the initial arbitration to read or write data to the selected column. Of course, the embodiment of the present disclosure may also successively generate a row activation command and a column strobe command for the same memory access request. The corresponding situation can be combined with the previous description and will not be expanded here.

[0224] In step S814, at most one row activation command, one column command, and one precharge command are simultaneously determined from the commands participating in the initial arbitration as request commands sent to the final arbitrator.

[0225] When performing initial arbitration on commands participating in the initial arbitration, the shared queue arbiter may simultaneously select at most one row activation command, one column command, and one precharge command from the commands participating in the initial arbitration as request commands to be sent to the final arbiter. Furthermore, the shared queue arbiter does not consider the virtual channel address of the memory access request corresponding to the command during the initial arbitration. The shared queue arbiter's initial arbitration strategy can be set based on actual circumstances and is not limited in the presently disclosed embodiments.

[0226] It can be seen that, unlike the method of setting up an independent control logic circuit for each virtual channel, the embodiment of the present disclosure does not require an independent queue arbiter for each virtual channel. For example, there is no need to independently set up a queue arbiter for the zeroth virtual channel, nor is there a need to independently set up a queue arbiter for the first virtual channel. Instead, without distinguishing the virtual channel addresses of the memory access requests, the queue arbiter shared by the zeroth virtual channel and the first virtual channel is used to determine the request command for the memory access request to be sent to the final arbiter. Furthermore, the embodiment of the present disclosure can reduce the number of queue arbiters. For example, compared with independently setting up queue arbiters for the zeroth virtual channel and the first virtual channel, the embodiment of the present disclosure can save one queue arbiter, thereby reducing the amount of control logic and overhead at the queue arbiter level.

[0227] In a further optional implementation, the commands generated by the common refresh control module may also be sent to the final arbitrator for participation in the final arbitration. For example, the commands generated by the common refresh control module may include refresh commands (single-block refresh commands, full-block refresh commands, etc.), and the refresh commands generated by the common refresh control module may be sent to the final arbitrator for participation in the final arbitration. For another example, the commands generated by the common refresh control module may also include pre-charge commands (single-block pre-charge commands, full-block pre-charge commands, etc.), RFMab commands, RFMpb commands, and other commands. Any of these commands may be sent to the final arbitrator for participation in the final arbitration.

[0228] Therefore, in an optional implementation, the command from the shared logic circuit in the final arbiter may be a command from the shared queue arbiter or a command from the shared refresh control module. Furthermore, the final arbiter can perform final arbitration on the commands input by the shared queue arbiter, shared refresh control module, and command replicator, determine the command that ultimately passes arbitration, and output it. The content of the arbitration scheduling command of the final arbiter can be found in the corresponding description above and will not be elaborated here.

[0229] It can be seen that the logical components in the shared control logic circuit include, but are not limited to, a shared command queue, a shared queue arbiter, a shared page record module, a shared refresh control module, a shared timing check module, etc., and the shared command queue stores the virtual channel address of the memory access request to indicate whether the column command is marked as true or false, and is not used for any other purpose. Therefore, these logical components can be shared by the zeroth virtual channel and the first virtual channel without considering the virtual channel address of the memory access request (i.e., without paying attention to or using the virtual channel address of the memory access request), thereby further reducing the amount of control logic in the memory controller and thus further reducing the memory controller's overhead. It should be further explained that the functional modules responsible for other functions in the memory controller (such as logical components) can also implement the functions of the functional modules without paying attention to or using the virtual channel address; for example, the low-power module can also implement low-power control without paying attention to or using the virtual channel address.

[0230] In a further optional implementation, Figure 9 exemplarily shows another example diagram of the memory controller provided by an embodiment of the present disclosure. In combination with Figures 2, 4A, 7 and 9, the memory controller may also include: a first interface 910, a write data cache 920, an address decoding module 930, a departure and response queue 940, and a second interface 950.

[0231] The first interface 910 may be an interface for the memory controller to connect to the processor core. For example, the first interface 910 is connected to the system bus, thereby connecting to the processor core through the system bus. The first interface 910 may receive memory access requests issued by an upstream module (e.g., a processor core) of the memory controller.

[0232] As an optional implementation, the type of memory access request issued by the processor core can be determined according to the processor architecture, memory type and chip design, and the embodiments of the present disclosure are not limited thereto. In one example, the memory access request can include any of the following: a read request and a write request.

[0233] The write data cache 920 is configured to store write data that needs to be written into the memory when the memory access request is a write request.

[0234] The address decoding module 930 can perform address decoding processing on the memory access request received by the first interface 910, and send the request information of the memory access request after address decoding processing to the shared control logic circuit, such as to the shared command queue. In an optional implementation, the address decoding module can map the physical address of the memory access request to the standard memory address according to the address mapping rules provided by the configuration register to implement address decoding processing on the memory access request; wherein the address mapping rules can record the mapping rules between the physical address of the memory access request and the standard memory address, and the mapping rules can be in the form of a mapping relationship or a mapping function.

[0235] It should be noted that the memory standard address can be regarded as the standard address format used by the memory, such as the standard address format of HBM3 memory, which corresponds to the actual storage location of the data stored in the memory. The physical address of the memory access request sent by the processor core is the upstream address. The format of the physical address of the memory access request is defined by the processor core. For example, the physical address of the memory access request is the address in the physical address space of the processor core, which is determined by the architecture and design of the processor core. By mapping the address in the physical address space of the processor core (the physical address of the memory access request) with the actual storage location of the data stored in the memory (the memory standard address), it can be ensured that the memory data of the memory access request can be correctly operated (for example, the memory data can be correctly read from or written to the memory). In addition, the memory controller can set a configuration register to record the above-mentioned address mapping rules; for example, the configuration register can be controlled by the memory controller and record a series of configuration information, and the configuration information includes the above-mentioned address mapping rules.

[0236] In an optional implementation, the request information obtained by the address decoding module 930 after performing address decoding processing on the memory access request may include, but is not limited to, the address information of the memory access request, the command flag of the memory access request, the data length of the memory access data (also known as the data size), and the priority of the memory access request. The request information of the memory access request may be sent to the shared control logic circuit (e.g., a shared command queue in the shared control logic circuit).

[0237] In an optional implementation, the address information of the memory access request may include: a standard memory address after the memory access request is processed by address decoding.

[0238] The command flag of the memory access request is used to indicate the memory access operation type of the memory access request, for example, indicating whether the memory access operation type of the memory access request is a read operation or a write operation; accordingly, the command flag may also be called a read / write flag.

[0239] The memory access data is data corresponding to the memory access operation of the memory access request, such as write data corresponding to a write request or read data corresponding to a read request. Accordingly, the data length of the memory access data is, for example, the data length of the write data or the data length of the read data. The data length corresponding to the memory access data of the memory access request may correspond to a second data length (e.g., 64 bytes) supported for transmission by a memory channel or a first data length (e.g., 32 bytes) supported for transmission by a virtual channel.

[0240] The priority of a memory access request may be the priority of a memory controller in responding to the memory access request. The priority of a memory access request may be defined by a processor core based on factors such as the urgency and importance of the memory access request when issuing the memory access request.

[0241] In a further optional implementation, when the address decoding module 930 performs address decoding processing on a memory access request, it can determine the virtual channel corresponding to the memory access request, such as determining the virtual channel address carried by the physical address of the memory access request (the virtual channel address carried by the physical address of the memory access request can be simply referred to as the virtual channel address of the memory access request). Thus, the virtual channel to which the virtual channel address of the memory access request belongs can be considered the virtual channel corresponding to the memory access request. As an optional implementation example, a set bit of the physical address of the memory access request can carry the virtual channel address, such as the fifth bit (bit 5) of the physical address of the memory access request can carry the virtual channel address. Thus, when the address decoding processing is performed on the memory access request, the virtual channel address can be determined from the set bit (e.g., bit 5) of the physical address of the memory access request, and the virtual channel to which the virtual channel address belongs can be used as the virtual channel corresponding to the memory access request. For example, if the virtual channel address of the memory access request belongs to the zeroth virtual channel, then the virtual channel corresponding to the memory access request is the zeroth virtual channel; if the virtual channel address of the memory access request belongs to the first virtual channel, then the virtual channel corresponding to the memory access request is the first virtual channel.

[0242] It should be noted that the data granularity controlled by the setting bit (e.g., bit 5) of the physical address of a memory access request can correspond to the amount of data transferred in one data transmission on a virtual channel. In one example, taking the data length corresponding to a read or write transaction of HBM3 technology as 32 bytes, the data granularity controlled by the setting bit (e.g., bit 5) of the physical address of the memory access request can be 32 bytes, corresponding to the amount of data transferred in one read or write transaction on a virtual channel of HBM3 technology.

[0243] It should be noted that although the shared control logic circuit does not distinguish the virtual channel address of the memory access request, when the memory access data of the memory access request is of the first data length (e.g., 32 bytes), the disclosed embodiment needs to use the virtual channel address of the memory access request when the final arbiter schedules the output of the column command to determine the virtual channel for actually transmitting the column command. Therefore, the virtual channel address of the memory access request can also be used as part of the request information of the memory access request (e.g., part of the address information of the memory access request). In other words, the request information of the memory access request can include the virtual channel address of the memory access request, and the virtual channel address of the memory access request is used to indicate whether the column command is marked as true or false when the final arbiter outputs the column command.

[0244] The dispatch and response queue 940 can be configured to receive the command output by the final arbitrator. That is, the command output by the final arbitrator can be sent to the dispatch and response queue 940. Thus, the dispatch and response queue 940 can send the command output by the final arbitrator to the memory according to the virtual channel indicated by the command output by the final arbitrator (e.g., the virtual channel address of the command output by the final arbitrator). In an optional implementation, the dispatch and response queue 940 can send the command to the memory via the second interface 950 and the memory physical layer, where the second interface 950 is connected to the memory physical layer.

[0245] In a further optional implementation, if the command output by the final arbitrator is a column command for a write operation, the departure and response queue 940 can send the column command for the write operation output by the final arbitrator and the corresponding write data stored in the write data cache 920 to the memory according to the virtual channel indicated by the column command for the write operation output by the final arbitrator.

[0246] In a further optional implementation, if the command output by the final arbitrator is a column command for a read operation, the dispatch and response queue 940 may send the column command for the read operation output by the final arbitrator to the memory according to the virtual channel indicated by the column command for the read operation output by the final arbitrator.

[0247] It should be noted that for the column command output by the final arbiter, if the column command is marked as true, the dispatch and response queue 940 sends the column command to the memory according to the virtual channel indicated by the column command (if the column command is a write command, it also sends the write data to the memory). If the column command output by the final arbiter is marked as false, the dispatch and response queue 940 discards the false column command and does not send it to the memory. The situations where the column command is marked as true and false can be referred to the corresponding description in the previous section and will not be elaborated here.

[0248] In a further optional implementation, since there is no real or fake labeling for row commands, the disclosed embodiment needs to ensure that the row commands (non-copied row commands and copied row commands) output by the final arbitrator can be truly sent to the memory. Therefore, when the command output by the final arbitrator is a row command, the dispatch and response queue 940 can send the row command output by the final arbitrator to the memory according to the virtual channel indicated by the row command output by the final arbitrator.

[0249] In a further optional implementation, in addition to sending the command output by the final arbitrator to the memory, the departure and response queue 940 can also receive read data returned from the memory after sending the read command to the memory. The read data corresponds to the column command of the read operation output by the final arbitrator (i.e., the read command). Therefore, the departure and response queue 940 can decide whether to return the received read data directly to the processor core based on the data length of the memory access request corresponding to the column command of the read operation, or wait until read data of sufficient data length is collected before returning the read data to the processor core.

[0250] In an implementation example, if the data length of the memory access request corresponding to the column command of the read operation is the second data length (for example, 64 bytes), then the data supported for transmission at one time based on a virtual channel is the first data length (for example, 32 bytes). The departure and response queue 940 can first cache the read data corresponding to the column command of a read operation, and then return the read data corresponding to the column command of the next read operation (that is, the read data returned in the next clock cycle) and the cached read data to the processor core together. A column command of a read operation corresponds to reading read data of the first data length.

[0251] That is, for a read request of a second data length (e.g., 64 bytes), the read data of the first data length (e.g., 32 bytes) returned by the first read command of the read request can be cached, and the read data of the first data length (e.g., 32 bytes) returned by the second read command of the read request (which can be a duplicate read command) in the next clock cycle can be not cached, but the read data returned by the second read command is sent to the processor core together with the read data of the cached first read command, thereby meeting the read requirement of the processor core for the second data length (e.g., 64 bytes). In an optional implementation, a read data cache can be set in the dispatch and response queues 940 to cache the read data; since the data length to be cached by the read data cache is the first data length (e.g., 32 bytes), the depth of the read data cache can support at least one column command of a read operation, and the width can at least correspond to the first data length; for example, the data cache capacity of the read data cache can be set to correspond to the first data length (e.g., 32 bytes). Of course, the disclosed embodiment can also support a data cache capacity of the read data cache greater than the first data length (e.g., 32 bytes).

[0252] Furthermore, if the data length of the memory access request corresponding to the column command of the read operation is the first data length, the dispatch and response queue 940 may return the read data directly to the processor core.

[0253] In a further optional implementation, for example, the dispatch and response queue 940 may send the command output from the final arbiter and the write data (for write commands) obtained from the write data cache 920 to the second interface 950 according to rules (for example, the dispatch and response queue 940 may decode the command into a format required by memory devices such as HBM3 and send it to the second interface 950 according to the rules required by HBM3). The command is then delivered to the memory via the second interface 950 and the memory physical layer. For read requests issued by the processor core, the dispatch and response queue 940 also receives read data returned from the memory. If the request is a 64-byte read, the dispatch and response queue 940 first stores the returned 32-byte read data in the internal read data cache. After collecting the next 32-byte read data, the dispatch and response queue 940 sends the returned 32-byte read data to the processor core along with the 32-byte read data already cached in the read data cache. If the request is a 32-byte read, the dispatch and response queue 940 may directly send the returned 32-byte read data to the processor core. It should be noted that since the corresponding read command for a 64-byte read request is sent to the memory in two consecutive clock cycles (a non-duplicate read command is sent to the memory in one clock cycle, and a duplicate read command is sent to the memory in the next clock cycle), the dispatch and response queue 940 can be configured with a depth of 1 (for example, to support one read command) and a read data buffer width of 32 bytes. Furthermore, the dispatch and response queue 940 can discard any column command marked as false and not send it to the memory.

[0254] The second interface 950 is an interface for connecting the memory controller to the memory physical layer. The second interface 950 can adopt the DFI (DDR PHY Interface) standard, etc. DFI can be regarded as an interface standard for connecting the memory controller and the memory physical layer. As a bridge between the memory controller and the memory physical layer, it can ensure normal communication and mutual coordination between the memory controller and the memory physical layer.

[0255] It should be noted that the memory access requests of the embodiments of the present disclosure are not limited to 64-byte and 32-byte. For example, the embodiments of the present disclosure can also support 128-byte memory access requests. For example, the 128-byte memory access request can be co-scheduled using two 64-byte memory channels. For example, the 128-byte memory access request is dispersed to two memory channels, and one memory channel processes the 64-byte memory access request, thereby processing the 64-byte memory access request through the two memory channels respectively to meet the 128-byte memory access requirement. Among them, the way in which the memory controller controls the zeroth virtual channel and the first virtual channel of a memory channel to process the 64-byte memory access request can be similarly referred to the description of the corresponding part above and will not be expanded here.

[0256] The disclosed embodiment can realize the coordinated control of the zeroth virtual channel and the first virtual channel through a set of control logic inside the memory controller, reduce the number of control logic circuits used by the memory controller (for example, the timing check module, page record module, queue arbiter, refresh control module and other arbitration-related control logic can be halved), thereby reducing the overhead of the memory controller. At the same time, the disclosed embodiment can preserve the correctness of memory access by ensuring the consistency of the timing and page status of the zeroth virtual channel and the first virtual channel. Moreover, for a memory access request of the second data length (for example, 64 bytes), the read data of the first data length (for example, 32 bytes) before and after the memory access request differ by only one clock cycle, so the depth of the read data cache is set to support a read command, which can reduce the depth of the read data cache.

[0257] The present disclosure also provides a chip, such as a system-on-chip chip, as shown in FIG1 , which may include: at least one processor core, at least one memory controller, a memory physical layer, and a memory;

[0258] In which, at least one processor core is connected to at least one memory controller; the memory physical layer includes at least one memory channel, and the memory channel includes a zeroth virtual channel and a first virtual channel; data is transmitted between the memory controller and the memory through the memory channel; the memory controller in the chip can be a memory controller provided in an embodiment of the present disclosure.

[0259] An embodiment of the present disclosure further provides an electronic device, such as a terminal device or a server device, which may include the chip provided by an embodiment of the present disclosure, or the memory controller provided by an embodiment of the present disclosure.

[0260] The above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed by the embodiments of the present disclosure.

[0261] Although the embodiments of the present disclosure are disclosed above, the present disclosure is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be based on the scope defined by the claims.

Claims

1. A memory controller comprising: The memory controller transmits data to the memory via a memory channel, wherein the memory channel includes a zeroth virtual channel and a first virtual channel; The memory controller includes: a shared control logic circuit, a final arbitrator and a command replicator; The shared control logic circuit is shared by the zeroth virtual channel and the first virtual channel, and the shared control logic circuit is configured to determine a request command corresponding to a memory access request and send the request command to a final arbiter; The command replicator is configured to, when the command output by the final arbitrator is a non-replicated request command and the request command meets a preset replication condition, replicate the request command to obtain a corresponding replicated request command; and send the replicated request command to the final arbitrator; and The final arbitrator is configured to perform final arbitration on the command sent to the final arbitrator; if the command passed by the final arbitration is a non-duplicate request command, output the request command and instruct it to be transmitted through the zeroth virtual channel; and at least one clock cycle after outputting the non-duplicate request command, if the command passed by the final arbitration corresponds to a duplicate request command, output the duplicate request command and instruct it to be transmitted through the first virtual channel; The non-copied request command comes from the shared control logic circuit, and the copied request command comes from the command copier.

2. The memory controller according to claim 1, wherein: The memory includes a plurality of blocks, wherein the blocks are arrays formed of rows and columns; The request commands corresponding to the memory access request are divided into row commands and column commands; The row command is used to control at least the block where the row pointed to by the memory access request is located, and the column command is used to perform a memory access operation on the column in the row pointed to by the memory access request.

3. The memory controller according to claim 2, wherein: The command replicator is configured to replicate the request command when the command output by the final arbitrator is a non-replicated request command and the request command meets a preset replication condition, so as to obtain a corresponding replicated request command, including: When the command output by the final arbitrator is a non-copy request command and a column command other than a memory access request marked as real and originating from the first data length, the request command is copied to obtain a corresponding copied request command; the first data length is the data length supported by a virtual channel for transmitting data. Spend.

4. The memory controller according to claim 3, wherein: The final arbiter is further configured to mark the outputted column command as false when the outputted request command is a column command and satisfies a condition; The conditions include: the column command output by the final arbiter is a non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the first virtual channel; when the output request command is a column command and does not meet the conditions, marking the output column command as true; The column command marked as true is sent to the memory after being output by the final arbitrator, and the column command marked as false is discarded after being output by the final arbitrator.

5. The memory controller according to claim 3, wherein: The final arbiter includes a column command arbiter and a row command arbiter; The column command arbiter is configured to perform final arbitration on the column commands sent to the final arbiter; if the column command that passes the final arbitration is a non-duplicate column command, the column command is output and instructed to be transmitted through the zeroth virtual channel; and if a corresponding duplicate column command exists for the output non-duplicate column command, at least one clock cycle after the output of the non-duplicate column command, the corresponding duplicate column command that passes the final arbitration is output, the duplicate column command is output and instructed to be transmitted through the first virtual channel; The row command arbiter is configured to perform final arbitration on the row command sent to the final arbiter; if the row command that passes the final arbitration is a non-duplicate row command, output the row command and instruct it to be transmitted through the zeroth virtual channel; and, at least one clock cycle after outputting the non-duplicate row command, output the corresponding duplicate row command and instruct it to be transmitted through the first virtual channel.

6. The memory controller according to claim 5, wherein: The command copier is configured to, when the command output by the final arbitrator is a non-copied request command and a column command other than a memory access request marked as real and originating from the first data length, copy the request command to obtain a corresponding copied request command, including: When the column command arbiter outputs a non-duplicate column command and the column command is other than a column command marked as true and originating from a memory access request of the first data length, the column command is copied to obtain a corresponding copied column command.

7. The memory controller according to claim 6, wherein: The column command arbiter is configured to output the column command and instruct transmission through the zeroth virtual channel if the column command finally passed the arbitration is a non-duplicate column command, including: If the column command finally passed by arbitration is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the zeroth virtual channel, then in the current cycle clock, the virtual channel address output belongs to the zeroth virtual channel and is marked as the real column command; The final arbiter is occupied by the command duplicator in the next clock cycle, but does not output a column command.

8. The memory controller according to claim 6, wherein: The column command arbiter is configured to output the column command and instruct transmission through the zeroth virtual channel if the column command finally passed the arbitration is a non-duplicate column command, including: If the column command finally passed by arbitration is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the first virtual channel, then in the current cycle clock, a column command is output whose virtual channel address belongs to the zeroth virtual channel and is marked as false; The column command arbiter is configured to, if a corresponding copied column command exists for an output non-copied column command, finally arbitrate the corresponding copied column command at least one clock cycle after the non-copied column command is output, and output the copied column command and instruct transmission through the first virtual channel, including: If the output column command is a non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request is the first virtual channel, then in the next clock cycle, the corresponding duplicate column command is finally arbitrated and a duplicate column command is output, indicating that the virtual channel address belongs to the first virtual channel and is marked as authentic.

9. The memory controller according to claim 6, wherein: The column command arbiter is configured to output the column command and instruct transmission through the zeroth virtual channel if the column command finally passed the arbitration is a non-duplicate column command, including: If the column command finally passed by arbitration is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the second data length, then in the current cycle clock, the virtual channel address output belongs to the zeroth virtual channel and is marked as a real column command, wherein the second data length is the total data length of data supported for transmission by the zeroth virtual channel and the first virtual channel included in the memory channel; The column command arbiter is configured to, if a corresponding copied column command exists for an output non-copied column command, finally arbitrate the corresponding copied column command at least one clock cycle after the non-copied column command is output, and output the copied column command and instruct transmission through the first virtual channel, including: If the output column command is a non-duplicate column command, and the data length of the memory access request corresponding to the column command is the second data length, then in the next clock cycle, the corresponding duplicate column command is arbitrated and a duplicate column command is output, in which the virtual channel address belongs to the first virtual channel and is marked as real.

10. The memory controller according to claim 5, wherein: If the column command output by the column command arbiter is derived from a memory access request of a first data length, the column command does not carry an automatic precharge instruction; if it is derived from a memory access request of a second data length, the column command may or may not carry an automatic precharge instruction.

11. The memory controller according to claim 5, wherein: The command copier is configured to, when the command output by the final arbitrator is a non-copied request command and a column command other than a memory access request marked as real and originating from the first data length, copy the request command to obtain a corresponding copied request command, including: When the row command arbiter outputs a non-replicated row command, the row command is replicated to obtain a corresponding replicated row command; The row command arbiter is configured to output the corresponding duplicated row command and instruct transmission through the first virtual channel at least one clock cycle after outputting the non-duplicated row command, including: According to the clock cycle of the command bus occupied by the output non-duplicate row command, at least one clock cycle after the output of the non-duplicate row command, a row command participating in the final arbitration is selected, and the duplicated row command is output and instructed to be transmitted through the first virtual channel.

12. The memory controller according to claim 11, wherein: The row command arbiter is configured to select a row command to participate in the final arbitration according to the clock cycle of the command bus occupied by the output non-duplicate row command, at least one clock cycle after the non-duplicate row command is output, including: If the output non-duplicate row command occupies 1.5 clock cycles of the command bus, then in the first clock cycle after the current clock cycle of the output non-duplicate row command, a row command that does not conflict with the output row command and occupies 0.5 clock cycles of the command bus is selected to participate in the final arbitration; and in the second clock cycle to the third clock cycle after the current clock cycle, the non-duplicate row command is prohibited from participating in the final arbitration; The row command arbiter is configured to output the copied row command and instruct transmission through the first virtual channel, comprising: From the second clock cycle to the third clock cycle, according to the time sequence of inputting the copied row commands from the current clock cycle to the first clock cycle, the copied row commands are output in sequence and the virtual channel address is indicated to belong to the first virtual channel; Among them, the selected row command that occupies 0.5 clock cycles of the command bus is output by the row command arbiter 0.5 clock cycles after the first clock cycle, the output row command is copied by the command copier, and the corresponding copied row command is output by the row command arbiter 0.5 clock cycles after the third clock cycle.

13. The memory controller according to claim 11, wherein: The row command arbiter is configured to select a row command to participate in the final arbitration according to the clock cycle of the command bus occupied by the output non-duplicate row command, at least one clock cycle after the non-duplicate row command is output, including: If the output non-duplicate row command occupies 1 clock cycle of the command bus, then in the first clock cycle after the current clock cycle in which the non-duplicate row command is output, the non-duplicate row command is prohibited from participating in the final arbitration; The row command arbiter is configured to output the copied row command and instruct transmission through the first virtual channel, comprising: In a first clock cycle after the current clock cycle, a row command corresponding to the copy is output and indicates that the virtual channel address belongs to the first virtual channel.

14. The memory controller according to claim 11, wherein: The row command arbiter is configured to select a row command to participate in the final arbitration according to the clock cycle of the command bus occupied by the output non-duplicate row command, at least one clock cycle after the non-duplicate row command is output, including: If the output non-duplicate row command occupies 0.5 clock cycles of the command bus, then in the 0.5 clock cycle after the current clock cycle of the output row command, a row command that does not conflict with the output row command and occupies 0.5 clock cycles of the command bus is selected to participate in the final arbitration; and in the first clock cycle after the current clock cycle, the non-duplicate row command is prohibited from participating in the arbitration; The row command arbiter is configured to output the copied row command and instruct transmission through the first virtual channel, comprising: In a first clock cycle after the current clock cycle, according to the time sequence of inputting the copied row commands in the current clock cycle, the copied row commands are output in sequence and the virtual channel address is indicated to belong to the first virtual channel; Among them, the selected row command that occupies 0.5 clock cycles of the command bus is output by the row command arbiter in the first clock cycle, the output row command is copied by the command copier, and the corresponding copied row command is output by the row command arbiter 0.5 clock cycles after the first clock cycle.

15. The memory controller according to any one of claims 1 to 14, wherein: The shared control logic circuit is further configured to, when the final arbitrator outputs a non-duplicate command, sample the command output by the final arbitrator, and start timing parameter counting for the sampled command based on the counting basis of the timing parameters; Among them, the counting basis of the timing parameters is: for commands that occupy 1.5 clock cycles of the command bus, the timing parameters are counted with the first clock rising edge of the command output by the final arbitrator as the starting position, so that the timing parameters of the commands that occupy 1.5 clock cycles of the command bus are counted one clock cycle earlier than the standard clock cycle.

16. The memory controller according to claim 15, wherein: The shared control logic circuit is configured to count the sampled command start timing parameters based on the counting basis of the timing parameters, including: Based on the counting basis of the timing parameters, the timing parameters of the currently sampled command are counted according to the change of the clock cycle of the command bus occupied by the sampled adjacent commands.

17. The memory controller according to claim 16, wherein: The shared control logic circuit is configured to count the timing parameters of the currently sampled command based on the counting basis of the timing parameters and according to the change of the clock cycle of the command bus occupied by the sampled adjacent commands, including: Determine the clock cycle change of the command bus occupied by the sampled adjacent commands; If the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 1 clock cycle to 1 clock cycle, 0.5 clock cycle to 0.5 clock cycle, 1.5 clock cycles to 1.5 clock cycles, 1 clock cycle to 0.5 clock cycle, and 0.5 clock cycle to 1 clock cycle, then based on the counting basis of the timing parameters, the timing parameters of the currently sampled command are counted according to the standard clock cycle; If the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 1.5 clock cycles to 0.5 clock cycles and 1.5 clock cycles to 1 clock cycle, then based on the counting basis of the timing parameters, the currently sampled command is counted according to the standard clock cycle plus 2 clock cycles; If the clock cycle of the command bus occupied by the sampled adjacent command changes to any one of 0.5 clock cycles to 1.5 clock cycles and 1 clock cycle to 1.5 clock cycles, then based on the counting basis of the timing parameters, the currently sampled command is counted according to the standard clock cycle minus 1 clock cycle.

18. The memory controller according to claim 15, wherein: The shared control logic circuit includes: a shared command queue shared by the zeroth virtual channel and the first virtual channel, a shared page recording module, a shared timing check module, a shared refresh control module and a shared queue arbiter; The shared command queue is configured to store request information of memory access requests; The shared page recording module is configured to record block information of blocks in the memory; The shared timing check module is configured to execute the step of sampling the command output by the final arbitrator when the final arbitrator outputs the non-duplicate command, and starting timing parameter counting for the sampled command based on the counting basis of the timing parameters; The shared refresh control module is configured to manage the refresh operation of the memory; The shared queue arbiter is configured to determine a request command corresponding to a memory access request and sent to a final arbiter based on information provided by at least one of the shared page recording module, the shared timing check module, and the shared refresh control module, and request information of the memory access request stored in the shared command queue.

19. The memory controller according to claim 18, wherein: The request information of the memory access request includes: a virtual channel address of the memory access request; the virtual channel address of the memory access request is used to indicate whether the column command is marked as true or false when the final arbitrator outputs the column command.

20. The memory controller according to claim 18, wherein: The memory controller further includes: a dispatch and response queue configured to send the command output by the final arbitrator to the memory according to the virtual channel indicated by the command output by the final arbitrator; Among them, if the command output by the final arbitrator is a column command marked as false, the departure and response queue discards the column command marked as false; if the command output by the final arbitrator is a column command marked as true, the departure and response queue sends the column command marked as true to the memory.

21. The memory controller according to claim 20, wherein: The departure and response queues are further configured to receive read data returned from the memory, the read data corresponding to the column command of the read operation output by the final arbitrator; If the data length of the memory access request corresponding to the column command of the read operation is the second data length, after caching the read data corresponding to the column command of the read operation, the read data corresponding to the column command of the next read operation and the cached read data are returned to the processor core, where the column command of the read operation corresponds to reading read data of the first data length; wherein the first data length is the data length of data supported for transmission by a virtual channel, and the second data length is the data length of data supported for transmission by a memory channel; If the data length of the memory access request corresponding to the column command of the read operation is the first data length, the read data is directly returned to the processor core; The dispatch and response queues are provided with a read data cache for caching read data, the depth of the read data cache at least supports a column command of a read operation, and the width at least corresponds to the first data length.

22. The memory controller according to any one of claims 1 to 14, or any one of claims 16 to 21, wherein: The zeroth virtual channel and the first virtual channel included in the memory channel have independent data buses and share a command bus.

23. A memory access method, applied to the memory controller according to any one of claims 1 to 22, wherein: The memory controller transmits data to the memory via a memory channel, wherein the memory channel includes a zeroth virtual channel and a first virtual channel; the method includes: determining a request command corresponding to the memory access request, wherein the request command corresponding to the memory access request participates in final arbitration; and when the command output by the final arbitration is a non-duplicate request command and the request command meets the preset replication condition, replicating the request command to obtain a corresponding replicated request command, wherein the replicated request command participates in the final arbitration; Perform final arbitration on the commands participating in the final arbitration; if the command that passes the final arbitration is a non-duplicate request command, output the request command and indicate transmission through the zeroth virtual channel; and, at least one clock cycle after the non-duplicate request command is output, the corresponding duplicate request command passes the final arbitration, output the duplicate request command and indicate transmission through the first virtual channel.

24. The method according to claim 23, wherein When the command output by the final arbitration is a non-copy request command and the request command meets the preset copy condition, copying the request command includes: When the command output by the final arbitration is a non-copied request command and a column command other than a memory access request marked as real and originating from a first data length, the request command is copied to obtain a corresponding copied request command; the first data length is the data length supported by a virtual channel for transmitting data.

25. The method according to claim 24, further comprising: When the request command output by the final arbitration is a column command and meets the conditions, the column command output by the final arbitration is marked as false; The conditions include: the column command output by the final arbiter is a non-duplicate column command, the data length of the memory access request corresponding to the column command is the first data length, and the virtual channel indicated by the memory access request corresponding to the column command is the first virtual channel; When the request command output by the final arbitration is a column command and does not meet the conditions, marking the column command output by the final arbitration as true; The column command marked as true is sent to the memory after being output by the final arbitrator, and the column command marked as false is discarded after being output by the final arbitrator.

26. The method of claim 24, further comprising: When the command output by the final arbitration is a non-copy command, sampling the command output by the final arbitration, and starting timing parameter counting for the sampled command based on the counting basis of the timing parameters; Among them, the counting basis of the timing parameters is: for commands that occupy 1.5 clock cycles of the command bus, the timing parameters are counted with the first clock rising edge at which the command is finally arbitrated and output as the starting position, so that the timing parameters of commands that occupy 1.5 clock cycles of the command bus are counted one clock cycle earlier than the standard clock cycle.

27. A chip, comprising: at least one processor core, at least one memory controller, a memory physical layer, and memory; The at least one processor core is connected to the at least one memory controller; the memory physical layer includes at least one memory channel, and the memory channel includes a zeroth virtual channel and a first virtual channel; data is transmitted between the memory controller and the memory via the memory channel; Wherein, the memory controller is the memory controller according to any one of claims 1-22.

28. An electronic device comprising the chip according to claim 27, or the memory controller according to any one of claims 1 to 22.

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