Annular-channel thin-film transistor and preparation method therefor

Abstract

The present application belongs to the technical field of semiconductors, and relates to an annular-channel thin-film transistor and a preparation method therefor, which solve the problem of unsatisfactory uniformity among existing transistor devices. The preparation method for the annular-channel thin-film transistor comprises the following steps: forming a patterned gate electrode on a substrate, wherein a pattern of the gate electrode comprises a circular ring and a square adjacent to a partial arc of the circular ring; sequentially growing a first gate dielectric, a second gate dielectric and an active layer material on the gate electrode and the substrate; performing patterning processing on the active layer material to obtain an active layer, a pattern of which is a circular ring; etching the first gate dielectric and the second gate dielectric above the square gate electrode to expose a partial region of the square gate electrode; growing a source-drain electrode material on the active layer and the second gate dielectric and performing patterning processing on the source-drain electrode material to form an annular channel between source and drain electrodes; and growing an encapsulation material on the source and drain electrodes and etching the encapsulation material to expose the gate electrode and the source and drain electrodes.

Description

A ring-shaped channel thin film transistor and a method for manufacturing the same Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a ring-channel thin film transistor and a method for preparing the same. Background Art

[0002] A thin film transistor (TFT) is a special type of field-effect transistor that is made by simply depositing an active semiconductor film, a dielectric layer, and a gate electrode layer on a flexible material called a substrate.

[0003] Currently, electronic applications are still primarily based on silicon-based manufacturing, but the demand for higher performance, new applications, and flexible integration has led to research into novel materials, including oxide channel materials. As electronic applications continue to evolve, the demand for device-to-device uniformity is becoming increasingly stringent. This inter-device uniformity is crucial for large-scale manufacturing. Therefore, how to fabricate devices with excellent inter-device uniformity is a pressing technical challenge.

[0004] Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present application aim to provide a ring-shaped channel thin film transistor and a method for manufacturing the same, so as to solve the problem of unsatisfactory uniformity between existing transistor devices.

[0006] On the one hand, an embodiment of the present application provides a method for preparing a ring-shaped channel thin film transistor, comprising the following steps:

[0007] forming a patterned gate electrode on a substrate, wherein the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring;

[0008] sequentially growing a first gate dielectric, a second gate dielectric, and an active layer material on the gate electrode and the substrate;

[0009] Performing patterning on the active layer material to obtain an active layer, wherein the pattern of the active layer is a circular ring;

[0010] Etching the first gate dielectric and the second gate dielectric above the square gate electrode to expose a portion of the square gate electrode;

[0011] Growing source and drain electrode materials on the active layer and the second gate dielectric and patterning the source and drain electrode materials to form an annular channel between the source and drain electrodes; and

[0012] A packaging material is grown on the source and drain electrodes and the packaging material is etched to expose the gate electrode and the source and drain electrodes.

[0013] Based on a further improvement of the above method, the second gate dielectric and the active layer material are grown in the same cavity and in the same pot using a magnetron sputtering process.

[0014] Based on a further improvement of the above method, the dielectric constant of the first gate dielectric is higher than the dielectric constant of the second gate dielectric.

[0015] Based on a further improvement of the above method, the active layer material is indium gallium zinc oxide.

[0016] Based on a further improvement of the above method, the first gate dielectric is aluminum oxide, and the second gate dielectric is silicon oxide.

[0017] Based on a further improvement of the above method, the thickness of the second gate dielectric is less than 10 nanometers.

[0018] Based on a further improvement of the above method, the packaging material is aluminum oxide and the thickness of the packaging material is 30 nanometers to 5 micrometers.

[0019] Based on a further improvement of the above method, the material of the gate electrode is a combination of one or more of the following:

[0020] Titanium nitride, gold, titanium, molybdenum, silver.

[0021] Based on a further improvement of the above method, the source-drain electrode material is a combination of one or more of the following:

[0022] Gold, titanium, silver.

[0023] On the other hand, an embodiment of the present application provides a ring-shaped channel thin film transistor, comprising:

[0024] substrate;

[0025] a patterned gate electrode, wherein the patterned gate electrode is formed on the substrate, and the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring;

[0026] a first gate dielectric layer and a second gate dielectric layer sequentially stacked on the patterned gate electrode and the substrate, wherein the first gate dielectric layer and the second gate dielectric layer have a first through hole at the position of the square gate electrode, and the first through hole exposes a partial area of ​​the square gate electrode;

[0027] a patterned active layer, wherein the patterned active layer is formed on the second gate dielectric layer, and the pattern of the active layer is a circular ring;

[0028] patterned source-drain electrodes, wherein the patterned source-drain electrodes are formed on the active layer and the second gate dielectric layer, and the pattern of the source-drain electrodes includes an annular through hole formed on the active layer;

[0029] An encapsulation layer is stacked on the patterned source and drain electrodes, and the encapsulation layer has a second through hole, a third through hole, and a fourth through hole. The second through hole and the third through hole expose the source and drain electrodes, and the fourth through hole overlaps with the first through hole.

[0030] Compared with the prior art, this application can achieve at least one of the following beneficial effects:

[0031] 1. The annular thin film transistor device provided in this application exhibits good uniformity in terms of performance, size, etc.

[0032] 2. This application uses a first gate dielectric layer with a higher dielectric constant, which changes the capacitance of the first gate dielectric layer, speeding up the turn-on and turn-off speeds of the thin-film transistor and reducing its power consumption. This also enhances the gate's control over the active layer, lowering the device's threshold voltage and reducing the short-channel effect.

[0033] 3. This application adopts the method of growing the second gate dielectric layer and the active layer material in the same cavity and the same pot, which reduces the interface defects between the grown active layer material and the second gate dielectric layer, effectively controls the threshold voltage drift phenomenon between different devices, and enhances the device uniformity.

[0034] 4. This application uses aluminum oxide as the encapsulation layer, which can isolate the active layer from external factors (such as water, oxygen, etc.) and improve the working life of the thin film transistor.

[0035] In this application, the above-mentioned technical solutions can be combined with each other to achieve more preferred combination solutions. Other features and advantages of this application will be described in the subsequent description, and some advantages will become apparent from the description or be understood by practicing this application. The objectives and other advantages of this application can be achieved and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present application. Throughout the drawings, the same reference symbols denote the same components.

[0037] FIG1 is a schematic flow chart of a method for manufacturing a ring-shaped channel thin film transistor according to an embodiment of the present application.

[0038] FIG. 2 is a conceptual diagram showing a patterned gate electrode formed according to step 101 .

[0039] FIG. 3 shows a conceptual diagram of the structure formed according to step 102 .

[0040] FIG. 4 is a conceptual diagram showing the active layer formed according to step 103 .

[0041] FIG. 5 shows a conceptual diagram of the structure formed according to step 104 .

[0042] FIG. 6 shows a conceptual diagram of the structure formed according to step 105 .

[0043] FIG. 7 shows a conceptual diagram of the structure formed according to step 106 .

[0044] FIG8 shows a comparison of transfer curves of thin film transistors with and without the second gate dielectric.

[0045] FIG9 shows a comparison of transfer curves of parallel and annular channel thin film transistors.

[0046] FIG10 shows the gate leakage current of the annular channel thin film transistor with different channel widths.

[0047] FIG. 11 shows a comparison of threshold voltage changes of flat and annular channel thin film transistors. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present application are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present application and are used together with the embodiments of the present application to illustrate the principles of the present application, and are not used to limit the scope of the present application.

[0049] FIG1 is a schematic flow chart of a method for manufacturing a ring-shaped channel thin film transistor according to an embodiment of the present application.

[0050] An embodiment of the present application is described below with reference to FIG1 .

[0051] As shown in FIG1 , the method for preparing the annular channel thin film transistor includes the following steps:

[0052] Step 101: forming a patterned gate electrode on a substrate, wherein the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring.

[0053] FIG. 2 is a conceptual diagram showing a patterned gate electrode formed according to step 101 .

[0054] Step 101 is described below with reference to FIG. 2 .

[0055] As shown in Figure 2, in step 101, a gate electrode material can be grown on a substrate 1, and the gate electrode material can be patterned using photolithography and dry etching processes to obtain a gate 2. The cross-sectional view in Figure 2 is a view obtained by cutting along the cross section AA' in the top view. In step 101, a magnetron sputtering method can be used to grow a gate electrode material on a substrate 1, and the gate electrode material can be patterned using photolithography and dry etching processes to form a gate electrode 2. The substrate 1 can include, but is not limited to, a hard and flexible substrate of materials such as SiO2, glass, and polyimide (PI), and the thickness can be 0.1mm-5mm. The gate electrode 2 can be one or a combination of titanium nitride, gold, titanium, molybdenum, and silver, and the thickness can be 30nm-300nm.

[0056] As can be seen from Figure 2, the gate 2 comprises two parts, one of which is a circular ring and the other is a square that is adjacent to a portion of the circular arc. Adjacent may mean that the edge of the square closest to the circular ring is tangent to the circular arc.

[0057] It should be noted that the schematic diagram in Figure 2 is for illustrative purposes only. The dimensions and proportional relationships in the figure are not drawn according to the actual dimensions of the device, and the dimensions and proportional relationships in the figure do not constitute a limitation on the scope of protection of the embodiments of the present application.

[0058] Step 102: sequentially growing a first gate dielectric, a second gate dielectric, and an active layer material on the gate electrode and the substrate.

[0059] FIG. 3 shows a conceptual diagram of the structure formed according to step 102 .

[0060] Step 102 is described below with reference to FIG. 3 .

[0061] As shown in FIG3 , in step 103, the first gate dielectric 3 may be grown on the gate electrode 2 and the substrate 1 by atomic layer deposition, wherein the growth temperature of the atomic layer deposition may be 100° C. to 300° C. The material of the first gate dielectric 3 may be a material having a higher dielectric constant than silicon oxide, and may optionally include but is not limited to aluminum oxide (AlO x The thickness of the first gate dielectric 3 may be 10 nm to 70 nm.

[0062] Continuing with FIG3 , in step 103, an atomic layer deposition method or a magnetron sputtering process can be used to sequentially grow a second gate dielectric 4 and an active layer material 5 on the first gate dielectric 3. The thickness of the second gate dielectric layer 4 can be less than 10 nanometers, and preferably, the thickness of the second gate dielectric 4 is 5 nanometers. The thickness of the active layer material 5 can be less than 10 nanometers, and preferably, the thickness of the active layer material 5 is 7 nanometers.

[0063] In some examples, the active layer material may be indium gallium zinc oxide. Indium gallium zinc oxide has good field effect mobility (>10cm 2 / V·s), a higher current switching ratio, lower off-state leakage current, and a lower manufacturing process temperature (<450°C). Using indium gallium zinc oxide as the active layer material improves device performance.

[0064] In some examples, the second gate dielectric 4 and the active layer material 5 are grown in the same chamber using a magnetron sputtering process. In this example, the second gate dielectric 4 and the active layer material 5 can be grown in the same chamber using magnetron sputtering on the first gate dielectric 3. By selecting the method of growing the second gate dielectric 4 and the active layer material 5 in the same chamber, the interface defects between the grown active layer material 5 and the second gate dielectric 4 are reduced, the threshold voltage drift between different devices is effectively controlled, and the device uniformity is enhanced.

[0065] Step 103: patterning the active layer material to obtain an active layer, wherein the pattern of the active layer is a circular ring.

[0066] FIG. 4 is a conceptual diagram showing the active layer formed according to step 103 .

[0067] Step 103 is described below with reference to FIG. 4 .

[0068] As shown in Figure 4, in step 103, the active layer material 5 in Figure 3 may be patterned by photolithography and wet etching to obtain the active layer 5 in Figure 4. The wet etching agent may be a dilute nitric acid solution.

[0069] 4 is a cross-sectional view taken along the cross section AA′ in the top view. As can be seen from FIG4 , the active layer 5 is annular and is located in the center above the annular bottom gate 2 .

[0070] It should be noted that the schematic diagram in Figure 4 is for illustrative purposes only. The dimensions and proportional relationships in the figure are not drawn according to the actual dimensions of the device, and the dimensions and proportional relationships in the figure do not constitute a limitation on the scope of protection of the embodiments of the present application.

[0071] Step 104 : Etching the first gate dielectric and the second gate dielectric above the square gate electrode to expose at least a portion of the square gate electrode.

[0072] FIG. 5 shows a conceptual diagram of the structure formed according to step 104 .

[0073] Step 104 will be described below with reference to FIG. 5 .

[0074] As shown in FIG5 , in step 104, the first gate dielectric 3 and the second gate dielectric 4 can be simultaneously photolithographically etched and sequentially wet-etched to form a through hole 8 in the first gate dielectric 3 and the second gate dielectric 4. The through hole 8 is located above the square region of the gate electrode 2 to expose a portion of the square gate electrode, forming the structure shown in FIG5 . The cross-sectional view in FIG5 is obtained by cutting along the cross section AA' in the top view. Exposing the through hole 8 of the gate electrode facilitates subsequent testing.

[0075] It should be noted that the schematic diagram in Figure 5 is for illustrative purposes only. The dimensions and proportional relationships in the figure are not drawn according to the actual dimensions of the device, and the dimensions and proportional relationships in the figure do not constitute a limitation on the scope of protection of the embodiments of the present application.

[0076] Step 105: growing source and drain electrode materials on the active layer and the second gate dielectric and patterning the source and drain electrode materials to form an annular channel between the source and drain electrodes.

[0077] FIG. 6 shows a conceptual diagram of the structure formed according to step 105 .

[0078] Step 105 will be described below with reference to FIG. 6 .

[0079] As shown in Figure 6, in step 105, the source and drain electrode materials can be grown on the active layer 5 and the second gate dielectric 4 by electron beam evaporation, and the source and drain electrode materials can be patterned by photolithography and stripping processes to form source and drain electrodes 6. The width of the channel region formed between the source and drain electrodes 6 can be 10nm-500μm. The source and drain electrode materials can be one or a combination of gold, titanium, and silver, and the thickness can be 30nm-80nm. The cross-sectional view in Figure 6 is a view obtained by cutting along the cross section AA' in the top view. As can be seen from Figure 6, an annular channel is formed between the source and drain electrodes, and the annular channel is located in the upper central area of ​​the annular active layer 5.

[0080] It should be noted that the schematic diagram in Figure 6 is for illustrative purposes only. The dimensions and proportions in the diagram are not drawn according to the actual dimensions of the device, and the dimensions and proportions in the diagram do not constitute a limitation on the scope of protection of the embodiments of this application. Step 106: Grow an encapsulation material on the source and drain electrodes and etch the encapsulation material to expose the gate electrode and the source and drain electrodes.

[0081] FIG. 7 shows a conceptual diagram of the structure formed according to step 106 .

[0082] Step 106 will be described below with reference to FIG. 7 .

[0083] As shown in Figure 7, in step 106, the packaging material 7 can be deposited on the source and drain electrodes 6 by atomic layer deposition, and then the packaging material 7 is etched by photolithography and etching processes to form three through holes 8, 9, and 10 in the packaging material 7, wherein the through holes 9, 10, and 8 respectively expose the source electrode, the drain electrode, and the gate electrode. Among them, the through hole 8 exposes a portion of the square gate electrode 2, the through hole 9 exposes the source and drain electrode material located on the outside of the circular bottom gate 2, and the through hole 10 exposes the source and drain electrode material located on the inside of the circular bottom gate 2. Preferably, the through hole 10 is an inner circle concentric with the circular bottom gate 2. The material of the packaging material 7 can be aluminum oxide, and the thickness can be 30nm-5μm.

[0084] It should be noted that the schematic diagram in Figure 7 is for illustrative purposes only. The dimensions and proportional relationships in the figure are not drawn according to the actual dimensions of the device, and the dimensions and proportional relationships in the figure do not constitute a limitation on the scope of protection of the embodiments of the present application.

[0085] Figure 8 compares the transfer curves of thin-film transistors with and without a second gate dielectric. As shown in Figure 8, compared to thin-film transistors without and with a second gate dielectric layer, the threshold voltages of thin-film transistors without and with a second gate dielectric layer vary significantly, while the differences between devices with and without the second gate dielectric layer are smaller.

[0086] Figure 9 shows a comparison of transfer curves for parallel and annular channel thin film transistors. As shown in Figure 9, compared to parallel and annular channel thin film transistors with the same process and channel width, the annular channel device has better device uniformity under the same process.

[0087] FIG10 shows the gate leakage current of the annular channel thin film transistor with different channel widths.

[0088] FIG. 11 shows a comparison of threshold voltage changes of flat and annular channel thin film transistors.

[0089] As shown in FIG10 , the method for preparing the annular channel thin film transistor provided in the present application can obtain a lower gate leakage current and is more suitable for application in integrated circuits requiring high speed and low power consumption.

[0090] As shown in Figure 11, the letter "R" on the horizontal axis represents a flat-channel thin-film transistor, while the letters "L4," "L10," and "L20" on the horizontal axis represent three different channel widths of annular-channel thin-film transistors. The vertical axis represents the threshold voltage, and "σ / μ" in the figure represents the rate of change of the threshold voltage. As can be seen from Figure 11, compared with parallel and annular-channel thin-film transistors, the annular-channel thin-film transistor has a smaller threshold voltage variation and better device uniformity.

[0091] The present application also proposes a ring-shaped channel thin film transistor, comprising:

[0092] substrate;

[0093] a patterned gate electrode, wherein the patterned gate electrode is formed on the substrate, and the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring;

[0094] a first gate dielectric layer and a second gate dielectric layer sequentially stacked on the patterned gate electrode and the substrate, wherein the first gate dielectric layer and the second gate dielectric layer have a first through hole at the position of the square gate electrode, and the first through hole exposes a partial area of ​​the square gate electrode;

[0095] a patterned active layer, wherein the patterned active layer is formed on the second gate dielectric layer, and the pattern of the active layer is a circular ring;

[0096] patterned source-drain electrodes, wherein the patterned source-drain electrodes are formed on the active layer and the second gate dielectric layer, and the pattern of the source-drain electrodes includes an annular through hole formed on the active layer;

[0097] An encapsulation layer is stacked on the patterned source and drain electrodes, and the encapsulation layer has a second through hole, a third through hole, and a fourth through hole. The second through hole and the third through hole expose the source and drain electrodes, and the fourth through hole overlaps with the first through hole.

[0098] Figure 7 is a schematic structural diagram of a ring-shaped channel thin film transistor according to an embodiment of the present application. Since the formation method and function of each part in Figure 7 have been described above, they will not be repeated here.

[0099] Compared with the prior art, the embodiments of the present application can achieve at least one of the following beneficial effects:

[0100] 1. The annular thin film transistor device provided in this application exhibits good uniformity in terms of performance, size, etc.

[0101] 2. This application uses a first gate dielectric layer with a higher dielectric constant, which changes the capacitance of the first gate dielectric layer, speeding up the turn-on and turn-off speeds of the thin-film transistor and reducing its power consumption. This also enhances the gate's control over the active layer, lowering the device's threshold voltage and reducing the short-channel effect.

[0102] 3. This application adopts the method of growing the second gate dielectric layer and the active layer material in the same cavity and the same pot, which reduces the interface defects between the grown active layer material and the second gate dielectric layer, effectively controls the threshold voltage drift phenomenon between different devices, and enhances the device uniformity.

[0103] 4. This application uses aluminum oxide as the encapsulation layer, which can isolate the active layer from external factors (such as water, oxygen, etc.) and improve the working life of the thin film transistor.

[0104] The above is only a preferred specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in this application should be covered by the scope of protection of the present application.

Claims

1. A method for preparing a ring-shaped channel thin film transistor, characterized in that: The steps include: forming a patterned gate electrode on a substrate, wherein the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring; sequentially growing a first gate dielectric, a second gate dielectric, and an active layer material on the gate electrode and the substrate; Performing patterning on the active layer material to obtain an active layer, wherein the pattern of the active layer is a circular ring; Etching the first gate dielectric and the second gate dielectric above the square gate electrode to expose a portion of the square gate electrode; Growing source and drain electrode materials on the active layer and the second gate dielectric and patterning the source and drain electrode materials to form an annular channel between the source and drain electrodes; as well as A packaging material is grown on the source and drain electrodes and the packaging material is etched to expose the gate electrode and the source and drain electrodes.

2. The method for preparing a ring-shaped channel thin film transistor according to claim 1, wherein: The second gate dielectric and the active layer material are grown in the same cavity and in the same pot by using a magnetron sputtering process.

3. The method for preparing a ring-shaped channel thin film transistor according to claim 1 or 2, wherein: The dielectric constant of the first gate dielectric is higher than the dielectric constant of the second gate dielectric.

4. The method for preparing a ring-shaped channel thin film transistor according to claim 1 or 2, wherein: The active layer material is indium gallium zinc oxide.

5. The method for preparing a ring-shaped channel thin film transistor according to claim 3, wherein: The first gate dielectric is aluminum oxide, and the second gate dielectric is silicon oxide.

6. The method for preparing a ring-shaped channel thin film transistor according to claim 1, 2 or 3, wherein: The thickness of the second gate dielectric is less than 10 nanometers.

7. The method for preparing a ring-shaped channel thin film transistor according to claim 1 or 2, wherein: The packaging material is aluminum oxide and has a thickness of 30 nanometers to 5 micrometers.

8. The method for preparing a ring-shaped channel thin film transistor according to claim 1 or 2, characterized in that: The material of the gate electrode is one or more of the following: Titanium nitride, gold, titanium, molybdenum, silver.

9. The method for preparing a ring-shaped channel thin film transistor according to claim 1 or 2, characterized in that: The source-drain electrode material is a combination of one or more of the following: Gold, titanium, silver.

10. A ring-channel thin film transistor, characterized in that: include: substrate; a patterned gate electrode, wherein the patterned gate electrode is formed on the substrate, and the pattern of the gate electrode includes a circular ring and a square adjacent to a partial arc of the circular ring; a first gate dielectric layer and a second gate dielectric layer sequentially stacked on the patterned gate electrode and the substrate, wherein the first gate dielectric layer and the second gate dielectric layer have a first through hole at the position of the square gate electrode, and the first through hole exposes a partial area of the square gate electrode; a patterned active layer, wherein the patterned active layer is formed on the second gate dielectric layer, and the pattern of the active layer is a circular ring; patterned source-drain electrodes, wherein the patterned source-drain electrodes are formed on the active layer and the second gate dielectric layer, and the pattern of the source-drain electrodes includes an annular through hole formed on the active layer; An encapsulation layer is stacked on the patterned source and drain electrodes, and the encapsulation layer has a second through hole, a third through hole, and a fourth through hole. The second through hole and the third through hole expose the source and drain electrodes, and the fourth through hole overlaps with the first through hole.

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