Adaptive frequency modulation method and apparatus

Abstract

Embodiments of the present application disclose an adaptive frequency modulation method and apparatus, which are used for improving the frequency modulation accuracy of a processor. The method in the embodiments of the present application comprises: a computing device acquiring real-time monitoring data of a processor, the real-time monitoring data comprising one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events comprising one or more of the following: the number of times of instruction execution, a cache hit rate, and a branch prediction error rate; on the basis of the real-time monitoring data, computing a predicted performance change rate of the processor, the predicted change rate being determined on the basis of a current performance change rate of the processor, the current performance change rate being determined on the basis of the real-time monitoring data, and the predicted performance change rate being used for indicating the ratio of a reference performance value of the processor relative to an operating performance value; and, on the basis of a target performance loss rate and the predicted performance change rate, determining a target frequency of the processor, the target performance loss rate being used for indicating a predicted performance change rate tolerable by the processor.

Description

Adaptive frequency modulation method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 30, 2024, with application number 202410138157.4 and application name “A Method and Device for Adaptive Frequency Modulation”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of computers, and in particular to an adaptive frequency modulation method and device. Background Art

[0003] With the development of cloud computing technology, one of the major challenges facing computing devices is the cost of energy consumption, which is particularly evident in supercomputing systems. Many supercomputing clusters are constrained by total operating power, necessitating reduced power consumption and improved energy efficiency. The central processing unit (CPU) often accounts for more than half of the total power consumption of a computing device, making it a key consideration when it comes to energy conservation.

[0004] In current CPU energy-saving solutions, since most CPUs in computing devices support dynamic frequency adjustment, computing devices can effectively reduce processor power consumption by lowering the processor frequency. However, current computing devices often adjust frequency based on CPU utilization. For example, when CPU utilization increases, the computing device can increase the frequency, and when CPU utilization decreases, the computing device can decrease the frequency.

[0005] However, in the actual task processing process, the CPU utilization cannot fully reflect the actual performance of the processor, and the frequency adjustment of the computing device based on the CPU utilization will result in poor frequency adjustment accuracy of the computing device and high processor power consumption.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide an adaptive frequency modulation method, enabling a computing device to obtain events collected by a processor's performance monitoring unit (PMU) and perform frequency modulation based on the collected PMU events, thereby improving frequency modulation accuracy and reducing processor power consumption. Embodiments of the present application also provide an adaptive frequency modulation apparatus, computing device, chip, computer-readable storage medium, and computer program product corresponding to the adaptive frequency modulation method.

[0008] In a first aspect, embodiments of the present application provide an adaptive frequency modulation method. The method can be performed by a computing device, or by a component of the computing device, such as a processor, chip, or chip system of the computing device. It can also be implemented by a logic module or software that implements all or part of the computing device's functions. Taking a computing device as an example, the method provided in the first aspect includes: the computing device collects real-time monitoring data from the processor, where the real-time monitoring data includes one or more events monitored by the processor's performance monitoring unit (PMU), where the events include one or more of the following: number of instruction executions, cache hit rate, and branch prediction error rate. The computing device calculates a predicted performance change rate of the processor based on the real-time monitoring data. The predicted change rate is determined based on the processor's current performance change rate, which is determined based on the real-time monitoring data. The predicted performance change rate indicates the ratio of the processor's reference performance value to its operating performance value. The reference performance value is the performance value corresponding to the processor's maximum frequency, and the operating performance value is the processor's performance value corresponding to the current frequency. The computing device determines a target frequency for the processor based on a target performance loss rate and the predicted performance change rate. The target performance loss rate indicates the predicted performance change rate that the processor can tolerate.

[0009] In the embodiment of the present application, the computing device can calculate the current performance change rate of the processor based on one or more events monitored by the performance monitoring unit PMU of the processor, and calculate the predicted performance change rate of the processor based on the current performance change rate of the processor, and further determine the target frequency based on the target performance loss rate and the predicted performance change rate. Compared with the prior art of adjusting the frequency of the processor according to the utilization rate of the processor, the embodiment of the present application based on PMU events can more accurately reflect the performance of the processor, and frequency adjustment based on PMU events improves the accuracy of the target frequency and reduces the power consumption of the processor.

[0010] In one possible implementation, when a computing device calculates a predicted performance change rate of a processor based on real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, where the performance change fitting relationship indicates the correlation between the performance change rate and the monitoring data. The computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate, where the frequency change rate is the ratio of a reference frequency to an operating frequency, where the reference frequency is the maximum frequency of the processor and the operating frequency is the frequency at the previous moment.

[0011] In the embodiment of the present application, the computing device can calculate the current performance change rate corresponding to the real-time monitoring data based on the performance change fitting relationship, and further calculate the predicted performance change rate of the processor based on the current performance change rate and the frequency change rate, thereby improving the accuracy of the predicted performance change rate.

[0012] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. In the process of the computing device calculating the predicted performance change rate based on the current performance change rate and the frequency change rate, the computing device calculates the frequency change rate based on the reference frequency and the frequency at the previous moment. Thereafter, the computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0013] In the embodiment of the present application, the computing device can calculate the predicted performance change rate of the processor based on the ratio of the processor performance value at the previous moment to the processor performance value at the current moment, and the frequency change rate corresponding to the current moment, thereby improving the feasibility of the solution for calculating the predicted performance change rate of the processor.

[0014] In one possible implementation, a computing device acquires historical monitoring data, where the historical monitoring data includes one or more events monitored by a processor's performance monitoring unit (PMU) at different frequencies. Based on the historical monitoring data, the computing device fits a formula for the processor's performance change relationship, also referred to as a performance change formula. The performance change formula is used to indicate the correlation between the current performance change rate and the event. Specifically, the computing device fits the processor's performance change formula based on the historical monitoring data and the corresponding performance change rate.

[0015] The computing device of the embodiment of the present application can fit the processor change formula based on historical monitoring data, thereby establishing a correlation between the current performance change rate of the processor and the PMU event, thereby improving the accuracy of the computing device in calculating the current performance change rate of the processor.

[0016] In one possible implementation, before fitting a processor performance change formula based on historical monitoring data, the computing device determines PMU events associated with a current performance change rate. Specifically, the computing device identifies PMU events whose correlation with the current performance change rate exceeds a threshold as associated PMU events. The computing device then fits the processor performance change formula based on the associated PMU events and the processor's current performance change rate corresponding to the associated PMU events.

[0017] In the embodiment of the present application, the computing device can treat PMU events whose correlation with the current performance change rate of the processor exceeds a threshold as associated PMU events, thereby reducing the complexity of the computing device in fitting the processor performance change formula based on historical monitoring data and improving the fitting efficiency of the processor performance change formula.

[0018] In one possible implementation, a computing device establishes a correlation between a processor's performance loss rate and a frequency change rate based on historical monitoring data. This correlation includes a blocking coefficient, which indicates the weight by which frequency influences the processor's performance value. The computing device may calculate the blocking coefficient based on the performance loss rate corresponding to the current frequency and the predicted performance change rate. The blocking coefficient is also used to calculate a target frequency for the processor based on the target performance loss rate.

[0019] In the embodiment of the present application, the computing device can establish a correlation between the processor performance loss rate and the frequency based on historical monitoring data, so that the computing device can calculate the target frequency of the processor based on the target performance loss rate, thereby improving the feasibility of the computing device to calculate the target frequency.

[0020] In one possible implementation, when a computing device determines a target frequency of a processor based on a target performance loss rate and a performance change rate, the computing device calculates a blocking coefficient corresponding to real-time monitoring data based on the processor's predicted performance change rate and frequency change rate. The predicted performance change rate indicates the ratio of a performance value corresponding to a reference frequency to a performance value corresponding to a current frequency, and the frequency change rate indicates the ratio of the processor's reference frequency to its current frequency. The computing device determines a target frequency based on the target performance loss rate and the blocking coefficient. The target frequency is the frequency to be adjusted by the processor at the next moment.

[0021] In the embodiment of the present application, the computing device can calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and frequency change rate of the processor, and determine the target frequency based on the target performance loss rate and the blocking coefficient, thereby improving the calculation efficiency of the target frequency.

[0022] In one possible implementation, when the processor's predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, that is, the performance loss rate corresponding to the current frequency is greater than or equal to the target performance loss rate, the processor frequency is increased. When the processor's predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, that is, the performance loss rate corresponding to the current frequency is less than the target performance loss rate, the processor frequency is decreased.

[0023] In an embodiment of the present application, the computing device can adjust the frequency of the processor by adjusting the frequency calculation corresponding to the predicted performance change rate of the processor, and compare the predicted performance change rate with the predicted performance change rate corresponding to the target performance loss rate, thereby adjusting the frequency of the processor, thereby improving the accuracy of the target frequency.

[0024] In one possible implementation, the real-time monitoring data collected by the computing device may include events collected by the Architecture Performance Monitoring Unit (AMU) in addition to PMU events. The real-time monitoring data may also include CPU utilization or other scenario-related performance indicators, such as transactions per second in a database scenario.

[0025] In the embodiments of the present application, the computing device can collect different types of real-time monitoring data in different application scenarios, and determine the processor predicted performance change rate based on different real-time monitoring data, thereby improving the calculation accuracy of the processor predicted performance change rate.

[0026] In the second aspect, an embodiment of the present application provides an adaptive frequency modulation device, which includes an acquisition unit and a processing unit. The acquisition unit is used to collect real-time monitoring data of the processor, and the real-time monitoring data includes one or more events monitored by the performance monitoring unit PMU of the processor, and the events include one or more of the following: number of instruction executions, cache hit rate, and branch prediction error rate. The processing unit is used to calculate the predicted performance change rate of the processor based on the real-time monitoring data. The predictive change rate is determined based on the current performance change rate of the processor. The current performance change rate is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value. The processing unit is also used to determine the target frequency of the processor based on the target performance loss rate and the predicted performance change rate. The target performance loss rate is used to indicate the predicted performance change rate that the processor can tolerate.

[0027] In one possible implementation, the processing unit is specifically used to calculate the current performance change rate of the processor based on real-time monitoring data and a performance change fitting relationship. The performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate. The frequency change rate is the ratio of the reference frequency to the operating frequency.

[0028] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit is specifically used to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0029] In one possible implementation, the processing unit is specifically configured to calculate a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate, and determine a target frequency according to the target performance loss rate and the blocking coefficient.

[0030] In one possible implementation, the processing unit is further configured to increase the processor frequency when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, and decrease the processor frequency when the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate.

[0031] In one possible implementation, the processing unit is further configured to obtain historical monitoring data including one or more events monitored by a performance monitoring unit PMU of the processor at different frequencies, and obtain a performance change fitting relationship based on fitting of the historical monitoring data.

[0032] In one possible implementation, the processing unit is further configured to establish a correlation between the performance loss rate and the frequency change rate based on historical monitoring data, where the correlation includes a blocking coefficient, which is configured to indicate a weight by which the processor's performance value is affected by the frequency.

[0033] In a third aspect, an embodiment of the present application provides a computing device, comprising a processor coupled to a memory, the processor being used to store instructions. When the instructions are executed by the processor, the computing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0034] In a fourth aspect, an embodiment of the present application provides a chip, which includes one or more processing circuits, which are coupled to a storage circuit. The processing circuit is used to store instructions. When the instructions are executed by the processing circuit, the chip executes the method described in the first aspect or any possible implementation method of the first aspect.

[0035] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed, the computer executes the method described in the first aspect or any possible implementation method of the first aspect.

[0036] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes instructions. When the instructions are executed, the computer implements the method described in the first aspect or any possible implementation method of the first aspect.

[0037] It can be understood that the beneficial effects that can be achieved by any of the adaptive frequency modulation devices, computing devices, chips, computer-readable media or computer program products provided above can be referred to the beneficial effects in the corresponding methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic diagram of the system architecture of an adaptive frequency modulation system provided in an embodiment of the present application;

[0039] FIG2 is a schematic flow chart of an adaptive frequency modulation method provided in an embodiment of the present application;

[0040] FIG3 is a schematic flow chart of another adaptive frequency modulation method provided in an embodiment of the present application;

[0041] FIG4 is a schematic flow chart of another adaptive frequency modulation method provided in an embodiment of the present application;

[0042] FIG5 is a schematic flow chart of another adaptive frequency modulation method provided in an embodiment of the present application;

[0043] FIG6 is a schematic structural diagram of an adaptive frequency modulation device provided in an embodiment of the present application;

[0044] FIG7 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0045] FIG8 is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The embodiments of the present application provide an adaptive frequency modulation method and apparatus for improving the frequency modulation accuracy of a computing device and reducing processor power consumption.

[0047] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0049] First, some terms involved in the embodiments of the present application are introduced to facilitate those skilled in the art to understand the technical solutions.

[0050] The performance monitoring unit (PMU) counter is a hardware component on the central processing unit (CPU) that measures system performance and resource utilization. PMU counters can record various processor events, such as instruction execution counts, cache hit rates, and memory access counts.

[0051] In order to make the technical solution of the present application clearer and easier to understand, the system architecture of the present application is introduced below with reference to the accompanying drawings.

[0052] Please refer to Figure 1, which is a schematic diagram of the system architecture of an adaptive frequency modulation system provided in an embodiment of the present application. In the example shown in Figure 1, the adaptive frequency modulation system 10 includes a system file interface module 101, a processor frequency modulation module 102, and a processor hardware module 103. The processor frequency modulation module includes a frequency modulation management submodule 1021, a frequency modulation core submodule 1022, and a frequency modulation driver submodule 1023. The following describes in detail the specific functions of each module in the adaptive frequency modulation system 10.

[0053] The system file interface module 101 provides the user space with an interface for accessing the processor frequency modulation module 102, also known as the sysfs module. User applications can use the system file interface module 101 to obtain information about various devices, drivers, and submodules in the processor frequency modulation module 102 in the form of files, and configure or adjust the processor frequency modulation module 102. For example, a user application can use the system file interface module 101 to query or set the CPU frequency.

[0054] The processor frequency modulation module 102, also known as the CPUfreq module, is used to control the frequency of the central processing unit (CPU) in kernel space. It includes a frequency modulation management submodule 1021, a frequency modulation core submodule 1022, a frequency modulation driver submodule 1023, and a frequency modulation data statistics submodule 1024.

[0055] Among them, the frequency modulation management submodule 1021 is also called the CPUfreq governor submodule. The frequency modulation management submodule 1021 is used to select the frequency strategy of the processor according to the load situation of the central processing unit. Frequency strategies include performance priority (performance) strategy, power consumption priority (powersave) strategy, user-set frequency (userspace) strategy, on-demand allocation (ondemand) strategy, smooth adjustment (conservatie) strategy and load frequency modulation (schedutil) strategy.

[0056] Frequency modulation core submodule 1022, also known as the CPUfreq core submodule, is responsible for overall management and control of processor frequency modulation module 102, including CPUfreq framework initialization, callback registration, event management, and driver management. Frequency modulation core submodule 1022 provides a common control interface and algorithm to coordinate the interactions between the various submodules of processor frequency modulation module 102.

[0057] For example, the frequency modulation core submodule 1022 can receive user inquiries or configuration requests regarding the CPU frequency and frequency policy through the system file interface module 101. The frequency modulation core submodule 1022 can also manage and modify the frequency policy of the frequency modulation management submodule 1021 and control the frequency modulation driver submodule 1023 to adjust the frequency based on the frequency policy. The frequency modulation core submodule 1022 can also monitor the CPU load and power consumption requirements.

[0058] The frequency modulation driver submodule 1023, also known as the CPUfreq driver module, implements the frequency or voltage modulation mechanism of the central processing unit (CPU). This submodule interacts with the processor hardware module 103 and adjusts the CPU frequency based on the frequency policy selected by the frequency modulation management submodule 1021. This submodule also reads the current CPU frequency from the processor hardware module 103 and adjusts the CPU frequency to achieve the desired performance or power consumption targets.

[0059] For example, the frequency modulation driver submodule 1023 can integrate a driver that interacts with the processor hardware module 103 to read and set the main frequency of the central processing unit. The frequency modulation driver submodule 1023 can also read the system energy consumption operating performance points (OPP) to obtain frequency and voltage gear information.

[0060] The frequency modulation data statistics submodule 1024, also known as the CPUfreq stats submodule, is used to collect processor frequency statistics and provide real-time and historical processor frequency data. For example, the frequency modulation data statistics submodule 1024 can track the time the processor operates at different frequencies, record the number of frequency transitions, and calculate the percentage and duration of each frequency. The frequency modulation data statistics submodule 1024 can also record and save historical processor frequency data, retain the data after a system restart, and provide an interface for querying historical data.

[0061] The processor hardware module 103 includes hardware components that interact with the processor frequency modulation module 102. The processor hardware module 103 can receive frequency acquisition or frequency adjustment instructions from the frequency modulation driver submodule 1023. The processor hardware module 103 may include, for example, the processor's power management module, power-related registers, and a power control unit (PCU), though these are not specifically limited.

[0062] For another example, the processor hardware module 103 also includes a performance monitoring unit (PMU) counter. In the embodiment of the present application, the processor frequency modulation module 102 can interact with the PMU counter to obtain the performance data of the processor. By analyzing the data of the PMU counter, the processor frequency modulation module 102 can obtain data such as the processor load, cache hit rate, power consumption and performance indicators, and decide whether it is necessary to adjust the operating frequency of the processor accordingly.

[0063] Based on the adaptive frequency modulation system 10 shown in Figure 1, the present application further provides an adaptive frequency modulation method. The adaptive frequency modulation method provided in the embodiment of the present application is described below in conjunction with an embodiment.

[0064] Please refer to Figure 2, which is a flow chart of an adaptive frequency modulation method provided by an embodiment of the present application. In the example shown in Figure 2, the method includes the following steps:

[0065] 201. The computing device collects real-time monitoring data of the processor, where the real-time monitoring data includes one or more events monitored by the performance monitoring unit (PMU) of the processor, where the events include one or more of the following: number of instruction executions, cache hit rate, and branch prediction error rate.

[0066] In the embodiments of the present application, the computing device needs to perform pre-frequency modulation initialization before performing adaptive frequency modulation. During the frequency modulation initialization phase of the computing device, the computing device needs to construct two formulas: a real-time performance change formula and a performance loss change formula. The frequency modulation initialization phase of the computing device is described in detail below.

[0067] First, the real-time performance change formula constructed by the computing device during the initialization phase in an embodiment of the present application is introduced.

[0068] In the process of constructing the real-time performance change formula, the computing device periodically collects monitoring data during the operation of the processor. These monitoring data can be called historical monitoring data. The monitoring data collected by the computing device includes one or more events monitored by the performance monitoring unit PMU, also called PMU events. PMU events include the number of instruction executions, cache hit rate and branch prediction error rate. Among them, the number of instruction executions refers to the number of instructions actually executed by the processor during the execution process, which can reflect the execution efficiency and performance of the processor. The cache hit rate refers to the proportion of data or instructions successfully obtained from the cache, which can reflect the processor's utilization of the cache. The branch prediction error rate refers to the accuracy of predicting whether the branch will be executed when there is a branch instruction in the program, which can also reflect the execution efficiency of the processor.

[0069] During the process of collecting monitoring data from the processor of the computing device, the computing device may set the main frequency of the central processing unit to a fixed value and record the corresponding relationship between the frequency, processor performance value, and PMU events of the central processing unit during task execution for a period of time. The computing device may then readjust the main frequency of the central processing unit and continue to record the corresponding relationship between the frequency, processor performance value, and PMU events of the central processing unit during task execution for a period of time.

[0070] By repeating the above acquisition process, the computing device can obtain multiple sets of corresponding relationship data between frequency, processor performance value, and PMU event, which can form a PMU event set. The processor performance value can be throughput, execution time, flow, latency, etc., without limitation.

[0071] After a computing device acquires multiple sets of data on the relationship between frequency, processor performance, and PMU events, it analyzes this data using a correlation coefficient analysis algorithm to identify one or more PMU events whose correlation with the processor's current performance change rate exceeds a threshold. The current performance change rate is the ratio of the processor's performance value at the previous moment to the current moment. These PMU events can form an event set used to fit the real-time performance change formula. Correlation coefficient analysis algorithms, such as the Pearson correlation coefficient analysis algorithm or the Spearman correlation coefficient analysis algorithm, can be used.

[0072] After obtaining the PMU event set, the computing device fits a relationship between the processor's current performance change rate and the PMU events in the PMU event set based on a regression model. The regression model can be a linear regression model, a logistic regression model, a polynomial regression model, etc. This relationship is the real-time performance change formula, which satisfies the following formula:

[0073] Among them, Y is the current performance change rate of the processor, X is the PMU event, is the coefficient of the PMU event, which is obtained based on the regression model fitting.

[0074] In one possible implementation, a computing device acquires historical monitoring data, where the historical monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of a processor at different frequencies. Based on the historical monitoring data, the computing device establishes a correlation between a processor performance loss rate and a frequency change rate. The correlation includes a blocking coefficient, which indicates the weight by which the processor performance value is affected by frequency.

[0075] Second, the performance loss change formula constructed by the computing device in the initialization phase in the embodiment of the present application is introduced.

[0076] In the process of constructing the performance loss change formula of computing equipment, the performance loss rate σ can be obtained by Q(f max ) and Q(f), where Q(f max ) represents the maximum frequency f max The corresponding performance value, Q(f) represents the performance value corresponding to f at the current frequency. Q(f max ) and Q(f) can also be expressed as the inverse ratio of execution time, that is, T(f) and T(f max ), where T(f) is the execution time at the current frequency f, and T(f max ) represents the maximum frequency f max Therefore, the performance loss change formula satisfies the following formula:

[0077] in, It can be the inverse of the change in the real-time performance of the task, i.e.

[0078] The performance loss of the processor in the embodiment of the present application can also be expressed as a formula related to the blocking coefficient β. Among them, the blocking coefficient β represents the weight of the actual performance of the processor being directly affected by the frequency modulation, and the blocking coefficient β takes a value between (0, 1). The larger the blocking coefficient β, the greater the actual performance is affected by the frequency. The smaller the blocking coefficient β, the less the actual performance of the processor is affected by the frequency modulation. The performance loss of the processor and the blocking coefficient β satisfy the following formula:

[0079] Please refer to Figure 3, which is a flowchart of another adaptive frequency modulation method provided by an embodiment of the present application. In steps a and b of the example shown in Figure 3, during the initialization phase of adaptive frequency modulation, the computing device needs to construct a real-time performance change formula and a performance loss formula based on historical monitoring data. The real-time performance change formula is used to indicate the relationship between the processor performance value and the PMU event, and the performance loss change formula is used to indicate the calculation formula for the performance loss rate.

[0080] Please refer to Figure 4, which is a flowchart of an adaptive frequency modulation provided by an embodiment of the present application. In steps a to b of the embodiment shown in Figure 4, during the initialization phase of the adaptive frequency modulation performed by the computing device, the computing device needs to analyze the collected historical monitoring data to determine the PMU events related to the current performance change rate of the processor. The computing device uses these PMU events and the current performance change rate of the processor corresponding to the PMU events to fit the relationship between the current performance change rate and the PMU events. During the initialization phase of the adaptive frequency modulation performed by the computing device, the computing device can calculate the current performance change rate of the processor based on the relationship between these performance values ​​and the PMU events.

[0081] The above describes the initialization work before the frequency modulation of the computing device in the embodiment of the present application. The following will continue to introduce the frequency modulation operation stage of the computing device.

[0082] During the frequency modulation phase, the computing device collects real-time monitoring data from the processor. This real-time monitoring data includes one or more events monitored by the processor's performance monitoring unit (PMU), including instruction execution counts, cache hit rates, and branch prediction error rates. The real-time monitoring data collected by the computing device can include PMU events at different times and frequencies. For example, the real-time monitoring data may include the PMU events at the current moment (now) and the PMU events at the previous moment (pre).

[0083] In one possible implementation, in addition to PMU events, real-time monitoring data collected by computing devices may also include events collected by the architectural performance monitoring unit (AMU), referred to as AMU events. Furthermore, real-time monitoring data may include CPU utilization or other scenario-related performance metrics, such as transactions per second (TPS) in database scenarios.

[0084] 202. The computing device calculates the predicted performance change rate of the processor based on real-time monitoring data, where the predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value.

[0085] The computing device calculates the predicted performance change rate of the processor at different frequencies based on real-time monitoring data. The predicted performance change rate can indicate the ratio of the processor's reference performance value to its operating performance value. The reference performance value of the processor is the performance value corresponding to the processor's maximum frequency, and the operating performance value is the performance value corresponding to the processor's current frequency.

[0086] Specifically, the computing device can calculate the current performance change rate based on the above real-time performance change formula, and then further calculate the predicted performance change rate based on the current performance change rate. The following details the process of the computing device calculating the predicted performance change rate:

[0087] In one possible implementation, when the computing device calculates the predicted performance change rate of the processor at different frequencies based on real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship, and the current performance change rate indicates the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the current frequency, wherein the performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. At the same time, the computing device calculates the ratio of the reference frequency and the frequency at the previous moment to obtain the frequency change rate, wherein the reference frequency is the maximum frequency of the processor. The computing device further calculates the predicted performance change rate based on the current performance change rate and the frequency change rate.

[0088] For example, the computing device collects the PMU event of the previous moment pre and the PMU event of the current moment now, and calculates Q(f pre ) and Q(f now ) ratio. Further, through the maximum frequency f max and the frequency f at the previous moment pre The ratio of Q(f pre ) and Q(f now ) proportional calculation Q(f max ) and Q(f now ) ratio. Among them, Q(f max ) and Q(f now The calculation of the ratio of ) satisfies the following formula.

[0089] 203. The computing device determines a target frequency of the processor based on a target performance loss rate and a predicted performance change rate, where the target performance loss rate is used to indicate a predicted performance change rate that the processor can tolerate.

[0090] After calculating the processor's predicted performance change rate, the computing device determines the processor's target frequency based on the target performance loss rate. The target performance loss rate indicates the predicted performance change rate the processor can tolerate. Specifically, during frequency modulation, the computing device sets a target performance loss rate, which is the permissible performance loss rate for the processor and is also referred to as a performance loss threshold.

[0091] There are two ways for a computing device to determine the target frequency of a processor based on a target performance loss rate. In the first method of determining the target frequency, the computing device can first calculate the blocking coefficient, and then calculate the target frequency based on the target performance loss rate and the blocking coefficient. In the second method of determining the target frequency, the computing device calculates the performance loss rate by adjusting the frequency. When the performance loss rate reaches the target performance loss rate, the target frequency can be determined. The following describes these two methods of determining the target frequency:

[0092] In the first target frequency determination method, when determining the processor's target frequency based on the target performance loss rate, the computing device calculates a blocking coefficient corresponding to real-time monitoring data based on the processor's predicted performance change rate and frequency change rate. The frequency change rate indicates the ratio of the processor's reference frequency to its current frequency. The computing device determines the target frequency based on the target performance loss rate and the blocking coefficient.

[0093] For example, when the computing device adjusts the target frequency at the next moment based on the PMU event at the previous moment pre and the PMU event at the current moment now, the computing device collects the PMU event at the previous moment pre and the PMU event at the current moment now, and calculates Q(f pre ) and Q(f now ) ratio, Q(f max ) and Q(f now ) ratio, which is the predicted performance change rate of the processor. Based on the above formulas (2) and (3), we can know that Q(f max ) and Q(f now The relationship between the ratio of ) and the blocking coefficient β satisfies the following formula:

[0094] Therefore, the computing device can be based on Q(f max ) and Q(f now ) ratio, and the maximum frequency f max and the current frequency f now The ratio of the calculation to obtain a blocking coefficient β is used to update the original blocking coefficient. After that, the computing device continues to calculate the blocking coefficient β and the target performance loss rate σ. targetCalculate the target frequency f at the next moment target Target performance loss rate σ target With the target frequency f target The relationship between them satisfies the following formula:

[0095] Computing equipment according to target performance loss rate σ target In the process of determining the target frequency and the blocking coefficient β, the computing device can calculate the target performance loss rate σ based on the formula (6) target Calculate the target frequency f target , f target This is the target frequency to be adjusted at the next moment.

[0096] Please continue to refer to Figure 3. In step c of the example shown in Figure 3, the computing device collects real-time monitoring data during the operation phase, updates the blocking coefficient based on the real-time monitoring data, and sets the target frequency based on the updated blocking coefficient and the target performance loss rate. For example, the computing device calculates the performance value Q(f) at the previous moment based on the above formula (1). pre ) and the performance value Q(f now ) ratio, that is And based on the above formula (4), the predicted performance change rate is further calculated At the same time, the blocking coefficient β is calculated using the above formula (5).

[0097] In the example shown in FIG3 , the computing device calculates the blocking coefficient β based on the set target performance loss rate σ. target Based on the above formula (6), the target frequency f can be calculated target .

[0098] Please continue to refer to Figure 4. In steps c to e shown in Figure 4, the computing device first sets the target performance loss rate and then collects real-time monitoring data. The real-time monitoring data includes the PMU events at the previous moment and the PMU events at the current moment. The computing device calculates the current performance change rate based on the real-time monitoring data, that is, the ratio of the performance value at the previous moment to the performance value at the current moment, and calculates the predicted performance change rate based on the current performance change rate. The predicted performance change rate is the ratio of the performance value at the maximum frequency to the performance value at the current moment.

[0099] In steps f to g illustrated in FIG4 , the computing device further calculates the blocking coefficient based on the ratio of the performance value at the maximum frequency to the performance value at the current moment and the target performance loss rate. The computing device calculates the target frequency based on the blocking coefficient and sets the target frequency as the frequency at the next moment.

[0100] In the second target frequency determination method, when the computing device determines the target frequency of the processor based on the target performance loss rate, if the predicted performance change rate of the processor is greater than the predicted performance change rate corresponding to the target performance loss rate, the processor frequency is increased. If the predicted performance change rate of the processor is less than the predicted performance change rate corresponding to the target performance loss rate, the processor frequency is decreased.

[0101] For example, when the computing device adjusts the target frequency at the next moment based on the PMU event at the previous moment pre and the PMU event at the current moment now, the computing device collects the PMU event at the previous moment pre and the PMU event at the current moment now, and calculates Q(f pre ) and Q(f now ) ratio, Q(f max ) and Q(f now ) ratio. Since Q(f max ) and Q(f now ) and performance loss satisfy the following formula:

[0102] Therefore, the computing device converts Q(f max ) and Q(f now ) and 1+σ target For comparison, when Q(f max ) and Q(f now ) is greater than or equal to 1+σ target , the computing device needs to increase the frequency of the processor by one level, Q(f max ) and Q(f now ) is less than 1+σ target , the computing device needs to reduce the frequency of the processor by one level, thereby achieving adaptive adjustment of the processor frequency.

[0103] Please refer to Figure 5, which is a schematic diagram of another adaptive frequency modulation process provided by an embodiment of the present application. In steps a through e of the example shown in Figure 5, after setting the target performance loss rate, the computing device also needs to calculate the current performance change rate based on the real-time monitoring data, that is, the ratio of the performance value at the previous moment to the performance value at the current moment, and calculate the predicted performance change rate based on the ratio of the performance value at the previous moment to the performance value at the current moment. The specific calculation process is similar to steps a through e of the example shown in Figure 4 above and will not be further described.

[0104] In steps f to h of the example shown in Figure 5, the computing device calculates the predicted performance change rate corresponding to the current frequency, and then calculates the performance loss rate corresponding to the current frequency based on the predicted performance change rate corresponding to the current frequency. If the performance loss corresponding to the current frequency is greater than or equal to the target performance loss rate, the computing device increases the current frequency by one level; if the performance loss corresponding to the current frequency is less than the target performance loss rate, the computing device decreases the current frequency by one level.

[0105] It can be seen from the above embodiments that the computing device in the embodiments of the present application can calculate the current performance change rate of the processor based on one or more events monitored by the performance monitoring unit PMU of the processor, and calculate the predicted performance change rate of the processor based on the current performance change rate of the processor, and further determine the target frequency based on the target performance loss rate and the predicted performance change rate. Since the performance value of the processor can be more accurately reflected based on the PMU event, the accuracy of the target frequency is improved and the power consumption of the processor is reduced.

[0106] Based on the above method embodiment, the embodiment of the present application further provides an adaptive frequency modulation device. The adaptive frequency modulation device provided by the embodiment of the present application is described in detail below.

[0107] Please refer to Figure 6, which is a schematic diagram of the structure of an adaptive frequency modulation device provided in an embodiment of the present application. In the example shown in Figure 6, the adaptive frequency modulation device 600 is used to implement the various steps performed by the computing device in the above embodiments. The adaptive frequency modulation device 600 includes an acquisition unit 601 and a processing unit 602.

[0108] Among them, the acquisition unit 601 is used to collect real-time monitoring data of the processor, and the real-time monitoring data includes one or more events monitored by the performance monitoring unit PMU of the processor, and the events include one or more of the following: number of instruction executions, cache hit rate and branch prediction error rate. The processing unit 602 is used to calculate the predicted performance change rate of the processor based on the real-time monitoring data. The predictive change rate is determined based on the current performance change rate of the processor. The current performance change rate is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value. The processing unit 602 is also used to determine the target frequency of the processor based on the target performance loss rate and the predicted performance change rate. The target performance loss rate is used to indicate the predicted performance change rate that the processor can tolerate.

[0109] In one possible implementation, the processing unit 602 is specifically used to calculate the current performance change rate of the processor based on real-time monitoring data and a performance change fitting relationship. The performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate. The frequency change rate is the ratio of the reference frequency to the operating frequency.

[0110] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit 602 is specifically used to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0111] In one possible implementation, the processing unit 602 is specifically configured to calculate a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate, and determine a target frequency according to the target performance loss rate and the blocking coefficient.

[0112] In one possible implementation, the processing unit 602 is further configured to increase the processor frequency when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, and decrease the processor frequency when the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate.

[0113] In one possible implementation, the processing unit 602 is further configured to obtain historical monitoring data including one or more events monitored by a performance monitoring unit PMU of the processor at different frequencies, and obtain a performance change fitting relationship based on fitting of the historical monitoring data.

[0114] In one possible implementation, the processing unit 602 is further configured to establish a correlation between the performance loss rate and the frequency change rate based on historical monitoring data, where the correlation includes a blocking coefficient, which is used to indicate the weight of the processor's performance value affected by the frequency.

[0115] It is understandable that the acquisition unit 601 and the processing unit 602 in the adaptive frequency modulation device 600 can be mapped as functional modules to the various modules in the adaptive frequency modulation system 10 in Figure 1, thereby realizing the functions of the various modules in the task processing system 10.

[0116] It should be understood that the division of units in the above device is merely a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. Moreover, the units in the device can all be implemented in the form of software called through processing elements; or they can all be implemented in the form of hardware; or some units can be implemented in the form of software called through processing elements, and some units can be implemented in the form of hardware. For example, each unit can be a separately established processing element, or it can be integrated into a certain chip of the device. In addition, it can also be stored in the memory in the form of a program, called by a certain processing element of the device and perform the function of the unit. In addition, all or part of these units can be integrated together, or they can be implemented independently. The processing element described here can also be a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each unit above can be implemented by the integrated logic circuit of the hardware in the processor element or in the form of software called through the processing element.

[0117] It is worth noting that, for the sake of simplicity of description, the above method embodiments are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited to the order of the actions described. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required for this application.

[0118] Other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be familiar with that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0119] Please refer to Figure 7, which is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. As shown in Figure 7, the computing device 700 includes: a processor 701, a memory 702, a communication interface 703, and a bus 704. The processor 701, the memory 702, and the communication interface 703 are coupled via a bus (not labeled in the figure). The memory 702 stores instructions. When the execution instructions in the memory 702 are executed, the computing device 700 performs the method performed by the computing device in the above method embodiment.

[0120] The computing device 700 may be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), one or more digital signal processors (DSPs), one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. For example, when a unit in the apparatus can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call a program. For example, these units may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0121] The processor 701 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0122] Memory 702 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Nonvolatile memory may be read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0123] The memory 702 stores executable program codes, and the processor 701 executes the executable program codes to implement the functions of the aforementioned units or modules, thereby implementing the aforementioned adaptive frequency modulation method. That is, the memory 702 stores instructions for executing the aforementioned adaptive frequency modulation method.

[0124] The communication interface 703 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 700 and other devices or a communication network.

[0125] In addition to the data bus, bus 704 may also include a power bus, a control bus, and a status signal bus. The bus may be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a unified bus (Ubus or UB), a Compute Express Link (CXL), or a Cache Coherent Interconnect for Accelerators (CCIX). Buses can be categorized as address buses, data buses, and control buses.

[0126] Please refer to Figure 8, which is a schematic diagram of the structure of a chip provided in an embodiment of the present application. As shown in Figure 8, chip 800 includes processing circuitry 801 and storage circuitry 802. Storage circuitry 802 in chip 800 may store instructions for executing the aforementioned adaptive frequency modulation method. When the instructions are executed by the processing circuitry, the chip performs the aforementioned adaptive frequency modulation method.

[0127] In another embodiment of the present application, a computer-readable storage medium is provided, in which computer-executable instructions are stored. When the processor of the device executes the computer-executable instructions, the device executes the method executed by the computing device in the above method embodiment.

[0128] In another embodiment of the present application, a computer program product is provided, the computer program product including computer-executable instructions stored in a computer-readable storage medium. When a processor of a device executes the computer-executable instructions, the device performs the method performed by the computing device in the above method embodiment.

[0129] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0131] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0132] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0133] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. An adaptive frequency modulation method, characterized in that: The method comprises: Collecting real-time monitoring data of the processor, the real-time monitoring data including one or more events monitored by a performance monitoring unit (PMU) of the processor, the events including one or more of the following: number of instruction executions, cache hit rate, and branch prediction error rate; Calculating a predicted performance change rate of the processor based on the real-time monitoring data, the predicted change rate being determined based on a current performance change rate of the processor, the current performance change rate being determined based on the real-time monitoring data, the predicted performance change rate being used to indicate a ratio of a reference performance value of the processor to an operating performance value; A target frequency of the processor is determined based on a target performance loss rate and the predicted performance change rate, where the target performance loss rate indicates a predicted performance change rate that the processor can tolerate.

2. The method according to claim 1, characterized in that Calculating the predicted performance change rate of the processor based on the real-time monitoring data includes: Calculating a current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, wherein the performance change fitting relationship is used to indicate a correlation relationship between the performance change rate and the monitoring data; The predicted performance change rate is calculated according to the current performance change rate and the frequency change rate, where the frequency change rate is a ratio of a reference frequency to an operating frequency.

3. The method according to claim 2, characterized in that The current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment, and calculating the predicted performance change rate based on the current performance change rate and the frequency change rate includes: Calculating the frequency change rate according to the reference frequency and the frequency at the previous moment; The predicted performance change rate is calculated according to the current performance change rate and the frequency change rate, and the predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

4. The method according to any one of claims 2 or 3, characterized in that Determining the target frequency of the processor based on the target performance loss rate and the predicted performance change rate includes: Calculating a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; A target frequency is determined according to the target performance loss rate and the blocking coefficient.

5. The method according to any one of claims 1 to 3, characterized in that The method further comprises: When the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, increasing the frequency of the processor; When the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, the frequency of the processor is reduced.

6. The method according to any one of claims 2 to 5, characterized in that The method further comprises: Acquire historical monitoring data, where the historical monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor at different frequencies; The performance change fitting relationship is obtained based on the historical monitoring data fitting.

7. The method according to claim 4, characterized in that The method further comprises: A correlation relationship between the performance loss rate and the frequency change rate is established based on the historical monitoring data, wherein the correlation relationship includes the blocking coefficient, and the blocking coefficient is used to indicate a weight of the performance value of the processor affected by the frequency.

8. An adaptive frequency modulation device, characterized in that: The device comprises: an acquisition unit, configured to collect real-time monitoring data of the processor, wherein the real-time monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor, wherein the events include one or more of the following: number of instruction executions, cache hit rate, and branch prediction error rate; a processing unit, configured to calculate a predicted performance change rate of the processor based on the real-time monitoring data, wherein the predicted performance change rate is determined based on a current performance change rate of the processor, which is determined based on the real-time monitoring data, and the predicted performance change rate is used to indicate a ratio of a reference performance value of the processor to an operating performance value; The processing unit is further configured to determine a target frequency of the processor based on a target performance loss rate and the predicted performance change rate, where the target performance loss rate indicates a predicted performance change rate that the processor can tolerate.

9. The device according to claim 8, characterized in that The processing unit is specifically configured to: Calculating a current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, wherein the performance change fitting relationship is used to indicate a correlation relationship between the performance change rate and the monitoring data; The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate, and the frequency change rate is the difference between the reference frequency and the running frequency. The ratio of row frequencies.

10. The device according to claim 9, characterized in that The current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit is specifically configured to: Calculating the frequency change rate according to the reference frequency and the frequency at the previous moment; The predicted performance change rate is calculated according to the current performance change rate and the frequency change rate, and the predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

11. The device according to any one of claims 9 or 10, characterized in that The processing unit is specifically configured to: Calculating a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; A target frequency is determined according to the target performance loss rate and the blocking coefficient.

12. The device according to any one of claims 8 to 11, characterized in that The processing unit is further configured to: When the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, increasing the frequency of the processor; When the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, the frequency of the processor is reduced.

13. The device according to any one of claims 9 to 12, characterized in that The processing unit is further configured to: Acquire historical monitoring data, where the historical monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor at different frequencies; The performance change fitting relationship is obtained based on the historical monitoring data fitting.

14. The device according to claim 11, characterized in that The processing unit is further configured to: A correlation relationship between the performance loss rate and the frequency change rate is established based on the historical monitoring data, wherein the correlation relationship includes the blocking coefficient, and the blocking coefficient is used to indicate a weight of the performance value of the processor affected by the frequency.

15. A computing device, characterized in that The computer comprises a processor coupled to a memory, wherein the memory is configured to store instructions. When the instructions are executed by the processor, the computer causes the computer to perform the method according to any one of claims 1 to 7.

16. A chip, characterized in that: The chip comprises a processing circuit coupled to a storage circuit, wherein the storage circuit is configured to store instructions. When the instructions are executed by the processing circuit, the chip performs the method according to any one of claims 1 to 7.

17. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed, the computer is caused to perform the method according to any one of claims 1 to 7.

18. A computer program product comprising instructions, characterized in that: When the instructions are executed, the computer is caused to implement the method according to any one of claims 1 to 7.

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