Memory structure, refreshing method, and memory

Abstract

A memory structure, a refreshing method, and a memory. The memory structure comprises: a refresh storage circuit arranged in a storage controller and used for storing supplementary refresh addresses, wherein the supplementary refresh addresses are used for indicating storage cells having a defect in charge retention capability; and a refresh register provided in each of a plurality of storage blocks. During power-on of the memory structure, the refresh storage circuit transmits the supplementary refresh addresses to the corresponding refresh registers; and each storage block is configured to: in a row hammer refresh period, refresh row hammer addresses on the basis of first refresh windows and a row hammer refresh identifier, or refresh the supplementary refresh addresses on the basis of second refresh windows and a supplementary refresh identifier, wherein the first refresh windows and the second refresh windows are distributed on the basis of row hammer refresh windows, and the ratio of the first refresh windows to the second refresh windows is a first preset value.

Description

Memory structure, refresh method and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 1, 2024, with application number 202410139681.3 and application name “Memory Structure, Refresh Method and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor circuit design, and in particular to a memory structure, a refresh method, and a memory. Background Art

[0003] Memory is a storage component used to store programs and various data. Memory can be categorized as either volatile or non-volatile. Dynamic Random Access Memory (DRAM), a type of volatile memory, stores data by charging or discharging capacitors within its storage cells. This data is lost when power is removed. Non-volatile memory, on the other hand, retains stored data even when power is removed.

[0004] DRAM cell failures are inevitable during the manufacturing process, and they become more severe with process scaling. For example, the number of weak cells in DRAM is increasing. Weak cells are cells with reduced data retention time due to leakage.

[0005] Repairing weak cells is crucial to improving DRAM performance.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a memory structure, a refresh method, and a memory to avoid the negative impact caused by repairing weak cells.

[0008] An embodiment of the present disclosure provides a memory structure, which includes a memory controller and multiple memory blocks. The memory structure includes: a refresh storage circuit, which is arranged in the memory controller and is used to store a supplementary refresh address, and the supplementary refresh address is used to indicate a memory cell with a defective charge retention capability; a refresh register, which is arranged in each of the multiple memory blocks; wherein, during the power-on process of the memory structure, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register; each memory block is configured to, during a row hammer refresh, refresh the row hammer address based on a first refresh window and a row hammer refresh identifier, or refresh the supplementary refresh address based on a second refresh window and a supplementary refresh identifier; wherein, the first refresh window and the second refresh window are allocated based on the row hammer refresh window, and the ratio of the first refresh window to the second refresh window is a first preset value.

[0009] The memory structure provided in this embodiment expands the memory's row hammer protection to enable row hammer protection and refresh of supplementary refresh addresses during the original row hammer protection period. Specifically, the original row hammer protection refreshes the row hammer refresh addresses based on a row hammer refresh window. After the row hammer protection is expanded, the row hammer refresh window is subdivided into a first refresh window and a second refresh window. The first refresh window continues to be used for row hammer protection, that is, refreshing the row hammer refresh addresses, while the second refresh window is used to refresh the supplementary refresh addresses. This allows the memory to better preserve data stored in weak cells and avoids the negative effects of repairing weak cells.

[0010] In some embodiments, the storage controller includes: a first refresh control circuit, configured to generate an identification signal; a second refresh control circuit, configured to generate a row hammer refresh window and a row hammer refresh signal; a refresh processing circuit, connecting the first refresh control circuit and the second refresh control circuit; if the identification signal is invalid, the refresh processing circuit is configured to generate a first refresh window based on the row hammer refresh window, and generate a row hammer refresh identification based on the row hammer refresh signal; if the identification signal is valid, the refresh processing circuit is configured to generate a judgment value based on a cycle count of the row hammer refresh signal, wherein, when the judgment value is valid, the refresh processing circuit is further configured to generate a second refresh window based on the row hammer refresh window, and generate a supplementary refresh identification based on the row hammer refresh signal; when the judgment value is invalid, the refresh processing circuit is further configured to generate a first refresh window based on the row hammer refresh window, and generate a row hammer refresh identification based on the row hammer refresh signal; the judgment value is used to configure the first preset value.

[0011] In some embodiments, the first refresh control circuit includes: a counting processing circuit, configured to count based on each refresh command to generate a refresh count value; the counting processing circuit is also configured to generate and output an identification signal when the refresh count value meets a second preset value; the second preset value is set to be less than or equal to k, where k is the product of the capacity of the corresponding refresh register to store the supplementary refresh address and the first preset value.

[0012] In some embodiments, the refresh processing circuit includes: a counter for generating a judgment value; a first AND logic circuit, a first input end connected to the output end of the counter, a second input end for receiving a row hammer refresh signal, and an output end for outputting a supplementary refresh flag; an inverter, an input end connected to the output end of the first AND logic circuit, and an output end for outputting a row hammer refresh flag; a second AND logic circuit, a first input end connected to the output end of the first AND logic circuit, a second input end for receiving a row hammer refresh window, and an output end for outputting a second refresh window; a third AND logic circuit, a first input end connected to the output end of the inverter, a second input end for receiving a row hammer refresh window, and an output end for outputting the first refresh window.

[0013] In some embodiments, each memory block includes: a row hammer refresh circuit configured to refresh a row hammer address based on a first refresh window and a row hammer refresh flag; and a supplementary refresh circuit configured to refresh a supplementary refresh address based on a second refresh window and a supplementary refresh flag.

[0014] In some embodiments, the operations of refreshing the row hammer address and refreshing the supplementary refresh address are cyclically executed in a preset order.

[0015] In some embodiments, the refresh memory circuit is based on an anti-fuse memory array arrangement.

[0016] In some embodiments, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register by broadcasting.

[0017] Another embodiment of the present disclosure also provides a refresh method, which is applied to the memory structure provided by the above embodiment, including: the storage controller transfers the set supplementary refresh address to the corresponding storage block; obtains a first refresh window and a row hammer refresh identifier, or obtains a second refresh window and a supplementary refresh identifier; during the row hammer refresh period, refreshes the row hammer address based on the first refresh window and the row hammer refresh identifier, or refreshes the supplementary refresh address based on the second refresh window and the supplementary refresh identifier; wherein the first refresh window and the second refresh window are allocated based on the row hammer refresh window, and the ratio of the first refresh window to the second refresh window is a first preset value.

[0018] In some embodiments, obtaining a first refresh window and a row hammer refresh identifier, or obtaining a second refresh window and a supplementary refresh identifier, includes: obtaining an identification signal; if the identification signal is invalid, generating a first refresh window based on the row hammer refresh window, and generating a row hammer refresh identifier based on the row hammer refresh signal; if the identification signal is invalid, cyclically counting based on the row hammer refresh signal to generate a judgment value, wherein, when the judgment value is valid, generating a second refresh window based on the row hammer refresh window, and generating a supplementary refresh identifier based on the row hammer refresh signal; when the judgment value is invalid, generating a first refresh window based on the row hammer refresh window, and generating a row hammer refresh identifier based on the row hammer refresh signal.

[0019] In some embodiments, a method for obtaining an identification signal includes: counting based on each refresh command to generate a refresh count value; generating and outputting an identification signal when the refresh count value meets a second preset value; the second preset value is set to be less than or equal to k, where k is the product of the capacity of the corresponding refresh register to store the supplementary refresh address and the first preset value.

[0020] Yet another embodiment of the present disclosure provides a memory, which is configured based on the memory structure provided in the above embodiments to avoid negative effects caused by repairing weak cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] FIG1 is a schematic diagram of a memory structure provided by an embodiment of the present disclosure;

[0023] FIG2 is a schematic diagram showing the principle of a refresh control circuit according to an embodiment of the present disclosure sending a supplementary refresh address to a refresh register;

[0024] FIG3 is a schematic diagram showing the principle of dividing a row hammer refresh window into a first refresh window and a second refresh window according to an embodiment of the present disclosure;

[0025] FIG4 is a schematic diagram illustrating examples of various allocations of first refresh windows and second refresh windows provided by an embodiment of the present disclosure;

[0026] FIG5 is a schematic diagram of a partial structure of a storage controller provided by an embodiment of the present disclosure;

[0027] FIG6 is a schematic structural diagram of a refresh processing circuit provided in an embodiment of the present disclosure;

[0028] FIG7 is a schematic flow chart of a refresh method provided in another embodiment of the present disclosure;

[0029] FIG8 is a schematic diagram of the structure of a memory provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As we know from the background, memory cell failure is an inevitable problem during the DRAM manufacturing process, and with process scaling, the problem of memory cell failure becomes more severe. For example, the number of weak cells in DRAM is increasing. Weak cells are memory cells with reduced data retention time due to leakage.

[0031] Specifically, weak cells can be repaired using redundant addresses (redundancy WL / BL) in the memory, by increasing the overall memory refresh rate, or by merging two word lines (WL) into a single architecture. Repairing weak cells based on redundant addresses, which have a limited number of redundant addresses, can strain memory repair resources. Increasing the overall memory refresh rate increases overall memory power consumption, while merging two word lines (WL) reduces memory capacity.

[0032] It can be seen from this that the current methods of repairing weak units will bring certain negative effects.

[0033] An embodiment of the present disclosure provides a memory structure to avoid the negative effects caused by repairing weak cells.

[0034] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0035] The memory structure provided by this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0036] 1 , which is a schematic diagram of a memory structure according to an embodiment of the present disclosure, includes a memory controller 10 and a plurality of memory blocks 20 . The memory structure includes a refresh memory circuit 101 and a refresh register 102 .

[0037] Among them, the refresh storage circuit 101 is provided in the memory controller 10 and is used to store a supplementary refresh address, which is used to indicate a memory cell with a defective charge retention capability. That is, the refresh storage circuit 101 is used to store the address of a weak cell. The refresh register 102 is provided in each memory block 20 of the plurality of memory blocks 20. During the power-up process of the memory structure, the refresh storage circuit 101 transmits the supplementary refresh address to the corresponding refresh register 102; each memory block 20 is configured to refresh the row hammer address based on the first refresh window and the row hammer refresh flag, or refresh the supplementary refresh address based on the second refresh window and the supplementary refresh flag during the row hammer refresh period; wherein the first refresh window and the second refresh window are allocated based on the row hammer refresh window, and the ratio of the first refresh window to the second refresh window is a first preset value.

[0038] Specifically, the supplementary refresh address stored in the refresh storage circuit 101 is obtained during the memory test phase. During the memory power-up process, the refresh storage circuit 101 transmits the stored supplementary refresh address to the refresh register 102 of the corresponding memory block 20. For example, referring to FIG2 , FIG2 is a schematic diagram illustrating the principle of the refresh control circuit according to an embodiment of the present disclosure issuing the supplementary refresh address to the refresh register. Assume that the memory structure includes 32 memory blocks, wherein refresh register 1 is set in memory block 1, refresh register 2 is set in memory block 2, and so on, refresh register 32 is set in memory block 32. The refresh storage circuit 101 stores 2560 supplementary refresh addresses. During the power-on process of the memory structure, the refresh storage circuit 101 sends the supplementary refresh addresses 1 to 80 to the storage block 1, and the refresh register 1 is used to store the supplementary refresh addresses 1 to 80... The refresh storage circuit 101 sends the supplementary refresh addresses 80n-79 to 80n to the storage block n, and the refresh register n is used to store the supplementary refresh addresses 80n-79 to 80n... The refresh storage circuit 101 sends the supplementary refresh addresses 2481 to 2560 to the storage block 32, and the refresh register 32 is used to store the supplementary refresh addresses 2481 to 2560.

[0039] In some embodiments, the refresh storage circuit 101 is configured based on an antifuse memory array. Specifically, based on the address of a weak memory cell obtained during the test phase, the memory device fuses the corresponding memory cell in the antifuse memory array, allowing the refresh storage circuit 101 to store the supplementary refresh address. The refresh storage circuit 101 configured with the antifuse memory array can relatively completely retain the set supplementary refresh address even if the memory structure loses power. In other embodiments, the refresh storage circuit can also store the supplementary refresh address using a register or capacitor.

[0040] In some embodiments, the refresh storage circuit 101 transmits the supplemental refresh address to the corresponding refresh register 102 via broadcast. Specifically, during the memory power-up process, the refresh storage circuit 101 transmits the stored supplemental refresh address to the refresh register 102 of the corresponding memory block 20 via broadcast to increase the speed of issuing the supplemental refresh address. In other embodiments, the refresh storage circuit can also be configured such that during the memory structure power-up process, based on a corresponding control signal, the supplemental refresh address is transmitted to the refresh register of the corresponding memory block.

[0041] Regarding the relationship between the row hammer refresh window, the first refresh window, and the second refresh window, refer to Figures 3 and 4. Figure 3 is a schematic diagram of the principle of dividing the row hammer refresh window into the first refresh window and the second refresh window provided in an embodiment of the present disclosure, and Figure 4 is an example schematic diagram of multiple allocations of the first refresh window and the second refresh window provided in an embodiment of the present disclosure. In the process of the memory executing the full memory refresh REFab, it includes multiple tRFCs (the time required to execute the refresh command), and row hammer protection is executed once every two tRFCs. When the memory needs to execute row hammer protection, the memory controller will provide a corresponding row hammer refresh window. This embodiment is used to allocate the row hammer refresh window into the first refresh window and the second refresh window according to the first preset value.

[0042] In an example, if the first preset value is 3:1, referring to Figure 4(A), every 4 row hammer refresh windows are allocated as 3 first refresh windows and 1 second refresh window; if the first preset value is 1:3, referring to Figure 4(B), every 4 row hammer refresh windows are allocated as 1 first refresh window and 3 second refresh windows; if the first preset value is 2:2, referring to Figure 4(C) and Figure 4(D), every 4 row hammer refresh windows are allocated as 2 first refresh windows and 2 second refresh windows.

[0043] Specifically, the setting of the first preset value must meet the row hammer protection condition and the weak protection condition. For the row hammer protection condition, the total number of row activations A within two adjacent row hammer protections is limited to no more than n1, that is, A<n1, and the total number of row activations in the memory is A=n*(tREFI-tRFC) / tRC, where n represents the number of tREFIs that have passed, tREFI represents the refresh instruction interval time, and tRC represents the single address activation time. The configuration of the first preset value must meet n. For the weak protection condition, the refresh time length of two identical weak cells is limited to no more than the minimum value of Retention Time, g is the number of tREFIs that have passed, that is, g*tREFI<Retention Time, and the configuration of the first preset value must meet g.

[0044] In an example, under the conditions of DDR5 16G, tREFI = 3.9us, tRFC = 295ns, tRC = 48ns, at this time n < 53, that is, the hammer protection can be not performed in a maximum of 52 consecutive tREFIs; if the minimum value of the Retention Time under certain process conditions is 16ms, at this time g < 4102, that is, the weak protection can be not configured in a maximum of 4102 consecutive tRFEIs, so as to comprehensively configure the first preset value.

[0045] In some embodiments, the operations of refreshing the row hammer address and refreshing the supplemental refresh address are performed cyclically in a predetermined order. Referring to FIG. 4(C) and FIG. 4(D), if the first predetermined ratio is 2:2, every four row hammer refresh windows are allocated as two first refresh windows and two second refresh windows. In this case, the first and second windows can be configured to be executed alternately, either individually or in pairs.

[0046] It should be noted that the description of the specific value of the first preset value in this embodiment is only for those skilled in the art to understand how to allocate the row hammer refresh window to the first refresh window and the second refresh window, and does not constitute a limitation on the first preset value. In specific applications, those skilled in the art can configure the first preset value on their own based on the row hammer protection condition and the weak protection condition.

[0047] The memory structure provided in this embodiment expands the memory's row hammer protection to enable row hammer protection and refresh of supplementary refresh addresses during the original row hammer protection period. Specifically, the original row hammer protection refreshes the row hammer refresh addresses based on a row hammer refresh window. After the row hammer protection is expanded, the row hammer refresh window is subdivided into a first refresh window and a second refresh window. The first refresh window continues to be used for row hammer protection, that is, refreshing the row hammer refresh addresses, while the second refresh window is used to refresh the supplementary refresh addresses. This allows the memory to better preserve data stored in weak cells and avoids the negative effects of repairing weak cells.

[0048] In some embodiments, referring to FIG5 , FIG5 is a schematic diagram of a portion of the structure of a memory controller provided in an embodiment of the present disclosure. The memory controller includes: a first refresh control circuit 201, a second refresh control circuit 202, and a refresh processing circuit 203. The first refresh control circuit 201 is configured to generate an identification signal, and the second refresh control circuit 202 is configured to generate a row hammer refresh window and a row hammer refresh signal. The refresh processing circuit 203 is connected to the first refresh control circuit 201 and the second refresh control circuit 202.

[0049] Specifically, if the identification signal is invalid, the refresh processing circuit 203 is configured to generate a first refresh window based on the row hammer refresh window, and generate a row hammer refresh identifier based on the row hammer refresh signal. If the identification signal is valid, the refresh processing circuit 203 is configured to generate a judgment value based on the cycle count of the row hammer refresh signal. When the judgment value is valid, the refresh processing circuit 203 is configured to generate a second refresh window based on the row hammer refresh window, and generate a supplementary refresh identifier based on the row hammer refresh signal. When the judgment value is invalid, the refresh processing circuit 203 is configured to generate a first refresh window based on the row hammer refresh window, and generate a row hammer refresh identifier based on the row hammer refresh signal. The judgment value is used to configure the first preset value.

[0050] Specifically, since the identification signal represents the start time for the supplemental refresh address, the memory structure will allocate the row hammer refresh window to implement the refresh of the supplemental refresh address only when the identification signal is valid. In one example, when the identification signal is at a high level, the identification signal is valid, and when the identification signal is at a low level, the identification signal is invalid. In another example, it can also be configured such that when the identification signal is at a low level, the identification signal is valid, and when the identification signal is at a high level, the identification signal is invalid.

[0051] Regarding the principle of generating a judgment value based on a cyclic count of a row hammer refresh signal, the judgment value is used to configure the first preset value as follows: assuming that the cyclic count value of the row hammer refresh signal is a1, that is, based on each row hammer refresh signal, counting +1 is performed from 0, and when the count reaches a1, the count is reset to restart. When the count value satisfies a2, a3…ai, a valid judgment value is generated. At this time, the judgment values ​​generated by a1-i values ​​in a1 are invalid, and the judgment values ​​generated by i values ​​are valid, that is, the first preset value is a1-i:i. In one example, when the judgment value is a high level, the judgment value is valid, and when the judgment value is a low level, the judgment value is invalid. In another example, it can also be configured so that when the judgment value is a low level, the judgment value is valid, and when the judgment value is a high level, the judgment value is invalid.

[0052] In a specific example, the loop count value is 5. When the count value satisfies 2 and 3, a valid judgment value is generated. At this time, the judgment values ​​generated by 3 values ​​are invalid, and the judgment values ​​generated by 2 values ​​are valid. The first preset value is 3:2. The refresh of the row hammer address and the supplementary refresh address is cyclically executed in the order of "row hammer-supplement-supplement-row hammer-row hammer".

[0053] In some embodiments, the first refresh control circuit 201 includes a counting processing circuit configured to count based on each refresh command to generate a refresh count value; the counting circuit is further configured to generate and output an identification signal when the refresh count value meets a second preset value. Whether the refresh count value meets the second preset value is used to set a time period for performing a supplementary refresh address refresh during a full memory refresh of the memory. In one example, a supplementary refresh address refresh is performed at the beginning of a full memory refresh period, and the second preset value is set to be less than or equal to k, where k is the product of the capacity of the corresponding refresh register 102 for storing the supplementary refresh address and the first preset value. For example, the capacity of the refresh register 102 for storing the supplementary refresh address is 80, and the first preset value is used to represent that there is one second refresh window for refreshing the supplementary refresh address in every three row hammer refresh windows. At this time, 240 row hammer refresh windows are required to complete the refresh of all supplementary refresh addresses, and two refresh commands in the memory of this embodiment correspond to one row hammer refresh window, that is, k is set to 240*2=480; in another example, a supplementary refresh address refresh is performed in the middle stage of a full memory refresh period; in another example, a supplementary refresh address refresh is performed at the end stage of a full memory refresh period.

[0054] In some embodiments, referring to FIG6 , FIG6 is a schematic diagram of the structure of a refresh processing circuit provided in an embodiment of the present disclosure. The refresh processing circuit 203 includes: a counter 301 for generating a judgment value; a first AND logic circuit 302, having a first input connected to the output of the counter 301, a second input for receiving a row hammer refresh signal, and an output for outputting a supplementary refresh flag. An inverter 303, having an input connected to the output of the first AND logic circuit 302, and an output for outputting a row hammer refresh flag. Specifically, if the judgment value is valid, the refresh processing circuit 203 generates a supplementary refresh flag based on the row hammer refresh signal. When the supplementary refresh flag is not generated, the inverter 303 connected to the first AND logic circuit 302 generates a row hammer refresh flag. A second AND logic circuit 304, having a first input connected to the output of the first AND logic circuit 302, a second input for receiving a row hammer refresh window, and an output for outputting a second refresh window. A third AND logic circuit 305, having a first input connected to the output of the inverter 303, a second input for receiving a row hammer refresh window, and an output for outputting the first refresh window.

[0055] It should be noted that the first AND logic circuit 302, the second AND logic circuit 304, and the third AND logic circuit 305 provided in FIG6 can be implemented based on AND gates, or based on AND gates cascaded with inverters, or can be implemented through a combination of other gate circuits.

[0056] In some embodiments, referring to Figure 1, the storage block 20 controls the refresh of the supplementary refresh address or the refresh of the row hammer refresh address through the refresh control circuit 103, wherein the refresh control circuit 103 includes: a row hammer refresh circuit and a supplementary refresh circuit, wherein the row hammer refresh circuit is configured to refresh the row hammer address based on the first refresh window and the row hammer refresh identifier; the supplementary refresh circuit is configured to refresh the supplementary refresh address based on the second refresh window and the supplementary refresh identifier.

[0057] In some embodiments, the counter is composed of cascaded D flip-flops, and the output of the judgment value can be achieved through a combination circuit composed of the output terminals of the corresponding D flip-flops and gate circuits. For example, if the judgment values ​​are 2 and 5, the judgment value 2 can be achieved through the output data of the second-stage D flip-flop, and the judgment value 5 can be achieved by connecting the first-stage D flip-flop and the third-stage D flip-flop with the gate.

[0058] The memory structure provided in this embodiment expands the memory's row hammer protection to enable row hammer protection and refresh of supplementary refresh addresses during the original row hammer protection period. Specifically, the original row hammer protection refreshes the row hammer refresh addresses based on a row hammer refresh window. After the row hammer protection is expanded, the row hammer refresh window is subdivided into a first refresh window and a second refresh window. The first refresh window continues to be used for row hammer protection, that is, refreshing the row hammer refresh addresses, while the second refresh window is used to refresh the supplementary refresh addresses. This allows the memory to better preserve data stored in weak cells and avoids the negative effects of repairing weak cells.

[0059] It should be noted that the features disclosed in the memory structures provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory structure embodiments.

[0060] Another embodiment of the present disclosure provides a refresh method, which provides a way to refresh weak cells to avoid negative effects caused by repairing the weak cells.

[0061] The refresh method provided by this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:

[0062] Referring to FIG. 7 , FIG. 7 is a flow chart of a refresh method provided in another embodiment of the present disclosure. The refresh method includes steps 401 to 404 .

[0063] Step 401: Record the supplementary refresh address in the memory controller.

[0064] Specifically, the supplementary refresh address stored in the refresh storage circuit is obtained by the memory during the test phase.

[0065] In some embodiments, the refresh storage circuit is configured based on an antifuse storage array. Specifically, based on the address of a weak memory cell obtained during the test phase, the memory device fuses the corresponding memory cell in the antifuse storage array, allowing the refresh storage circuit 101 to store the supplementary refresh address. The refresh storage circuit configured with the antifuse storage array allows the set supplementary refresh address to be relatively intact even if the memory structure loses power. In other embodiments, the refresh storage circuit can also store the supplementary refresh address using a register or capacitor.

[0066] Step 402: The memory controller transmits the set supplementary refresh address to the corresponding memory block.

[0067] Specifically, the memory controller transmits the set supplementary refresh address to the corresponding memory block.

[0068] In some embodiments, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register via broadcast. Specifically, during the memory power-up process, the refresh storage circuit transmits the stored supplementary refresh address to the refresh register of the corresponding memory block via broadcast to increase the speed of issuing the supplementary refresh address. In other embodiments, the refresh storage circuit can also be configured such that during the memory structure power-up process, based on a corresponding control signal, the supplementary refresh address is transmitted to the refresh register of the corresponding memory block.

[0069] Step 403: Obtain a first refresh window and a row hammer refresh flag, or obtain a second refresh window and a supplementary refresh flag.

[0070] The first refresh window and the second refresh window are allocated based on the row hammer refresh window, and a ratio of the first refresh window to the second refresh window is a first preset value.

[0071] In some embodiments, step 403 specifically includes: obtaining an identification signal, and determining whether the identification signal is valid.

[0072] If the identification signal is invalid, a first refresh window is generated based on the row hammer refresh window, and a row hammer refresh identifier is generated based on the row hammer refresh signal. If the identification signal is valid, a cyclic count is performed based on the row hammer refresh signal to generate a judgment value. When the judgment value is valid, a second refresh window is generated based on the row hammer refresh window, and a supplementary refresh identifier is generated based on the row hammer refresh signal. When the judgment value is invalid, a first refresh window is generated based on the row hammer refresh window, and a row hammer refresh identifier is generated based on the row hammer refresh signal. The judgment value is used to configure the first preset value.

[0073] Specifically, since the identification signal represents the start time for the supplemental refresh address, the memory structure will allocate the row hammer refresh window to implement the refresh of the supplemental refresh address only when the identification signal is valid. In one example, when the identification signal is at a high level, the identification signal is valid, and when the identification signal is at a low level, the identification signal is invalid. In another example, it can also be configured such that when the identification signal is at a low level, the identification signal is valid, and when the identification signal is at a high level, the identification signal is invalid.

[0074] Regarding the principle of generating a judgment value based on a cyclic count of a row hammer refresh signal, the judgment value is used to configure the first preset value as follows: assuming that the cyclic count value of the row hammer refresh signal is a1, that is, based on each row hammer refresh signal, counting +1 is performed from 0, and when the count reaches a1, the count is reset to restart. When the count value satisfies a2, a3…ai, a valid judgment value is generated. At this time, the judgment values ​​generated by a1-i values ​​in a1 are invalid, and the judgment values ​​generated by i values ​​are valid, that is, the first preset value is a1-i:i. In one example, when the judgment value is a high level, the judgment value is valid, and when the judgment value is a low level, the judgment value is invalid. In another example, it can also be configured so that when the judgment value is a low level, the judgment value is valid, and when the judgment value is a high level, the judgment value is invalid.

[0075] In a specific example, the loop count value is 5. When the count value satisfies 2 and 3, a valid judgment value is generated. At this time, the judgment values ​​generated by 3 values ​​are invalid, and the judgment values ​​generated by 2 values ​​are valid. The first preset value is 3:2. The refresh of the row hammer address and the supplementary refresh address is cyclically executed in the order of "row hammer-supplement-supplement-row hammer-row hammer".

[0076] In some embodiments, the method for acquiring the identification signal includes: counting based on each refresh command to generate a refresh count value, and generating and outputting the identification signal when the refresh count value meets a second preset value.

[0077] The time period for performing supplemental refresh address refresh during a full memory refresh of the memory is set by determining whether the refresh count value meets a second preset value. In one example, the supplemental refresh address refresh is performed at the beginning of the full memory refresh period. In this case, the second preset value is set to be less than or equal to k, where k is the product of the capacity of the corresponding refresh register 102 for storing supplemental refresh addresses and the first preset value. For example, the capacity of the refresh register 102 for storing supplemental refresh addresses is 80, and the first preset value indicates that there is one second refresh window for refreshing the supplemental refresh addresses in every three row hammer refresh windows. In this case, 240 row hammer refresh windows are required to complete the refreshing of all supplemental refresh addresses. In the memory of this embodiment, two refresh commands correspond to one row hammer refresh window, i.e., k is set to 240*2=480. In another example, the supplemental refresh address refresh is performed in the middle of the full memory refresh period. In yet another example, the supplemental refresh address refresh is performed at the end of the full memory refresh period.

[0078] Step 404 : During the row hammer refresh period, refresh the row hammer address based on the first refresh window and the row hammer refresh flag, or refresh the supplementary refresh address based on the second refresh window and the supplementary refresh flag.

[0079] It should be noted that the features disclosed in the refresh methods provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh method embodiments. In addition, this embodiment can be implemented in conjunction with the refresh control structure provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment and will not be repeated here to reduce repetition.

[0080] FIG8 is a schematic diagram of a memory structure according to another embodiment of the present disclosure. Referring to FIG8 , another embodiment of the present disclosure provides a memory 1 that is configured based on the memory structure 2 provided in the above embodiment to avoid the negative effects of repairing weak cells.

[0081] Specifically, the row hammer protection of the memory 1 is expanded to perform row hammer protection and refresh of the supplementary refresh address during the original row hammer protection period.

[0082] Specifically, the original row hammer protection refreshes the row hammer refresh address based on the row hammer refresh window. After the row hammer protection is expanded, the row hammer refresh window is subdivided into a first refresh window and a second refresh window. The first refresh window continues to be used for row hammer protection, that is, the row hammer refresh address is refreshed, and the second refresh window is used to refresh the supplementary refresh address, so that the memory 1 can better preserve the data stored in the weak unit and avoid the negative impact brought by repairing the weak unit.

[0083] The memory 1 may be a memory unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), a thyristor random access memory (TRAM), or the like; or may be a non-volatile memory, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), or the like.

[0084] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A memory structure, characterized in that: The memory structure includes a memory controller (10) and a plurality of memory blocks (20), and the memory structure includes: A refresh storage circuit (101) is provided in the storage controller (10) and is used to store a supplementary refresh address, wherein the supplementary refresh address is used to indicate a storage unit having a defective charge storage capability; a refresh register (102) provided in each memory block (20) of the plurality of memory blocks (20); Wherein, during the power-on process of the memory structure, the refresh storage circuit (101) transmits the supplementary refresh address to the corresponding refresh register (102); Each of the memory blocks (20) is configured to, during a row hammer refresh period, refresh a row hammer address based on a first refresh window and a row hammer refresh flag, or refresh the supplementary refresh address based on a second refresh window and a supplementary refresh flag; The first refresh window and the second refresh window are allocated based on a row hammer refresh window, and a ratio of the first refresh window to the second refresh window is a first preset value.

2. The memory structure according to claim 1, wherein: The storage controller (10) comprises: A first refresh control circuit (201) is configured to generate an identification signal; A second refresh control circuit (202) is configured to generate a row hammer refresh window and a row hammer refresh signal; A refresh processing circuit (203) connected to the first refresh control circuit (201) and the second refresh control circuit (202); If the identification signal is invalid, the refresh processing circuit (203) is configured to generate the first refresh window based on the row hammer refresh window, and generate the row hammer refresh identification based on the row hammer refresh signal; If the identification signal is valid, the refresh processing circuit (203) is configured to generate a judgment value based on the cycle count of the row hammer refresh signal, wherein when the judgment value is valid, the refresh processing circuit (203) is further configured to generate the second refresh window based on the row hammer refresh window, and generate the supplementary refresh identification based on the row hammer refresh signal; when the judgment value is invalid, the refresh processing circuit (203) is further configured to generate the first refresh window based on the row hammer refresh window, and generate the row hammer refresh identification based on the row hammer refresh signal; The judgment value is used to configure the first preset value.

3. The memory structure according to claim 2, wherein: The first refresh control circuit (201) comprises: a count processing circuit configured to count based on each refresh command to generate a refresh count value; The counting processing circuit is further configured to generate and output the mark when the refresh count value meets the second preset value. Recognize signals; The second preset value is set to be less than or equal to k, wherein k is the product of the capacity of the corresponding refresh register (102) for storing the supplementary refresh address and the first preset value.

4. The memory structure according to claim 2, wherein: The refresh processing circuit (203) comprises: A counter (301), configured to generate the judgment value; A first AND logic circuit (302), wherein a first input terminal is connected to an output terminal of the counter (301), a second input terminal is used to receive the row hammer refresh signal, and an output terminal is used to output the supplementary refresh flag; an inverter (303), the input end of which is connected to the output end of the first AND logic circuit (302), and the output end of which is used to output the row hammer refresh flag; A second AND logic circuit (304), having a first input end connected to the output end of the first AND logic circuit (302), a second input end for receiving the row hammer refresh window, and an output end for outputting the second refresh window; The third AND logic circuit (305) has a first input terminal connected to the output terminal of the inverter (303), a second input terminal for receiving the row hammer refresh window, and an output terminal for outputting the first refresh window.

5. The memory structure according to claim 2, wherein: Each of the storage blocks (20) comprises: a row hammer refresh circuit, configured to refresh a row hammer address based on the first refresh window and the row hammer refresh flag; The supplementary refresh circuit is configured to perform a refresh on the supplementary refresh address based on the second refresh window and the supplementary refresh flag. The memory structure according to claim 1 , wherein: The operations of refreshing the row hammer address and refreshing the supplementary refresh address are executed in a cyclic manner in a preset order.

7. The memory structure according to claim 1, wherein: The refresh memory circuit (101) is arranged based on an anti-fuse memory array.

8. The memory structure according to claim 1, wherein: The refresh storage circuit (101) transmits the supplementary refresh address to the corresponding refresh register (102) by broadcasting.

9. A refresh method, applied to the memory structure according to any one of claims 1 to 8, characterized in that: include: (401:) recording the supplementary refresh address in the memory controller (10); (402:) The memory controller (10) transmits the set supplementary refresh address to the corresponding memory block (20); (403:) Acquire the first refresh window and the row hammer refresh flag, or acquire the second refresh window and the supplementary refresh flag; (404): During a row hammer refresh period, refreshing a row hammer address based on the first refresh window and the row hammer refresh identifier, or refreshing the supplementary refresh address based on the second refresh window and the supplementary refresh identifier; The first refresh window and the second refresh window are allocated based on a row hammer refresh window, and a ratio of the first refresh window to the second refresh window is a first preset value.

10. The refreshing method according to claim 9, wherein: The memory controller (10) further comprises a first refresh control circuit (201) and a second refresh control circuit (202), wherein the first refresh control circuit (201) is configured to generate the identification signal, and the second refresh control circuit (202) is configured to generate a row hammer refresh window and a row hammer refresh signal, wherein obtaining the first refresh window and the row hammer refresh identification, or obtaining the second refresh window and the supplementary refresh identification, comprises: acquiring the identification signal; If the identification signal is invalid, generating the first refresh window based on the row hammer refresh window, and generating the row hammer refresh identification based on the row hammer refresh signal; If the identification signal is invalid, a judgment value is generated based on a cyclic count of the row hammer refresh signal, wherein, when the judgment value is valid, the second refresh window is generated based on the row hammer refresh window, and the supplementary refresh identification is generated based on the row hammer refresh signal; when the judgment value is invalid, the first refresh window is generated based on the row hammer refresh window, and the row hammer refresh identification is generated based on the row hammer refresh signal.

11. The refreshing method according to claim 10, wherein: The method for obtaining an identification signal includes: Counting based on each refresh command to generate a refresh count value; When the refresh count value meets the second preset value, the identification signal is generated and output; The second preset value is set to be less than or equal to k, where k is the product of the capacity of the corresponding refresh register for storing the supplementary refresh address and the first preset value.

12. A memory (1), characterized in that The memory is arranged based on the memory structure (2) according to any one of claims 1 to 8.

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