Chip packaging structure, manufacturing method therefor, and electronic device

Abstract

Provided in the present application are a chip packaging structure, a manufacturing method therefor, and an electronic device. The chip packaging structure comprises a carrier plate, a plastic packaging structure and an interconnection layer. A die comprises a substrate and a wiring layer arranged on the substrate, the surface of the wiring layer facing the interconnection layer and the surface of a filling portion facing the interconnection layer being located in the same plane. The wiring layer comprises a first connection portion, and the interconnection layer comprises a first wire, the first connection portions in two adjacent dies being connected via the first wire. In this way, the first wire in the interconnection layer can interconnect the dies, so as to achieve communication between the dies. In addition, the wiring layer of the die is directly connected to the interconnection layer, that is, connecting the wiring layer and the interconnection layer does not need solder balls as in the prior art, such that it is unnecessary to take into account the limitation of solder balls when setting the density of wiring in the interconnection layer, and the wiring density can be set to the maximum extent according to an actual condition. Thus, the density of wiring in the interconnection layer can be effectively increased, thereby improving the interconnection density of the chip packaging structure.

Description

Chip packaging structure, manufacturing method thereof and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on January 29, 2024, with application number 202410128407.6 and application name “A chip packaging structure, its manufacturing method and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip technology, and in particular to a chip packaging structure, a manufacturing method thereof, and an electronic device. Background Art

[0004] Chip packaging typically integrates multiple die onto a single substrate, resulting in higher packaging density and interconnection density. Solder balls are placed on the die's surface, and the die is flipped onto an adapter board, connecting the solder balls to traces on the board's surface to interconnect the die. Through-silicon vias (TSVs) are also located on the adapter board's surface facing away from the die. These TSVs electrically connect the solder balls on the die's surface to those on the adapter board, enabling signal routing.

[0005] However, when the solder balls on the die are larger, fewer traces can be routed between them, resulting in a low interconnect density that cannot meet the performance requirements of high-end server processor chips. While it is possible to reduce the size of the solder balls on the die to increase the number of traces that can be routed between them, the solder balls are still limiting, preventing further increases in interconnect density.

[0006] Summary of the Invention

[0007] The present application provides a chip packaging structure, a manufacturing method thereof, and an electronic device for increasing the interconnection density of the chip packaging structure.

[0008] In a first aspect, embodiments of the present application provide a chip packaging structure, the chip packaging structure comprising: a carrier, a plastic encapsulation structure, and an interconnection layer stacked in sequence, the plastic encapsulation structure comprising at least two dies and a filling portion, the filling portion filling an area between the carrier and the interconnection layer excluding the dies; wherein the dies are arranged side by side and spaced apart on the carrier surface, wherein "side by side on the carrier surface" means that the arrangement direction of the dies is parallel to the carrier surface, so that there is a gap between adjacent dies; in this case, the filling portion may fill an area between the carrier and the interconnection layer excluding the dies, so that the filling portion may wrap around all four sides of the dies; if the surface of the dies facing the carrier and the surface of the dies facing the interconnection layer are both referred to as the large surface of the dies, and the surface between the two large surfaces is referred to as the side surface, the filling portion may only wrap around the side surface of the dies; when the dies comprise: a substrate and a wiring layer disposed on the substrate, the wiring layer is disposed between the substrate and the interconnection layer, and the surface of the wiring layer facing the interconnection layer and the surface of the filling portion facing the interconnection layer are coplanar; the wiring layer comprises a first connection portion, the interconnection layer comprises a first trace, and the first connection portions of two adjacent dies are connected by the first trace. In this way, the first routing lines in the interconnection layer can be used to interconnect the dies, thereby enabling communication between the dies. Furthermore, because the surface of the wiring layer facing the interconnection layer and the surface of the filling portion facing the interconnection layer are located in the same plane, the wiring layer of the dies is directly connected to the interconnection layer. That is, the wiring layer and the interconnection layer do not need to be connected via solder balls as in the prior art. Consequently, when setting the routing density in the interconnection layer, there is no need to consider the limitations of solder balls. The routing density can be set to the maximum value based on actual conditions, effectively increasing the routing density in the interconnection layer and thus improving the interconnection density of the chip packaging structure. Furthermore, because the wiring layer of the dies is directly connected to the interconnection layer and there are no solder balls between the wiring layer and the interconnection layer, interference caused by the presence of solder balls can be avoided during signal transmission, thereby improving the effectiveness and accuracy of signal transmission.

[0009] Optionally, a solder ball is disposed on a surface of the interconnect layer facing away from the plastic encapsulation structure, the wiring layer includes a second connection portion, and the interconnect layer includes a second trace, the second trace connecting the solder ball and the second connection portion. Thus, the second trace can connect the second connection portion to the outside world via the second trace, enabling signal input and output. Furthermore, the interconnect layer can include at least two dielectric layers and at least one conductive layer, the dielectric layers and the conductive layers being arranged alternately. The second trace includes a first segment located in each dielectric layer and a second segment located in each conductive layer, the first segment connected to the second segment. This indicates that the interconnect layer is composed of alternating dielectric and conductive layers, unlike structures such as silicon substrates, silicon baseplates, or silicon interposers that are constructed of silicon material. Furthermore, when the second trace includes a first segment located in the dielectric layer and a second segment located in the conductive layer, and the first and second segments are connected, the second trace is distinct from a through-silicon via (TSV). Therefore, when connecting the second connection portion to the solder ball via the interconnect layer, a TSV is not required; the second trace in the interconnect layer can be used. This reduces both manufacturing difficulty and cost for signal input and output.

[0010] Optionally, the material used to make the filling portion may include an inorganic insulating material. The reasons for this arrangement include: in the prior art, the material used to make the filling portion is usually an organic material, while the substrate in the bare chip is mostly an inorganic material, the conductive layer in the bare chip wiring layer is also mostly an inorganic material, and the dielectric layer in the bare chip wiring layer is also mostly an inorganic material. This means that when an organic material is used to fill the gap between the bare chips, it may cause a stress mismatch between the inorganic material and the organic material, resulting in an increased risk of bare chip breakage and reduced reliability of the chip packaging structure. If an inorganic insulating material is used to make the filling portion, the stress of the filling portion and the bare chip is more matched, which can reduce the risk of bare chip breakage, thereby improving the reliability of the chip packaging structure and safety of use. Among them, the inorganic insulating material used to make the filling portion may include, but is not limited to, silicon materials, and the silicon materials may include, but are not limited to, silicon oxide, silicon nitride, etc. The type of inorganic insulating material can be selected according to actual needs and is not specifically limited here.

[0011] Optionally, the carrier board is provided with heat dissipation channels, which can increase the heat dissipation of the chip and improve the heat dissipation capacity of the chip packaging structure, thereby improving the reliability of the chip packaging structure. Multiple heat dissipation channels can be provided, and each heat dissipation channel extends parallel to the large surface of the chip. The heat dissipation channels are spaced apart. This can improve the heat dissipation effect at various locations on the large surface of the chip, making the temperature of the chip more uniform at different locations, avoiding localized excessively high or low temperatures, and thus improving the functionality of the chip. Furthermore, a heat dissipation agent can be provided in the heat dissipation channels to further increase the heat dissipation capacity of the chip packaging structure. The heat dissipation agent can be any substance with heat dissipation function known to those skilled in the art and is not specifically limited here.

[0012] Optionally, the chip packaging structure may further include a semiconductor device, which is disposed on a side of the plastic packaging structure facing away from the interconnect layer. The semiconductor device is connected to the bare die. The semiconductor device can increase the performance of the bare die and expand the functionality of the bare die, thereby improving the performance of the chip packaging structure and expanding its application areas. The semiconductor device can be disposed between the carrier and the plastic packaging structure. In this case, there is no need to process the carrier, and an additional semiconductor device can be added between the carrier and the plastic packaging structure, thereby reducing the difficulty of manufacturing the chip packaging structure. Alternatively, the semiconductor device can be disposed within the carrier, that is, embedded within the carrier. This can reduce the volume of the chip packaging structure and achieve a miniaturized, integrated design of the chip packaging structure. Furthermore, the substrate may also be provided with through-holes, and the semiconductor device is connected to the interconnect layer via the through-holes and connecting wires in the wiring layer to connect the semiconductor device to the outside world.

[0013] Exemplarily, the semiconductor device can be a passive device, such as but not limited to a capacitor or an inductor. When the semiconductor device is a capacitor, the capacitor can store electrical energy, that is, the electrical energy transmitted through the interconnect layer can be stored in the capacitor, so that when the power supply of the bare chip is abnormal, the capacitor can power the bare chip to ensure the normal operation of the bare chip; when the semiconductor device is an inductor, the inductor can convert the voltage transmitted through the interconnect layer, so that the high voltage input through the interconnect layer is converted into a low voltage and then output to the bare chip, ensuring that the bare chip can operate normally. Alternatively, the semiconductor device can also be an active device, such as but not limited to a memory. The memory can provide storage space for the bare chip so that the bare chip can store data in the memory, thereby increasing the storage bandwidth and storage capacity of the chip packaging structure. The specific form of the semiconductor device can be designed according to actual needs and is not specifically limited here.

[0014] In a second aspect, embodiments of the present application further provide a method for manufacturing a chip packaging structure, the method being used to manufacture the chip packaging structure described in the first aspect and any one of the embodiments of the first aspect. The method may include: forming a plastic encapsulation structure on a carrier; wherein the plastic encapsulation structure includes at least two bare chips and a filling portion, the filling portion filling the area between the carrier and the interconnection layer except for the bare chips; the bare chips include: a substrate, and a wiring layer disposed on the substrate, the surface of the wiring layer facing away from the carrier and the surface of the filling portion facing away from the carrier being located in the same plane; forming an interconnection layer on the plastic encapsulation structure; wherein the wiring layer includes a first connection portion, the interconnection layer includes a first routing line, and the first connection portions of two adjacent bare chips are connected by the first routing line. In this way, the first routing line in the interconnection layer can be used to interconnect the bare chips to achieve communication between the bare chips. Furthermore, the bare die's wiring layer is directly connected to the interconnect layer, meaning that the two layers do not need to be connected via solder balls, as in the prior art. Consequently, when setting the routing density within the interconnect layer, there is no need to consider the limitations of solder balls. The routing density can be set to the maximum possible based on practical circumstances, effectively increasing the routing density within the interconnect layer and, consequently, improving the interconnect density of the chip package structure. Furthermore, because the bare die's wiring layer is directly connected to the interconnect layer, without solder balls between them, interference caused by the presence of solder balls is avoided during signal transmission, thereby improving the effectiveness and accuracy of signal transmission.

[0015] Optionally, forming the interconnect layer may include: forming the interconnect layer using a back-end-of-line (BOL) process. That is, dielectric layers and conductive layers are alternately formed on the plastic package structure using a BOL process, and various traces (including the first trace and second trace mentioned above) are formed in the alternating dielectric layers and conductive layers, thereby eliminating the need for TSVs. Compared to using an adapter plate and providing TSVs, this eliminates the need for TSV fabrication, thereby reducing the difficulty and cost of manufacturing the chip package structure.

[0016] It is worth noting that when the interconnection layer is formed on the plastic packaging structure, it can be done through the back-end process, without the need for solder ball welding or through-silicon vias to transmit signals. Therefore, the interconnection layer is formed directly on the plastic packaging structure, so that the interconnection layer and the wiring layer in the bare chip can be directly in contact and connected. This not only improves the interconnection density in the interconnection layer, but also avoids interference with signal transmission caused by solder balls and reduces production costs.

[0017] It should be understood that since the principle of solving the problem of the chip packaging structure produced by this manufacturing method is similar to the principle of solving the problem of the aforementioned chip packaging structure, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned chip packaging structure, and the repeated parts will not be repeated.

[0018] In a third aspect, an embodiment of the present application further provides a method for manufacturing a chip packaging structure, the method being used to manufacture the chip packaging structure described in the first aspect and any one of the embodiments of the first aspect, the method comprising: forming an interconnection layer on a support plate; wherein the interconnection layer comprises a first trace; forming a plastic encapsulation structure on the interconnection layer; wherein the plastic encapsulation structure comprises at least two bare chips and a filling portion, the filling portion filling an area between the carrier plate and the interconnection layer except for the bare chips; the bare chips comprising: a substrate and a wiring layer disposed on the substrate, wherein a surface of the wiring layer facing the interconnection layer and a surface of the filling portion facing the interconnection layer are located in the same plane; the wiring layer comprises a first connection portion, wherein the first connection portions of two adjacent bare chips are connected by a first trace; forming a carrier plate on the plastic encapsulation structure; separating the support plate from the interconnection layer and removing the support plate. In this way, the interconnection layer can be formed first, and then the plastic encapsulation structure can be formed on the interconnection layer. This not only improves the interconnection density in the interconnection layer and prevents interference of solder balls on signal transmission, but also increases the flexibility of chip packaging structure manufacturing to meet the design requirements of different application scenarios.

[0019] It is worth noting that the interconnect layer can also be formed using a back-end process. Furthermore, when the interconnect layer is formed first, a bonding pad can be reserved on the surface of the interconnect layer facing away from the support plate. This allows the connection portions in the bare die wiring layer to connect to the bonding pads on the surface of the interconnect layer when the plastic encapsulation structure is formed above the interconnect layer, thereby enabling interconnection between the dies and the routing of signals between the dies.

[0020] It should be understood that since the principle of solving the problem of the chip packaging structure produced by this manufacturing method is similar to the principle of solving the problem of the aforementioned chip packaging structure, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned chip packaging structure, and the repeated parts will not be repeated.

[0021] In a fourth aspect, an embodiment of the present application further provides an electronic device, which may include: a circuit board, and a chip packaging structure as described in the first aspect and any one of the embodiments of the first aspect; the chip packaging structure is electrically connected to the circuit board.

[0022] It should be understood that since the principle of solving the problem of the chip packaging structure produced by this manufacturing method is similar to the principle of solving the problem of the aforementioned chip packaging structure, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned chip packaging structure, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0024] FIG2 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0025] FIG3 is a schematic diagram of a partial structure of an interconnection layer provided in an embodiment of the present application;

[0026] FIG4 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0027] FIG5 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0028] FIG6 is a schematic diagram of a method for manufacturing a chip packaging structure provided in an embodiment of the present application;

[0029] FIG7 is a schematic diagram of another method for manufacturing a chip packaging structure provided in an embodiment of the present application.

[0030] Figure numerals: 100-circuit board, 200-chip packaging structure, 10-carrier board, 11-heat dissipation channel, 12-heat dissipation agent, 13-semiconductor device, 20-plastic package structure, 21-bare die, 21a-substrate, 21b-wiring layer, 22-filling part, 30-interconnection layer, 31-first dielectric layer, 32-second dielectric layer, 33-conductive layer, 34-second routing, 34a-first section, 34b-second section, 40-solder ball, 50-substrate, 60-bonding layer, m1-first connecting part, m2-second connecting part, n1-first routing, T0-through hole, T1-through silicon via. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0032] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrating relative positional relationships and do not represent true proportions.

[0033] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first explained below.

[0034] The chip packaging structure proposed in the embodiment of the present application can be applied to various electronic devices, for example, it can be applied to electronic devices such as smart phones, smart TVs, smart TV set-top boxes, personal computers (PCs), wearable devices, smart broadband, etc. It should be noted that the chip packaging structure proposed in the embodiment of the present application is intended to include but is not limited to applications in these and any other suitable types of electronic devices. Figure 1 exemplarily shows a structural schematic diagram of an electronic device. As shown in Figure 1, the electronic device may include: a circuit board 200, and a chip packaging structure 100. The chip packaging structure 100 is electrically connected to the circuit board 200. Among them, the circuit board 200 can be a printed circuit board (PCB). Of course, the circuit board 200 can also be other types of circuit boards 200, which are not limited here.

[0035] Typically, the chip package structure 100 integrates multiple dies 21 on the same substrate 50, which can achieve a higher packaging density and a greater interconnection density. For example, solder balls 40 are provided on the surface of the die 21, and the die 21 is flip-chip mounted on the substrate 50, so that the solder balls 40 are connected to the traces on the surface of the substrate 50 to achieve interconnection between the dies 21. Furthermore, through-silicon vias T1 are provided in the substrate 50, and solder balls 40 are also provided on the side of the substrate 50 facing away from the die 21. The through-silicon vias T1 can electrically connect the solder balls 40 on the surface of the die 21 with the solder balls 40 on the surface of the substrate 50, thereby enabling signal input and output. The solder balls 40 on the surface of the substrate 50 are then connected to the circuit board 200, thereby achieving electrical connection between the chip package structure 100 and the circuit board 200.

[0036] However, when the solder balls 40 on the die 21 are larger, the number of traces routed between the two solder balls 40 is smaller, resulting in a low interconnect density that cannot meet the performance requirements of high-end server processing chips. Although the size of the solder balls 40 on the die 21 can be reduced to increase the number of traces routed between the two solder balls 40, the solder balls 40 are still limited, preventing further improvement in interconnect density.

[0037] Based on this, an embodiment of the present application provides a chip packaging structure for improving the interconnection density of the chip packaging structure. The chip packaging structure will be explained and illustrated in conjunction with specific embodiments below.

[0038] FIG2 exemplarily shows a schematic structural diagram of a chip packaging structure provided by the present application. As shown in FIG2 , the chip packaging structure may include: a carrier 10, a plastic encapsulation structure 20, and an interconnection layer 30 stacked in sequence. The plastic encapsulation structure 20 includes at least two bare dies 21 and a filling portion 22. The bare dies 21 are arranged side by side and spaced apart on the surface of the carrier 10. The side-by-side arrangement on the surface of the carrier 10 means that the arrangement direction of the bare dies 21 is parallel to the surface of the carrier 10, so that there is a gap between adjacent bare dies 21. In this case, the filling portion 22 can fill the area between the carrier 10 and the interconnection layer 30 except the bare dies 21, so that the filling portion 22 can wrap all four sides of the bare dies 21. If the surface of the bare die 21 facing the carrier 10 and the surface of the bare die 21 facing the interconnection layer 30 (the surface shown by b1 in FIG3 ) are both referred to as the large surface of the bare die 21, and the surface between the two large surfaces is referred to as the side surface, the filling portion 22 can only wrap the side surface of the bare die 21.

[0039] The die 21 may include a substrate 21a and a wiring layer 21b disposed on the substrate 21a. The wiring layer 21b is disposed between the substrate 21a and the interconnection layer 30. The surface b1 of the wiring layer 21b facing the interconnection layer 30 and the surface b2 of the filling portion 22 facing the interconnection layer 30 are coplanar. The wiring layer 21b includes a first connection portion m1, and the interconnection layer 30 includes a first trace n1. The first connection portions m1 in two adjacent die 21 are connected via the first trace n1. Thus, the first trace n1 in the interconnection layer 30 enables interconnection and communication between the die 21. Furthermore, the wiring layer 21b of the die 21 is directly connected to the interconnection layer 30, meaning that the wiring layer 21b and the interconnection layer 30 do not need to be connected via solder balls as in the prior art. Consequently, when setting the trace density in the interconnection layer 30, there is no need to consider the limitations of solder balls. The trace density can be set to the maximum value according to actual conditions. This effectively increases the trace density in the interconnection layer 30, thereby improving the interconnect density of the chip package structure. In addition, since the wiring layer 21b of the bare chip 21 is directly connected to the interconnection layer 30 and there are no solder balls between the wiring layer 21b and the interconnection layer 30, interference caused by the presence of solder balls can be avoided during signal transmission, thereby improving the effectiveness and accuracy of signal transmission.

[0040] Furthermore, as shown in FIG3 , a solder ball 40 may be provided on the surface of the interconnect layer 30 facing away from the plastic encapsulation structure 20. The wiring layer 21b includes a second connection portion m2. The interconnect layer 30 includes a second trace 34. The second trace 34 connects the solder ball 40 and the second connection portion m2, thereby connecting the second connection portion m2 to the outside world and enabling the input and output of signals. For example, the interconnect layer 30 may include: at least two dielectric layers and at least one conductive layer 33, with the dielectric layers and the conductive layers 33 being arranged alternately. This indicates that the interconnect layer 30 is composed of alternating dielectric layers and conductive layers 33, unlike structures such as silicon substrates, silicon base plates, or silicon adapter plates that are composed of silicon materials. In this case, the second trace 34 may include: a first segment 34a located in each dielectric layer, and a second segment 34b located in each conductive layer 33, with the first segment 34a connected to the second segment 34b.

[0041] Taking the interconnection layer 30 shown in FIG3 as an example, the interconnection layer 30 includes two dielectric layers and a conductive layer 33. The conductive layer 33 is located between the two dielectric layers. If the dielectric layer between the conductive layer 33 and the wiring layer 21b is called the first dielectric layer 31, and the dielectric layer between the conductive layer 33 and the solder ball 40 is called the second dielectric layer 32, the first dielectric layer 31 has a first through hole, and the conductive material filled in the first through hole forms a first segment 34a, and the first segment 34a is connected to the second connecting portion m2; the second dielectric layer 32 has a second through hole, and the conductive material filled in the second through hole forms another first segment 34a, and the first segment 34a is connected to the solder ball 40; the conductive layer 33 has a second segment 34b, and the second segment 34b is respectively connected to the two first segments 34a, so that the second connecting portion m2 and the solder ball 40 are connected in sequence through one of the first segments 34a, the second segment 34b, and the other first segment 34a. Obviously, the second routing 34 is different from the through-silicon via, so when the second connection portion m2 is connected to the solder ball 40 through the interconnection layer 30, there is no need to set a through-silicon via, and the second routing 34 in the interconnection layer 30 can be used. In this way, when implementing the introduction and extraction of signals, not only the manufacturing difficulty can be reduced, but also the manufacturing cost can be reduced.

[0042] Optionally, the filling portion 22 may be made of an inorganic insulating material. The reasons for this arrangement include: in the prior art, the filling portion 22 is typically made of an organic material, while the substrate 21a in the bare die 21 is mostly made of an inorganic material, the conductive layer in the wiring layer 21b of the bare die 21 is also mostly made of an inorganic material, and the dielectric layer in the wiring layer 21b of the bare die 21 is also mostly made of an inorganic material. This means that when an organic material is used to fill the gaps between the bare die 21, there may be a stress mismatch between the inorganic and organic materials, resulting in an increased risk of the bare die 21 breaking and reducing the reliability of the chip packaging structure. If an inorganic insulating material is used to make the filling portion 22, the stress of the filling portion 22 and the bare die 21 is more closely matched, which can reduce the risk of the bare die 21 breaking, thereby improving the reliability and safety of the chip packaging structure. The inorganic insulating material used to make the filling portion 22 may include, but is not limited to, silicon materials, and silicon materials may include, but are not limited to, silicon oxide, silicon nitride, etc. The type of inorganic insulating material can be selected according to actual needs and is not specifically limited here.

[0043] FIG4 exemplarily illustrates a schematic structural diagram of a chip package structure provided by the present application. As shown in FIG4 , the chip package structure in this embodiment is substantially similar to the chip package structure shown in FIG2 and FIG3 in the aforementioned embodiments, with the difference being that a heat dissipation channel 11 is provided in the carrier 10. This heat dissipation channel 11 can increase heat dissipation from the die, improving the heat dissipation capability of the chip package structure and thereby enhancing the reliability of the chip package structure. For example, as shown in FIG4 , multiple heat dissipation channels 11 can be provided, each extending parallel to the die's large surface. Each heat dissipation channel 11 is spaced apart. This improves heat dissipation across the die's large surface, ensuring a more uniform temperature at different locations on the die, avoiding localized overheating and underheating, and thereby enhancing the die's functionality. Furthermore, a heat sink 12 can be provided in the heat sink 11 to further enhance the heat dissipation capability of the chip package structure. The heat sink 12 can be any heat dissipation material known to those skilled in the art and is not specifically limited herein.

[0044] It should be understood that the similarities between the chip packaging structure in this embodiment and the chip packaging structure shown in FIG. 2 and FIG. 3 in the aforementioned embodiments can be found in the relevant introduction in the aforementioned embodiments, and the repeated parts will not be repeated.

[0045] FIG5 exemplarily illustrates a schematic structural diagram of a chip packaging structure provided by the present application. Referring to FIG5 , the chip packaging structure in this embodiment is substantially similar to the chip packaging structure shown in FIG2 and FIG3 in the aforementioned embodiments, with the difference being that a semiconductor device 13 is disposed in the carrier 10. For example, referring to FIG5 , since the semiconductor device 13 is disposed in the carrier 10, the semiconductor device 13 is disposed on a side of the plastic package structure 20 facing away from the interconnection layer 30, and the semiconductor device 13 is connected to the bare die 21. A through-hole T0 is disposed in the substrate 21a of the bare die 21, and the semiconductor device 13 is further connected to the interconnection layer 30 via the through-hole T0 in the substrate 21a and the connecting wire (not shown in FIG5 ) in the wiring layer 21b.

[0046] Among them, the semiconductor device 13 can be a passive device, such as but not limited to a capacitor or an inductor. When the semiconductor device 13 is a capacitor, the capacitor can store electrical energy, that is, the electrical energy transmitted through the interconnect layer 30 can be stored in the capacitor, so that when the power supply of the bare chip 21 is abnormal, the capacitor can power the bare chip 21, ensuring the normal operation of the bare chip 21; when the semiconductor device 13 is an inductor, the inductor can convert the voltage transmitted through the interconnect layer 30, so that the high voltage input through the interconnect layer 30 is converted into a low voltage and then output to the bare chip 21, ensuring the normal operation of the bare chip 21. Alternatively, the semiconductor device 13 can also be an active device, such as but not limited to a memory. The memory can provide storage space for the bare chip 21, so that the bare chip 21 can store data in the memory, thereby increasing the storage bandwidth and storage capacity of the chip packaging structure.

[0047] It should be understood that the similarities between the chip packaging structure in this embodiment and the chip packaging structure shown in FIG. 2 and FIG. 3 in the aforementioned embodiments can be found in the relevant introduction in the aforementioned embodiments, and the repeated parts will not be repeated.

[0048] FIG6 exemplarily shows a schematic diagram of a manufacturing process of a chip packaging structure provided by the present application. As shown in FIG6 , the manufacturing method may include:

[0049] Step 1: As shown in FIG6 (a), the front side (ie, the surface shown by b1) of each die 21 is temporarily bonded to a support plate, with a gap between adjacent die 21, which can be, but is not limited to, set to no more than 100 μm.

[0050] Among them, the temporary bonding can be released, so that the bare chip 21 can be separated from the support plate. Exemplarily, a high molecular polymer or silicone material can be used as an adhesive to achieve temporary bonding between the bare chip 21 and the support plate. It should be understood that the back of the bare chip 21 can be regarded as the side surface of the substrate of the bare chip 21 away from the wiring layer (such as the surface shown by b3), and the front of the bare chip 21 can be regarded as the side surface of the wiring layer away from the substrate (i.e., the surface shown by b1). The material of the support plate can include: any one of silicon, glass, and metal.

[0051] Step 2. As shown in (a) of Figure 6, since the front side of the bare chip 21 is bonded to the support plate, the back side of the bare chip 21 (the surface shown as b3) is exposed. At this time, mechanical grinding, chemical mechanical planarization, wet etching or dry etching can be used to thin the back side of the bare chip 21 so that the thickness of the bare chip 21 is reduced to less than 20μm.

[0052] Step 3, as shown in (b) of Figure 6, a process such as plasma enhanced chemical deposition or atomic layer vapor deposition is used, but not limited to, and silicon oxide is used to deposit silicon oxide on the surface of the exposed support plate so that the silicon oxide fills the gaps between the bare chips 21. At this time, the deposited silicon oxide serves as the filling part 22, and the filling part 22 and the bare chip 21 constitute a plastic package structure 20.

[0053] Step 4, as shown in FIG6 (b), the plastic package structure 20 is permanently bonded to the carrier by, but not limited to, thermal oxygen bonding, metal-metal bonding, metal-dielectric hybrid bonding, etc., and the back side of the bare die 21 is permanently bonded to the carrier.

[0054] For example, in step 4, other substances such as silicon oxide, metal or organic matter may be used as adhesive to achieve permanent bonding between the die 21 and the carrier, and a bonding layer 60 is provided between the carrier and the plastic package structure 20 .

[0055] Step 5, as shown in (c) of Figure 6, temporary bonding and debonding processes, wet etching, dry etching and other processes are used to remove the support plate to expose the front side of the bare chip 21; at this time, a plastic encapsulation structure 20 is formed on the carrier, and the surface of the wiring layer facing away from the carrier and the surface of the filling portion 22 facing away from the carrier are located in the same plane.

[0056] Step 6, as shown in (c) of Figure 6, a back-end process is used to form an interconnection layer 30 on the plastic package structure 20. The interconnection layer 30 includes a first trace and a second trace. The first trace can connect the first connection portion in two adjacent bare chips 21, and the second trace can connect the second connection portion in the bare chip 21 and the solder ball on the side of the interconnection layer 30 away from the bare chip 21.

[0057] Among them, the first routing line and the second routing line can be made of, but not limited to, at least one metal such as copper, aluminum, or nickel, and can be made of, but not limited to, a Damascus electroplating process. The dielectric layer in the interconnection layer 30 can be made of, but not limited to, materials such as silicon oxide or silicon nitride. It is worth noting that since the wiring layer is directly connected to the interconnection layer 30, there is no need to set solder balls on the surface of the wiring layer, so the line width of the routing line in the interconnection layer 30 can be set to, but not limited to, 0.4 μm, and the line width of adjacent routing lines can be set to, but not limited to, 0.4 μm, thereby effectively increasing the routing density in the interconnection layer 30. In order to avoid over-complication of the drawings, the first routing line, the second routing line, the first connecting portion, and the second connecting portion are not shown in (c) of Figure 6.

[0058] 3 , the specific process of forming the interconnection layer 30 using the back-end process may include: first depositing a first dielectric layer 31 on the surface of the plastic package structure; etching the first dielectric layer 31 to form a through hole penetrating the first dielectric layer 31 (not shown in FIG3 ); depositing a conductive layer 33 on the surface of the first dielectric layer 31 with the through hole formed therein, and depositing material of the conductive layer 33 to fill the through hole to form a first segment 34 a located in the first dielectric layer 31; patterning the conductive layer 33 to form a second segment 34 b, which is connected to the first segment 34 a located in the first dielectric layer 31; continuing deposition to form a second dielectric layer 32; etching the second dielectric layer 32 to form a through hole penetrating the second dielectric layer 32 (not shown in FIG3 ); filling the through hole in the second dielectric layer 32 to form a first segment 34 a located in the second dielectric layer 32, which is connected to the second segment 34 b located in the second dielectric layer 32, thereby obtaining the interconnection layer 30 and the second trace 34. Thus, the structure of the interconnection layer 30 is different from the silicon substrate in the prior art, and the second trace 34 is also different from the through silicon via in the prior art. Therefore, by providing the interconnection layer 30, the through silicon via can be avoided, thereby reducing the manufacturing cost of the chip packaging structure.

[0059] Step 7, as shown in (c) of FIG6 , solder balls 40 are formed on the interconnect layer 30 . The diameter of the solder balls 40 may be, but not limited to, 10 μm to 85 μm, and the pitch of the solder balls 40 may be, but not limited to, 15 μm to 200 μm.

[0060] The interconnect layer 30 can be connected to other structures (such as but not limited to the substrate) through the solder balls 40, thereby realizing the input and output of signals. The solder balls 40 can be, but are not limited to, micro bumps, C4 bumps, or copper pillars, and can be configured according to actual conditions and are not specifically limited here.

[0061] It is worth noting that, in this manufacturing method, the die 21 is first bonded to the carrier, and then the interconnection layer 30 is formed on the front surface of the die 21 .

[0062] In this way, the first traces in the interconnection layer 30 can be used to interconnect the dies 21, thereby enabling communication between the dies 21. Furthermore, the wiring layer of the die 21 is directly connected to the interconnection layer 30, meaning that the wiring layer and the interconnection layer 30 do not need to be connected via solder balls as in the prior art. Consequently, when setting the trace density in the interconnection layer 30, there is no need to consider the limitations of solder balls. The trace density can be set to the maximum value based on actual conditions, effectively increasing the trace density in the interconnection layer 30 and thereby improving the interconnection density of the chip packaging structure.

[0063] FIG7 exemplarily shows a schematic diagram of a manufacturing process of a chip packaging structure provided by the present application. Referring to FIG7 , the manufacturing process of the chip packaging structure in this embodiment is substantially similar to the manufacturing process shown in FIG6 of the aforementioned embodiment, with the difference being that the interconnection layer 30 is formed first and then connected to the die 21. Exemplarily, as shown in FIG7 , the manufacturing method may include:

[0064] Step 1. As shown in (a) of Figure 7 , an interconnection layer 30 is formed on a support plate using a back-end process, and connection pads (i.e., bonding pads, not shown in Figure 7 ) are reserved on the surface of the interconnection layer 30 ; wherein the bonding pads may be, but are not limited to, circular, square, polygonal, or other shapes, the size of the bonding pads may be, but are not limited to, set to 1 μm to 20 μm, and the gaps between the bonding pads may be, but are not limited to, set to 2 μm to 80 μm.

[0065] Step 2, as shown in (a) of Figure 7, adopt but not limited to a metal-dielectric layer bonding process to connect the front side of each die 21 to the interconnection layer 30, wherein the connection portion on the front side of the die 21 (not shown in Figure 7) needs to be connected to the bonding pad on the surface of the interconnection layer 30.

[0066] Step 3, as shown in (b) of FIG7 , the back side of the die 21 (the surface shown as b3 ) is thinned by using processes such as mechanical grinding, chemical mechanical planarization, wet etching or dry etching.

[0067] Step 4, as shown in (b) of Figure 7, using but not limited to plasma enhanced chemical deposition or atomic layer vapor deposition processes, using but not limited to silicon oxide, silicon oxide is deposited on the exposed support plate surface to form a filling portion 22, thereby forming a plastic package structure 20.

[0068] Step 5, as shown in FIG7 (b), the plastic package structure 20 is permanently bonded to the carrier by methods such as but not limited to thermal oxygen bonding, metal-metal bonding, and metal-dielectric hybrid bonding, and the back side of the bare die 21 is permanently bonded to the carrier.

[0069] Step 6: As shown in FIG. 7 ( c ), a wet etching process, a dry etching process, or the like is used to remove the support plate and expose the interconnection layer 30 .

[0070] Step 7: As shown in FIG. 7 ( c ), solder balls 40 are formed on the interconnection layer 30 .

[0071] It should be understood that the similarities between the manufacturing method in this embodiment and the manufacturing method shown in FIG6 of the aforementioned embodiment can be found in the relevant introduction of the aforementioned embodiment, and the repeated parts will not be repeated.

[0072] In the above-mentioned Figures 2 to 5, the wiring within the interconnect layer 30 is only shown for illustrative purposes to illustrate that wiring is provided within the interconnect layer 30. However, this does not represent the actual arrangement of the wiring within the interconnect layer 30. In order to avoid overly complex drawings, the wiring within the interconnect layer 30 is not shown in Figures 6 and 7.

[0073] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A chip packaging structure, characterized in that: include: A carrier board, a plastic package structure, and an interconnection layer stacked in sequence, wherein the plastic package structure includes at least two bare dies and a filling portion, wherein the filling portion fills an area between the carrier board and the interconnection layer except for the bare dies; The bare chip includes: a substrate, and a wiring layer provided on the substrate, wherein the wiring layer is provided between the substrate and the interconnection layer, and a surface of the wiring layer facing the interconnection layer and a surface of the filling portion facing the interconnection layer are located in the same plane; The wiring layer includes a first connection portion, the interconnection layer includes a first routing line, and the first connection portions in two adjacent dies are connected through the first routing line.

2. The chip packaging structure according to claim 1, wherein: A solder ball is provided on a surface of the interconnection layer facing away from the plastic package structure, the wiring layer includes a second connection portion, and the interconnection layer includes a second trace, and the second trace connects the solder ball and the second connection portion; The interconnection layer comprises: at least two dielectric layers and at least one conductive layer, wherein the dielectric layers and the conductive layers are alternately arranged; The second trace includes: a first segment located in each of the dielectric layers, and a second segment located in each of the conductive layers, wherein the first segment is connected to the second segment.

3. The chip packaging structure according to claim 1 or 2, wherein: The filling portion is made of an inorganic insulating material.

4. The chip packaging structure according to any one of claims 1 to 3, wherein: The carrier board is provided with a heat dissipation channel.

5. The chip packaging structure according to claim 4, wherein: A heat dissipation agent is provided in the heat dissipation channel.

6. The chip packaging structure according to any one of claims 1 to 5, wherein: The chip packaging structure further includes a semiconductor device, which is arranged on a side of the plastic packaging structure away from the interconnection layer, and is connected to the bare chip.

7. The chip packaging structure according to claim 6, wherein: The substrate is provided with a through hole, and the semiconductor device is connected to the interconnection layer through the through hole and the connection line in the wiring layer.

8. The chip packaging structure according to claim 6 or 7, wherein: The semiconductor device is arranged in the carrier.

9. A method for manufacturing a chip packaging structure, characterized in that: include: A plastic encapsulation structure is formed on a carrier board; wherein the plastic encapsulation structure includes at least two bare dies and a filling portion, wherein the filling portion fills an area between the carrier board and the interconnect layer except for the bare dies; the bare dies include: a substrate and a wiring layer provided on the substrate, wherein a surface of the wiring layer facing away from the carrier board and a surface of the filling portion facing away from the carrier board are located in the same plane; An interconnection layer is formed on the plastic package structure; wherein the wiring layer includes a first connection portion, the interconnection layer includes a first trace, and the first connection portions in two adjacent dies are connected via the first trace.

10. A method for manufacturing a chip packaging structure, characterized in that: include: forming an interconnection layer on the support plate; wherein the interconnection layer includes a first trace; A plastic encapsulation structure is formed on the interconnection layer; wherein the plastic encapsulation structure includes at least two bare chips and a filling portion, wherein the filling portion fills the area between the carrier and the interconnection layer except the bare chips; the bare chips include: a substrate, and a wiring layer provided on the substrate, wherein a surface of the wiring layer facing the interconnection layer and a surface of the filling portion facing the interconnection layer are located in the same plane; the wiring layer includes a first connecting portion, wherein the first connecting portions of two adjacent bare chips are connected by the first trace; forming a carrier board on the plastic packaging structure; The support plate is separated from the interconnection layer and the support plate is removed.

11. The method according to claim 9 or 10, wherein: Forming the interconnection layer includes: forming the interconnection layer using a back-end process.

12. An electronic device, characterized in that: include: A circuit board, and a chip packaging structure according to any one of claims 1 to 8; The chip packaging structure is electrically connected to the circuit board.

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