Display substrate and display apparatus

Abstract

Provided in the present disclosure are a display substrate and a display apparatus. The display substrate comprises a display region and a peripheral region located on the periphery of the display region. The display substrate further comprises: a first signal transmission layer, a flexible circuit board, a control circuit board and at least two driving chips. The first signal transmission layer comprises a portion located in the display region and a portion located in the peripheral region; the at least two driving chips are arranged in a first binding region in the peripheral region; the flexible circuit board is arranged in a second binding region in the peripheral region; each driving chip is coupled to the flexible circuit board, and each driving chip is directly coupled to the first signal transmission layer, or each driving chip is indirectly coupled to the first signal transmission layer via the flexible circuit board and the control circuit board; the flexible circuit board is coupled to the control circuit board; by means of the flexible circuit board, the control circuit board is used for controlling each driving chip to transmit to the first signal transmission layer a first signal.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410120692.7 filed in China on January 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and people's requirements for display quality are correspondingly becoming higher and higher. To further improve the display quality of display products, the complexity of display products has also increased. Taking organic light-emitting diode display products as an example, the sub-pixel driving circuits they use require the input of multiple signals, and the stability of each signal directly affects the display quality of the display product. Therefore, how to improve the stability of the signals input into display products has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] An object of the present disclosure is to provide a display substrate and a display device.

[0006] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0007] A first aspect of the present disclosure provides a display substrate.

[0008] The display substrate includes: a display area and a peripheral area located around the display area, the peripheral area includes a first binding area and a second binding area, the first binding area is located between the display area and the second binding area, and the display substrate further includes:

[0009] a first signal transmission layer, the first signal transmission layer including a portion located in the display area and a portion located in the peripheral area;

[0010] a flexible circuit board, wherein the flexible circuit board is arranged in the second binding area;

[0011] a control circuit board coupled to the flexible circuit board;

[0012] a plurality of driver chips, the plurality of driver chips being disposed in the first binding area, each of the driver chips being coupled to the flexible circuit board, and each of the driver chips being directly coupled to the first signal transmission layer, or each of the driver chips being indirectly coupled to the first signal transmission layer via the flexible circuit board and the control circuit board;

[0013] The control circuit board is used to control each of the driving chips to transmit a first signal to the first signal transmission layer through the flexible circuit board.

[0014] Optionally, the driver chip includes at least one first output pin; the control circuit board includes a signal connection line;

[0015] The flexible circuit board includes at least two first terminals and at least two second terminals, the at least two first terminals are bound to the second binding area, and the at least two second terminals are bound to the control circuit board;

[0016] The at least two first terminals include a target first terminal and a non-target first terminal;

[0017] The target first terminal is coupled to the corresponding first output pin, and the target first terminal is also coupled to the corresponding second terminal to form a first transmission path from the target first terminal to the second terminal;

[0018] The non-target first terminal is coupled to the first signal transmission layer, and the non-target first terminal is also coupled to the corresponding second terminal to form a second transmission path from the second terminal to the non-target first terminal;

[0019] The at least two second terminals are respectively coupled to the signal connection lines.

[0020] Optionally, the driver chip includes at least two first output pins;

[0021] The flexible circuit board includes a plurality of first terminals and a plurality of second terminals, and the plurality of first terminals and the plurality of second terminals are divided into at least two terminal connection groups, each terminal connection group includes one first transmission path and one second transmission path, and each of the target first terminals in the at least two terminal connection groups is coupled one-to-one with the at least two first output pins.

[0022] Optionally, the driver chip includes at least one second output pin, and the second output pin is directly coupled to the first signal transmission layer and is used to transmit the first signal to the first signal transmission layer.

[0023] Optionally, the first output pin is coupled to the corresponding second output pin.

[0024] Optionally, the driver chip further includes at least one connecting pin, and the first output pin is coupled to the corresponding second output pin through the corresponding connecting pin.

[0025] Optionally, in at least one driver chip, the first output pins included in the driver chip are coupled, and / or the second output pins included in the driver chip are coupled, and / or the connection pins included in the driver chip are coupled.

[0026] Optionally, the at least two driver chips include a main driver chip and at least one auxiliary driver chip;

[0027] The display substrate further includes at least one protection module, which is connected in series between the first transmission path corresponding to the auxiliary driving chip and the signal connection line, and is used to achieve unidirectional conduction from the first transmission path to the signal connection line.

[0028] Optionally, the protection module includes a diode, an anode of the diode is coupled to the second terminal in the first transmission path, and a cathode of the diode is coupled to the signal connection line.

[0029] Optionally, the first signal transmission layer includes a first signal bus and a plurality of first signal branch lines, the first signal bus is located in the peripheral area, the first signal branch lines include at least a portion located in the display area, and the first signal branch lines are coupled to the first signal bus;

[0030] The first output pin is coupled to the first signal bus; and / or the second output pin is coupled to the first signal bus.

[0031] Optionally, the display substrate also includes a plurality of sub-pixels located in the display area, and the sub-pixels include a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit includes a second reset transistor, the first electrode of the second reset transistor is coupled to the first signal transmission layer, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element.

[0032] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0034] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0035] FIG2 is a schematic diagram of a frequency conversion timing of a pixel structure in a display substrate provided by an embodiment of the present disclosure;

[0036] FIG3 is a schematic diagram of a three-part screen display substrate in the related art;

[0037] FIG4 is a schematic diagram of a first structure of a display substrate provided in an embodiment of the present disclosure;

[0038] FIG5 is a second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0039] FIG6 is a third structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0040] FIG7 is a fourth structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0041] FIG8 is a schematic diagram of pin connections of a driver chip according to an embodiment of the present disclosure;

[0042] FIG9 is a schematic cross-sectional connection diagram of a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0044] As shown in Figures 1 and 2, Figure 1 shows a circuit structure diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure; Figure 2 is a frequency conversion timing diagram of a pixel structure in a display substrate provided by an embodiment of the present disclosure.

[0045] The sub-pixel driving circuit adopts an 8T1C (i.e., including 8 transistors and 1 capacitor) circuit structure, specifically including: a driving transistor T3, a first reset transistor T1, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emitting control transistor T6, a second reset transistor T7, a third reset transistor T8 and a storage capacitor Cst.

[0046] The display substrate further includes a first initialization signal line Vinit1, a reference signal line Vref, a power line VDD, a data line Data, a first reset signal line Preset1, a second reset signal line Preset2, a light emitting control signal line EM, a first scan line Ngate, and a second scan line Pgate.

[0047] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Preset1, the first electrode of the first reset transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3 (i.e., the third node N3).

[0048] The gate of the compensation transistor T2 is coupled to the corresponding first scan line Ngate, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3 (ie, the first node N1).

[0049] The gate of the data writing transistor T4 is coupled to the corresponding second scan line Pgate, the first electrode of the data writing transistor T4 is coupled to the corresponding data line Data, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 (i.e., the second node N2).

[0050] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0051] The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control signal line EM, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the light emitting element.

[0052] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Preset2, the first electrode of the second reset transistor T7 is coupled to the second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is coupled to the anode of the light emitting element (ie, the fourth node N4).

[0053] A gate of the third reset transistor T8 is coupled to the corresponding second reset signal line Preset2 , a first electrode of the third reset transistor T8 is coupled to the reference signal line Vref, and a second electrode of the third reset transistor T8 is coupled to the first electrode of the driving transistor T3 .

[0054] The first plate of the storage capacitor Cst is coupled to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is coupled to the power line VDD. Exemplarily, the gate of the driving transistor T3 is reused as the first plate of the storage capacitor Cst.

[0055] For example, assuming that the basic refresh rate is 120 Hz, a refresh rate of 40 Hz can be achieved through the Frame Skip method as shown in FIG2 ; and similarly, display effects of different refresh rates can be achieved by changing the number of maintained frames.

[0056] It should be noted that in order to meet the driving requirements of the driver chip, the display substrate is designed to include a Normal area and a Blank area, which are arranged in a scanning order, with the Normal area in front and the Blank area in the back. The Normal area corresponds to the actual display area of ​​the display substrate and can display the picture. The Blank area refers to a timing concept, corresponding to the non-display time, which can be used to prepare and transmit picture data without actual picture display. The Blank area can be distributed between the last row of pixels in the display area writing the data of the previous frame of the picture to the first row of pixels writing the data of the next frame of the picture.

[0057] As shown in Figure 2, EM off (i.e., EM is at a high level) / Preset2 on (i.e., Preset2 is at a low level) is used as a pulse. When all three pulses are in the Normal area, the second initialization signal is written with the loading value Lx; when the first pulse enters the Blank area and the next two pulses are in the Normal area, the second initialization signal is written with the loading value Ly; when Preset2 is on, the N4 node is charged, and the voltage of the second initialization signal is pulled up. Since the overall load is relatively small after the first pulse enters the Blank area, the amplitude of the second initialization signal being pulled up is relatively small, and the potential of the N4 node is relatively low, and the corresponding pixel is relatively dark, forming a dark stripe 90 as shown in Figure 3. It should be noted that Figure 3 schematically shows the display area 10 and the peripheral area 20 included in the display product. The lower frame area included in the peripheral area 20 (located below the display area 10 in Figure 3) is the binding side of the display product.

[0058] More specifically, in large-size display products, a row of pixels contains approximately 3,000 pixel units, each of which includes RGB (red, green, and blue) sub-pixels. Therefore, a row of sub-pixels contains approximately 9,000 sub-pixels. When one row of GOA drives two rows of sub-pixels, and all three pulses are in the Normal region, the second initialization signal simultaneously drives 3*2*9,000 sub-pixels. When the first pulse enters the Blank region and the next two pulses are in the Normal region, the second initialization signal simultaneously drives 2*2*9,000 sub-pixels, a difference of 18,000 pixels. This results in a significant three-screen split, as shown in Figure 3. It should be noted that the number of split screens is related to the number of pulses, and the above description uses a three-screen split as an example.

[0059] From the above analysis, it can be seen that due to the difference in writing loading of the second initialization signal, the display product will cause a split-screen problem. By enhancing the fast recovery capability of the second initialization signal by design, the picture quality can be effectively improved and the split-screen problem can be overcome.

[0060] Referring to Figures 4 to 9, an embodiment of the present disclosure provides a display substrate, comprising: a display area 10 and a peripheral area 20 located around the display area 10, wherein the peripheral area includes a first binding area and a second binding area, wherein the first binding area is located between the display area and the second binding area. The display substrate further comprises: a first signal transmission layer 30, a flexible circuit board 40, a control circuit board 50, and a plurality of driver ICs.

[0061] The first signal transmission layer 30 includes a portion located in the display area 10 and a portion located in the peripheral area 20;

[0062] The flexible circuit board 40 is arranged in the second binding area;

[0063] The control circuit board 50 is coupled to the flexible circuit board 40;

[0064] The plurality of driver chip ICs are disposed in the first binding area, each of the driver chip ICs is coupled to the flexible circuit board 40, and each of the driver chip ICs is directly coupled to the first signal transmission layer 30, or each of the driver chip ICs is indirectly coupled to the first signal transmission layer 30 through the flexible circuit board 40 and the control circuit board 50;

[0065] The control circuit board 50 is used to control each of the driving chips IC to transmit a first signal to the first signal transmission layer 30 through the flexible circuit board 40 .

[0066] Exemplarily, the display substrate includes a display area 10 and a peripheral area 20, wherein the peripheral area 20 surrounds the display area 10, but is not limited thereto. The lower frame area of ​​the peripheral area 20 includes the first binding area and the second binding area.

[0067] Exemplarily, the flexible circuit board 40 is bound to the second binding area in a binding manner; and the plurality of driver chips ICs are bound to the first binding area in a binding manner.

[0068] Exemplarily, the first signal transmission layer 30 includes a portion located in the display area 10 and a portion located in the peripheral area 20; the first signal transmission layer 30 may extend from the display area 10 to the peripheral area 20. Each of the driver ICs may be coupled to the portion of the first signal transmission layer 30 located in the peripheral area 20 to provide a first signal to the first signal transmission layer 30. Exemplarily, the first signal includes an initialization signal, but is not limited thereto.

[0069] Exemplarily, the flexible circuit board 40 is connected between the control circuit board 50 and the driver chip IC. The control circuit board 50 is used to control each driver chip IC to transmit the first signal to the first signal transmission layer 30 through the flexible circuit board 40 .

[0070] According to the specific structure of the display substrate described above, the display substrate provided by the embodiment of the present disclosure includes at least two driver chip ICs disposed in the peripheral region 20. Each driver chip IC is coupled to the first signal transmission layer 30 and the flexible circuit board 40, respectively. The flexible circuit board 40 is coupled to the control circuit board 50, and the control circuit board 50 is used to control each driver chip IC to transmit a first signal to the first signal transmission layer 30 via the flexible circuit board 40. This arrangement enables the control circuit board 50 to control the at least two driver chip ICs, via the flexible circuit board 40, to jointly provide the first signal to the first signal transmission layer 30. This allows the first signals output by the at least two driver chip ICs to jointly drive all pixels in the display substrate, thereby effectively improving the stability of the first signal and reducing first signal drop.

[0071] Therefore, in the display substrate provided by the embodiment of the present disclosure, the stability of the first signal is improved, thereby enhancing the ability of the first signal to quickly recover, thereby effectively improving the image quality and overcoming the split-screen problem.

[0072] As shown in FIG7 and FIG8 , in some embodiments, the driver chip IC includes at least one first output pin 61 ; the control circuit board 50 includes a signal connection line 501 ;

[0073] The flexible circuit board 40 includes at least two first terminals 401 and at least two second terminals 402 , wherein the at least two first terminals 401 are bound to the second binding area, and the at least two second terminals 402 are bound to the control circuit board 50 ;

[0074] The at least two first terminals 401 include a target first terminal 4011 and a non-target first terminal 4012;

[0075] The target first terminal 4011 is coupled to the corresponding first output pin 61 , and the target first terminal 4011 is also coupled to the corresponding second terminal 402 , forming a first transmission path 71 from the target first terminal 4011 to the second terminal 402 ;

[0076] The non-target first terminal 4012 is coupled to the first signal transmission layer 30 , and the non-target first terminal 4012 is also coupled to the corresponding second terminal 402 , forming a second transmission path 72 from the second terminal 402 to the non-target first terminal 4012 ;

[0077] The at least two second terminals 402 are respectively coupled to the signal connection lines 501 .

[0078] Illustratively, among the at least two first terminals 401 , a portion of the first terminals serve as target first terminals 4011 , and another portion of the first terminals serve as non-target first terminals 4012 .

[0079] Exemplarily, the target first terminal is respectively coupled to the corresponding first output pin 61 and the corresponding second terminal 402, and the first signal output by the first output pin 61 is transmitted to the target first terminal, and then transmitted to the second terminal 402 via the first transmission path 71 from the target first terminal to the second terminal 402, and then transmitted from the second terminal 402 to the signal connection line 501; the signal connection line 501 transmits the first signal to the non-target first terminal via the second transmission path 72, and then the non-target first terminal transmits the first signal to the first signal transmission layer 30.

[0080] Exemplarily, the flexible circuit board 40 includes a plurality of circuit board units, each corresponding one to the driver chip IC. When the driver chip IC includes one first output pin 61, the circuit board unit includes two first terminals and two second terminals 402, wherein the two first terminals include one target first terminal and one non-target first terminal. When the driver chip IC includes two first output pins 61, the circuit board unit includes four first terminals and four second terminals 402, wherein the four first terminals include two target first terminals and two non-target first terminals, and so on.

[0081] Illustratively, the signal connection line 501 is respectively coupled to all the second terminals 402 included in each of the circuit board units.

[0082] Exemplarily, the control circuit board 50 further includes a control circuit, and the control circuit can be electrically connected to each of the driver chips IC through the flexible circuit board 40 , thereby controlling the working state of each of the driver chips IC.

[0083] This arrangement enables the first signal output by the first output pin 61 of the driver chip IC to be transmitted sequentially through the first transmission path 71, the signal connection line 501, and the second transmission path 72 to the first signal transmission layer 30, thereby achieving indirect coupling between the first output pin 61 and the first signal transmission layer 30. This arrangement enables at least two driver chip ICs to jointly provide the first signal to the first signal transmission layer 30 via the indirect coupling transmission path, thereby effectively improving the stability of the first signal.

[0084] As shown in Figures 4 and 7, in some embodiments, the driver chip IC includes at least two first output pins 61; the flexible circuit board 40 includes multiple first terminals 401 and multiple second terminals 402, and the multiple first terminals 401 and the multiple second terminals 402 are divided into at least two groups of terminal connection groups A, each group of terminal connection groups A includes one first transmission path 71 and one second transmission path 72, and each of the target first terminals 4011 in the at least two groups of terminal connection groups A is coupled one-to-one with the at least two first output pins 61.

[0085] Exemplarily, the driver chip IC includes two first output pins 61, and the circuit board unit includes four first terminals and four second terminals 402, wherein the four first terminals include two target first terminals and two non-target first terminals. The four first terminals and the four second terminals 402 are divided into two terminal connection groups A, each terminal connection group A including one first transmission path 71 and one second transmission path 72.

[0086] Exemplarily, the first signal output by the first output pin 61 is transmitted to the first transmission path 71 in the corresponding terminal connection group A, then transmitted by the first transmission path 71 to the signal connection line 501, then transmitted by the signal connection line 501 to the second transmission path 72 in the corresponding terminal connection group A, and finally transmitted by the second transmission path 72 to the first signal transmission layer 30.

[0087] The above configuration enables each driver chip IC to provide the first signal to the first signal transmission layer 30 through at least two indirectly coupled transmission paths, thereby effectively improving the stability of the first signal.

[0088] As shown in FIG. 7 and FIG. 8 , in some embodiments, the driver chip IC includes at least one second output pin 62 , which is directly coupled to the first signal transmission layer 30 for transmitting the first signal to the first signal transmission layer 30 .

[0089] For example, the control circuit on the control circuit board 50 can control the second output pin 62 of each driver chip IC to output the first signal through the flexible circuit board 40. The control circuit on the control circuit board 50 can also control the first output pin 61 of each driver chip IC to output the first signal through the flexible circuit board 40.

[0090] Exemplarily, the first signal outputted by the second output pin 62 of the driver chip IC is directly transmitted to the first signal transmission layer 30 .

[0091] The above configuration enables at least two driver chips IC to jointly provide the first signal to the first signal transmission layer 30 through the above directly coupled transmission path, thereby effectively improving the stability of the first signal.

[0092] In the display substrate provided in the above embodiments, the first signal is provided to the first signal transmission layer 30 through multiple paths of multiple chips (indirectly coupled transmission paths, directly coupled transmission paths). By externally injecting the first signal for verification, the above method can effectively improve the stability of the first signal.

[0093] As shown in FIG. 7 and FIG. 8 , in some embodiments, the first output pin 61 is coupled to the corresponding second output pin 62 .

[0094] The above configuration is not only conducive to further improving the stability of the first signal output by the first output pin 61 and the second output pin 62 , but also conducive to simplifying the internal complexity of the driver chip IC.

[0095] As shown in FIG. 7 and FIG. 8 , in some embodiments, the driver chip IC further includes at least one connecting pin 63 , and the first output pin 61 is coupled to the corresponding second output pin 62 through the corresponding connecting pin 63 .

[0096] In at least one driver chip IC, the first output pins 61 included in the driver chip IC are coupled to each other, and / or the second output pins 62 included in the driver chip IC are coupled to each other, and / or the connection pins 63 included in the driver chip IC are coupled to each other.

[0097] The above configuration further improves the stability of the first signal in the peripheral area 20 .

[0098] As shown in Figures 5 and 6, in some embodiments, the at least two driver chips IC include a main driver chip IC1 and at least one auxiliary driver chip IC2; the display substrate also includes at least one protection module 80, and the protection module 80 is connected in series between the first transmission path 71 corresponding to the auxiliary driver chip IC2 and the signal connection line 501, for realizing unidirectional conduction from the first transmission path 71 to the signal connection line 501.

[0099] Exemplarily, the protection module 80 includes a diode, an anode of the diode is coupled to the second terminal 402 in the first transmission path 71 , and a cathode of the diode is coupled to the signal connection line 501 .

[0100] Exemplarily, one protection module 80 is connected in series between each first transmission path 71 and the signal connection line 501 in each auxiliary driver chip IC2 .

[0101] Exemplarily, the main driver chip IC1 and the auxiliary driver chip IC2 synchronously output the first signal.

[0102] In the display substrate provided by the above embodiment, the protection module 80 is set in series between the first transmission path 71 corresponding to the auxiliary driver chip IC2 and the signal connection line 501, so that the auxiliary driver chip IC2 can only transmit the first signal to the signal connection line 501 through the first transmission path 71, and no reverse transmission will occur, thereby avoiding the signal backflow problem caused by the delay in the output time of each driver chip IC or the difference in voltage.

[0103] As shown in FIG4 to FIG7 , in some embodiments, the first signal transmission layer 30 includes a first signal bus 301 and a plurality of first signal branches 302 , wherein the first signal bus 301 is located in the peripheral area 20 , and the first signal branches 302 include at least a portion located in the display area 10 , and the first signal branches 302 are coupled to the first signal bus 301 ;

[0104] The first output pin 61 is coupled to the first signal bus 301 ; and / or the second output pin 62 is coupled to the first signal bus 301 .

[0105] Exemplarily, the multiple sub-pixels are distributed in an array, and the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. The multiple rows of sub-pixels are arranged along a first direction, and each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and the first direction intersects with the second direction.

[0106] Exemplarily, the multiple first signal branches 302 are arranged along the first direction, the first signal branch 302 includes at least a portion extending along the second direction, and the first signal branch 302 is respectively coupled to each sub-pixel in a corresponding row of sub-pixels for providing the first signal to the sub-pixel driving circuit in the sub-pixel to which it is coupled.

[0107] Exemplarily, the multiple first signal branches 302 are arranged along the second direction, and the first signal branch 302 includes at least a portion extending along the first direction. The first signal branch 302 is respectively coupled to each sub-pixel in a corresponding column of sub-pixels, and is used to provide the first signal to the sub-pixel driving circuit in the sub-pixel to which it is coupled.

[0108] Exemplarily, the first signal branch lines 302 can extend from the display area 10 to the peripheral area 20 , the first signal bus 301 surrounds the display area 10 , and the first signal bus 301 is coupled to each of the first signal branch lines 302 .

[0109] In the display substrate provided in the above embodiment, the first output pin 61 is coupled to the first signal bus 301; and / or the second output pin 62 is coupled to the first signal bus 301, so that the first output pin 61 and / or the second output pin 62 can transmit the first signal to the first signal branch 302 through the first signal bus 301, and then transmit it to the sub-pixel.

[0110] As shown in Figures 1 and 4, in some embodiments, the display substrate also includes a plurality of sub-pixels located in the display area 10, and the sub-pixels include a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit includes a second reset transistor T7, and the first electrode T7-1 of the second reset transistor T7 is coupled to the first signal transmission layer 30, and the second electrode T7-2 of the second reset transistor T7 is coupled to the anode of the light-emitting element.

[0111] It should be noted that the first signal transmission layer 30 includes a first signal bus 301 and a plurality of first signal branches 302. The first signal branches 302 include a second initialization signal line Vinit2. It should be noted that FIG4 to FIG6 illustrate the coupling of the sub-pixel P to the first signal branch 302.

[0112] Exemplarily, the structure of the sub-pixel driving circuit is diverse, as shown in Figure 1, for example: the sub-pixel driving circuit adopts an 8T1C (i.e., including 8 transistors and 1 capacitor) circuit structure, specifically including: a driving transistor T3, a first reset transistor T1, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emitting control transistor T6, a second reset transistor T7, a third reset transistor T8 and a storage capacitor Cst.

[0113] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Preset2, and the first electrode of the second reset transistor T7 is coupled to the first signal transmission layer 30. Specifically, the first electrode of the second reset transistor T7 is coupled to the first signal branch 302, and the first signal transmission layer 30 is used to transmit the second initialization signal; the second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element (i.e., the fourth node N4).

[0114] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0115] Illustratively, the display device includes an active matrix organic light emitting diode display device, which may specifically adopt low temperature polycrystalline oxide technology, but is not limited thereto.

[0116] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board 40, a printed circuit board and a backplane.

[0117] In the display substrate provided in the above embodiment, at least two driver chip ICs are disposed in the peripheral region 20, each of which is coupled to the first signal transmission layer 30 and the flexible circuit board 40. The flexible circuit board 40 is coupled to the control circuit board 50, which is used to control each of the driver chip ICs to transmit a first signal to the first signal transmission layer 30 via the flexible circuit board 40. This arrangement enables the control circuit board 50 to control the at least two driver chip ICs via the flexible circuit board 40 to jointly provide the first signal to the first signal transmission layer 30, thereby effectively improving the stability of the first signal. Therefore, the display device provided in the embodiment of the present disclosure, when including the above display substrate, also has the above-mentioned beneficial effects, which will not be further elaborated here.

[0118] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0119] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0120] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0121] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0122] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0123] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0124] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0125] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A display area and a peripheral area located around the display area, the peripheral area including a first binding area and a second binding area, the first binding area being located between the display area and the second binding area, the display substrate further comprising: a first signal transmission layer, the first signal transmission layer including a portion located in the display area and a portion located in the peripheral area; a flexible circuit board, wherein the flexible circuit board is arranged in the second binding area; a control circuit board coupled to the flexible circuit board; a plurality of driver chips, the plurality of driver chips being disposed in the first binding area, each of the driver chips being coupled to the flexible circuit board, and each of the driver chips being directly coupled to the first signal transmission layer, or each of the driver chips being indirectly coupled to the first signal transmission layer via the flexible circuit board and the control circuit board; The control circuit board is used to control each of the driving chips to transmit a first signal to the first signal transmission layer through the flexible circuit board.

2. The display substrate according to claim 1, wherein The driver chip includes at least one first output pin; the control circuit board includes a signal connection line; The flexible circuit board includes at least two first terminals and at least two second terminals, the at least two first terminals are bound to the second binding area, and the at least two second terminals are bound to the control circuit board; The at least two first terminals include a target first terminal and a non-target first terminal; The target first terminal is coupled to the corresponding first output pin, and the target first terminal is also coupled to the corresponding second terminal to form a first transmission path from the target first terminal to the second terminal; The non-target first terminal is coupled to the first signal transmission layer, and the non-target first terminal is also coupled to the corresponding second terminal to form a second transmission path from the second terminal to the non-target first terminal; The at least two second terminals are respectively coupled to the signal connection lines.

3. The display substrate according to claim 2, wherein: The driver chip includes at least two first output pins; The flexible circuit board includes a plurality of first terminals and a plurality of second terminals, and the plurality of first terminals and the plurality of second terminals are divided into at least two terminal connection groups, each terminal connection group includes one first transmission path and one second transmission path, and each of the target first terminals in the at least two terminal connection groups is coupled one-to-one with the at least two first output pins.

4. The display substrate according to claim 2, wherein: The driving chip includes at least one second output pin, which is directly coupled to the first signal transmission layer and is used to transmit the first signal to the first signal transmission layer.

5. The display substrate according to claim 4, wherein: The first output pin is coupled to the corresponding second output pin. The display substrate according to claim 5 , wherein: The driver chip further includes at least one connecting pin, and the first output pin is coupled to the corresponding second output pin through the corresponding connecting pin.

7. The display substrate according to claim 6, wherein: In at least one driver chip, the first output pins included in the driver chip are coupled to each other, and / or the second output pins included in the driver chip are coupled to each other, and / or the connection pins included in the driver chip are coupled to each other.

8. The display substrate according to any one of claims 2 to 7, wherein The at least two driver chips include a main driver chip and at least one auxiliary driver chip; The display substrate further includes at least one protection module, which is connected in series between the first transmission path corresponding to the auxiliary driving chip and the signal connection line, and is used to achieve unidirectional conduction from the first transmission path to the signal connection line.

9. The display substrate according to claim 8, wherein: The protection module includes a diode, an anode of the diode is coupled to the second terminal in the first transmission path, and a cathode of the diode is coupled to the signal connection line.

10. The display substrate according to claim 4, wherein The first signal transmission layer includes a first signal bus and a plurality of first signal branches, the first signal bus is located in the peripheral area, the first signal branches include at least a portion located in the display area, and the first signal branches are coupled to the first signal bus; The first output pin is coupled to the first signal bus; and / or the second output pin is coupled to the first signal bus.

11. The display substrate according to claim 1, wherein: The display substrate also includes a plurality of sub-pixels located in the display area, and the sub-pixels include a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit includes a second reset transistor, a first electrode of the second reset transistor is coupled to the first signal transmission layer, and a second electrode of the second reset transistor is coupled to the anode of the light-emitting element.

12. A display device comprising the display substrate according to any one of claims 1 to 11.

Images