Fabrication method

Abstract

A method of fabricating a dielectric structure is described. The method comprises providing a first dielectric layer on a first substrate, patterning the first dielectric layer according to a first pattern, etching at least one trench through the first dielectric layer and into the first substrate to a first depth, etching the first substrate according to the first pattern to form etched regions, wherein the etched regions and the at least one trench are etched features, bonding a second dielectric layer to the first dielectric layer, wherein the second dielectric layer is provided on a second substrate, removing a portion of the first substrate to reveal the etched features, patterning the second dielectric layer according to a pattern defined by the etched features, etching the second substrate according to the pattern defined by the etched features, and removing a remaining portion of the first substrate.

Description

[0001] Fabrication Method

[0002] Technical Field

[0003] The present invention relates to methods of fabricating dielectric structures, such as photonic integrated circuits or subsections thereof.

[0004] Background

[0005] Some photonic integrated circuits (PICs) require thick dielectric films / layers, for example 20 um thick or thicker.

[0006] The fabrication of thick dielectric films can pose certain challenges.

[0007] Thick film dielectrics, such as those made from silicon dioxide, SiCh, or silicon nitride, SisN4, can be difficult to etch whilst maintaining low surface roughness - or they require a thick photoresist mask.

[0008] However, the use of typical photoresist masks limits the resolution and the critical dimension of etched features in the dielectric film. This can be problematic, as having precise resolution and dimensions of etched features is important for achieving good optical coupling between the PIC and other devices / components. This is especially the case when SiO2 / SisN4 dielectric structuring is required to minimize the edge coupling losses between a PIC and an optical fibre.

[0009] Edge couplers typically require thick dielectric films thicker than 10 um to 40 um. The fabrication of these films by etching can pose significant challenges due to the limitation on etch resolution in conventional fabrication methods. A typical photoresist mask in this case may require a thickness of at least 8 um to allow good facet etch quality. However, such a photoresist mask may not provide a sufficient etching selectivity, while a thicker photoresist mask may not provide a sufficient resolution.

[0010] In the art, this problem is addressed by employing a hard mask instead of a photoresist mask. However, this comes with additional processing complexity. Specifically, if alignment between features on the PIC and the facet(s) needs to be well controlled, the use of a hard mask may require special processing to allow for alignment < lum.

[0011] Furthermore, proportional ratios scale up with thicker films. This means that, for instance, if a PIC requires a dielectric film to be 20 um thick or thicker, the possible resolution limit proportionally increases. The achievable alignment tolerance also worsens with thicker films.

[0012] Summary

[0013] According to a first aspect of the present invention, there is provided a method of fabricating a dielectric structure. The method comprises providing a first dielectric layer on a first substrate, patterning the first dielectric layer according to a first pattern, etching at least one trench through the first dielectric layer and into the first substrate to a first depth, etching the first substrate according to the first pattern to form etched regions, wherein the etched regions and the at least one trench are etched features, bonding a second dielectric layer to the first dielectric layer, wherein the second dielectric layer is provided on a second substrate, removing a portion of the first substrate to reveal the etched features, patterning the second dielectric layer according to a pattern defined by the etched features, etching the second substrate according to the pattern defined by the etched features, and removing a remaining portion of the first substrate.

[0014] The method can provide a dielectric structure having a thick dielectric layer. Fabrication of the dielectric structure may be simplified due to the self-alignment capabilities of the method.

[0015] The at least one trench may be aligned with the first pattern.

[0016] The dielectric structure may be for use in a photonic integrated circuit. The dielectric structure may be a photonic integrated circuit.

[0017] The dielectric structure may be for use as a photonic optical Input / Output facet.

[0018] Etching the at least one trench may comprise etching a single trench or multiple trenches, such as 2 or 3 trenches.

[0019] The first substrate may be used as a hard mask for patterning the second dielectric layer.

[0020] The first dielectric layer and the second dielectric layer may have different thicknesses.

[0021] The method may be performed iteratively such that a dielectric layer is added to the dielectric structure and patterned in each iteration. A thickness of the remaining portion of the first substrate may be different in each iteration.

[0022] The portion of the first substrate may be removed by grinding a backside of the first substrate.

[0023] Each substrate may comprise a handle region which is positioned at an opposite side to the first dielectric layer.

[0024] The handle region may be for mechanical manipulation of the dielectric structure.

[0025] The handle region may herein also be referred to as a "handle layer".

[0026] The second dielectric layer may be bonded to the first dielectric layer using glue or by die attach.

[0027] The first dielectric layer may have a thickness of at least 2 um.

[0028] The second dielectric layer may have a thickness of at least 10 um.

[0029] The first dielectric layer and / or the second dielectric layer may comprise one or more grooves.

[0030] The grooves may help to prevent voids forming in the dielectric layer(s) during the bonding process.

[0031] The first and / or second dielectric layer may be formed of silicon dioxide, SiO2, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2O5:SiO2, lithium niobate, LNOI, or barium titanate, BTO.

[0032] Any subsequent dielectric layer may be formed of silicon dioxide, SiO2, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2O5:SiO2, lithium niobate, LNOI, or barium titanate, BTO.

[0033] The first and / or second dielectric layer may be doped with one or more rare-earth elements.

[0034] Any subsequent dielectric layer may be doped with one or more rare-earth elements. The rare earth elements may include Erbium, Er, Thulium, Tm, Ytterbium, Yb, and Niobium, Nb.

[0035] The first and / or second substrate(s) may be formed of silicon, Si.

[0036] Any subsequent substrates may be formed of silicon, Si.

[0037] One or more photonic layers may be embedded in the first dielectric layer and / or the second dielectric layer(s).

[0038] One or more photonic layers may be embedded in any subsequent dielectric layers.

[0039] According to a second aspect of the present invention, there is provided a method of fabricating a plurality of dielectric structures. The method comprises providing a first dielectric layer on a first substrate, bonding a plurality of second dielectric layers on the first dielectric layer, wherein each second dielectric layer is provided on a separate second substrate forming a first die, patterning the first dielectric layer according to a second pattern defined by the placement of the first dies, and etching a plurality of trenches into the first substrate, wherein the trenches are aligned with the second pattern.

[0040] The method may further comprise removing a portion of the first substrate to reveal the trenches.

[0041] The method may further comprise removing each second substrate, bonding a respective third dielectric layer to each second dielectric layer, wherein each third dielectric layer is provided on a separate third substrate forming a second die, bonding a single handle wafer to the third substrates, removing a portion of the first substrate to reveal the trenches, etching exposed regions of each second die such that the second dies align with the first dies, etching a plurality of trenches into the handle wafer, wherein the trenches in the handle wafer align with the exposed regions, removing a remaining portion of the first substrate, and removing the handle wafer.

[0042] The first substrate may be used as a hard mask.

[0043] A surface of each third substrate may be polished prior to bonding the handle wafer. Each dielectric structure may be a photonic integrated circuit.

[0044] The second substrate may be used as a hard mask.

[0045] The first and / or second dielectric layer may be formed of silicon dioxide, SiO?, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2Os:SiO2, lithium niobate, LNOI, or barium titanate, BTO.

[0046] The second dielectric layer and / or any subsequent dielectric layers may be formed of silicon dioxide, SiCh, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2Os:SiO2, lithium niobate, LNOI, or barium titanate, BTO.

[0047] The first and / or second dielectric layer may be doped with one or more rare-earth elements.

[0048] The third dielectric layer and / or any subsequent dielectric layers may be doped with one or more rare-earth elements.

[0049] The rare earth elements may include Erbium, Er, Thulium, Tm, Ytterbium, Yb, and Niobium, Nb.

[0050] The first and / or second substrate(s) may be formed of silicon, Si.

[0051] The third substrate may be formed of silicon, Si. Subsequent substrates may be formed of silicon, Si.

[0052] One or more photonic layers may be embedded in the first dielectric layer and / or the second dielectric layer(s).

[0053] One or more photonic layers may be embedded in the third dielectric layer and / or any subsequent dielectric layers.

[0054] According to a third aspect of the present invention, there is provided a dielectric structure formed according to the method according to the first aspect or the second aspect. Brief Description of Drawings

[0055] Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:

[0056] Figure 1 shows a process flow diagram of a first method of fabricating a dielectric structure;

[0057] Figure 2a schematically illustrates a step in the first method of fabricating a dielectric structure;

[0058] Figure 2b schematically illustrates a step in the first method of fabricating a dielectric structure;

[0059] Figure 2c schematically illustrates a step in the first method of fabricating a dielectric structure;

[0060] Figure 2d schematically illustrates a step in the first method of fabricating a dielectric structure;

[0061] Figure 2e schematically illustrates a step in the first method of fabricating a dielectric structure;

[0062] Figure 2f schematically illustrates a step in the first method of fabricating a dielectric structure;

[0063] Figure 2g schematically illustrates a step in the first method of fabricating a dielectric structure;

[0064] Figure 2h schematically illustrates a step in the first method of fabricating a dielectric structure;

[0065] Figure 2i schematically illustrates a step in the first method of fabricating a dielectric structure;

[0066] Figure 2j schematically illustrates a step in the first method of fabricating a dielectric structure;

[0067] Figure 3 schematically illustrates a dielectric structure;

[0068] Figure 4 shows a process flow diagram of a second method of fabricating a dielectric structure;

[0069] Figure 5a schematically illustrates a step in the second method of fabricating a dielectric structure;

[0070] Figure 5b schematically illustrates a step in the second method of fabricating a dielectric structure;

[0071] Figure 5c schematically illustrates a step in the second method of fabricating a dielectric structure;

[0072] Figure 5d schematically illustrates a step in the second method of fabricating a dielectric structure;

[0073] Figure 5e schematically illustrates a step in the second method of fabricating a dielectric structure; Figure 5f schematically illustrates a step in the second method of fabricating a dielectric structure;

[0074] Figure 6 shows a process flow diagram of a third method of fabricating a dielectric structure;

[0075] Figure 7a schematically illustrates a step in the third method of fabricating a dielectric structure;

[0076] Figure 7b schematically illustrates a step in the third method of fabricating a dielectric structure;

[0077] Figure 7c schematically illustrates a step in the third method of fabricating a dielectric structure;

[0078] Figure 7d schematically illustrates a step in the third method of fabricating a dielectric structure;

[0079] Figure 7e schematically illustrates a step in the third method of fabricating a dielectric structure;

[0080] Figure 7f schematically illustrates a step in the third method of fabricating a dielectric structure;

[0081] Figure 7g schematically illustrates a step in the third method of fabricating a dielectric structure; and

[0082] Figure 7h schematically illustrates a step in the third method of fabricating a dielectric structure;

[0083] Detailed Description of Certain Embodiments

[0084] In the following, like parts are denoted by like references.

[0085] The present application is concerned with methods of fabricating a dielectric structure. The dielectric structure may be a photonic integrated circuit or incorporated into a photonic integrated circuit.

[0086] The dielectric structure produced by these fabrication methods has a thick dielectric layer on a substrate. As will be hereinafter described, the thickness of the dielectric layer may be gradually increased as the methods are performed iteratively.

[0087] Referring to Figure 1, a first method of fabrication (herein "first fabrication method") will now be described.

[0088] Each step of the first fabrication method is schematically illustrated in Figures 2a to 2j, which will be referred to in combination with Figure 1. Figures 2a to 2j show cross-sectional views in the x-y plane of the dielectric structure at different stages of its fabrication. The schematic illustrations in these figures are merely example illustrations.

[0089] First, in step Sl.l, a dielectric layer 1 is provided on a first substrate 2 (shown in Figure 2a).

[0090] The first substrate 2 may comprise a handle region 3 ("first handle region"). The handle region 3 may be at an opposite side or face of the first substrate 2 relative to the first dielectric layer 1. The handle region 3 provides mechanical stability / robustness to the first substrate 2. Thus, the handle region 3 may help to mechanically manipulate the first substrate 2 and / or process the first substrate 2 without the first substrate 2 fracturing or otherwise becoming damaged.

[0091] The first substrate 2 may be formed of silicon, Si, or fused silica, for example. The first dielectric layer 1 may be formed of silicon dioxide, SiO?, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2Os:SiO2, lithium niobate, LNOI, or barium titanate, BTO. Further, the first dielectric layer 1 may be doped with one or more rare-earth elements, such as Erbium, Er, Thulium, Tm, Ytterbium, Yb, and / or Niobium, Nb.

[0092] In some examples, a silicon nitride, SiN, film may be disposed between the first substrate 2 and the first dielectric layer 1.

[0093] Next, in step SI.2, the first dielectric layer 1 is patterned. This layer 1 may be patterned via conventional photolithography.

[0094] The resulting patterned first dielectric layer 1 (shown in Figure 2b) comprises patterned regions 4. The patterned regions 4 are the regions of the first dielectric layer 1 removed during the patterning to expose the underlying first substrate 1.

[0095] After patterning the first dielectric layer 1, one or more trenches 5 are etched into the first substrate 2 (step SI.3). The trench(es) 5 may be etched with a wet chemical.

[0096] Each trench 5 is etched through the first dielectric layer 1 into the first substrate 2. Preferably, each trench 5 is etched via one of the patterned regions 4 (shown in Figure 2c) so that each trench 5 aligns with the pattern (herein "first pattern") formed in the first dielectric layer 1 in step SI.2. However, in some examples, the trench(es) 5 may not align with the first pattern.

[0097] The trench(es) 5 can help to align the layers of the dielectric structure (see Figure 2j) as it is being formed.

[0098] A single trench 5 may be etched into the first substrate 2, as shown in Figure 2c. Alternatively, a plurality of trenches 5 may be etched. The plurality of trenches 5 may follow or align with a subsection of the first pattern.

[0099] Next, in step SI.4, the first substrate 2 is further etched according to the first pattern. In other words, the etching in step SI.4 follows or aligns with the first pattern. The regions where the substrate 2 has been removed in this step are herein referred to as "etched regions" 6 (shown in Figure 2d).

[0100] At the end of step SI.4, the first substrate 2 includes the trench(es) 5 and the etched regions 6, which herein are collectively referred to as "etched features" 7 (shown in Figure 2e) of the first substrate 2. In examples wherein the trench(es) 5 align with the first pattern, all etched features 7 align with the first pattern. In other examples, only the etched regions 6 align with the first pattern.

[0101] The trench(es) 5 is etched to a depth ("first depth") of at least 1 um.

[0102] After etching the first substrate 2, in step SI.5, a second dielectric layer 8 is bonded to the patterned surface 9 of the first dielectric layer 1 (shown in Figure 2e), for example by using glue or by die attach.

[0103] The second dielectric layer 8 is formed of the same dielectric material as the first dielectric layer 1. However, the first and second dielectric layers 1, 8 may have different thicknesses. For example, the first dielectric layer 1 may have a thickness of at least 2 um, whereas the second dielectric layer 8 may have a thickness of at least 10 um.

[0104] For each structure shown in Figures 2a to 2j, and hereinafter Figures 5a to 5f and 7a to 7h, the thickness direction is along the y-axis. The thickness of the first and / or second dielectric layer 1, 8 can be minimized in order to achieve improved resolution and alignment capabilities for the subsequent etch processes.

[0105] The first dielectric layer 1 and / or the second dielectric layer 8 may comprises one or more grooves (not shown). The grooves may help to prevent voids forming in the dielectric layer(s) 1, 8 during the bonding process. Furthermore, the first dielectric layer 1 and / or the second dielectric layer 8 may comprise photonic circuits, layers, and / or features.

[0106] As shown in Figure 2e, the second dielectric layer 8 has a bonding surface 10 to which the second dielectric layer 8 bonds to the first dielectric layer 1. Prior to bonding, a second substrate 11 is disposed on an opposite side of the second dielectric layer 8 relative to the bonding surface 10.

[0107] An unpatterned dielectric layer on which is disposed a substrate, such as the second substrate 11 and the second dielectric layer 8, are herein referred to as a "dielectricsubstrate stack" 12.

[0108] Thus, at the end of step SI.5, a dielectric-substrate stack 12 has been bonded to the first dielectric layer 1 (shown in Figure 2f).

[0109] The second substrate 11 may be formed of the same material as the first substate 2, but the substrates 2, 11 may have different thicknesses.

[0110] After step SI.5, the structure formed in step SI.5 may be flipped or rotated 180° (for example, by using the handle region 3) such that the second substrate 11 is at the base of the structure and a backside 13 of the first substrate 2 is at the top of the structure.

[0111] As will now be explained with reference to Figures 2g to 2i, the first substrate 2 is used as a hard mask.

[0112] Firstly, if present, the handle region 3 is removed (step SI.6).

[0113] Then, in step SI.7, a region or portion of the first substrate 2 is removed (shown in Figure 2g). This region is herein referred to as the "removal region" 14. The removal region 14 is removed such that the etched features 7 are exposed or revealed (shown in Figure 2h).

[0114] The removal region 14 and, if present, the handle region 3 may be removed by grinding the backside 13 of the first substrate 2.

[0115] In step SI.8, the second dielectric layer 8 is patterned according to a pattern defined by the etched features 7 (shown in Figure 2h). This is done by using the first substrate 2 as a hard mask to define the regions of the second dielectric layer 8 to be removed.

[0116] Using the first substrate 2 as a hard mask helps to align the patterning of the second dielectric layer 8 with the patterning of the first dielectric layer 1. In this way, the first fabrication method is self-aligning.

[0117] The second substrate 11 is etched in step SI.9 according to a pattern defined by the etched features 7 (shown in Figure 2i). The first substrate 2 is also utilised as a hard mask in this step.

[0118] Firstly, the etching process in step SI.9 involves etching the trench(es) 5 as described in step SI.3. The first substrate 2, acting as the hard mask, already defines the regions where the trench(es) 5 are to be etched.

[0119] Then, after the trench(es) 5 are etched, the second substrate 11 is further etched according to the pattern defined by the etched features 7. The trench(es) 5 in the second substrate 11 may help to align the second substrate 11 with the other layers of the dielectric structure during this etching step.

[0120] Thus, at the end of step SI.9, the second substrate 11 comprises etched features 15 which align with the etched features 7 of the first substrate 2.

[0121] In step SI.10, the remaining portion of the first substrate 2 (in other words, the portion of the first substrate 2 not removed in step SI.7) is removed (shown in Figure 2j).

[0122] At the end of step SI.10, the dielectric structure 16 has been formed.

[0123] The first fabrication method may be performed iteratively. After completing step SI.10, a further sequence of fabrication steps corresponding to steps SI.5 to S.10 may be performed, as will now be described.

[0124] In a first iteration, steps Sl.l to SI.10 are performed as hereinbefore described.

[0125] Then, in a second iteration, a further dielectric-substrate stack 12 is bonded to the dielectric structure 16 (as described in step SI.5). This further dielectric-substrate stack 12 consists of a third dielectric layer (not shown) and a third substate (not shown). The third dielectric layer is then patterned (in a corresponding way to step SI.8) and the third substrate is etched (in a corresponding way to step SI.9) by using the second substrate 11 as a hard mask. As hereinbefore described, one or more trenches 5 are etched into the third substrate, which may help to align the third substrate with the other layers of the dielectric structure 16 as it is further etched.

[0126] Subsequent iterations may be performed. In each subsequent iteration, a sequence of steps corresponding to steps SI.5 to SI.10 are performed. Thus, in each iteration, a dielectric layer is added to the dielectric structure and patterned.

[0127] In this way, the first fabrication method can produce a dielectric structure having a thick dielectric layer.

[0128] Each iteration uses the substrate remaining from the preceding iteration as a hard mask. This can help to reduce the processing complexity compared to convention methods involving hard masks.

[0129] At least 1 iteration may be performed. For example, between 1 and 10 iterations may be performed.

[0130] Each substrate (second substrate 11, etc.) in each iteration may comprise a handle region (in the same way that the first substrate 2 has the first handle region 3).

[0131] Referring now to Figure 3, a first example of the dielectric structure 16i, 16 is shown in which multiple iterations have been performed.

[0132] The dielectric structure 16i has a thick dielectric layer 17 consisting of a stack of constituent dielectric layers 18. Each constituent dielectric layer 18 has been added in a respective iteration and may have the same or different thicknesses. The dielectric structure 16i also comprises a base substrate 19 which was incorporated into the dielectric structure 16i in the final iteration.

[0133] The thick dielectric layer 17 may have a thickness from 30 um to 150 um. The thick dielectric layer 17 may be as thick as the base substrate 19.

[0134] In some examples, the base substrate 19 is formed of silicon and the thick dielectric layer 17 is formed of SiO?. In such examples, for the base substrate 19 having a diameter of 100 mm, the thick dielectric layer 17 may have a thickness of between 240 um and 270 um, for example 252 um. For the base substrate 19 having a diameter of 200 mm, the thick dielectric layer 17 may have a thickness of between 740 um and 760 um, for example 750 um.

[0135] Referring now to Figure 4, a second method of fabrication (herein "second fabrication method") will now be described.

[0136] The second fabrication method will be described also with reference to Figures 5a to 5f, which each schematically illustrate different steps in the second fabrication method.

[0137] First, in step S2.1, the first dielectric layer 1 is provided on the first substrate 2 (shown in Figure 5a).

[0138] Then, in step S2.2, a plurality of dielectric-substrate stacks 12 (shown in Figure 5b) are provided on the first dielectric layer 1, rather than a single stack 12 (as shown in Figure 2e).

[0139] Each dielectric-substrate stack 12 of the second fabrication method is herein referred to as a die 20. Each die 20 consists of the second dielectric layer 8 and the second substrate 11 hereinbefore described. Each die 20 is bonded to the first dielectric layer 1 via the bonding surface 10 of the first dielectric layer 1. The dies 20 are die-attached or die-bonded to the first dielectric layer 1.

[0140] The thickness of the second dielectric layer 8 and the second substrate 11 may be the same or different across different dies 20— as schematically shown in Figure 5b.

[0141] The dies 20 are spaced apart from each other by a distance di. Distance di may be between 1 um and 3 cm. In some examples, the plurality of dies 20 may consist of two dies 20 spaced apart according to a distance limited by the diameter of the first substrate 2. The dies 20 may be uniformly or non-uniformly spaced apart.

[0142] In step S2.3, the first dielectric layer 1 is patterned according to a second pattern defined by the placement of the dies 20. The resulting patterned first dielectric layer 1 (shown in Figure 5c) comprises the patterned regions 4.

[0143] In a similar way as hereinbefore described, the second substrates 11 of the dies 20 collectively act as a hard mask. This means that the patterned regions 4 are formed in the regions of the first dielectric layer 1 left exposed by the dies 20. Thus, the pattern regions 4 follow or align with the second pattern and are self-aligned with the edges 21 of the dies 20 (herein "die edges").

[0144] After the first dielectric layer 1 has been etched, a plurality of trenches 5 are etched into the first substrate 2 (step S2.4). The trenches 5 are self-aligned with the die edges 21 and follow the second pattern, as shown in Figure 5d.

[0145] The trenches 5 are each etched to a depth ("second depth") of at least 1 um. The trenches 5 may be etched with a wet chemical.

[0146] Then, the removal region 14 (hereinbefore described) of the first substrate 2 is removed such that the plurality of trenches 5 are exposed or revealed (step S2.5), as shown in Figure 5e.

[0147] The removal region 14 may be removed by grinding or polishing backside 13 of the first substrate 2.

[0148] After the removal region 14 is removed, a plurality of dielectric structures 16 are formed (as shown in Figure 5f). The dielectric structures 16 may be separate PICs.

[0149] As hereinbefore explained, one or more of the dielectric layers 1, 8 may be a simple dielectric layer or a multi-layered dielectric layer. For example, the first dielectric layer 1 may include a patterned silicon nitride photonic layer embedded into silicon dioxide.

[0150] Referring now to Figure 6, a third method of fabrication (herein "third fabrication method") will now be described. The third fabrication method will be described also with reference to Figures 7a to 5h, which each schematically illustrate different steps in the third fabrication method.

[0151] Steps S3.1 to S3.4 (Figure 6) are the same as steps S2.1 to S2.4 (Figure 4) hereinbefore described.

[0152] After the trenches 5 are etched into the first substrate 2 in step S3.4, the second substrate 11 of each die 20 is completely removed (step S3.5).

[0153] The second substrates 11 may be removed by grinding or polishing until each second dielectric layer 8 is completely exposed (as shown in Figure 7a). The surface of the second dielectric layer 8 exposed during step S3.5 is referred to as an exposed surface 22.

[0154] Next, a die 20 is provided on the exposed surface 22 of each second dielectric layer 8 by die-attaching or die-bonding (step S3.6), as shown in Figure 7b.

[0155] Each die 20 introduced in step S3.6 consists of a third dielectric layer 23 and a third substrate 24. Each third dielectric layer 23 is bonded to a respective second dielectric layer 8.

[0156] As shown in Figure 7b, the dies 20 introduced in step S3.6 have greater widths compared to the dies 20 introduced in step S3.2. In other words, the die edges 21 of different pluralities of dies 20 do not align.

[0157] In step S3.7, the surface 25 of each third substrate 24 which faces away from the third dielectric layer 23 (herein "third substrate backside") may be polished.

[0158] After polishing, a single handle wafer 26 is bonded to all the third substrate backsides 25 (step S3.8), as shown in Figure 7c. The handle wafer 26 may be formed of silicon, Si.

[0159] The handle wafer 26 may help to provide mechanical stability / robustness to the dielectric structures 16 as they are being formed.

[0160] Next, the removal region 14 of the first substrate 2 is removed (step S3.9), as shown in Figure 7d, as hereinbefore described in step S2.5. As hereinbefore described, the dies 20 introduced in step S3.6 (herein "second dies") have greater widths compared to the dies 20 introduced in step S3.2 (herein "first dies"). Thus, the third dielectric layer 23 of each second die 20 comprises exposed regions 27 which are not overlapped by a respective first die 20. An exposed region 27 is on each side of the third dielectric layer 23, as shown in Figure 7e.

[0161] In step S3.10, the third dielectric layers 23 are etched to remove the exposed regions 27. This etching extends to the third substrate 24.

[0162] The first substrate 2 is used as a hard mask in this step, in a similar way as previously described.

[0163] Removing the exposed regions 27 reveals the regions 28 of the third substrate 24 which are positioned directly under the exposed regions 27 (herein "exposed substrate regions").

[0164] In step S3.11, the third substrates 24 are etched to remove the exposed substrate regions 28. The etching during this step is extended into the handle wafer 26 such that trenches 5 are formed in the handle wafer 26, as shown in Figure 7f.

[0165] Step S3.11 may be performed using an etching plasma inside an inductively coupled plasma ("ICP") reactor. Again, this etching is masked by the first substrate 2, which acts as a self-aligned hard mask.

[0166] The trenches 5 in the handle wafer 26 are each etched to a depth ("third depth") of at least 1 um.

[0167] In step S3.12, the remaining portion of the first substrate 2 (in other words, the portion of the first substrate 2 not removed in step S3.9) is removed (as shown in Figure 7g).

[0168] On completion of step S3.12, a plurality of dielectric structures 16 are formed (as shown in Figure 7g). The dielectric structures 16 may be separate PICs.

[0169] Lastly, in step S3.13, the handle wafer 26 is removed in order to separate the dielectric structures 16 / PICs.

[0170] Typical methods to remove the handle wafer 26 include grinding and polishing. The fabrication methods according to the present application are self-aligning. This allows for facet quality to be optimized for each constituent dielectric layer. In some examples, the fabrication method can be iterated until a given dielectric thickness is reached.

[0171] Using the substrates (first substrate 2, second substrate 11, etc.) as hard masks allows for an improved etching selectivity and thick dielectric layers.

[0172] The fabrication methods according to the present application allow for fabrication of complex 3D photonic circuits. Bonding alignment between substrates enables the convenient coupling of light or optical signals to and from SiN layers (if present), whose distance is mostly dictated by the dielectric layer thicknesses.

[0173] Modifications

[0174] It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0175] Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicant hereby gives notice that new claims may be formulated to such features and / or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

Claims1. A method of fabricating a dielectric structure, the method comprising : providing a first dielectric layer on a first substrate; patterning the first dielectric layer according to a first pattern; etching at least one trench through the first dielectric layer and into the first substrate to a first depth; etching the first substrate according to the first pattern to form etched regions, wherein the etched regions and the at least one trench are etched features; bonding a second dielectric layer to the first dielectric layer, wherein the second dielectric layer is provided on a second substrate; removing a portion of the first substrate to reveal the etched features; patterning the second dielectric layer according to a pattern defined by the etched features; etching the second substrate according to the pattern defined by the etched features; and removing a remaining portion of the first substrate.

2. The method according to claim 1, wherein the dielectric structure is for use in a photonic integrated circuit.

3. The method according to claim 2, wherein the dielectric structure is for use as a photonic optical Input / Output facet.

4. The method according to any preceding claim, wherein the first substrate is used as a hard mask for patterning the second dielectric layer.

5. The method according to any preceding claim, wherein the first dielectric layer and the second dielectric layer have different thicknesses.

6. The method according to any preceding claim, wherein the method is performed iteratively such that a dielectric layer is added to the dielectric structure and patterned in each iteration.

7. The method according to any preceding claim, wherein the portion of the first substrate is removed by grinding a backside of the first substrate.

8. The method according to any preceding claim, wherein each substrate comprises a handle region which is positioned at an opposite side to the first dielectric layer.

9. The method according to any preceding claim, wherein the second dielectric layer is bonded to the first dielectric layer using glue or by die attach.

10. The method according to any preceding claim, wherein the first dielectric layer has a thickness of at least 2 um.

11. The method according to any preceding claim, wherein the second dielectric layer has a thickness of at least 10 um.

12. The method according to any preceding claim, wherein the first dielectric layer and / or the second dielectric layer comprises one or more grooves.

13. A method of fabricating a plurality of dielectric structures, the method comprising : providing a first dielectric layer on a first substrate; bonding a plurality of second dielectric layers on the first dielectric layer, wherein each second dielectric layer is provided on a separate second substrate forming a first die; patterning the first dielectric layer according to a second pattern defined by the placement of the first dies; and etching a plurality of trenches into the first substrate, wherein the trenches are aligned with the second pattern.

14. The method according to claim 13, the method further comprising : removing a portion of the first substrate to reveal the trenches.

15. The method according to claim 13, the method further comprising : removing each second substrate; bonding a respective third dielectric layer to each second dielectric layer, wherein each third dielectric layer is provided on a separate third substrate forming a second die; bonding a single handle wafer to the third substrates; removing a portion of the first substrate to reveal the trenches;etching exposed regions of each second die such that the second dies align with the first dies; etching a plurality of trenches into the handle wafer, wherein the trenches in the handle wafer align with the exposed regions; removing a remaining portion of the first substrate; and removing the handle wafer.

16. The method of claim 15, wherein the first substrate is used as a hard mask.

17. The method according to any one of claims 15 or 16, wherein a surface of each third substrate is polished prior to bonding the handle wafer.

18. The method according to any one of claims 13 to 17, wherein each dielectric structure is a photonic integrated circuit.

19. The method according to any one of claims 13 to 18, wherein the second substrate is used as a hard mask.

20. The method according to any preceding claim, wherein the first and / or second dielectric layer is formed of silicon dioxide, SiO?, aluminium oxide, AI2O3, silicon nitride, phosphorus pentoxide silica gel, P2Os:SiO2, lithium niobate, LNOI, or barium titanate, BTO.

21. The method according to claim 20, wherein the first and / or second dielectric layer is doped with one or more rare-earth elements.

22. The method according to claim 21, wherein the rare earth elements include Erbium, Er, Thulium, Tm, Ytterbium, Yb, and Niobium, Nb.

23. The method according to any preceding claim, wherein the first and / or second substrate(s) is formed of silicon, Si.

24. The method according to any preceding claim, wherein one or more photonic layers are embedded in the first dielectric layer and / or the second dielectric layer(s).

25. A dielectric structure formed according to the method of any preceding claim.

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