Arithmetic circuit, arithmetic device, and electronic equipment

Abstract

Provided is an arithmetic circuit that can multiply one multiplier by each of a plurality of multiplicands all at once. The arithmetic circuit comprises first to fifth transistors and first to third capacitive elements. A source or a drain of the first transistor is electrically connected to a first terminal of the first capacitive element and a gate of the third transistor, and the other of the source and the drain of the first transistor is electrically connected to a first terminal of the second capacitive element, a gate of the fourth transistor, and the source or drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to a first terminal of the third capacitive element and the source or drain of the fifth transistor. A gate of the first transistor, a gate of the second transistor, and a gate of the fifth transistor are each electrically connected to a first wiring.

Description

Arithmetic circuit, arithmetic device and electronic device

[0001] One embodiment of the present invention relates to an arithmetic circuit, an arithmetic device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There are also attempts to use a computing device that configures an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing device that configures an artificial neural network to adjust the brightness, color tone, etc. of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al. , “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. J. Zhang et al. , “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924.

[0008] There are various models of artificial neural networks. For example, a model called a convolutional neural network (CNN) is used in image analysis. A convolutional neural network is a type of neural network that exhibits excellent performance in the field of image recognition, and its computational load is determined by factors such as image resolution and filter size. Specifically, for example, the higher the image resolution, the larger the filter size, or the smaller the stride, the greater the computational load in the convolutional neural network, which tends to result in longer processing times by the computing device. Furthermore, the greater the computational load, the higher the power consumption of the computing device.

[0009] Furthermore, in a convolutional neural network, feature extraction is performed for each of the divided images using the same filter. Therefore, the filter is repeatedly used for each calculation, resulting in frequent read operations of the filter from a memory circuit or the like. Because the power consumption of both the read operation and the data transmission operation of the filter or the like is high, it is desirable for the calculation circuit that performs the calculation of the convolutional neural network to have a function called in-memory computing, as well as a function to retain the filter value, which is the multiplier, for a long period of time.

[0010] An object of one embodiment of the present invention is to provide an arithmetic circuit with reduced power consumption.An object of one embodiment of the present invention is to provide an arithmetic circuit that can retain data for a long period of time.An object of one embodiment of the present invention is to provide an arithmetic circuit that can multiply one multiplier by each of a plurality of multiplicands at once.An object of one embodiment of the present invention is to provide a novel arithmetic circuit.An object of one embodiment of the present invention is to provide an arithmetic device including the above-described arithmetic circuit.An object of one embodiment of the present invention is to provide an electronic device including the above-described arithmetic device.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0012] In the convolution process used in a convolutional neural network, each of the divided images is used as input data and multiplied by the same filter value. Therefore, in one aspect of the present invention, multiple retention nodes that retain the same filter value as a potential are required to perform the multiplication with each input data. Furthermore, by inputting a potential corresponding to the input data to each retention node via a capacitive element, the potential of the retention node becomes the sum of the potential of the filter value and the potential corresponding to the input data due to capacitive coupling.

[0013] When an n-channel transistor operates in the subthreshold region, the source-drain current (sometimes called the subthreshold current) is calculated by dividing the gate-source voltage by V ＧＳ As a result, exp{V ＧＳ -V ｔｈ}. Note that V ｔｈ is the threshold voltage of the transistor. At this time, the gate potential is set to a potential V Ｆ and the potential V corresponding to the input data ＩＮ The source potential is the sum of V ＧＮＤ Then, exp{V ＧＳ -V ｔｈ} is exp{V Ｆ}exp{V ＩＮ}exp{V ＧＮＤ -V ｔｈ}, and the subthreshold current is Ｆ} and exp{V ＩＮ}.

[0014] As described above, an arithmetic circuit according to one embodiment of the present invention includes a circuit in which one of a pair of electrodes of a capacitor and a gate of a transistor are connected to each other. Note that the connection point is a storage node. Furthermore, since each of a plurality of input data items is multiplied by the same filter, it is preferable that the number of such circuits is equal to the number of input data items. Furthermore, since the same filter value is held in each of the storage nodes of the plurality of such circuits, it is more preferable that the storage nodes are connected via a switch or the like. For example, by turning on the switch, electrical continuity is established between the storage nodes, making it possible to write the same filter value. Furthermore, by turning off the switch, electrical continuity is established between the storage nodes, making it possible to hold the potential of each storage node.

[0015] A specific configuration of one embodiment of the present invention will be described below.

[0016] (1) One embodiment of the present invention is an arithmetic circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, and a third capacitor.

[0017] One of the source or drain of the first transistor is electrically connected to a first terminal of the first capacitance element and a gate of the third transistor, the other of the source or drain of the first transistor is electrically connected to a first terminal of the second capacitance element, a gate of the fourth transistor, and one of the source or drain of the second transistor, the other of the source or drain of the second transistor is electrically connected to a first terminal of the third capacitance element and one of the source or drain of the fifth transistor, the gate of the first transistor is electrically connected to a first wiring, the gate of the second transistor is electrically connected to the first wiring, and the gate of the fifth transistor is electrically connected to the first wiring.

[0018] (2) Alternatively, in one embodiment of the present invention, in the above-described (1), each of the first to fifth transistors may include an oxide semiconductor in a channel formation region. In particular, the oxide semiconductor preferably includes one or more elements selected from indium, zinc, and an element M.

[0019] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0020] (3) Alternatively, one aspect of the present invention is an arithmetic device including the arithmetic circuit of (2), a first drive circuit, a second drive circuit, a third drive circuit, a fourth drive circuit, and a fifth drive circuit.

[0021] The first driver circuit has a function of applying a first potential corresponding to first data to the other of the source and drain of the fifth transistor. The second driver circuit has a function of applying a second potential corresponding to second data to the second terminal of the first capacitor and a function of applying a third potential corresponding to third data to the second terminal of the second capacitor. The third driver circuit has a function of transmitting a selection signal to the first wiring to write the first data to the arithmetic circuit.

[0022] The fourth driving circuit has a function of acquiring a first current flowing through one of the source or drain of the third transistor in accordance with the multiplication of the first data and the second data, and outputting a result of an operation of a first function using the first current as an input value, and a function of acquiring a second current flowing through one of the source or drain of the fourth transistor in accordance with the multiplication of the first data and the third data, and outputting a result of an operation of a second function using the second current as an input value. In addition, the fifth driving circuit has a function of applying a potential to the second terminal of the third capacitive element.

[0023] (4) Alternatively, one embodiment of the present invention can have a structure according to (3) above, including a first layer and a second layer located above the first layer. In particular, the first layer preferably includes a single crystal substrate containing silicon. Furthermore, the single crystal substrate preferably includes first to fifth driver circuits, and each of the first to fifth driver circuits preferably includes a transistor formed over the single crystal substrate. Furthermore, the second layer preferably includes an arithmetic circuit.

[0024] (5) Another embodiment of the present invention is an arithmetic circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor.

[0025] One of the source and the drain of the first transistor is electrically connected to a first terminal of the first capacitance element and a gate of the third transistor, the other of the source and the drain of the first transistor is electrically connected to a first terminal of the second capacitance element, a gate of the fourth transistor, and one of the source and the drain of the second transistor, the gate of the first transistor is electrically connected to a first wiring, and the gate of the second transistor is electrically connected to the first wiring.

[0026] (6) Alternatively, in one embodiment of the present invention, in the above-described (5), each of the first to fourth transistors can include an oxide semiconductor in a channel formation region. In particular, the oxide semiconductor preferably includes one or more elements selected from indium, zinc, and an element M.

[0027] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0028] (7) Another embodiment of the present invention is an arithmetic device including the arithmetic circuit of (6), a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit.

[0029] The first driver circuit has a function of applying a first potential corresponding to first data to the other of the source and drain of the second transistor. The second driver circuit has a function of applying a second potential corresponding to second data to the second terminal of the first capacitor and a function of applying a third potential corresponding to third data to the second terminal of the second capacitor. The third driver circuit has a function of transmitting a selection signal to the first wiring to write the first data to the arithmetic circuit.

[0030] The fourth driving circuit has a function of acquiring a first current flowing through either the source or drain of the third transistor in response to the multiplication of the first data and the second data, and outputting the result of an operation of a first function using the first current as an input value, and a function of acquiring a second current flowing through either the source or drain of the fourth transistor in response to the multiplication of the first data and the third data, and outputting the result of an operation of a second function using the second current as an input value.

[0031] (8) Alternatively, one embodiment of the present invention can have a structure according to the above (7) including a first layer and a second layer located above the first layer. In particular, the first layer preferably includes a single crystal substrate containing silicon. Furthermore, the single crystal substrate preferably includes first to fourth driver circuits, and each of the first to fourth driver circuits preferably includes a transistor formed over the single crystal substrate. Furthermore, the second layer preferably includes an arithmetic circuit.

[0032] (9) Another embodiment of the present invention is an electronic device including the arithmetic device described in (4) or (8) above and a housing.

[0033] As in the configurations (1) and (5) above, the connection point between the first terminal of the first capacitance element and the gate of the third transistor is the first holding node, the connection point between the first terminal of the second capacitance element and the gate of the fourth transistor is the second holding node, and the first holding node and the second holding node are connected via the first transistor.By this, when the first transistor is in the on state, it is possible to write the same filter value to each of the first holding node and the second holding node, and when the first transistor is in the off state, it is possible to hold the filter values ​​of the first holding node and the second holding node.

[0034] Furthermore, when the third transistor and the fourth transistor are operated in the subthreshold region and the same filter value is held at the first hold node and the second hold node, respectively, by applying potentials corresponding to different input data to the second terminal of the first capacitance element and the second terminal of the second capacitance element, respectively, a subthreshold current corresponding to the multiplication result of the input data and the filter value flows in each of the third transistor and the fourth transistor. In this way, the configurations of (1) and (5) make it possible to multiply one multiplier by each of multiple multiplicands at once.

[0035] Furthermore, the configurations (2) and (6) above allow the potentials written to the first and second hold nodes to be held for a long period of time, thereby allowing the same multipliers written to the first and second hold nodes to be held for a long period of time, thereby enabling continuous calculations.

[0036] Furthermore, as in the configurations (4) and (8), by arranging a driver circuit that drives an arithmetic circuit below the arithmetic circuit, the circuit area of ​​the arithmetic device can be reduced. Furthermore, by stacking the arithmetic circuit and the driver circuit, the materials of the transistors included in each circuit can be made different. For example, a transistor that can hold a potential for a long time and has a small off-state current can be used as the transistor included in the arithmetic circuit, and a transistor that has a large on-state current can be used as the transistor included in the driver circuit to increase the driving speed.

[0037] According to one embodiment of the present invention, an arithmetic circuit with reduced power consumption can be provided. According to another embodiment of the present invention, an arithmetic circuit capable of retaining data for a long period of time can be provided. According to another embodiment of the present invention, an arithmetic circuit capable of multiplying one multiplier by each of a plurality of multiplicands at once can be provided. According to one embodiment of the present invention, a novel arithmetic circuit can be provided. According to one embodiment of the present invention, an arithmetic device including the above-described arithmetic circuit can be provided. According to one embodiment of the present invention, an electronic device including the above-described arithmetic device can be provided.

[0038] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0039] FIG. 1 is a diagram showing an example of the configuration of an arithmetic circuit and an arithmetic device including the arithmetic circuit. FIGS. 2A and 2B are diagrams showing an example of the configuration of a drive circuit included in the arithmetic device. FIGS. 3A to 3D are diagrams showing an example of the configuration of a drive circuit included in the arithmetic device. FIG. 4 is a timing chart showing an example of the operation of the arithmetic device. FIG. 5 is a diagram showing an example of the configuration of an arithmetic circuit and an arithmetic device including the arithmetic circuit. FIG. 6 is a diagram showing an example of the configuration of an arithmetic device. FIG. 7 is a diagram showing an example of the configuration of an arithmetic circuit and an arithmetic device including the arithmetic circuit. FIG. 8 is a diagram showing an example of the configuration of an arithmetic circuit and an arithmetic device including the arithmetic circuit. FIG. 9 is a diagram showing an example of the configuration of an arithmetic circuit. FIG. 10 is a schematic plan view showing an example of the configuration of an arithmetic circuit. FIG. 11 is a diagram showing an example of a convolutional neural network. FIG. 12 is a diagram explaining an example of convolution processing. FIG. 13 is a diagram explaining an example of convolution processing. FIG. 14 is a block diagram showing an example of the operation of convolution processing in the arithmetic device. FIGS. 15A and 15B are diagrams explaining an example of pooling processing. FIG. 16 is a schematic perspective view showing an example of the configuration of an arithmetic device. FIG. 17 is a block diagram showing an example of the configuration of a computing device. FIG. 18 is a schematic cross-sectional view showing an example of the configuration of a computing device. FIGS. 19A and 19B are schematic perspective views showing an example of the configuration of a transistor. FIG. 20A is a schematic plan view showing an example of the configuration of a transistor, and FIGS. 20B to 20D are schematic cross-sectional views showing an example of the configuration of a transistor. FIGS. 21A to 21C are schematic cross-sectional views showing an example of the configuration of a transistor. FIG. 22 is a schematic cross-sectional view showing an example of the configuration of a computing device. FIG. 23A is a schematic plan view showing an example of the configuration of a computing device, and FIG. 23B is a schematic cross-sectional view showing an example of the configuration of a computing device. FIG. 24 is a schematic perspective view showing an example of the configuration of a portion of a computing device. FIG. 25 is a schematic perspective view showing an example of the configuration of a portion of a computing device. FIG. 26 is a schematic cross-sectional view showing an example of the configuration of a capacitive element that can be applied to a computing device. FIG. 27 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 28A to 28D are diagrams showing examples of electronic components. 29A and 29B are diagrams showing an example of electronic equipment, and Fig. 29C is a diagram showing an example of a mainframe computer. Fig. 30 is a diagram showing an example of space equipment.Fig. 31 is a diagram showing an example of a storage system applicable to a data center. Fig. 32A1 to Fig. 32(A7) and Fig. 32B1 to Fig. 32B6 are circuit diagrams for explaining electrical connections.

[0040] (Additional Notes Related to This Specification) In this specification, etc., a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0041] In this specification, "connection" includes, for example, "electrical connection."

[0042] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0043] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0044] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 32A1 and 32A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 32A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0045] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 32A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 32A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0046] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing at which an electrical signal is exchanged or potential interaction occurs between A and B. An example of this is when, as shown in Figures 32A6 and 32A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 32A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 32A6 and 32A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0047] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0048] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 32B1, 32B2, and 32B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 32B4 and 32B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 32B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0049] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0050] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0051] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0052] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0053] In this specification, a switch refers to a device that can be turned on or off and has the function of controlling whether or not a current flows, or a device that has the function of selecting and switching a path through which a current flows.

[0054] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0055] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0056] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0057] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0058] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain may be referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain may be referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0059] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0060] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0061] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0062] Furthermore, in this specification and the like, a selector may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, a selector may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, a selector may refer to a circuit that selects one of the multiple output terminals and outputs an input signal input to the input terminal to the selected output terminal. In other words, a selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, a selector may refer to an analog multiplexer or an analog demultiplexer.

[0063] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0064] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0065] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0066] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0067] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0068] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0069] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0070] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0071] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0072] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term such as "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0073] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. To clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally shifted.

[0074] Furthermore, in this specification and the like, flowcharts may be used to explain the operation method of a semiconductor device. Furthermore, in this specification and the like, the processes shown in the flowcharts are classified by operation and shown as mutually independent steps. However, in actual processing, it is difficult to separate the processes shown in the flowcharts by operation, and there are cases where one step involves multiple steps, or where one step involves multiple steps. Therefore, the processes shown in the flowcharts are not limited to the steps described in the specification, and can be appropriately rearranged depending on the situation. Specifically, the order of steps can be rearranged, steps can be added, and steps can be deleted depending on the situation.

[0075] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0076] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0077] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0078] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0079] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0080] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0081] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0082] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0083] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0084] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0085] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0086] Embodiment 1 In this embodiment, an arithmetic circuit according to one embodiment of the present invention will be described.

[0087] <Configuration Example 1 of Achievement Circuit> An arithmetic circuit of one embodiment of the present invention is an arithmetic cell that can multiply one multiplier by each of a plurality of multiplicands. Specifically, for example, when one multiplier is W and a plurality of multiplicands are X, １ , X ２ When this is done, the calculation cell is X １ ×W and X ２ ×W can be performed simultaneously.

[0088] As described above, a convolutional neural network, which is a type of artificial neural network, is an example of a case in which one multiplier is multiplied by each of multiple multiplicands. The convolutional neural network will be described in the second embodiment. In one example, a filter containing a certain feature is multiplied by image data. In particular, a convolutional neural network multiplies the feature of one filter, which serves as a multiplier, by multiple image data, which serve as multiplicands. Therefore, it is preferable to use the above-described arithmetic cell to perform this multiplication.

[0089] In this specification, the multiplier is referred to as the first data, and each of the multiple multiplicands is referred to as the second data. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the multiplier can be referred to as the second data, and each of the multiple multiplicands can be interchangeable as the first data.

[0090] 1 shows an example of an arithmetic cell IM, which is an arithmetic circuit of one embodiment of the present invention. In addition, in order to describe the operation of the arithmetic cell IM later, FIG. 1 also shows a driver circuit WCD, a driver circuit XCD, a driver circuit WSD, a driver circuit SED, and a driver circuit ITS for driving the arithmetic cell IM. Therefore, in this specification and the like, a circuit including the arithmetic cell IM and the above-listed driver circuits may be referred to as an arithmetic device CDV.

[0091] 1 is an arithmetic circuit that can multiply one first data item by one of two second data items, and multiply one first data item by the other of the two second data items. Furthermore, by changing the circuit configuration of the arithmetic cell IM in FIG. 1, it is possible to multiply one first data item by three or more second data items, as will be described in detail later.

[0092] The calculation cell IM includes, for example, a transistor MA_1, a transistor MA_2, a transistor MB_1, a transistor MB_2, a transistor MC, a capacitor CA_1, and a capacitor CA_2.

[0093] The transistors MA_1, MA_2, and MC each function as a write transistor (sometimes called a hold transistor) in the operation cell IM, and the transistors MB_1 and MB_2 each function as a transistor (sometimes called an amplifying transistor) for outputting the multiplication result of the multiplier and the multiplicand.

[0094] 1 , the transistors MA_1, MA_2, MB_1, MB_2, and MC are preferably OS transistors, for example. In particular, examples of metal oxides in the channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from indium, an element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0095] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail in Embodiment 3.

[0096] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider a two-layer oxide layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0097] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0098] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0099] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (for example, 1° C. or higher and 30° C. or lower). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0100] In particular, by using transistors including the oxide in their semiconductor layers as the transistors MA_1, MA_2, and MC, the off-state current of each of the transistors MA_1, MA_2, and MC can be extremely small. As described above, the transistors MA_1, MA_2, and MC each function as a write transistor for storing first data in the calculation cell IM. Therefore, it is preferable to use an OS transistor with extremely low off-state current as each of the transistors MA_1, MA_2, and MC.

[0101] The transistors MA_1, MA_2, MB_1, MB_2, and MC can be, other than OS transistors, transistors whose channel formation regions contain silicon (hereinafter referred to as Si transistors). Si transistors have higher on-state current than OS transistors and are therefore suitable for passing large currents.

[0102] Furthermore, for each of the transistors MA_1, MA_2, MB_1, MB_2, and MC, in addition to an OS transistor and a Si transistor, a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region can be used.

[0103] The first terminal of transistor MA_1 is connected to the gate of transistor MB_1 and the capacitor CA_1. The second terminal of transistor MA_1 is connected to the first terminal of transistor MA_2, the gate of transistor MB_2, and the first terminal of capacitor CA_2. The gate of transistor MA_1 is connected to wiring WSL. The second terminal of transistor MA_2 is connected to the first terminal of transistor MC and the first terminal of capacitor CB. The gate of transistor MA_2 is connected to wiring WSL. The second terminal of transistor MC is connected to wiring WCL, and the gate of transistor MC is connected to wiring WSL. The first terminal of transistor MB_1 is connected to wiring VE1, and the second terminal of transistor MB_1 is connected to wiring IL_1. The first terminal of transistor MB_2 is connected to wiring VE1, and the second terminal of transistor MB_2 is connected to wiring IL_2.

[0104] A second terminal of the capacitor CA_1 is connected to the wiring XCL_1, a second terminal of the capacitor CA_2 is connected to the wiring XCL_2, and a second terminal of the capacitor CB is connected to the wiring SEL.

[0105] 1, the connection point between the first terminal of transistor MA_1, the gate of transistor MB_1, and the capacitor CA_1 is indicated as node N1. The connection point between the second terminal of transistor MA_1, the first terminal of transistor MA_2, the gate of transistor MB_2, and the first terminal of capacitor CA_2 is indicated as node N2. The connection point between the first terminal of transistor MC, the second terminal of transistor MA_2, and the second terminal of capacitor CB is indicated as node NA.

[0106] The driver circuit WCD is connected to the wiring WCL. The driver circuit XCD is connected to the wirings XCL_1 and XCL_2. The driver circuit WSD is connected to the wiring WSL. The driver circuit SED is connected to the wiring SEL. The driver circuit ITS is connected to the wirings IL_1, IL_2, OL_1, and OL_2.

[0107] The wiring WCL functions as a wiring for applying a potential corresponding to the first data to the operation cell IM. Note that, as will be described in detail later, this potential is generated by the drive circuit WCD.

[0108] For example, the wiring XCL_1 functions as a wiring for supplying a potential corresponding to one of the two second data to the calculation cell IM. Also, for example, the wiring XCL_2 functions as a wiring for supplying a potential corresponding to the other of the two second data to the calculation cell IM. Note that the potentials corresponding to both of the second data are generated by the driving circuit XCD.

[0109] For example, the wiring WSL functions as a wiring for transmitting a selection signal for selecting the processing cell IM into which the first data is to be written. The selection signal is generated by the driving circuit WSD.

[0110] For example, the wiring SEL functions as a wiring for applying a fixed potential or a variable potential, which is generated by the driver circuit SED.

[0111] For example, the wiring IL_1 functions as a wiring for supplying a current corresponding to the multiplication of the first data and one of the two second data output from the processing cell IM. The wiring IL_2 functions as a wiring for supplying a current corresponding to the multiplication of the first data and the other of the two second data output from the processing cell IM. The current corresponding to each multiplication flows to the drive circuit ITS.

[0112] For example, the wiring VE1 functions as a wiring that applies a fixed potential. Specifically, the wiring VE1 functions as a wiring that applies the fixed potential to each of the transistors MB_1 and MB_2. In particular, the fixed potential is set to a potential within a range in which each of the transistors MB_1 and MB_2 operates in a subthreshold region. Specifically, the fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, or the like. Alternatively, depending on the situation, the fixed potential can be a high-level potential, a positive potential, or the like.

[0113] The driving circuit WCD has a function as a driving circuit for writing first data to the computation cell IM. Specifically, for example, the driving circuit WCD has a function of acquiring first data W, which is digital data, from the outside, converting the first data W into an analog potential, and outputting the analog potential to the wiring WCL.

[0114] 1, the drive circuit WCD includes, for example, a circuit WCDa and a switch SW1. An output terminal of the circuit WCDa is connected to a first terminal of the switch SW1, and a second terminal of the switch SW1 is connected to the wiring WCL. Furthermore, a control terminal of the switch SW1 is connected to the wiring SWL1.

[0115] The switch SW1 can be, for example, an electrical switch such as an analog switch or a transistor. In particular, the above-described transistor is preferably used as the electrical switch for the switch SW1, and an OS transistor is more preferably used. When an electrical switch is used for the switch SW1, a Si transistor or the like can be used as the electrical switch other than an OS transistor. Alternatively, a mechanical switch, for example, can be used for the switch SW1.

[0116] In this specification, the switch SW1 shown in FIG. 1 is assumed to be in an on state when a high-level potential is applied to the control terminal, and in an off state when a low-level potential is applied to the control terminal.

[0117] The wiring SWL1 functions as a wiring for transmitting a signal for controlling switching between the on state and the off state of the switch SW1.

[0118] For example, the circuit WCDa has a function of converting digital data input to an input terminal into an analog potential and outputting the analog potential to an output terminal, and therefore preferably includes a digital-to-analog converter circuit.

[0119] In particular, the analog potential output from the circuit WCDa is set to a potential within a range in which the transistors MB_1 and MB_2 operate in the subthreshold region. Therefore, in the above-described digital-to-analog converter circuit, the first data is set to W as the digital data input to the input terminal, and the potential output to the output terminal is set to V. Ｗ Then, W and V Ｗ The relationship between V and V satisfies the following formula (1.1). Ｗ is proportional to log{W}. In this specification, the expression log{A} indicates the natural logarithm of A.

[0120]

[0121] When W is 0, it is preferable that the circuit WCDa outputs a ground potential or a negative potential from the output terminal.

[0122] When writing the first data W to the computation cell IM, the circuit WCDa acquires the first data W, which is digital data, from the outside and converts the first data W into an analog potential. After that, a high-level potential is applied to the wiring SWL1 to turn on the switch SW1, and the first data W, which is an analog potential output from the output terminal of the circuit WCDa, is transmitted to the wiring WCL.

[0123] After the first data W has been written to the computation cell IM, it is preferable to apply a low-level potential to the wiring SWL1 to turn off the switch SW1, thereby increasing the impedance of the output terminal of the circuit WCDa, stopping the transmission of the first data W from the output terminal of the circuit WCDa to the wiring WCL, and reducing the power consumption of the circuit WCDa.

[0124] The driving circuit XCD has a function as a driving circuit for transmitting two pieces of second data to the operation cell IM. Specifically, for example, the driving circuit XCD receives two pieces of second data X １ and X ２ Get X １ and X ２ and a function of converting the first data and the second data into an analog potential, and a function of converting the first data and the second data into an analog potential. １ is output to the wiring XCL_1, and X ２ to the wiring XCL_2.

[0125] The driver circuit XCD also has a function of applying a reference potential to the wirings XCL_1 and XCL_2 when the first data W is written to the computation cell IM.

[0126] 1, the driver circuit XCD includes, for example, a circuit XVG_1 and a circuit XVG_2. Note that in this specification, the circuits XVG_1 and XVG_2 are collectively referred to as a circuit XCDa.

[0127] Each of the circuits XVG_1 and XVG_2 has a first input terminal, a second input terminal, and an output terminal. The second input terminals of the circuits XVG_1 and XVG_2 are connected to the wiring EN, the output terminal of the circuit XVG_1 is connected to the wiring XCL_1, and the output terminal of the circuit XVG_2 is connected to the wiring XCL_2.

[0128] For example, each of the circuits XVG_1 and XVG_2 has a function of converting second data, which is digital data input to a first input terminal, into an analog potential and generating the analog potential. Therefore, each of the circuits XVG_1 and XVG_2 preferably includes a digital-to-analog converter. As will be described in detail later, the circuit XVG_1 outputs an analog potential, which can change the potential of the node N1 through capacitive coupling by the capacitor CA_1. Similarly, the circuit XVG_2 outputs an analog potential, which can change the potential of the node N2 through capacitive coupling by the capacitor CA_2. In particular, the potential of the node N1 that changes due to capacitive coupling by the capacitor CA_1 is set to a potential within a range in which the transistor MB_1 operates in the subthreshold region. Similarly, the potential of the node N2 that changes due to capacitive coupling by the capacitor CA_2 is set to a potential within a range in which the transistor MB_2 operates in the subthreshold region.

[0129] As an example, each of the circuits XVG_1 and XVG_2 has a function of outputting a reference potential from an output terminal when a first signal is input to a second input terminal, and a function of outputting an analog potential, which is the second data input to the first input terminal, from an output terminal when a second signal is input to the second input terminal.

[0130] That is, when the first data W is written in the arithmetic cell IM, the circuits XVG_1 and XVG_2 apply a reference potential to the wirings XCL_1 and XCL_2, and when the first data W is multiplied by the second data W in the arithmetic cell IM, the circuits XVG_1 and XVG_2 apply a reference potential to the wirings XCL_1 and XCL_2. １ An analog potential corresponding to ２ It gives an analog voltage according to

[0131] The driver circuit WSD has a function of applying a selection signal to the wiring WSL when selecting a computation cell IM to which the first data is to be written, in order to turn on the write transistors MA_1, MA_2, and MC. The driver circuit WSD also has a function of applying a non-selection signal to the wiring WSL of a computation cell IM to which the first data is not to be written, in order to turn off the transistors MA_1, MA_2, and MC. In the circuit configuration of FIG. 1, the selection signal is preferably set to a high potential and the non-selection signal is preferably set to a low potential.

[0132] As an example, the drive circuit SED has a function of generating a fixed potential or a variable potential to be applied to the second terminal of the capacitance element CB provided in the processing cell IM.

[0133] For example, the driver circuit ITS receives the first data W output by the processing cell IM and one of the two second data X １ The amount of current corresponding to the multiplication with is obtained, and the activation function F is calculated using the amount of current as an input value, and the output data Z １ = F (W x X １ ) that flows through the wiring IL_2. ２ The amount of current corresponding to the multiplication with is obtained, and the activation function F is calculated using the amount of current as an input value, and the output data Z ２ = F (W x X ２ ) is also available.

[0134] The activation function is a function that determines the magnitude of the value output by a neuron in an artificial neural network model. The activation function may be a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. A configuration example of the driver circuit ITS that performs the ReLU function calculation will be described later.

[0135] In the calculation device CDV, when it is not necessary to perform the calculation of the activation function by the driving circuit ITS, the driving circuit ITS calculates the first data W and one of the two second data X １ The current corresponding to the multiplication of １ =WX １ and the first data W and the other of the two second data X ２ The current corresponding to the multiplication of ２ =WX ２ Alternatively, if it is not necessary to perform the calculation of the activation function by the driving circuit ITS, the calculation device CDV may be configured not to include the driving circuit ITS.

[0136] 1 , the driver circuit ITS includes, for example, a circuit ITSa_1, a circuit ITSa_2, a switch SW2_1, and a switch SW2_2. A first terminal of the switch SW2_1 is connected to a wiring IL_1, a second terminal of the switch SW2_1 is connected to an input terminal of the circuit ITSa_1, and a control terminal of the switch SW2_1 is connected to a wiring SWL2. A first terminal of the switch SW2_2 is connected to a wiring IL_2, a second terminal of the switch SW2_2 is connected to an input terminal of the circuit ITSa_2, and a control terminal of the switch SW2_2 is connected to a wiring SWL2. An output terminal of the circuit ITSa_1 is connected to a wiring OL_1, and an output terminal of the circuit ITSa_2 is connected to a wiring OL_2.

[0137] For example, the switches applicable to the switch SW1 can be used as the switches SW2_1 and SW2_2. Therefore, the description of the switch SW1 can be referred to for the switches SW2_1 and SW2_2.

[0138] The wiring SWL2 functions as a wiring for transmitting a signal for controlling switching between the on state and the off state of the switches SW2_1 and SW2_2.

[0139] For example, each of the circuits ITSa_1 and ITSa_2 has a function of calculating an activation function using a value corresponding to the amount of current input to an input terminal as an input value, and also has a function of converting the result of the calculation into digital data, an analog potential, or an analog current and outputting the result to an output terminal.

[0140] Next, an example of the configuration of the drive circuit XCD and the drive circuit ITS for driving the processing cell IM will be described.

[0141] <<Driver Circuit XCD>> An example of the configuration of the circuit XCDa provided in the driver circuit XCD of FIG. 1 will be described.

[0142] 2A is an example of a circuit configuration that can be applied to the circuit XCDa shown in FIG. 1 and is also an example of a circuit configuration of the circuits XVG_1 and XVG_2. Each of the circuits XVG_1 and XVG_2 includes an inverter INV, a switch SWX1, a switch SWX2, and a digital-to-analog conversion circuit XDAC.

[0143] In each of the circuits XVG_1 and XVG_2, the output terminal of the digital-to-analog conversion circuit XDAC is connected to a first terminal of the switch SWX2. The output terminal of the inverter INV is connected to a control terminal of the switch SWX2. The first terminal of the switch SWX1 is connected to the wiring VRE.

[0144] In the circuit XVG_1, the second terminal of the switch SWX1 and the second terminal of the switch SWX2 are connected to the output terminal of the circuit XVG_1, and the output terminal of the circuit XVG_1 is connected to the wiring XCL_1. The input terminal of the digital-to-analog conversion circuit XDAC is connected to the first input terminal of the circuit XVG_1. The first input terminal of the circuit XVG_1 is connected to one of the two second data, XCL_1. １ In addition, the control terminal of the switch SWX1 and the input terminal of the inverter INV are connected to the second input terminal of the circuit XVG_1.

[0145] In the circuit XVG_2, the second terminal of the switch SWX1 and the second terminal of the switch SWX2 are connected to the output terminal of the circuit XVG_2, and the output terminal of the circuit XVG_2 is connected to the wiring XCL_2. The input terminal of the digital-to-analog conversion circuit XDAC is connected to the first input terminal of the circuit XVG_2. The other of the two second data, X ２ In the circuit XVG_2, the control terminal of the switch SWX1 and the input terminal of the inverter INV are connected to the second input terminal of the circuit XVG_2.

[0146] The second input terminals of the circuits XVG_1 and XVG_2 are connected to the wiring EN.

[0147] The digital-analog conversion circuit XDAC has a function of converting digital data input to an input terminal into an analog potential and outputting the analog potential to an output terminal.

[0148] In particular, the analog potential output from the digital-analog conversion circuit XDAC is set to a potential within a range in which each of the transistors MB_1 and MB_2 operates in a subthreshold region. Therefore, in the above-described digital-analog conversion circuit, the second data is set to X (X １ or X ２ The potential output to the output terminal is V Ｘ When X and V are Ｘ The relationship between V and V satisfies the following formula (1.2). Ｘ is proportional to log{X}.

[0149]

[0150] When X is 0, it is preferable that the digital-to-analog conversion circuit XDAC outputs a ground potential or a negative potential from the output terminal.

[0151] For example, the wiring VRE functions as a wiring that provides a reference potential to be input to the second terminal of the capacitor CA_1 and the second terminal of the capacitor CA_2 when first data is written to the calculation cell IM.

[0152] As the reference potential, for example, when digital data of X=1 is input to the input terminal of the digital-to-analog conversion circuit XDAC, an analog potential V Ｘ That is, the reference potential is preferably equal to the analog potential V corresponding to the value "1" of the second data in the digital-to-analog conversion by the digital-to-analog conversion circuit XDAC. Ｘ In the following description, the reference potential given by the wiring VRE is preferably equal to V ＸＵＴ It is written as follows.

[0153] The wiring EN functions as a wiring for transmitting a signal for controlling the switching between the on state and the off state of the switches SWX1 and SWX2.

[0154] For example, when a high-level potential is input to the wiring EN as a first signal, the high-level potential is input to the control terminal of the switch SWX1, and a low-level potential converted from the high-level potential by the inverter INV is input to the control terminal of the switch SWX2. As a result, the switch SWX1 is turned on, and the switch SWX2 is turned off. Therefore, conduction is established between the wiring VRE and the wirings XCL_1 and XCL_2, and the reference potential from the wiring VRE is applied to each of the wirings XCL_1 and XCL_2.

[0155] At this time, the switch SWX2 is turned off, so that the impedance of the output terminal of the digital-analog conversion circuit XDAC increases, and the transmission of the second data from the output terminal of the digital-analog conversion circuit XDAC to the wiring XCL_1 or XCL_2 can be stopped, thereby reducing the power consumption of the digital-analog conversion circuit XDAC.

[0156] Furthermore, for example, when a low-level potential is input to the wiring EN as a second signal, the low-level potential is input to the control terminal of the switch SWX1, and a high-level potential converted from the low-level potential by the inverter INV is input to the control terminal of the switch SWX2. As a result, the switch SWX1 is turned off, and the switch SWX2 is turned on. Therefore, conduction is established between the output terminal of the digital-analog conversion circuit XDAC and the wirings XCL_1 and XCL_2. Therefore, in the circuit XVG_1, one of the two second data signals XCL_1 and XCL_2 output from the output terminal of the digital-analog conversion circuit XDAC is input to the wiring XCL_1. １ Analog potential V according to Ｘ１ Similarly, in the circuit XVG_2, the wiring XCL_2 is connected to one of the two second data signals X ２ Analog potential V according to Ｘ２ is given.

[0157] During the writing of the first data to the computation cell IM, the switch SW1 is turned on, and a high-level potential is applied to the wiring SWL1. At this time, a high-level potential is input to the wiring EN as a first signal, turning the switch SWX1 on and the switch SWX2 off. Therefore, when the driver circuit WCD of FIG. 1 and the circuit XCDa of FIG. 2 are provided in the same location, the wiring SWL1 and the wiring EN can be the same wiring. This allows the signals input to the wiring SWL1 and the wiring EN to be the same, thereby reducing the number of signals for driving the computation cell IM. Reducing the number of signals allows the number of circuits that generate these signals to be reduced, thereby reducing the circuit area of ​​a semiconductor device having the computation cell IM.

[0158] 2A illustrates a configuration in which the circuit XCDa includes an inverter INV in each of the circuit XVG_1 and the circuit XVG_2, but the configuration of the circuit XCDa in the arithmetic circuit of one embodiment of the present invention is not limited to the circuit configuration in FIG. 2A. For example, the configuration of the circuit XCDa in the arithmetic circuit of one embodiment of the present invention can be the circuit configuration of the circuit XCDa illustrated in FIG. 2B.

[0159] The circuit XCDa in Fig. 2B has a circuit configuration in which the multiple inverters INV included in the circuit XCDa in Fig. 2A are combined into one. Therefore, the input terminal of the inverter INV is connected to the control terminal of the switch SWX1 of each of the circuits XVG_1 and XVG_2, and the output terminal of the inverter INV is connected to the control terminal of the switch SWX2 of each of the circuits XVG_1 and XVG_2.

[0160] As in the circuit XCDa of FIG. 2B, by reducing the number of inverters INV to one, the circuit area of ​​the circuit XCDa can be reduced.

[0161] <<Driver Circuit ITS>> Next, a configuration example of the circuit ITSa_1 and the circuit ITSa_2 included in the driver circuit ITS in FIG. 1 will be described.

[0162] 3A is an example of a circuit configuration that can be applied to the circuits ITSa_1 and ITSa_2 shown in FIG. 1. The circuit ITSa includes a circuit FC and a conversion circuit CVT. Note that in FIG. 3A, a wiring IL, a wiring SWL2, a wiring OL, and a switch SW2 are also shown to explain the connection configuration of the circuit ITSa.

[0163] The wiring IL corresponds to the wiring IL_1 or IL_2 shown in Fig. 1, and the wiring OL corresponds to the wiring OL_1 or OL_2 shown in Fig. 1. The switch SW2 corresponds to the switch SW2_1 or SW2_2 shown in Fig. 1.

[0164] The input terminal of the circuit FC is connected to the input terminal of the circuit ITSa, and the output terminal of the circuit FC is connected to the input terminal of the conversion circuit CVT, and the output terminal of the conversion circuit CVT is connected to the output terminal of the circuit ITSa.

[0165] The first terminal of the switch SW2 is connected to the wiring IL, the second terminal of the switch SW2 is connected to the input terminal of the circuit ITSa, and the control terminal of the switch SW2 is connected to the wiring SWL2. The wiring OL is connected to the output terminal of the circuit ITSa.

[0166] 3A is a circuit that performs the above-described activation function calculation. Specifically, the circuit FC, for example, acquires the amount of current flowing through the wiring IL and performs the activation function calculation using a value corresponding to the amount of current as an input value. Furthermore, the circuit FC, for example, outputs the result of the calculation as a current to an output terminal of the circuit FC.

[0167] 3A has a function of acquiring a current output from the circuit FC flowing into the input terminal of the conversion circuit CVT and generating a digital value or an analog potential according to the amount of the current. In other words, the conversion circuit CVT has a function of converting the result of the calculation by the circuit FC into data in the form of a digital value or an analog potential. The conversion circuit CVT also has a function of outputting the data to the output terminal of the circuit ITSa. Therefore, for example, a current-voltage conversion circuit can be applied to the conversion circuit CVT.

[0168] As described above, the circuit ITSa can use the result of the multiplication calculated in the operation cell IM to calculate the activation function and output the result to the wiring OL.

[0169] Next, a specific example of the configuration of the circuit FC included in the circuit ITSa in FIG. 3A will be described.

[0170] FIG. 3D is a circuit diagram showing, as an example, a specific configuration of the circuit FC included in the circuit ITSa of FIG. 3A, and the circuit FC of FIG. 3D has a function of performing the calculation of the ReLU function.

[0171] The circuit FC shown in FIG. 3D includes, as an example, transistors MP1i, MP1o, transistors MP2i, MP2o, transistors MP3i, MP3o, transistors MP4i, MP4o, transistors MN1i, MN1o, transistors MN2i, MN2o, and a constant current source CNI.

[0172] 3D, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o. A second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o. A third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o.

[0173] The drain of transistor MP1i is connected to wiring IL, and the drain of transistor MP1o is connected to the input terminal of constant current source CNI and the drain of transistor MN2i. The drain of transistor MN2o is connected to the drain of transistor MP3i. Transistor MP3o is connected to the output terminal of circuit FC. The output terminal of constant current source CNI is connected to wiring VGE.

[0174] For example, the wiring VGE functions as a wiring that applies a fixed potential. The fixed potential may be, for example, a low-level potential, a negative potential, a ground potential, etc. Depending on the situation, the fixed potential applied by the wiring VGE may be a high-level potential, a positive potential, etc.

[0175] The first current mirror circuit ideally has a function of passing a current between the source and drain of transistor MP2o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has a function of passing a current between the source and drain of transistor MN1o that is equal to the source-drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has a function of passing a current between the source and drain of transistor NP4o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP4i.

[0176] In the first current mirror circuit, the transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of the transistor MP2i due to drain-induced barrier lowering (DIBL). Similarly, the transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of the transistor MP2o due to drain-induced barrier lowering. Therefore, the gates of the transistors MP1i and MP1o are connected to a wiring RSWL1 that applies a desired bias potential.

[0177] In the second and third current mirror circuits, the transistors MN2i, MN2o, MP3i, and MP3o also function as clamp transistors to prevent a decrease in the threshold voltage of the transistors connected in series due to a drain-induced barrier lowering. In this case, the wirings RSWL2 and RSWL3 each function as wirings that apply a desired bias potential.

[0178] The bias potentials applied to the wirings RSWL1 to RSWL3 can be made equal to each other, so that the wirings RSWL1 to RSWL3 can be the same wiring.

[0179] Each of the transistors MP1i and MP1o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MP1i and MP1o. Furthermore, by turning off each of the transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing power consumption in the circuit FC.

[0180] Similarly, by making the transistors MN2i and MN2o function as switching transistors, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL2 function as wiring for controlling the switching between the on and off states of the transistors MN2i and MN2o. Similarly, by making the transistors MP3i and MP3o function as switching transistors, it is possible to stop the third current mirror circuit at a desired timing. In this case, it is preferable that the wiring RSWL3 function as wiring for controlling the switching between the on and off states of the transistors MP3i and MP3o.

[0181] Note that the transistors MP1i and MP1o, and the transistors MP3i and MP3o can be simultaneously turned on or off. Therefore, the wiring RSWL1 and the wiring RSWL3 can be the same wiring.

[0182] In the first current mirror circuit, the source of the transistor MP2i and the source of the transistor MP2o are each connected to a wiring VDE. The first current mirror circuit is configured with p-channel transistors, and therefore also functions as a current source circuit. Therefore, the wiring VDE functions as a wiring that provides a high-level potential as a high power supply potential for the first current mirror circuit. Similarly, the third current mirror also functions as a current source circuit, and therefore the high-level potential provided by the wiring VDE also functions as a high power supply potential for the third current mirror circuit.

[0183] In the second current mirror circuit, the source of the transistor M1i and the source of the transistor MN1o are connected to a wiring VSE. The second current mirror circuit is configured with n-channel transistors, and therefore also functions as a current sink circuit. Therefore, the wiring VSE functions as a wiring that provides a low-level potential as a low power supply potential of the second current mirror circuit.

[0184] The constant current source CNI is, for example, a constant current I ＩＢ The current flows from the drains of the transistors MP1o and MN2i to the wiring VGE.

[0185] When a high-level potential is applied to the line SWL2, the high-level potential is applied to the control terminal of the switch SW2, turning the switch SW2 on. At this time, the line IL is supplied with an amount I corresponding to the value multiplied by the operation cell IM. ＩＬ Therefore, a current of the amount I flows from the wiring VDE to the wiring IL. ＩＬ Therefore, the amount of the source-drain current of the transistor MP2o is also I ＩＬ This becomes:

[0186] Also, when the constant current source CNI is operating, I ＩＬ =I ＩＢ +I ＯＬ is established. Note that I ＯＬis the amount of current flowing between the source and drain of the transistor MN1i. Therefore, the amount of source-drain current of the transistor MN1o is also I ＯＬ This becomes:

[0187] The amount of source-drain current of the transistor MN1o is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4i is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4o is also I ＯＬ The input terminal of the conversion circuit CVT is connected to the quantity I ＯＬ A current of flows.

[0188] The circuit FC is ＩＬ Ga I Ｂ If it is greater than , the difference is the amount I ＯＬ A current of I flows through the input terminal of the conversion circuit CVT. ＩＬ Ga I Ｂ When the following condition is satisfied, the current flowing between the input terminal and the output terminal of the constant current source CNI is I ＩＬ And also, I ＯＬ = 0. In this case, no current flows from the circuit FC to the input terminal of the conversion circuit CVT. In other words, the ReLU function can be calculated by the circuit FC shown in FIG.

[0189] In the circuit ITSa of FIG. 3A, the data output to the wiring OL may be an analog current instead of a digital value or an analog potential. In this case, it is preferable to use a configuration in which the conversion circuit CVT is not provided, as in the circuit ITSa of FIG. 3B, instead of the circuit ITSa of FIG. 3A. Since the conversion circuit CVT is not provided in the circuit ITSa of FIG. 3B, the circuit area of ​​the driver circuit ITS can be reduced by using the circuit ITSa of FIG. 3B. Furthermore, the power consumption for driving the conversion circuit CVT can be reduced.

[0190] 3A , the circuit ITSa may be configured to convert the amount of current flowing through the wiring IL into a digital value or an analog potential, and then use the converted digital value or analog potential as an input value to calculate the activation function, rather than converting the result of the calculation into a digital value or an analog potential. Specifically, the circuit ITSa in FIG. 3A can be configured as the circuit ITSa in FIG. 3C.

[0191] The circuit ITSa shown in Figure 3C is configured such that the input terminal of the conversion circuit CVT is connected to the input terminal of the circuit ITSa, the output terminal of the conversion circuit CVT is connected to the input terminal of the circuit FC, and the output terminal of the circuit FC is connected to the output terminal of the circuit ITSa.

[0192] <Example of Operation of Arithmetic Circuit> Next, an example of the operation method of the arithmetic cell IM will be described.

[0193] 4 is a timing chart illustrating an example of the operation method of the arithmetic cell IM in FIG. 4. The timing chart in FIG. 4 shows fluctuations in the potentials of the wirings SWL1, SWL2, EN, WCL, WSL, XCL_1, XCL_2, SEL, the node N1, the node N2, and the node NA during or near the periods T1 to T8. The timing chart in FIG. 4 also shows fluctuations in the amount of current flowing through the wiring IL_1 and the amount of current flowing through the wiring IL_2.

[0194] It is also assumed that the circuit XCDa shown in Fig. 2A is applied as the circuit XCDa included in the drive circuit XCD that drives the computation cell IM in Fig. 1. It is also assumed that the circuit ITSa included in the drive circuit ITS shown in Fig. 1 is applied as the circuit ITSa shown in Fig. 3A and Fig. 3D.

[0195] In this example of operation, the potential given by the wiring VE1 is equal to the ground potential V Ｇ The potential applied to the wiring SEL by the driver circuit SED is a reference potential V ＸＵＴ , or the reference potential V ＸＵＴ Higher V than ＢBefore the period T1, the potentials of the wirings IL_1 and IL_2 are set to the ground potential V Ｇ Let's say.

[0196] [Period T1] During the period T1, the wiring SWL1 is supplied with a low-level potential V Ｌ is applied to the wiring SWL2, and a low-level potential V Ｌ is applied to the wiring EN, and a low-level potential V Ｌ Further, the driver circuit SED shown in FIG. 1 applies a reference potential V ＸＵＴ is given.

[0197] The wiring SWL1 is V Ｌ is given, so that the control terminal of the switch SW1 is V Ｌ is applied to the wiring SWL2, turning the switch SW1 off. Ｌ is given to the control terminals of the switches SW2_1 and SW2_2, V Ｌ is applied, and the switches SW2_1 and SW2_2 are each turned off.

[0198] In addition, the wiring EN has V Ｌ , in the circuit XCDa of FIG. 2A, the control terminals of the switches SWX1 of the circuits XVG_1 and XVG_2 are connected to V Ｌ is applied to the control terminals of the switches SWX2 of the circuits XVG_1 and XVG_2, turning them off. Ｌ The logic of the high-level potential V Ｈ are applied, and each switch SWX2 is turned on.

[0199] At this time, digital data of value "0" is input to the input terminals of the digital-analog conversion circuits XDAC of the circuits XVG_1 and XVG_2, and the ground potential V Ｇ In other words, in this example of operation, the analog potential corresponding to the digital data of value "0" is set to the ground potential V ＧTherefore, V is output from the output terminal of the digital-to-analog conversion circuit XDAC of each of the circuits XVG_1 and XVG_2. Ｇ is output, and V is supplied to each of the wirings XCL_1 and XCL_2 via the switch SWX2. Ｇ is given.

[0200] The wiring SEL is V Ｇ is given, the potential of the second terminal of the capacitance element CB of the calculation cell IM is V Ｇ This becomes:

[0201] During the period T1, the wiring WCL is in a floating state, and in this operation example, the wiring WCL is connected to the ground potential V Ｇ It is assumed that the above is true.

[0202] In addition, during the period T1, the potentials of the nodes N1, N2, and NA are indefinite, and are indicated by hatching in the timing chart of FIG.

[0203] In addition, in the period T1, the switches SW2_1 and SW2_2 are both off, so no current flows through the wirings IL_1 and IL_2. Specifically, the source-drain current of each of the transistors MB_1 and MB_2 included in the processing cell IM is zero. At this time, the wirings IL_1 and IL_2 are supplied with the same ground potential V as the potential of the wiring VE1. Ｇ is given, and it is preferable that the voltage between the source and drain of each of the transistors MB_1 and MB_2 is set to 0.

[0204] Also, it is assumed that the first data W is input as digital data to the driving circuit WCD. As a result, the first data W is converted from digital data to an analog potential V by a circuit WCDa included in the driving circuit WCD. Ｗ and V is input to the output terminal of the circuit WCDa. Ｗ will be output.

[0205] [Period T2] In the period T2, the wiring SWL1 is supplied with a high-level potential V Ｈ is applied to the wiring EN, and a high-level potential V Ｈis given.

[0206] The wiring SWL1 is V Ｈ is given, so that the control terminal of the switch SW1 is V Ｈ is applied to the switch SW1, turning it on. As a result, the output terminal of the circuit WCDa and the wiring WCL are electrically connected, and V Ｗ is given.

[0207] In addition, the wiring EN has V Ｈ , in the circuit XCDa of FIG. 2A, the control terminals of the switches SWX1 of the circuits XVG_1 and XVG_2 are connected to V Ｈ is applied to the control terminals of the switches SWX2 of the circuits XVG_1 and XVG_2, and the high-level potential V Ｈ The logic of the low-level potential V Ｌ are applied, and each switch SWX2 is turned off.

[0208] Therefore, the wiring VRE and the wiring XCL_1 are electrically connected, and the wiring XCL_1 is supplied with the reference potential V ＸＵＴ Similarly, conduction is established between the wiring VRE and the wiring XCL_2, and the reference potential V ＸＵＴ is given.

[0209] [Period T3] In the period T3, the wiring WSL is supplied with a high-level potential V Ｈ Therefore, V is applied to the gates of the transistors MA_1, MA_2, and MC. Ｈ is applied, and the transistors MA_1, MA_2, and MC are turned on.

[0210] Since the transistors MA_1, MA_2, and MC are turned on, electrical continuity is established between the wiring WCL and the node N1 via the nodes NA and N2. As a result, the potential V Ｗ is applied, and the potentials of the nodes NA, N2, and N1 are set to the same V as that of the wiring WCL. Ｗ This becomes:

[0211] At this time, the gate-source voltages of the transistors MB_1 and MB_2 are V Ｗ -V Ｇ In the periods T1 to T4 of this operation example, the potentials of the wirings IL_1 and IL_2 are set to V Ｇ Therefore, the source-drain voltage of each of the transistors MB_1 and MB_2 is 0 V. Therefore, in the periods T1 to T4, no current flows between the source and drain of each of the transistors MB_1 and MB_2.

[0212] Here, a case will be considered in which a high-level potential is applied to the wirings IL_1 and IL_2, a voltage is generated between the source and the drain of each of the transistors MB_1 and MB_2, and a subthreshold current flows through each of the transistors MB_1 and MB_2. ０ can be expressed as the following equation (1.3).

[0213]

[0214] In addition, I ａ is V Ｗ -V Ｇ V ｔｈ The source-drain current when V ｔｈ is the threshold voltage of the transistor MB_1 and the transistor MB_2. ｔｈ Furthermore, J is a correction coefficient determined by the temperature, device structure, etc. of each of the transistors MB_1 and MB_2.

[0215] The first data W can be written as in equation (1.4). ＵＴ is defined as in equation (1.5). By using equations (1.4) and (1.5), equation (1.3) can be rewritten as equation (1.6).

[0216]

[0217] [Period T4] In the period T4, the wiring WSL is supplied with a low-level potential V Ｌ Therefore, V is applied to the gates of the transistors MA_1, MA_2, and MC. Ｌ , and the transistors MA_1, MA_2, and MC are turned off. Ｗ is held by the capacitive element CB, the capacitive element CA_2, and the capacitive element CA_1.

[0218] In addition, the wiring WSL is supplied with a low-level potential V Ｌ After this, the wiring SWL1 is supplied with a low-level potential V Ｌ Therefore, the control terminal of the switch SW1 is supplied with V Ｌ is applied to the switch SW1, turning it off. This brings the output terminal of the circuit WCDa and the wiring WCL into a non-conductive state, so that the potential V Ｗ In this operation example, during the period T4, the potential of the wiring WCL is lowered to the ground potential V Ｇ This shows an example where the

[0219] [Period T5] During the period T5, the driver circuit SED shown in FIG. 1 applies a potential V Ｂ In addition, V Ｂ is V ＸＵＴ The potential is set to be higher than

[0220] The potential of the wiring SEL is V ＸＵＴ From V ＢWhen the capacitance coupling coefficient of the capacitance element CB is P, the potential of the node NA is V Ｗ From V Ｗ +P(V Ｂ -V ＸＵＴ ) In this specification and elsewhere, (V Ｂ -V ＸＵＴ ) = ΔV Ｂ It may be written as follows.

[0221] The potential of the node NA is V Ｗ From V Ｗ +P(V Ｂ -V ＸＵＴ ), it is possible to prevent a decrease in the potentials of the nodes N2 and N1 due to leakage currents in the transistors MC, MA_2, and MA_1. For example, when the leakage path of the charges of the nodes N1 and N2 is from the node N1 or N2 to the wiring WCL via the transistor MC, it is possible to prevent leakage of the charges from the node N1 or N2 by making the potential of the node NA higher than that of the nodes N1 and N2.

[0222] [Period T6] During the period T6, the wiring EN is supplied with a low-level potential V Ｌ Therefore, in the circuit XCDa of FIG. 2A, V is applied to the control terminal of the switch SWX1 of each of the circuits XVG_1 and XVG_2. Ｌ is applied to the control terminals of the switches SWX2 of the circuits XVG_1 and XVG_2, turning them off. Ｌ The logic of the high-level potential V Ｈ are applied, and each switch SWX2 is turned on.

[0223] At this time, the value X is input to the input terminal of the digital-to-analog conversion circuit XDAC of the circuit XVG_1. １ The digital data is input, and the output terminal of the digital-to-analog conversion circuit XDAC outputs X １ Analog potential V according toＸ１ Similarly, the value X is output to the input terminal of each digital-to-analog conversion circuit XDAC of the circuit XVG_2. ２ The digital data is input, and the output terminal of the digital-to-analog conversion circuit XDAC outputs X ２ Analog potential V according to Ｘ２ Therefore, the wiring XCL_1 is connected to the V output from the digital-to-analog conversion circuit XDAC of the circuit XVG_1. Ｘ１ is supplied via the switch SWX2, and the V output from the digital-to-analog conversion circuit XDAC of the circuit XVG_2 is supplied to the wiring XCL_2. Ｘ２ is provided via switch SWX2.

[0224] The potential of the wiring XCL_1 is V ＸＵＴ From V Ｘ１ When the capacitance coupling coefficient of the capacitance element CA_1 is P, which is the same as that of the capacitance element CB, the potential of the node N1 changes as follows: V Ｗ From V Ｗ +P(V Ｘ１ -V ＸＵＴ ) changes to

[0225] Similarly, when the potential of the wiring XCL_2 is V ＸＵＴ From V Ｘ２ When the capacitance coupling coefficient of the capacitor CA_2 is P, which is the same as that of the capacitors CB and CA_1, the potential of the node N2 changes as follows: V Ｗ From V Ｗ +P(V Ｘ２ -V ＸＵＴ ) changes to

[0226] In this specification, one of the two second data X １ can be written as in equation (1.7). Ｘ１ -V ＸＵＴ ΔV Ｘ１ In addition, the other of the two second data X ２can be written as in equation (1.8). Ｘ２ -V ＸＵＴ ΔV Ｘ２ is replaced with:

[0227]

[0228] [Period T7] In the period T7, the wiring SWL2 is supplied with a high-level potential V Ｈ Therefore, V is applied to the control terminals of the switches SW2_1 and SW2_2. Ｈ is applied, turning on the switches SW2_1 and SW2_2. As a result, electrical continuity is established between the input terminal of the circuit ITSa_1 and the wiring IL_1, and electrical continuity is established between the input terminal of the circuit ITSa_2 and the wiring IL_2.

[0229] At this time, the circuit ITSa_1 supplies V Ｇ Similarly, the circuit ITSa_2 applies a potential higher than V Ｇ A higher potential is applied.

[0230] Furthermore, the gate-source voltage of the transistor MB_1 during the period T7 continues to be V Ｗ +P(V Ｘ１ -V ＸＵＴ ) -V Ｇ Therefore, the source-drain current I １ can be written as in equation (1.9) by using equations (1.4), (1.5) and (1.7).

[0231]

[0232] That is, the source-drain current I of the transistor MB_1 １ is a first data W and one of two second data X １ In addition, in the period T7, a voltage is generated between the source and drain of the transistor MB_1, and therefore, a source-drain current I １ is playing.

[0233] Similarly, the gate-source voltage of the transistor MB_2 during the period T7 continues to be V Ｗ +P(V Ｘ２ -V ＸＵＴ ) -V Ｇ Therefore, the source-drain current I ２ can be written as in equation (1.10) by using equations (1.4), (1.5) and (1.8).

[0234]

[0235] That is, the source-drain current I of the transistor MB_2 ２ is the first data W and the other of the two second data X ２ In addition, in the period T7, a voltage is generated between the source and drain of the transistor MB_2, and therefore, the source-drain current I ２ is playing.

[0236] The amount of current flowing through the wiring IL_1 is I １ is treated as an input value of the circuit FC included in the circuit ITSa_1 of the driving circuit ITS. １ The value of the function Z according to １ Calculate and Z １ is output to the wiring OL_1. Similarly, the amount of current I ２ is treated as an input value of the circuit FC included in the circuit ITSa_2 of the driving circuit ITS. ２ The value of the function Z according to ２ Calculate Z ２ is output to the wiring OL_2.

[0237] Therefore, by using the calculation cell IM, the calculations of the following formulas (1.11) and (1.12) can be performed simultaneously. Note that F can be an activation function in the circuit FC included in the circuit ITSa_1 and the circuit ITSa_2.

[0238]

[0239] [Period T8] In the period T8, the wiring SWL2 is supplied with a low-level potential V Ｌ Therefore, V is applied to the control terminals of the switches SW2_1 and SW2_2. Ｌ is applied, turning off the switches SW2_1 and SW2_2. As a result, there is no continuity between the input terminal of the circuit ITSa_1 and the wiring IL_1, and there is no continuity between the input terminal of the circuit ITSa_2 and the wiring IL_2.

[0240] As a result, the current flowing from the circuit ITSa_1 to the wiring VE1 through the wiring IL_1 and the transistor MB_1 becomes 0. Similarly, the current flowing from the circuit ITSa_2 to the wiring VE1 through the wiring IL_2 and the transistor MB_2 becomes 0.

[0241] After the period T8, for example, the period T6 is entered, and two second data X １ and X ２ By changing the value of , it is possible to perform calculations of different equations (1.11) and (1.12). Also, for example, by moving to period T1, it is possible to rewrite the first data W held in the calculation cell IM and perform calculations of different equations (1.11) and (1.12).

[0242] Note that the operation method of the arithmetic circuit of one embodiment of the present invention is not limited to the timing chart in Fig. 4. The operation method of the arithmetic circuit of one embodiment of the present invention may be changed depending on the situation.

[0243] For example, when it is not necessary to hold the first data W held in the operation cell IM for a long period of time, specifically when the leakage currents of the transistors MA_1, MA_2, and MC are small, the operation during the period T5 can be omitted. Ｂ Since no voltage is applied, the power consumption during the operation of the processing cell IM can be reduced.

[0244] Furthermore, in the timing chart of FIG. 4, an example of an operation method for one arithmetic cell IM has been explained, but by providing a plurality of arithmetic cells IM in the arithmetic unit CDV, it is possible to perform a product-sum operation.

[0245] For example, as shown in Fig. 5, consider a calculation device CDVA in which the number of calculation cells IM is m, and calculation cells IM[1] to IM[m] are arranged in an m x 1 matrix. Note that the calculation cells IM[1] to IM[m] all have the same circuit configuration.

[0246] 5, the driver circuit XCD includes circuits XCDa[1] to XCDa[m] corresponding to the circuit XCDa shown in FIG. 1. Each of the circuits XCDa[1] to XCDa[m] includes a circuit XVG_1 and a circuit XVG_2.

[0247] The second terminals of the transistors MB_1 included in each of the calculation cells IM[1] to IM[m] are all connected to the wiring IL_1. The second terminals of the transistors MC included in each of the calculation cells IM[1] to IM[m] are all connected to the wiring WCL.

[0248] 5, wirings XCL[1]_1 to XCL[m]_1 corresponding to the wiring XCL_1 shown in FIG. 1 extend in the row direction, and wirings XCL[1]_2 to XCL[m]_2 corresponding to the wiring XCL_2 shown in FIG. 1 extend in the row direction. Also, in the arithmetic device CDVA shown in FIG. 5, wirings WSL[1] to WSL[m] corresponding to the wiring WSL shown in FIG. 1 extend in the row direction, and wirings SEL[1] to SEL[m] corresponding to the wiring SEL shown in FIG. 1 extend in the row direction.

[0249] In a computation cell IM[i] (not shown), where i is an integer greater than or equal to 1 and less than or equal to m, the gates of the transistors MA_1, MA_2, and MC are connected to a wiring WSL[i] (not shown). The second terminal of the capacitor CA_1 is connected to a wiring XCL[i]_1 (not shown), the second terminal of the capacitor CA_2 is connected to a wiring XCL[i]_2 (not shown), and the second terminal of the capacitor CB is connected to a wiring SEL[i] (not shown).

[0250] The wirings WSL[1] to WSL[m] are connected to the driver circuit WSD, the wirings SEL[1] to SEL[m] are connected to the driver circuit SED, and the wirings XCL[1]_1 to XCL[m]_1 and the wirings XCL[1]_2 to XCL[m]_2 are connected to the driver circuit XCD.

[0251] In particular, the wiring XCL[i]_1 is connected to the circuit XVG_1 in the circuit XCDa[i] included in the driver circuit XCD, and the wiring XCL[i]_2 is connected to the circuit XVG_2 in the circuit XCDa[i] included in the driver circuit XCD. Note that in FIG. 5, the circuits XVG_1 and XVG_2 included in the circuit XCDa[1] and the circuits XVG_1 and XVG_2 included in the circuit XCDa[m] are selectively illustrated.

[0252] In the calculation circuit shown in Figure 5, when writing first data to each of the calculation cells IM[1] to IM[m], it is preferable to sequentially send selection signals to the wirings WSL[1] to WSL[m], and send the desired first data to each calculation cell IM to which the selection signal is sent by the driving circuit WCD.

[0253] For example, the driver circuit WSD first applies a high-level potential as a selection signal to the wiring WSL[1] and a low-level potential as a non-selection signal to each of the wirings WSL[2] to WSL[m]. This turns on the transistors MA_1, MA_2, and MC of the computation cell IM[1] and turns off the transistors MA_1, MA_2, and MC of the computation cells IM[2] to IM[m]. At this time, the driver circuit WCD transmits the first data W[1] to the wiring WCL, thereby writing the first data W[1] to the computation cell IM[1]. Then, the driver circuit WCD applies a low-level potential as a non-selection signal to the wiring WSL[1], thereby turning off the transistors MA_1, MA_2, and MC of the computation cell IM[1].

[0254] Next, the driver circuit WSD applies a high-level potential as a selection signal to the wiring WSL[2] and a low-level potential as a non-selection signal to the wiring WSL[1] and the wirings WSL[3] to WSL[m]. This turns on the transistors MA_1, MA_2, and MC of the arithmetic cell IM[2] and turns off the transistors MA_1, MA_2, and MC of the arithmetic cell IM[1] and the arithmetic cells IM[3] to IM[m]. At this time, the driver circuit WCD transmits the first data W[2] to the wiring WCL, thereby writing the first data W[2] to the arithmetic cell IM[2]. Then, the driver circuit WCD applies a low-level potential as a non-selection signal to the wiring WSL[2]. This turns off the transistors MA_1, MA_2, and MC of the arithmetic cell IM[2].

[0255] As described above, by sequentially sending selection signals to wirings WSL[1] to WSL[m] and sequentially sending first data W[1] to first data W[m] from the driver circuit WCD to wirings WCL, the first data W[1] to first data W[m] can be written separately to each of the calculation cells IM[1] to IM[m].

[0256] Next, the driver circuit XCD transmits one of the two second data signals XCL[i]_1 to the wiring XCL[i]_2. １ [i] is given to the wiring XCL[i]_2, and one of the two second data X ２ [i] is given, and V is given to the wiring IL_1 and the wiring IL_2. Ｇ By applying a potential higher than W[i]X to the wiring VE1 from the wiring IL_1 through the transistor MB_1, the calculation cell IM[i] １ Current I according to the value of [i] １ [i] flows from the wiring IL_2 to the wiring VE1 via the transistor MB_2. ２ Current I according to the value of [i] ２ [i] plays.

[0257] Since all of the calculation cells IM[1] to IM[m] are connected to the wiring IL_1, the source-drain current I １ [1] to I １ Similarly, since all of the processing cells IM[1] to IM[m] are connected to the wiring IL_2, the source-drain current I of the transistor MB_2 of each of the processing cells IM[1] to IM[m] flows through the wiring IL_2. ２ [1] to I ２ At this time, the total current flowing through the wiring IL_1 is I １Ｓ The sum of the currents flowing through the wiring IL_2 is I ２Ｓ Then, I １Ｓ and I ２Ｓ can be expressed as the following equations (1.13) and (1.14), respectively.

[0258]

[0259] Therefore, the amount of current flowing through the wiring IL_1 is I Ｓ１ flows into the circuit ITSa_1, the circuit FC Ｓ１ The value of the function Z according to １ Calculate Z １ is output to the wiring OL_1. Similarly, the amount of current I ２ flows into the circuit ITSa_2, the circuit FC Ｓ２ The value of the function Z according to ２ Calculate Z ２ is output to the wiring OL_2.

[0260] This allows Z １ and Z ２ can be expressed as the following equations (1.15) and (1.16) using the above equations (1.11) and (1.12), respectively. In this way, by arranging the operation cells IM in an m×1 matrix, the first data W[1] to W[m] and one of the two second data X １ [1] to X １ [m], and the first data W[1] to W[m] and the other of the two second data X １ [1] to X １ This can be done simultaneously with the multiplication and addition operation with [m].

[0261]

[0262] 1 can be arranged in an m×n matrix (n is an integer equal to or greater than 1). For example, as shown in FIG. 6, consider a computing device CDVB having a cell array MCA provided with n columns, each column including m computing cells IM as shown in FIG. 5.

[0263] 6, the symbol [i, j] is added to the reference number of the calculation cell IM located at the address of row i, column j (j is an integer between 1 and n). Furthermore, calculation cells IM[1,1] to IM[m,n] have the same circuit configuration as calculation cell IM shown in Fig. 1, and the description of calculation cell IM in Fig. 1 can be referred to for the circuit configuration of each of calculation cells IM[1,1] to IM[m,n].

[0264] In addition, in the calculation device CDVB shown in Figure 6, the driver circuit WCD has circuits WCDa[1] to WCDa[n] corresponding to the circuit WCDa shown in Figure 1 and switches SW1[1] to SW1[n] corresponding to the switch SW1 shown in Figure 1.

[0265] 6, the driver circuit ITS includes circuits ITSa[1]_1 to ITSa[n]_1 corresponding to the circuit ITSa_1 shown in FIG. 1, circuits ITSa[1]_2 to ITSa[n]_2 corresponding to the circuit ITSa_2, switches SW2[1]_1 to SW2[n]_1 corresponding to the switch SW2_1 shown in FIG. 1, and switches SW2[1]_2 to SW2[n]_2 corresponding to the switch SW2_2 shown in FIG. 1.

[0266] 6, wirings WCL[1] to WCL[n] corresponding to the wiring WCL shown in Fig. 1 extend in the column direction. In addition, in the computing device CDVB shown in Fig. 6, wirings IL[1]_1 to IL[n]_1 corresponding to the wiring IL_1 shown in Fig. 1 extend in the column direction, and wirings IL[1]_2 to IL[n]_1 corresponding to the wiring IL_2 shown in Fig. 1 extend in the column direction.

[0267] In particular, the wiring WCL[j] is connected to the second terminal of the switch SW1[j], and the first terminal of the switch SW1[j] is connected to the output terminal of the circuit WCDa[1]. The wiring IL_1 is connected to the first terminal of the switch SW2[j]_1, and the second terminal of the switch SW2[j]_1 is connected to the input terminal of the circuit ITSa[j]_1. The output terminal of the circuit ITSa[j]_1 is connected to the wiring OL[j]_1. The wiring IL_2 is connected to the first terminal of the switch SW2[j]_2, and the second terminal of the switch SW2[j]_2 is connected to the input terminal of the circuit ITSa[j]_2. The output terminal of the circuit ITSa[j]_2 is connected to the wiring OL[j]_2.

[0268] 5 , the arithmetic device CDVB shown in FIG. 6 includes wirings XCL[1]_1 to XCL[m]_1, wirings XCL[1]_2 to XCL[m]_2, wirings SEL[1] to SEL[m], and wirings WSL[1] to WSL[m] extending in the row direction. Similarly to the arithmetic device CDVA shown in FIG. 5 , the arithmetic device CDVB shown in FIG. 6 includes a driver circuit XCD, a driver circuit WSD, and a driver circuit SED. Therefore, the description of the arithmetic device CDVA shown in FIG. 5 can be referred to for the wirings and driver circuits shown in FIG. 6 .

[0269] In the calculation cell IM[i,j] (not shown), the gates of the transistors MA_1, MA_2, and MC are connected to a wiring WSL[i] (not shown). The second terminal of the capacitor CA_1 is connected to a wiring XCL[i]_1 (not shown), the second terminal of the capacitor CA_2 is connected to a wiring XCL[i]_2 (not shown), and the second terminal of the capacitor CB is connected to a wiring SEL[i] (not shown).

[0270] In addition, in the calculation cell IM[i, j] (not shown), the second terminal of the transistor MC is connected to the wiring WCL[j] (not shown), the second terminal of the transistor MB_1 is connected to the wiring IL[j]_1 (not shown), and the second terminal of the transistor MB_2 is connected to the wiring IL[j]_2 (not shown).

[0271] In the arithmetic device CDVB of FIG. 6 , W[1,1] to W[m,n] are written separately as first data to the arithmetic cells IM[1,1] to IM[m,n], respectively. Specifically, for example, W[1,1] to W[m,1], which are sequentially input to the input terminal of the circuit WCDa[1], are written to the arithmetic cells IM[1,1] to IM[m,n], respectively, arranged in the first column. Similarly, W[1,n] to W[m,n], which are sequentially input to the input terminal of the circuit WCDa[n], are written to the arithmetic cells IM[1,n] to IM[m,n], respectively, arranged in the nth column. Note that the description of the arithmetic device CDVA of FIG. 5 can be referred to for the write operation.

[0272] After W[1,1] to W[m,n] are written separately as first data to the calculation cells IM[1,1] to IM[m,n], respectively, the circuits XCDa[1]_1 to XCDa[m]_1 and the circuits XCDa[1]_2 to XCDa[m]_2 write second data X １ [1] to X １ [m] and X ２ [1] to X ２ By transmitting W[i,j] to the calculation cell IM of each row, the first data held in each calculation cell IM[1,1] to IM[m,n] is multiplied by the transmitted second data. For example, in calculation cell IM[i,j], W[i,j] and X １ Multiplication of [i] and W[i,j] and X ２ Multiplication by [i] is performed.

[0273] In the j-th column of the cell array MCA, a current corresponding to the sum of the results of multiplications performed in the arithmetic cells IM[1, j] to IM[m, j] flows through each of the wirings IL[j]_1 and IL[j]_2. Specifically, the current flowing through the wiring IL[j]_1 is expressed as I Ｓ１ [j], and the current flowing through the wiring IL[j]_2 is I Ｓ２ When [j] is used, they can be expressed as in the following equations (1.17) and (1.18).

[0274]

[0275] Therefore, the amount of current flowing through the wiring IL[j]_1 is I Ｓ１ [j] flows into the circuit ITSa[j]_1, and the circuit FC Ｓ１ The value Z of the function according to [j] １ Calculate [j] and Z １ [j] is output to the wiring OL[j]_1. Similarly, the amount of current I ２ [j] flows to the circuit ITSa[j]_2, and the circuit FC Ｓ２ The value Z of the function according to [j] ２ Calculate [j] and Z ２ [j] is output to wiring OL[j]_2.

[0276] This allows Z １ [j] and Z ２ [j] can be expressed as the following equations (1.19) and (1.20) using the above equations (1.17) and (1.18), respectively. In this way, by arranging the operation cells IM in an m×n matrix, the first data W[1,j] to W[m,j] and one of the two second data X １ [1] to X １ [m] and the result of the multiplication and addition operation, and the calculation of a function using the result as an input value, and the first data W[1,j] to W[m,j] and the other of the two second data X １ [1] to X １ 6 is arranged in n columns, it is possible to perform 2n product-sum operations and function operations using the respective results as input values.

[0277]

[0278] <Configuration Example 2 of Achievement Circuit> Next, a configuration example of an arithmetic circuit according to one embodiment of the present invention, which is different from the arithmetic cell IM illustrated in FIG. 1, will be described.

[0279] The operation cell IMA shown in FIG. 7 is a modified example of the operation cell IM shown in FIG. 1, and differs from the operation cell IM shown in FIG. 1 in that it does not include the transistor MC.

[0280] 7, the second terminal of the transistor MA_2 is directly connected to the wiring WCL. Furthermore, since the calculation cell IMA does not include the transistor MC, the driving circuit SED and the wiring SEL are not shown in FIG.

[0281] In the calculation cell IM of FIG. 1, the provision of the transistor MC can prevent fluctuations in the potentials of the nodes N1 and N2. However, when the leakage currents of the transistors MA_1 and MA_2 are small, it is preferable to directly connect the wiring WCL and the transistor MA_2 without providing the transistor MC, as in the calculation cell IMA of FIG. 7.

[0282] By adopting a configuration in which the transistor MC is not provided, the circuit area of ​​the calculation cell IMA can be made smaller than that of the calculation cell IM in Fig. 1. Furthermore, since the drive circuit SED for generating the potential to be input to the gate of the transistor MC is also not required, the circuit area of ​​the calculation device CDV including the calculation cell IMA can also be reduced.

[0283] <Configuration Example 3 of Arithmetic Circuit> Fig. 8 shows an arithmetic cell IMB having a configuration different from that of the arithmetic cell IM in Fig. 1 and the arithmetic cell IMA in Fig. 7. The arithmetic cell IMB shown in Fig. 8 is an arithmetic cell that can perform multiplication of first data and each of three or more third data.

[0284] The calculation cell IMB includes transistors MA_1 to MA_K (K is an integer equal to or greater than 3), transistors MB_1 to MB_K, and a transistor MC. Note that the transistors MA_1 to MA_K in FIG. 8 correspond to the transistors MA_1 and MA_2 in the calculation cell IM in FIG. 1, the transistors MB_1 to MB_K in FIG. 8 correspond to the transistors MB_1 and MB_2 in the calculation cell IM in FIG. 1, and the transistor MC in FIG. 8 corresponds to the transistor MC in the calculation cell IM in FIG. 1.

[0285] In the driver circuit XCD, the circuit XCDa includes circuits XVG_1 to XVG_K. Note that the circuits XVG_1 to XVG_K in FIG. 8 correspond to the circuits XVG_1 and XVG_2 in FIG. 1. The driver circuit ITS includes circuits ITSa_1 to ITSa_K and switches SW2_1 to SW2_K. Note that the circuits ITSa_1 to ITSa_K in FIG. 8 correspond to the circuits ITSa_1 and ITSa_2 in FIG. 1, and the switches SW2_1 to SW2_K in FIG. 8 correspond to the switches SW2_1 and SW2_2 in FIG. 1.

[0286] A first terminal of the transistor MA_1 is connected to the gate of the transistor MB_1 and the second terminal of the capacitor CA_1. The gate of the transistor MA_1 is connected to the wiring WSL. The second terminal of the capacitor CA_1 is connected to the wiring XCL_1.

[0287] A first terminal of transistor MA_k+1 (k is an integer greater than or equal to 1 and less than or equal to K-1) is connected to a second terminal of transistor MA_k, a gate of transistor MB_k, and a first terminal of capacitor CA_k. The gate of transistor MA_k is connected to wiring WSL. The second terminal of capacitor CA_k is connected to wiring XCL_k. Note that transistor MA_k+1, transistor MA_k, transistor MB_k, capacitor CA_k, and wiring XCL_k are not shown in FIG. 8 .

[0288] A first terminal of the transistor MC is connected to a second terminal of the capacitance element CB, a gate of the transistor MC is connected to a wiring WSL, and a second terminal of the capacitance element CB is connected to a wiring SEL.

[0289] The wirings XCL_1 to XCL_K are separately connected to the circuits XVG_1 to XVG_K included in the circuit XCDa. The wiring EN is connected to the second input terminals of the circuits XVG_1 to XVG_K.

[0290] A first terminal of the transistor MB_k is connected to the wiring VE1, and a second terminal of the transistor MB_k is connected to the wiring IL_k. Similarly, a first terminal of the transistor MB_K is connected to the wiring VE1, and a second terminal of the transistor MB_K is connected to the wiring IL_K. Note that the transistor MB_k and the wiring IL_k are not shown in FIG. 8.

[0291] First terminals of the switches SW2_1 to SW2_K are connected to the wirings IL_1 to IL_K, respectively. Second terminals of the switches SW2_1 to SW2_K are connected to the input terminals of the circuits ITSa_1 to ITSa_K, respectively. Control terminals of the switches SW2_1 to SW2_K are connected to the wiring SWL2. Output terminals of the circuits ITSa_1 to ITSa_K are connected to the wirings OL_1 to OL_K, respectively.

[0292] In the calculation cell IMB, the gates of the transistors MB_1 to MB_K serve as retention nodes, and the retention nodes are separately retained by the capacitance elements CA_1 to CA_K. Therefore, in the calculation cell IMB, the first data W is retained in each of the K retention nodes.

[0293] The circuits XVG_1 to XVG_K included in the driver circuit XCD respectively transmit the second data X １ ~X Ｋ For example, the second data X １ A potential according to the second data X Ｋ A potential according to this is applied to the wiring XCL_K.

[0294] The wirings XCL_1 to XCL_K are each provided with a second data X １ ~X Ｋ, and a potential higher than the potential of the wiring VE1 is applied to each of the wirings IL_1 to IL_K. As a result, similar to the operation example of the arithmetic cell in FIG. 1, each of the transistors MB_1 to MB_K can pass a source-drain current proportional to the product of the first data and the second data.

[0295] The source-drain currents flowing through the transistors MB_1 to MB_K are input to the circuits ITSa_1 to ITSa_K, respectively. As a result, the activation functions are calculated in the circuits ITSa_1 to ITSa_K using the amounts of the input source-drain currents as input values. １ ~Z Ｋ are output to the wirings OL_1 to OL_K, respectively.

[0296] As described above, by using the operation cell IMB, it is possible to multiply the first data by each of three or more third data.

[0297] <Configuration Example 4 of Achievement Circuit> A configuration example of an arithmetic circuit of one embodiment of the present invention, which is different from the arithmetic cell illustrated in FIG. 1, will be described.

[0298] The operation cell IMC shown in FIG. 9 is a modified example of the operation cell IM of FIG. 1, and differs from the operation cell IM of FIG. 1 in that transistors MD_1 and MD_2 are newly provided.

[0299] The first terminal of the transistor MD_1 is connected to the second terminal of the transistor MB_1, and the wiring IL_1 is connected to the second terminal of the transistor MD_1. Similarly, the first terminal of the transistor MD_2 is connected to the first terminal of the transistor MB_2, and the wiring IL_2 is connected to the second terminal of the transistor MD_2.

[0300] The transistor MD_1 functions as a clamp transistor to prevent drain-induced barrier lowering (DIBL) in the transistor MB_1. Similarly, the transistor MD_2 functions as a clamp transistor to prevent drain-induced barrier lowering (DIBL) in the transistor MB_2. This prevents a decrease in the threshold voltage of the transistor MD_1 due to a high-level potential being applied to the second terminal of the transistor MD_1. Similarly, it prevents a decrease in the threshold voltage of the transistor MD_2 due to a high-level potential being applied to the second terminal of the transistor MD_2.

[0301] <Example of Layout of Arithmetic Circuit> Next, an example of the layout of the above-mentioned arithmetic cell IM will be described.

[0302] Fig. 10 is a plan view schematic diagram showing an example of the layout of the computation cell IM shown in Fig. 1. In Fig. 10, the computation cell IM has, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Note that, to clearly show the layout, insulating layers included in the computation cell IM are not shown in Fig. 10.

[0303] As an example, the semiconductor layer SMC is located below the conductive layers SDM and GEM. Also, as an example, the conductive layer PLG is located above the conductive layers SDM and GEM. Also, as an example, the conductive layer WIR is located above the conductive layer PLG. The order of formation can be as follows: first, the semiconductor layer SMC, second, one of the conductive layers SDM and GEM, third, the other of the conductive layers SDM and GEM, fourth, the conductive layer PLG, and fifth, the conductive layer WIR.

[0304] For example, a portion of the conductive layer GEM functions as the gates of the transistors MA_1, MA_2, MB_1, MB_2, and MC, respectively, and also functions as one of a pair of electrodes of the capacitors CA_1, CA_2, and CB, respectively.

[0305] Furthermore, a part of the conductive layer GEM can be a wiring extending around the periphery of the processing cell IM. For example, in FIG. 10, each of the wiring WCL, wiring VE1, wiring IL_1, and wiring IL_2 extending around the periphery of the processing cell IM can be formed as a part of the conductive layer GEM.

[0306] As an example, a part of the conductive layer SDM functions as a source or a drain of each of the transistors MA_1, MA_2, MB_1, MB_2, and MC.

[0307] For example, parts of the conductive layer WIR function as the other of the pair of electrodes of each of the capacitors CA_1, CA_2, and CB.

[0308] Furthermore, a part of the conductive layer WIR can be a wiring extending around the periphery of the processing cell IM. For example, in FIG. 10, each of the wiring WSL, wiring XCL_1, wiring XCL_2, and wiring SEL extending around the periphery of the processing cell IM can be formed as a part of the conductive layer WIR.

[0309] The conductive layer GEM, the conductive layer SDM, the conductive layer WIR, and the semiconductor layer SMC can each be formed using, for example, a lithography method. Specifically, for example, when forming the conductive layer GEM, a conductive material to be the conductive layer GEM can be formed using one or more methods selected from a sputtering method, a CVD (Chemical Vapor Deposition) method, a PLD (Pulsed Laser Deposition) method, and an ALD (Atomic Layer Deposition) method, and then a desired pattern can be formed using a lithography method. In addition, the conductive layer SDM, the conductive layer WIR, the semiconductor layer SMC, and the conductive layer PLG can also be formed using the same method as above.

[0310] Furthermore, insulating layers may be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDM, and between the conductive layer WIR and the conductive layer GEM. In particular, the insulating layer provided between the semiconductor layer SMC and the conductive layer GEM may function as a gate insulating film (sometimes referred to as a front gate insulating film, etc.). Furthermore, in the region where the capacitance elements CA_1, CA_2, and CB are provided, an insulating layer that functions as a dielectric for each of the capacitance elements CA_1, CA_2, and CB is preferably provided between the conductive layer WIR and the conductive layer GEM.

[0311] Furthermore, an opening is provided in the region where a portion of the conductive layer SDM overlaps a portion of the conductive layer WIR, and a conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer SDM and a portion of the conductive layer WIR via the conductive layer PLG. Similarly, an opening is provided in the region where a portion of the conductive layer GEM overlaps a portion of the conductive layer WIR, and another conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer GEM and a portion of the conductive layer WIR via the conductive layer PLG.

[0312] The layout of the arithmetic circuit of one embodiment of the present invention is not limited to the schematic plan view of FIG. 10 . The layout of the arithmetic circuit of one embodiment of the present invention may be the schematic plan view of FIG. 10 , which is appropriately modified. For example, in the schematic plan view of FIG. 10 , the transistors MA_2 and MC are formed to share an island-shaped semiconductor layer SMC. However, similar to the transistors MA_1, MB_1, and MB_2, each of the transistors may have a separate island-shaped semiconductor layer SMC. For example, in the circuit diagram of FIG. 1 , the transistors MA_1, MA_2, and MC are connected in series, so these transistors can be formed to share the island-shaped semiconductor layer SMC. Furthermore, the transistors MB_1 and MB_2 are connected to the wiring VE1, so these transistors can also be formed to share the island-shaped semiconductor layer SMC.

[0313] In addition, in the schematic plan view of Figure 10, each of the capacitance elements CA_1, CA_2, and CB is a parallel plate type capacitance element, but they can be changed to a capacitance element in which a pair of electrodes and a dielectric are embedded in an opening in an insulating layer, as shown in Figure 26 described later.

[0314] 10, the wiring WCL, wiring VE1, wiring IL_1, and wiring IL_2 are respectively provided below the wiring WSL, wiring XCL_1, wiring XCL_2, and wiring SEL, but the vertical relationship of the wirings is not particularly limited. For example, the wiring WCL, wiring VE1, wiring IL_1, and wiring IL_2 can be respectively provided above the wiring WSL, wiring XCL_1, wiring XCL_2, and wiring SEL. Furthermore, selected one or more of the above-mentioned wirings can be provided in a vertical direction (a direction substantially perpendicular to the plan view) rather than in the planar direction shown in the plan view. For example, in FIG. 10, the above-mentioned wirings can be formed using a conductive layer that can be formed vertically, such as a plug.

[0315] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0316] Second Embodiment In this embodiment, a convolutional neural network, which is a type of artificial neural network, will be described. Note that by using the arithmetic device described in the above embodiment, it is possible to suitably perform calculations for the convolutional neural network.

[0317] AlexNet will be described as an example of a convolutional neural network. AlexNet is an artificial neural network model shown in Figure 11. AlexNet includes an input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, PL5, and fully connected layers FC6 to FC8. As shown in Figure 11, AlexNet is configured in the following order: input layer INLY, convolutional layer CNV1, pooling layer PL1, convolutional layer CNV2, pooling layer PL2, convolutional layer CNV3, convolutional layer CNV4, convolutional layer CNV5, pooling layer PL5, fully connected layer FC6, fully connected layer FC7, and fully connected layer FC8.

[0318] [Input Layer INLY] As an input to AlexNet, the input layer INLY includes, for example, a 224×224 pixel image P ｉｎ It is assumed that one pixel includes red, green, and blue sub-pixels, and the total number of sub-pixels is 3 colors (red, green, blue) x 224 x 224. ｉｎ The number of channels of the image P is three, namely red, green and blue. ｉｎ The number of image data to the input layer INLY included in is 3×224×224.

[0319] In this example, the image P ｉｎ In this case, the input value in the xth row and yth column included in the zth input channel (where z is an integer between 1 and 3) is expressed as p ｉｎ It is written as [x, y, z]. Note that x is the ｉｎ and y indicates the address of the row of the image P ｉｎ That is, in the input layer INLY, x is an integer between 1 and 224, and y is an integer between 1 and 224.

[0320] [Convolutional Layer CNV1] In the convolutional layer CNV1, image P ｉｎ Specifically, a filter (also called a kernel) used in the convolution process CNV1 and the image P ｉｎ Region A selected from ｉｎThe image data included in is subjected to a multiplication and accumulation operation.

[0321] In the convolution layer CNV1, the filter size (also called kernel size) is 11, the number of output channels (also called kernel number) is 96, and the stride is 4. ｉｎ The convolution process is performed on the region selected from the above. The number of filter values ​​in one kernel is (filter size) ２ × (number of input channels) Image P ｉｎ Since the number of input channels is 3, the number of filter values ​​in one kernel in the convolution layer CNV1 is 11 × 11 × 3 = 363.

[0322] Here, the sth (here, s is an integer between 1 and 96) kernel in the convolution layer CNV1 is K Ｃ１ （ｓ） Also, kernel K Ｃ１ The filter values ​​contained in Ｃ１ （ｓ） It is written as [p, q, r], where p indicates the row address of the kernel, q indicates the column address of the kernel, and r indicates the ordinal number of the input channel. That is, in the convolution layer CNV1, p is an integer between 1 and 11, q is an integer between 1 and 11, and r is an integer between 1 and 3.

[0323] For example, in FIG. ｉｎ Region A selected from ｉｎ (1) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１ （１） This shows an example of outputting (1). ｉｎ The x in (x) is the image P ｉｎ The data p Ｃ１ （ｓ） The s in (x) indicates the ordinal number of the output channel. Ｃ１ （ｓ） The x in (x) is the area A ｉｎ (x) indicates the ordinal number x.

[0324] Also, since the stride is 4, area A ｉｎ The area shifted four positions in the row direction from (1) is area A. ｉｎ For example, in FIG. ｉｎ Region A selected from ｉｎ (2) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１ （１） An example of outputting (2) is shown.

[0325] In addition, image P ｉｎ If the number of pixels in image P is 224x224 and the stride is 4, ｉｎ The number of regions to be selected is 3025 (=55 ２ ) In this embodiment, the area A ｉｎ (1) to area A ｉｎ It is called (3025).

[0326] As described above, depending on the number of strides, the image P ｉｎ The region selected from is shifted sequentially, and each time the region is shifted, the region and the kernel K Ｃ１ （１） By performing a product-sum operation with K, a matrix of output data with 55 rows and 55 columns is obtained. In addition, the kernel included in the convolution layer CNV1 is the kernel K Ｃ１ （１） Kernel K Ｃ１ （９６） (because the number of kernels in the convolutional layer CNV1 is 96), as a result, the convolutional layer CNV1 outputs 55 × 55 × 96 output data, P Ｃ１ will be output.

[0327] In the convolution process in the convolution layer CNV1, for one kernel, ｉｎ For this reason, the calculation circuit may be configured to calculate the product of each of the filter values ​​included in one kernel and the image P ｉｎ It is preferable to simultaneously perform the multiplication of data included in each of the plurality of regions selected from .

[0328] For example, in the configuration of the calculation device CDVA shown in FIG. 5, the kernel K Ｃ１ （１） are written to the calculation cells IM[1] to IM[m] (where m is an integer equal to or greater than 11×11×3=363). In addition, the image P ｉｎ Region A selected from ｉｎ (1) is input, and the other of the two second data, image P ｉｎ Region A selected from ｉｎ (2) is preferably input. This allows the kernel K Ｃ１ （１） and area A ｉｎ The multiplication and addition operation of (1) and the kernel K Ｃ１ （１） and area A ｉｎ This can be performed simultaneously with the multiplication and accumulation operation in (2).

[0329] Also, each of the operation cells IM[1] to IM[m] of the arithmetic unit CDVA shown in Fig. 5 can be replaced with the operation cell IMB shown in Fig. 8. For this purpose, it is preferable to replace the circuit XCDa shown in Fig. 5 with the circuit XCDa shown in Fig. 8. As a result, the operation cell IMB stores the kernel K Ｃ１ （１） For example, in the convolution layer CNV1, the image P ｉｎ The region selected from region A ｉｎ (1) to area A ｉｎ (3025), by setting K to the maximum of 3025, the kernel K Ｃ１ （１） and area A ｉｎ (1) to area A ｉｎ(3025) and the sum of products can be calculated. ｉｎ (1) to area A ｉｎ (3025) may be input to the arithmetic unit CDVA in two separate steps to perform the product-sum operation.

[0330] Furthermore, in the configuration of the arithmetic unit CDVB shown in FIG. Ｃ１ （ｊ） (where j is an integer between 1 and 96) is preferably written in each of the calculation cells IM[1,j] to IM[m,j] arranged in the j-th column of the cell array MCA. In other words, it is preferable that the calculation device CDVB shown in FIG. 6 writes a different kernel filter value for each column. For this reason, it is preferable that the number of columns n is 96 or more. As a result, for example, the area A input as the second data ｉｎ (1) and the kernel K held for each column Ｃ１ （１） ~K Ｃ１ （９６） The filter values ​​of and the multiplication and accumulation operations can be performed simultaneously.

[0331] Furthermore, by replacing the calculation cell IM of the calculation device CDVB of FIG. 6 with the calculation cell IMB of FIG. 8 and replacing the circuit XCDa of the calculation device CDVA of FIG. 6 with the circuit XCDa of FIG. 8, it is possible to input three or more regions as second data to the calculation device CDVB and perform a product-sum operation on the three or more regions and the filter value.

[0332] For example, consider a cell array MCA in which the operation cells IM are arranged in a 363×96 matrix as shown in FIG. 14. The kernel K Ｃ１ （１） As the filter value of Ｃ１ （１） [1,1,1] to k Ｃ１ （１）[11, 11, 3] are written separately. In addition, the kernel K Ｃ１ （９６） As the filter value of Ｃ１ （９６） [1,1,1] to k Ｃ１ （９６） Write [11,11,3] separately.

[0333] Then, the wirings XCL[1]_1 to XCL

[363] _1 are each provided with a region A ｉｎ As the respective values ​​of (1), a ｉｎ (1) [1, 1, 1] to a ｉｎ (1) By inputting [11, 11, 3] separately, the kernel K Ｃ１ （１） and area A ｉｎ p, which is the result of the multiplication and addition operation of (1), ｃ１ （１） (1) is output, and the kernel K is output from the wiring IL

[96] _1. Ｃ１ （９６） and area A ｉｎ p, which is the result of the multiplication and addition operation of (1), ｃ１ （９６） (1) is output.

[0334] Similarly, the wirings XCL[1]_2 to XCL

[363] _2 are each provided with a region A ｉｎ (2) As the respective values, a ｉｎ (2) [1, 1, 1] to a ｉｎ (2) By inputting [11, 11, 3] separately, the kernel K Ｃ１ （１） and area A ｉｎ p, which is the result of the multiplication and addition operation of (2) ｃ１ （１） (2) is output, and the kernel K is output from the wiring IL

[96] _1. Ｃ１ （９６） and area A ｉｎ p, which is the result of the multiplication and addition operation of (2) ｃ１ （９６） (2) is output.

[0335] Similarly, the wirings XCL[1]_3025 to XCL

[363] _3025 are each provided with a region A ｉｎ As the respective values ​​of (3025), a ｉｎ (3025) [1, 1, 1] to a ｉｎ (3025) [11, 11, 3] are input separately, and the kernel K Ｃ１ （１） and area A ｉｎ p, which is the result of the multiplication and addition of (3025) ｃ１ （１） (3025) is output, and the kernel K Ｃ１ （９６） and area A ｉｎ p, which is the result of the multiplication and addition of (3025) ｃ１ （９６） (3025) is output.

[0336] As described above, by using the arithmetic device according to one embodiment of the present invention, the area A ｉｎ (1) to area A ｉｎ (3025) and kernel K Ｃ１ （１） ~K Ｃ１ （９６） The filter value of and the output data P from the convolution layer CNV1 are input. Ｃ１ can be obtained.

[0337] [Pooling Layer PL1] In the pooling layer PL1, P Ｃ１ Pooling is performed on the data. Pooling is a process in which predetermined regions are sequentially selected from the data output from the convolution layer, and predetermined processing is performed on each region to extract features, which are then arranged in a matrix.

[0338] As shown in FIG. 11, in the pooling layer PL1, the kernel size is set to 3, and the data P Ｃ１ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0339] For example, in FIG. 15A, data P Ｃ１ Region A selected from the first input channel of Ｃ１ｉｎ （１） In (1), the maximum pooling process is performed, and the processed data p ｐ１ （１） In this example, the kernel size is 3, so the area A Ｃ１ｉｎ （１） (1) contains 3 x 3 data.

[0340] In addition, area A Ｃ１ｉｎ （ｓ） (A) s is the data P Ｃ１ indicates the ordinal number of the input channel of area A Ｃ１ｉｎ （ｓ） The A in (A) is data P Ｃ１ indicates the ordinal number of the selected region from the data p ｐ１ （ｓ） In (A), s indicates the ordinal number of the output channel, and data p ｐ１ （ｓ） The A in (A) is area A Ｃ１ｉｎ （ｓ） (A) indicates the ordinal number A.

[0341] Also, since the stride is 2, area A Ｃ１ｉｎ （１） The area shifted two positions in the row direction from (1) is area A Ｃ１ｉｎ （１） For example, in FIG. 15B, data P Ｃ１ Region A selected from Ｃ１ｉｎ （１） In (2), the maximum pooling process is performed, and the processed data p ｐ１ （１） An example of outputting (2) is shown.

[0342] In addition, data P Ｃ１ The number of data is 55 × 55 × 96, and the stride is 2. Ｃ１ The number of regions to be selected is 729 (=27 ２ )

[0343] As described above, the data P Ｃ１By sequentially performing pooling processing on the regions selected from the data P Ｃ１ The first input channel of the pooling layer PL1 is described above, but the second to 96th input channels are also pooled in the same way. As a result, the pooling layer PL1 outputs 27 x 27 x 96 output data P Ｐ１ will be output.

[0344] [Convolutional Layer CNV2] In the convolutional layer CNV2, the data P output by the pooling layer PL1 is Ｐ１ Specifically, the kernel used in the convolution process CNV2 and P Ｐ１ A multiplication and accumulation operation is performed on the data included in the selected area.

[0345] As shown in Figure 11, in the convolution layer CNV2, the kernel size is set to 5, the number of kernels is set to 256, and P Ｐ１ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0346] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV2, the convolutional layer CNV2 outputs 27 × 27 × 256 output data, P Ｃ２ will be output.

[0347] Similarly to the convolutional layer CNV1, the convolutional layer CNV2 can use the arithmetic device of one embodiment of the present invention. For example, 256 kernels of the convolutional layer CNV2 are written to each column of the cell array MCA, and P Ｐ１ By inputting each region selected from the above by the driving circuit XCD, P Ｃ２ can be obtained.

[0348] [Pooling Layer PL2] In the pooling layer PL2, P Ｃ２ The pooling process is performed on the

[0349] As shown in FIG. 11, in the pooling layer PL2, the kernel size is set to 3, and the data PＣ２ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0350] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL2, the pooling layer PL2 outputs 13×13×256 output data, P Ｐ２ will be output.

[0351] [Convolutional Layer CNV3] In the convolutional layer CNV3, the data P output by the pooling layer PL2 is Ｐ２ Specifically, the kernel used in the convolution process CNV3 and P Ｐ２ A multiplication and accumulation operation is performed on the data included in the selected area.

[0352] As shown in Figure 11, in the convolution layer CNV3, the kernel size is set to 3 and the number of kernels is set to 384. Ｐ２ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0353] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV3, the convolutional layer CNV3 outputs 13 × 13 × 384 output data, P Ｃ３ will be output.

[0354] Furthermore, for the operation of the arithmetic unit in the convolutional layer CNV3, reference can be made to the description of the operation of the arithmetic unit CDVA in FIG. 5 or the arithmetic unit CDVB in FIG. 6 in the convolutional layer CNV1.

[0355] [Convolutional Layer CNV4] In the convolutional layer CNV4, the data P output by the convolutional layer CNV3 is Ｃ３ Specifically, the kernel used in the convolution process CNV4 and P Ｃ３ A multiplication and accumulation operation is performed on the data included in the selected area.

[0356] As shown in Figure 11, in the convolution layer CNV4, the kernel size is set to 3 and the number of kernels is set to 384.Ｃ３ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0357] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV4, the convolutional layer CNV4 outputs 13 × 13 × 384 output data, P Ｃ４ will be output.

[0358] Furthermore, for the operation of the arithmetic unit in the convolutional layer CNV4, reference can be made to the description of the operation of the arithmetic unit CDVA in FIG. 5 or the arithmetic unit CDVB in FIG. 6 in the convolutional layer CNV1.

[0359] [Convolutional Layer CNV5] In the convolutional layer CNV5, the data P output from the convolutional layer CNV4 is Ｃ４ Specifically, the kernel used in the convolution process CNV5 and P Ｃ４ A multiplication and accumulation operation is performed on the data included in the selected area.

[0360] As shown in Figure 11, in the convolution layer CNV5, the kernel size is set to 3, the number of kernels is set to 256, and P Ｃ４ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0361] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV5, the convolutional layer CNV5 outputs 13 × 13 × 256 output data, P Ｃ５ will be output.

[0362] For the operation of the arithmetic unit in the convolutional layer CNV5, reference can be made to the description of the operation of the arithmetic unit CDVA in FIG. 5 or the arithmetic unit CDVB in FIG. 6 in the convolutional layer CNV1.

[0363] [Pooling Layer PL5] In the pooling layer PL5, P Ｃ５ The pooling process is performed on the

[0364] As shown in FIG. 11, in the pooling layer PL5, the kernel size is set to 3, and the data PＣ５ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0365] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL5, the pooling layer PL5 outputs 6×6×256 output data, P Ｐ５ will be output.

[0366] [Fully Connected Layer FC6] In the fully connected layer FC6, P Ｐ５ The fully connected layer is calculated for

[0367] As shown in Figure 11, the fully connected layer FC6 has 9126 (= 6 x 6 x 256) input channels and 4096 output channels. In the fully connected layer, a multiply-and-accumulate operation is performed on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and the activation function value is calculated using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC6 is 4096 x 9126.

[0368] The data to be the Nth output channel of the fully connected layer FC6 (where N is an integer between 1 and 4096) is z ＦＣ６ (N), then z ＦＣ６ (N) can be expressed by the following formula (2.1).

[0369]

[0370] where f is the activation function in the fully connected layer FC6. The activation function may be, for example, an activation function that can be calculated by the circuit FC described in the first embodiment. Specific examples include a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. ＦＣ６ (N) is as shown in the following formula (2.2).

[0371]

[0372] In addition, pｐ５ （ｓ） (A) is the A-th data of the s-th output channel output in the pooling layer PL5. ＦＣ６（Ｎ） （ｓ） (A) shows the Nth channel of the fully connected layer FC6 and p ｐ５ （ｓ） (A) and the corresponding weighting coefficient (first data).

[0373] By using the above formulas (2.1) and (2.2), z ＦＣ６ (1) to z ＦＣ６ (4096) can be obtained.

[0374] It is preferable that the calculation of the fully connected layer FC6 be performed by, for example, a calculation device CDVB shown in FIG. 6. The second data in the calculation device CDVB is p ｐ５ （ｓ） Since (A) is used, for example, the first input terminal of the circuit XVG_1 of each of the circuits XCDa[1] to XCDa[m] is connected to p ｐ５ （ｓ） It is preferable to input the value of each component of (A) and input the value “0” to the first input terminal of the circuit XVG_2 of each of the circuits XCDa[1] to XCDa[m]. ｐ５ （ｓ） The value of each component of (A) and the corresponding weighting coefficient w ＦＣ６（Ｎ） （ｓ） As a result, the arithmetic circuit outputs u ＦＣ６ (1) can be output.

[0375] When the calculation of the fully connected layer FC6 is performed by the calculation device CDVB shown in Figure 6, it is preferable that the number of rows m of the cell array MCA is 9126, which is the number of input channels, and the number of columns n of the cell array MCA is 4096, which is the number of output channels.

[0376] As a result of the above, the cell array MCA stores the first data (weighting coefficient) and the second data (P Ｐ５ ) is multiplied and added, and uＦＣ６ (1) to u ＦＣ６ (4096) is obtained. Also, by the driving circuit ITS shown in FIG. ＦＣ６ (1) to u ＦＣ６ The activation function is calculated using each of the input values ​​(4096), and z ＦＣ６ (1) to z ＦＣ６ (4096) is obtained. As a result, z ＦＣ６ (1) to z ＦＣ６ An output signal of (4096) is output.

[0377] [Fully connected layer FC7] In the fully connected layer FC7, z ＦＣ６ (1) to z ＦＣ６ The fully connected layer is calculated for (4096).

[0378] 11 , the fully connected layer FC7 has 4096 input channels and 4096 output channels. As with the fully connected layer FC6, the fully connected layer FC7 performs a multiply-and-accumulate operation on the data of all input channels and corresponding weighting coefficients (first data) as one output channel, and calculates the value of an activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC7 is 4096 x 4096.

[0379] For the product-sum operation and activation function operation in the fully connected layer FC7, the description of the fully connected layer FC6 can be referred to.

[0380] In the fully connected layer FC7, the data of the output channel from the fully connected layer FC6, z ＦＣ６ (1) to z ＦＣ６ By inputting (4096), the data of the 1st to 4096th output channels of the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ (4096) is output.

[0381] [Fully Connected Layer FC8] In the fully connected layer FC8, z ＦＣ７ (1) to z ＦＣ７The fully connected layer is calculated for (4096).

[0382] 11 , the fully connected layer FC8 has 4096 input channels and 1000 output channels. As with the fully connected layer FC6, the fully connected layer FC8 performs a multiply-and-accumulate operation on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and calculates the value of an activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC8 is 1000×4096.

[0383] For the product-sum operation and activation function operation in the fully connected layer FC8, the description of the fully connected layer FC6 can be referred to.

[0384] In the fully connected layer FC8, the data of the output channel from the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ By inputting (4096), the data of the 1st to 1000th output channels of the fully connected layer FC8, z ＦＣ８ (1) to z ＦＣ８ (1000) is output.

[0385] For the fully connected layer FC8, the above description of the operation of the fully connected layer FC7 can be referred to.

[0386] As described above, the calculation of AlexNet shown in FIG. 11 can be performed by using the calculation device of one embodiment of the present invention.

[0387] In this operation example, the operation of the calculation device described in the first embodiment to perform the AlexNet calculation shown in Fig. 11 is described, but the calculation model performed by the calculation device is not limited to AlexNet. For example, in the input layer INLY, an image P ｉｎis input to the arithmetic device, but the image size may be determined arbitrarily. The number of kernels used in convolutional layers CNV1 to CNV5 and the filter values ​​included therein may also be determined arbitrarily. A convolutional neural network other than the AlexNet arithmetic model of FIG. 11 may also be operated by the arithmetic device.

[0388] In this operation example, the pooling process has been described as maximum pooling, but depending on the situation, average pooling, Lp pooling, etc. may also be used.

[0389] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0390] Embodiment Mode 3 In this embodiment mode, a configuration example of the arithmetic device described in the above embodiment mode will be described.

[0391] Fig. 16 is a perspective view schematically showing the arithmetic unit CDV, arithmetic unit CDVA, arithmetic unit CDVB, etc. described in embodiment 1. The arithmetic unit CDVS shown in Fig. 16 has, as an example, a circuit layer PHRL and an arithmetic layer OMAL. The circuit layer PHRL is located below the arithmetic layer OMAL.

[0392] FIG. 17 is a block diagram showing an example of the configuration of the circuit layer PHRL and the arithmetic layer OMAL shown in FIG.

[0393] 17, the circuit layer PHRL has, for example, the drive circuits WCD, XCD, ITS, WSD, and SED described in embodiment 1. The operation layer OMAL has, for example, the cell array MCA described in embodiment 1.

[0394] Note that one or more selected from the driving circuits WCD, XCD, ITS, WSD, and SED described in the first embodiment may be included in the arithmetic layer OMAL.

[0395] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of usable substrates include an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, lamination films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the computing device CDVS includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0396] In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0397] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, XCD, ITS, WSD, and SED can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can therefore pass large on-state currents. This makes it possible to increase the drive speed of each of the drive circuits listed above and to widen the signal range.

[0398] The stacked structure of the circuit layer PHRL and the arithmetic layer OMAL can be fabricated by forming the arithmetic layer OMAL directly on top of the circuit layer PHRL, or by mounting the arithmetic layer OMAL on top of the circuit layer PHRL as a structure in which circuit elements such as transistors and capacitive elements are provided on a substrate.

[0399] When the arithmetic layer OMAL is formed directly on the circuit layer PHRL, the arithmetic layer OMAL preferably includes an OS transistor. Since OS transistors can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even on a conductive film, an insulating film, or a semiconductor film, they can be easily provided on a semiconductor substrate (on the circuit layer PHRL) on which Si transistors are formed.

[0400] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the arithmetic layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the arithmetic layer OMAL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the arithmetic layer OMAL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper is bonded to each other is called Cu-Cu (copper-copper) direct bonding.

[0401] <Cross-sectional configuration example 1 of arithmetic device> Next, a specific configuration example of the arithmetic device CDVS shown in Fig. 16 and Fig. 17 will be described. Fig. 18 is a schematic cross-sectional view of one example of the arithmetic device CDVS shown in Fig. 16 and Fig. 17.

[0402] Fig. 18 shows a schematic cross-sectional view of the circuit layer PHRL and the arithmetic layer OMAL. Note that the arithmetic device CDV in Fig. 18 shows a configuration in which the arithmetic layer OMAL is formed directly on the circuit layer PHRL.

[0403] 18 illustrates a transistor 400 included in the circuit layer PHRL. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, insulating layers 315 and 317 functioning as gate insulating films, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions including part of the substrate. The transistor 400 may be a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single-crystal silicon substrate.

[0404] Here, in the transistor 400 shown in FIG. 18 , a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0405] Note that the transistor 400 illustrated in FIG. 18 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0406] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0407] For example, an insulating layer 320, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0408] The insulating layer functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method to improve the planarity.

[0409] 18 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0410] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Contact plugs or wiring are preferably embedded in the insulating layer 354 to connect to an upper circuit (for example, a circuit included in the circuit included in the arithmetic layer OMAL).

[0411] 18 illustrates a part of the arithmetic cell included in the arithmetic layer OMAL. Specifically, FIG. 18 illustrates a part of the transistors MA_1, MA_2, MB_1, MB_2, capacitors CA_1, CA_2, and capacitors CB included in the arithmetic cell. Note that the arithmetic cell may be the arithmetic cell IM illustrated in FIG. 1 described in the above embodiment.

[0412] 18 , the transistors MB_1 and MB_2 are formed on an insulating layer STJ1. The transistors MA_1 and MA_2 are formed on an insulating layer STJ2. The capacitors CA_1, CA_2, and CB are formed on an insulating layer STJ3. The insulating layer STJ2 is located above the insulating layer STJ1, and the insulating layer STJ3 is located above the insulating layer STJ2. Therefore, the capacitors CA_1, CA_2, and CB are located above the transistors MA_1 and MA_2, and the transistors MA_1 and MA_2 are located above the transistors MB_1 and MB_2.

[0413] Note that it is preferable that each of the insulating layers STJ1 to STJ3 function as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layers STJ1 to STJ3 can suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be applied to each of the insulating layers STJ1 to STJ3, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0414] A conductive layer functioning as a wiring IL_1 is connected to one of the source electrode or drain electrode of the transistor MB_1 through a plug, and a conductive layer functioning as a wiring VE1 is connected to the other of the source electrode or drain electrode of the transistor MB_1 through a plug. A conductive layer functioning as a wiring IL_2 is connected to one of the source electrode or drain electrode of the transistor MB_2 through a plug, and a conductive layer functioning as a wiring VE1 is connected to the other of the source electrode or drain electrode of the transistor MB_2 through a plug. The wirings IL_1, IL_2, and VE1 are, for example, extended in the channel width direction of the transistor MA_1 or the transistor MA_2.

[0415] In addition, a conductive layer that functions as one of a pair of electrodes of a capacitor element CA_1 is connected to one of the gate electrodes of transistor MB_1 via a plug, and a conductive layer that functions as one of a pair of electrodes of a capacitor element CA_2 is connected to one of the gate electrodes of transistor MB_2 via a plug.

[0416] A conductive layer functioning as one of a pair of electrodes of a capacitor CA_1 is connected to one of the source electrode or drain electrode of the transistor MA_1 through a plug, a conductive layer functioning as one of a pair of electrodes of a capacitor CA_2 is connected to the other of the source electrode or drain electrode of the transistor MA_1 through a plug, a conductive layer functioning as one of a pair of electrodes of a capacitor CA_2 is connected to one of the source electrode or drain electrode of the transistor MA_2 through a plug, and a conductive layer functioning as one of a pair of electrodes of a capacitor CB is connected to the other of the source electrode or drain electrode of the transistor MA_2 through a plug.

[0417] A conductive layer functioning as a wiring WSL is connected to the gate electrode of the transistor MA_1, and a conductive layer functioning as a wiring WSL is connected to the gate electrode of the transistor MA_2.

[0418] The conductive layers serving as the gate electrodes of the transistors MA_1 and MA_2 extend in the channel width direction.

[0419] An insulating layer functioning as an interlayer film is formed between the transistors MB_1 and MB_2 and the transistors MA_1 and MA_2. The insulating layer has openings in regions overlapping with the gate electrodes of the transistors MB_1 and MB_2, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping with the source or drain electrodes of the transistors MB_1 and MB_2, and conductive layers serving as plugs are embedded in the openings.

[0420] An insulating layer functioning as an interlayer film is formed between the transistors MA_1 and MA_2 and the capacitors CA_1 and CA_2. The insulating layer has openings in regions overlapping with the gate electrodes of the transistors MA_1 and MA_2, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping with the source or drain electrodes of the transistors MA_1 and MA_2, and conductive layers serving as plugs are embedded in the openings.

[0421] The conductive layer that functions as one of the pair of electrodes of the capacitor CA_1 is formed so as to be embedded in the insulating layer STJ4 on the insulating layer STJ3. Similarly, the conductive layer that functions as one of the pair of electrodes of the capacitor CA_2 and the conductive layer that functions as one of the pair of electrodes of the capacitor CB are also formed so as to be embedded in the insulating layer STJ4.

[0422] A conductive layer that functions as the other electrode of the capacitor CA_1 is provided above one of the pair of electrodes of the capacitor CA_1 and a part of the insulating layer STJ4, with an insulating layer that functions as a dielectric interposed therebetween. The conductive layer also functions as the wiring XCL_1.

[0423] Similarly, a conductive layer that functions as the other of the pair of electrodes of the capacitor CA_2 is provided between one of the pair of electrodes of the capacitor CA_2 and another part of the insulating layer STJ4, with an insulating layer that functions as a dielectric interposed therebetween. Note that this conductive layer also functions as the wiring XCL_2.

[0424] Similarly, a conductive layer that functions as the other of the pair of electrodes of the capacitance element CB is provided on one of the pair of electrodes of the capacitance element CB and another part of the insulating layer STJ4, with the insulating layer that functions as the dielectric interposed therebetween. Note that the conductive layer also functions as the wiring SEL.

[0425] By embedding the conductive layer that functions as one of the pair of electrodes of the capacitor CA_1 in the insulating layer STJ4, the conductive layer that functions as one of the pair of electrodes of the capacitor CA_1 and the insulating layer STJ4 can be planarized to be flush with each other. This allows an insulating layer that functions as a dielectric and a conductive layer that functions as the other of the pair of electrodes of the capacitor CA_1 to be formed with good flatness on the upper surfaces of the conductive layer that functions as one of the pair of electrodes of the capacitor CA_1 and the insulating layer STJ4, which have good flatness. By improving the flatness of both the pair of electrodes of the capacitor CA_1 and the insulating layer that functions as a dielectric, localized concentration of the electric field can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitor CA_1 can be prevented. Furthermore, one of the pair of electrodes of the capacitor CA_1 (here, the lower electrode) is configured to have a smaller area than the other of the pair of electrodes of the capacitor CA_1 (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that may occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitor CA_1, thereby realizing a highly reliable semiconductor device. Note that the same applies to the capacitor CA_2 and the capacitor CB.

[0426] In addition, in the configuration example of FIG. 18 , the conductive layer that functions as the wiring XCL_1, the conductive layer that functions as the wiring XCL_2, and the conductive layer that functions as the wiring SEL are each extended in the channel width direction of the transistor MA_1, the transistor MA_2, the transistor MB_1, and the transistor MB_2.

[0427] 18 , a conductive layer functioning as a back gate may be provided under the island-shaped semiconductor layer of each of the transistors MA_1, MA_2, MB_1, and MB_2. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0428] For example, by providing a back gate to each of the transistors MA_1, MA_2, MB_1, and MB_2, the influence of an external electric field can be reduced and the transistors can be stably maintained in an off state. Therefore, data written to the first terminals of the capacitors CA_1 and CB can be stably held. In this way, providing a back gate stabilizes the operation of the computation cell IM and improves the reliability of the computation layer OMAL including the computation cell IM.

[0429] As the semiconductor layers in which the channels of the transistors MA_1, MA_2, MB_1, and MB_2 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0430] Note that each of the transistors MA_1, MA_2, MB_1, and MB_2 is preferably a transistor (OS transistor) that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the arithmetic cell can be reduced. Therefore, the power consumption of the arithmetic device CDVS including the arithmetic cell IM can be reduced.

[0431] 18 is also an example of the calculation cell IM in Fig. 1, and therefore can hold the first data. Therefore, the calculation cell or calculation unit CDVS in Fig. 18 can be called an "OS memory."

[0432] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0433] In the configuration example of FIG. 18, in order to prevent formation of parasitic capacitance with the back gate of the transistor MA_1, the conductive layer functioning as the wiring VE1 is divided into two portions and extends.

[0434] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor called a GL (Gate Last) structure that can be applied to the transistor MA_1, the transistor MA_2, the transistor MB_1, and the transistor MB_2 shown in Fig. 18 will be described. A transistor 500 shown in Fig. 19A and Fig. 19B is an example of a transistor with a GL structure that can be applied to the transistor MA_1, the transistor MA_2, the transistor MB_1, and the transistor MB_2 shown in Fig. 10.

[0435] In particular, FIG. 19A shows a schematic cross-sectional view of the transistor 500 in the channel length direction, and FIG. 19B shows a schematic cross-sectional view of the transistor 500 in the channel width direction.

[0436] 19A and 19B , for example, the transistor 500 includes a semiconductor layer 531a, a semiconductor layer 531b, a conductive layer 505, a conductive layer 542a, a conductive layer 542b, an insulating layer 580, a conductive layer 560, an insulating layer 514, an insulating layer 516, an insulating layer 520, an insulating layer 522, an insulating layer 524, an insulating layer 550, an insulating layer 554, an insulating layer 574, an insulating layer 580, and an insulating layer 581. Note that the transistor 500 does not necessarily include all of the above components. For example, the conductive layer 505 functions as a backgate electrode of the transistor 500, but the transistor 500 may not include the conductive layer 505.

[0437] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0438] The conductive layer 505 (conductive layer 505a and conductive layer 505b) and the insulating layer 516 are disposed above a substrate (not shown). In particular, the conductive layer 505 is preferably provided so as to be embedded in the insulating layer 516. Specifically, the conductive layer 505a is preferably provided in contact with a bottom surface and a sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is preferably provided so as to be embedded in a recess formed in the conductive layer 505a. Note that in the transistor 500 shown in FIGS. 19A and 19B , the height of the top surface of the conductive layer 505b is approximately equal to the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0439] The insulating layer 516 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 320. Therefore, the insulating layer 516 can be made of a material that functions as a planarizing film, similar to the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced.

[0440] For this reason, the insulating layer 516 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 516 can be made of, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating. Alternatively, the insulating layer 516 can be made of, for example, a resin. The material used for the insulating layer 516 may be an appropriate combination of the above-mentioned insulating materials.

[0441] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0442] The semiconductor layer 531 and the conductive layer 560 are disposed in a region overlapping with the conductive layer 505. The semiconductor layer 531b is disposed on the semiconductor layer 531a. The conductive layers 542a and 542b are disposed on the semiconductor layer 531b and spaced apart from each other. The insulating layer 580 is disposed on the conductive layers 542a and 542b. In particular, an opening is formed in the insulating layer 580 in a region between the conductive layers 542a and 542b. The conductive layer 560 is disposed in the opening. The insulating layer 550 is disposed between the semiconductor layer 531b, the conductive layers 542a and 542b, and the insulating layer 580 and the conductive layer 560. Here, as shown in FIGS. 19A and 19B , it is preferable that the top surface of the conductive layer 560 be substantially flush with the top surfaces of the insulating layers 550 and 580. Note that hereinafter, the conductive layers 505a and 505b may be collectively referred to as conductive layers 505. The semiconductor layers 531a and 531b may be collectively referred to as semiconductor layers 531. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0443] 19A , a region 543a may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542a and in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. Therefore, the region 543a can be one of a source electrode and a drain electrode, and the region 543b can be the other of the source electrode and the drain electrode. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0444] Providing the conductive layer 542a in contact with the semiconductor layer 531 may reduce the oxygen concentration in the region 543a. Furthermore, a metal compound layer containing the metal contained in the conductive layer 542a and components of the semiconductor layer 531 may be formed in the region 543a. Similarly, providing the conductive layer 542b in contact with the semiconductor layer 531 may reduce the oxygen concentration in the region 543b. Furthermore, a metal compound layer containing the metal contained in the conductive layer 542b and components of the semiconductor layer 531 may be formed in the region 543b. Furthermore, the regions 543a and 543b may have high impurity concentrations such as hydrogen, nitrogen, and metal elements. In such cases, the carrier concentrations of the regions 543a and 543b increase, and the regions 543a and 543b become low-resistance regions. That is, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentrations than the channel formation region.

[0445] On the other hand, the channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0446] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0447] Note that when the carrier concentration of the semiconductor layer 531 is reduced, the impurity concentration in the semiconductor layer 531 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic. Note that an oxide semiconductor (or a metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0448] In order to stabilize the electrical characteristics of the transistor 500, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 531. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 531, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 531 refer to, for example, elements other than the main components constituting the semiconductor layer 531. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0449] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 531. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0450] In a transistor using an oxide semiconductor for the semiconductor layer 531, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0451] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 500 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0452] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. Furthermore, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0453] 19A and 19B , the side surfaces of the conductive layers 542a and 542b facing the conductive layer 560 have a substantially perpendicular shape. Note that the transistor 500 shown in FIGS. 19A and 19B is not limited thereto, and the angle between the side surface and the bottom surface of the conductive layers 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 542a and 542b may have a plurality of surfaces.

[0454] Note that the transistor 500 has a two-layer structure in which the semiconductor layer 531a and the semiconductor layer 531b are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this. For example, the semiconductor layer 531b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 531a and the semiconductor layer 531b may have a stacked structure of two or more layers.

[0455] The conductive layer 560 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 542a and the conductive layer 542b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and in the region sandwiched between the conductive layer 542a and the conductive layer 542b. Here, the conductive layer 560, the conductive layer 542a, and the conductive layer 542b are self-aligned with the opening of the insulating layer 580. That is, in the transistor 500, the first gate electrode can be self-aligned between the source electrode and the drain electrode. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 500. This allows for an increase in the density of arithmetic cells in the arithmetic device.

[0456] 19A and 19B , the conductive layer 560 is shown as having a two-layer structure. Here, the conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0457] The conductive layer 560a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen.

[0458] Furthermore, since the conductive layer 560a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 580, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0459] The conductive layer 560b is preferably a conductive layer with high conductivity. For example, the conductive layer 560b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0460] For the conductive layers 542a and 542b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b. When a conductive material containing metal and nitrogen is used for the conductive layers 542a and 542b, the conductive layers 542a and 542b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 560a and 560b.

[0461] For example, the conductive layers 540a and 540b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.

[0462] For example, the conductive layer 540 a and the conductive layer 540 b can have a stacked structure including a plurality of layers. In particular, it is preferable to stack a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity.

[0463] The conductive layer 505 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 505 may be changed independently of the potential applied to the conductive layer 560, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 505, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 505, the drain current when the potential applied to the conductive layer 560 is 0 V can be made smaller than when no negative potential is applied.

[0464] 19B , the conductive layer 505 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 531. That is, on the outside of the side surface of the semiconductor layer 531 in the channel width direction, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween.

[0465] 19A , the conductive layer 560 preferably includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 is shown as having a two-layer stacked structure in FIGS. 19A and 19B , the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0466] 19A and 19B , the transistor 500 preferably includes an insulating layer 512 disposed on a substrate (not shown), an insulating layer 514 disposed on the insulating layer 512, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 520 disposed on the insulating layer 516 and the conductive layer 505, an insulating layer 522 disposed on the insulating layer 520, and an insulating layer 524 disposed on the insulating layer 522. A semiconductor layer 531 a is preferably disposed on the insulating layer 524.

[0467] 19A and 19B, an insulating layer 554 is preferably disposed between the insulating layer 522, the insulating layer 524, the semiconductor layer 531a, the semiconductor layer 531b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. Here, the insulating layer 554 is preferably in contact with the side surface of the insulating layer 550, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces and top surfaces of the semiconductor layer 531a, the semiconductor layer 531b, and the insulating layer 524, and the top surface of the insulating layer 522, as shown in FIG.

[0468] An insulating layer 574 and an insulating layer 581 functioning as interlayer films are preferably provided over the transistor 500. Here, the insulating layer 574 is preferably provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, and the insulating layer 580. In this case, the top surface of the insulating layer 580 is preferably planarized.

[0469] It is preferable to provide a conductive layer 540 (conductive layer 540a and conductive layer 540b) that is connected to the transistor 500 and functions as a plug. Therefore, the conductive layer 540 is provided in contact with inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In particular, a first conductive layer of the conductive layer 540 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 540 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 540 can be made approximately the same as the height of the top surface of the insulating layer 581.

[0470] Specifically, for example, a first conductive layer of the conductive layer 540a is provided in contact with one of the inner walls of the two openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a second conductive layer of the conductive layer 540a is formed in contact with the side surface of the first conductive layer. Note that a conductive layer 542a is located in part of the bottom of the opening, and the conductive layer 540a is in contact with the conductive layer 542a. Similarly, for example, a first conductive layer of the conductive layer 540b is provided in contact with the other inner wall of the two openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a second conductive layer of the conductive layer 540b is formed in contact with the side surface of the first conductive layer. Note that the conductive layer 542b is located in part of the bottom of the opening, and the conductive layer 540b is in contact with the conductive layer 542b.

[0471] Note that although the transistor 500 has a structure in which the first conductive layer of the conductive layer 540 and the second conductive layer of the conductive layer 540 are stacked, the present invention is not limited to this. For example, the conductive layer 540 may have a single layer structure or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0472] 19B , in a region of the semiconductor layer 531b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 531, the side surface of the semiconductor layer 531 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 531, and as a result, the channel formation region of the semiconductor layer 531 can be electrically surrounded by the electric field of the conductive layer 560. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved.

[0473] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 580 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0474] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0475] The upper surfaces of the insulating layers 580 may be planarized, so that the insulating layers 580 also function as planarizing films.

[0476] As described above, the insulating layer 580 can be formed using a material similar to that of the insulating layer 516 .

[0477] <<Constituent Materials of Transistor>> Next, the materials that constitute the transistor 500 will be described.

[0478] [Metal Oxide (Oxide Semiconductor)] The transistor 500 preferably includes a metal oxide that functions as an oxide semiconductor, including a channel formation region. For example, the metal oxide that forms the channel formation region preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Specifically, for example, in the case of the transistor 500 in FIGS. 19A and 19B , the semiconductor layer 531 preferably includes a metal oxide that functions as an oxide semiconductor.

[0479] Note that the structure of a metal oxide can be divided into a single crystal structure and other structures (non-single crystal structures). Examples of non-single crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures may be used. However, the use of a crystalline metal oxide, typified by a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0480] The metal oxide can be an oxide semiconductor having an axial growth CAAC (AG CAAC) structure. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced by solid-phase growth of a metal oxide contained in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer, using the second layer as a nucleus or seed.

[0481] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The first layer may be formed by a wet method. Alternatively, molecular beam epitaxy (MBE), which is a film formation method for growing a thin film having a crystal structure that reflects the crystal system of the substrate, may be used. These film formation methods can reduce damage to the surface on which the film is formed, compared to sputtering.

[0482] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). By forming the second layer after the first layer, in particular, it is possible to prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, it is possible to prevent impurities contained in the surface on which the second layer is formed from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0483] In addition, methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include, for example, heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0484] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0485] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor layer by the ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0486] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0487] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0488] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably room temperature or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0489] In addition to the above-described method for forming an oxide semiconductor layer, treatment for increasing the crystallinity of the oxide semiconductor layer can be performed, whereby a highly reliable transistor can be provided.

[0490] As described in the above embodiment, the metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the element M is contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more selected from aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of gallium and tin.

[0491] Specifically, for example, the metal oxide may be In-Ga-Zn oxide (indium-gallium-zinc oxide), Ga-Zn oxide, gallium oxide, or indium oxide.

[0492] The metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. Alternatively, a metal oxide having an atomic ratio of In:Zn=4:1 may be used.

[0493] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0494] [Conductive Layer] For the conductive layer included in the transistor 500, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more selected from the above metal elements, or an alloy combining two or more selected from the above metal elements. For the conductive layer, it is preferable to use, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0495] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0496] 19A and 19B , a conductive layer functioning as a second gate electrode, for example, the conductive layer 505 shown in FIGS. 19A and 19B , is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has a function of suppressing the diffusion of oxygen is preferably used. In particular, examples of conductive materials that have a function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0497] In addition to the above, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0498] 19A and 19B , a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. For example, the conductive layer preferably includes tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0499] The conductive layer functioning as the first gate electrode, for example, the conductive layer 560 shown in FIGS. 19A and 19B, is preferably a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferably a conductive material having a function of suppressing the diffusion of oxygen. Examples of conductive materials having a function of suppressing the diffusion of oxygen include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductive layer, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0500] The conductive layer functioning as the first gate electrode is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer also functions as a wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0501] The conductive layer may be formed using, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon. The conductive layer may be formed using, for example, indium gallium zinc oxide containing nitrogen. The use of such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0502] [Insulating Layer] Examples of the insulating layer included in the transistor 500 include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

[0503] The insulating layer that can be provided in the transistor preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layer of the transistor 500 from the substrate side. Therefore, the insulating layer is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0504] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include, for example, single-layer or multi-layer insulating layers containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0505] The second gate insulating film in contact with the metal oxide contained in the channel formation region, for example, the insulating layer 522 and the insulating layer 524 shown in FIGS. 19A and 19B, preferably has oxygen released by heating. In this specification and the like, oxygen released by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be used as the second gate insulating film as appropriate. By providing an insulating layer containing oxygen in contact with the metal oxide, oxygen vacancies in the metal oxide can be reduced, and the reliability of the transistor can be improved.

[0506] Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulating layer. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms by thermal desorption spectrometry (TDS) is 1.0×10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0×10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0507] Furthermore, the insulating layer included in the transistor may preferably contain an oxide of one or both of aluminum and hafnium, which are insulating materials. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide and hafnium oxide. Another example is an oxide containing aluminum and hafnium (hafnium aluminate). When such a material is used to form an insulating layer around a transistor, the insulating layer can function as a layer that suppresses oxygen release and the intrusion of impurities such as hydrogen from the periphery of the transistor into the metal oxide.

[0508] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to an insulating layer included in a transistor. Alternatively, these insulating layers may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layer.

[0509] The insulating layer included in the transistor may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) may be used as a single layer or a laminate.

[0510] 19A and 19B , an insulating layer serving as a first gate insulating film, for example, the insulating layer 550 shown in FIG. 19A and FIG. 19B , is preferably disposed in contact with the upper surface of the metal oxide. The insulating layer can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable to heat.

[0511] <<Transistor Configuration Example 2>> For each of the transistors MA_1, MA_2, MB_1, and MB_2 provided in the arithmetic layer OMAL of the arithmetic device CDVS shown in FIG. 18, a transistor having a different structure can be used instead of the transistor 500 having the GL structure shown in FIG. 19.

[0512] For example, the structure of transistor 500mf including two fin-shaped and circumferentially shaped semiconductor layers shown in each of Figures 20A to 20D can be applied instead to each of transistors MA_1, MA_2, MB_1, and MB_2 in Figure 18.

[0513] Fig. 20A is a schematic plan view of the transistor 500mf, and Figs. 20B to 20D are schematic cross-sectional views of the transistor 500mf. In particular, Fig. 20B is a schematic cross-sectional view of the portion indicated by dashed-dotted line A1-A2 in Fig. 20A and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 20C is a schematic cross-sectional view of the portion indicated by dashed-dotted line A3-A4 in Fig. 20A and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 20D is a schematic cross-sectional view of the portion indicated by dashed-dotted line A5-A6 in Fig. 20A and is also a schematic cross-sectional view of the transistor 500mf in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the schematic plan view of FIG. 20A, some elements are omitted for clarity, and some elements are shown transparently. FIG. 21A shows an enlarged view of the vicinity of the conductive layer 560 in FIG. 20D. FIG. 21B shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 20B. FIG. 21C shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 20C.

[0514] The transistor 500mf includes an insulating layer 516 over the insulating layer 514, an insulating layer 521 over the insulating layer 516, an insulating layer 522 over the insulating layer 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 550 over the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 550. Note that hereinafter, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0515] An insulating layer 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulating layer 575. The openings reach the semiconductor layer 530, and the insulating layer 550 is in contact with the semiconductor layer 530 within the openings. An insulating layer 582 is provided over the insulating layer 580 and the conductive layer 560. An insulating layer 583 is provided over the insulating layer 582.

[0516] An insulating layer 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of the opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulating layers 541a and 541b may be collectively referred to as the insulating layer 541.

[0517] For the insulating layers 541 a and 541 b, an insulating film having a function of suppressing oxygen permeation is preferably used to prevent a decrease in conductivity due to oxidation of the conductive layers 542 a and 542 b. For example, a silicon nitride film is preferably formed by a PEALD method.

[0518] For the insulating layer 516, the description of the insulating layer 516 shown in FIGS. 19A and 19B can be referred to.

[0519] For the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350. Therefore, for the insulating layers 521 and 522, it is preferable to use an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 324 and 350.

[0520] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500mf. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500mf. The insulating layer 550 has a region that functions as a first gate insulating film of the transistor 500mf.

[0521] In particular, a metal oxide functioning as an oxide semiconductor can be used for the semiconductor layer 530. In this case, the transistor 500mf is an OS transistor. Note that the semiconductor layer 531 shown in FIGS. 19A and 19B or any of the above-described metal oxides can be used for the semiconductor layer 530.

[0522] In particular, the semiconductor layer 530 can include the oxide semiconductor AG CAAC described above as a metal oxide.

[0523] 21B, the semiconductor layer 530 may include a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. Preferably, the side surfaces of the semiconductor layer 530 (the semiconductor layers 530a to 530c) are also perpendicular or substantially perpendicular to the substrate surface.

[0524] As described above, in a cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a transmission electron microscope (TEM) image, it is confirmed that metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In other words, in a cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the semiconductor layer 530.

[0525] In this way, by using the semiconductor layer 530 made of AG CAAC in the channel formation region of the transistor 500mf, a transistor with large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability can be provided. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0526] The semiconductor layers 530a to 530c can be formed, for example, by providing a pillar that functions as a sacrificial layer on the insulating layer 522, depositing a first semiconductor film that will become the semiconductor layer 530a, a second semiconductor film that will become the semiconductor layer 530b, and a third semiconductor film that will become the semiconductor layer 530c on the side surfaces of the pillar in this order, removing the first to third semiconductor films located on the top surfaces of the insulating layer 522 and the pillars, and then removing the pillars.

[0527] Furthermore, when the semiconductor layer 530 has a three-layer structure of semiconductor layers 530a to 530c as described above, the semiconductor layer 530 is formed in the order of semiconductor layer 530a, semiconductor layer 530b, and semiconductor layer 530c, with the region where the pillars were formed at the center. In other words, as shown in Fig. 20A , the semiconductor layer 530 has a structure that surrounds the region where the pillars were formed in a plan view.

[0528] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the semiconductor layer 530. At least a part of the channel formation region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0529] 21B , the insulating layer 550 includes an insulating layer 550a, an insulating layer 550b, an insulating layer 550c, and an insulating layer 550d. The insulating layers 550a to 550d function as part of a first gate insulating film. The insulating layers 550a to 550d are provided in an opening formed in the insulating layer 580, similar to the conductive layer 560 described later. To miniaturize the transistor 500mf, the insulating layers 550a to 550d are preferably thin. The thicknesses of the insulating layers 550a to 550d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is only necessary that at least a part of each of the insulating layers 550a to 550d has a region with the above-described thickness.

[0530] The thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm to 3 nm.

[0531] In order to thin the insulating layers 550a to 550d as described above, it is preferable to form the insulating layers 550a to 550d by atomic layer deposition (ALD). Furthermore, it is preferable to form the insulating layers 550a to 550d in openings such as the insulating layer 580 by ALD. Examples of ALD include thermal ALD, in which a precursor and a reactant are reacted using only thermal energy, and PEALD, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, enabling film formation at a lower temperature.

[0532] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 550 can be formed with good coverage on the side surface of the opening formed in the insulating layer 580 and with the thin film thickness as described above.

[0533] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0534] Although the insulating layer 550 has been described above as having a four-layer structure of insulating layers 550a to 550d, the present invention is not limited to this. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By forming the insulating layer 550 using one, two, or three of the insulating layers 550a to 550d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0535] For example, the insulating layer 550 may have a three-layer structure. In this case, it is preferable that the insulating layer 550 has a laminated structure of an insulating layer 550a, an insulating layer 550b on the insulating layer 550a, and an insulating layer 550c on the insulating layer 550b. In other words, this is a structure obtained by removing the insulating layer 550d from the structure shown in FIG. 21A.

[0536] It is preferable to use the ALD process two or more times in forming the insulating layer 550. For example, the insulating layer 550 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 550. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0537] For example, the insulating layer 550a is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550b is preferably made of silicon oxide, which has a high dielectric strength. The insulating layer 550c is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550d is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0538] 19A and 19B can be referred to for the conductive layer 560. For the conductive layer 560a and the conductive layer 560b, for example, the same material as that of the conductive layer included in the transistor 500 can be used.

[0539] In the transistor 500mf, the conductive layer 560 is arranged in a self-aligned manner to fill an opening formed in the insulating layer 580 or the like. Here, the side surfaces of the insulating layer 580 in the openings coincide or substantially coincide with the side surfaces of the conductive layer 542a and the conductive layer 542b. Therefore, the conductive layer 560 can be arranged to overlap the region between the conductive layer 542a and the conductive layer 542b without alignment.

[0540] The conductive layer 542a has a region functioning as one of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0541] The conductive layers 540a and 540b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 540 may have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 541 and a second conductive layer is provided further inside. In this case, the above-described conductive material may be used as the second conductive layer. The conductive layers 540a and 540b may also be made of materials that can be used for the conductive layers 560a and 560b. Here, the first conductive layer corresponds to the conductive layer 540a1 shown in FIG. 21A , and the second conductive layer corresponds to the conductive layer 540a2 shown in FIG. 21A .

[0542] Furthermore, when the conductive layer 540 has a stacked structure, a first conductive layer disposed near the insulating layer 583, the insulating layer 582, the insulating layer 580, and the insulating layer 575 is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 583 can be prevented from entering the semiconductor layer 530 through the conductive layer 540a and the conductive layer 540b.

[0543] For example, the insulating layer 575 is preferably a barrier insulating film against oxygen. Examples of the barrier insulating film against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0544] For the insulating layer 580, the description of the insulating layer 580 included in the transistor 500 in FIGS. 19A and 19B can be referred to.

[0545] One or both of the insulating layers 582 and 583 preferably function as a barrier insulating layer that suppresses diffusion of impurities from above the insulating layers 582 and 583 to the transistor 500mf or the like. Therefore, one or both of the insulating layers 582 and 583 preferably include an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (through which the impurities are less likely to permeate). Alternatively, one or both of the insulating layers 582 and 583 preferably includes an insulating material that has a function of suppressing diffusion of oxygen (through which the oxygen is less likely to permeate).

[0546] The insulating layers 582 and 583 preferably have an insulating layer that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and can be made of, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulating layer 583 is preferably made of silicon nitride, which has a higher hydrogen barrier property. For example, the insulating layer 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.

[0547] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. As shown in Figures 21B and 21C, the semiconductor layer 530 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. For this reason, the semiconductor layer 530 can also be said to have a fin-like shape.

[0548] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the semiconductor layer 530 in the direction of the dashed dotted line A1-A2 (which can also be referred to as the width L of the semiconductor layer 530) to the length H of the semiconductor layer 530 in a direction perpendicular to the surface on which the semiconductor layer 530 is formed (for example, the insulating layer 522) (which can also be referred to as the height H of the semiconductor layer 530). The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range in which the semiconductor layer 530 does not collapse during the manufacturing process of the transistor 500mf. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 is preferably greater than 1 time and less than 400 times the width L of the semiconductor layer 530, more preferably 2 times to 100 times, even more preferably 5 times to 40 times, and even more preferably 10 times to 20 times. Furthermore, for example, the height H is preferably 2 to 10 times the width L. Furthermore, for example, the width L is preferably 5 to 100 nm, more preferably 5 to 50 nm, and even more preferably 10 to 30 nm. Furthermore, for example, the height H is preferably 50 to 2000 nm, and more preferably 100 to 1000 nm. Furthermore, for example, the height H is preferably 50 to 100 nm.

[0549] 21B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0550] An insulating layer 550, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500mf, as shown in FIG. 21B , a portion of the insulating layer 550 and a portion of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 550 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500mf is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0551] As described above, the increase in channel width allows the on-state current of the transistor 500mf to be increased. Furthermore, the mutual conductance of the transistor 500mf is improved. Furthermore, the frequency characteristics of the transistor 500mf are improved. By using the transistor 500mf in one or both of the pixel circuit and the driver circuit included in a display device, a display device with a high frame frequency can be provided. Furthermore, in the above structure, the provision of the semiconductor layer 530 allows the channel width to be increased without increasing the area occupied by the transistor 500mf. This allows for miniaturization or high integration of the pixel circuit and the driver circuit.

[0552] 20B , the upper portion of the semiconductor layer 530 may have a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 550 and the conductive layer 542 near the upper portion of the semiconductor layer 530. While FIGS. 20B and 20C illustrate a symmetrical structure in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 530, the present invention is not limited to this. For example, an asymmetrical structure may also be obtained in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 530.

[0553] Because the semiconductor layer 530 has a shape with a high aspect ratio, it is preferable to form the semiconductor layer 530 by, for example, first forming a pillar and then forming the semiconductor layer 530 in a sidewall shape on the side surface of the pillar. Therefore, it is preferable to form the semiconductor layer 530 using an atomic layer deposition (ALD) method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0554] 20A , by forming the semiconductor layer 530 in a sidewall shape in contact with the side surfaces of the plurality of pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillar. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistor 500mf can be reduced, and a higher integration of the display device can be achieved.

[0555] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 20A , the top surface shape of the semiconductor layer 530 is a circumferential shape with both ends coinciding (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape). The semiconductor layer 530 can also be said to have a shape with an opening in the center. Note that in FIG. 20A , the top surface shape of the semiconductor layer 530 is line-symmetrical about the dashed dotted line A1-A2, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 530 may be asymmetrical.

[0556] The structure shown in FIG. 20A includes two pillars arranged in the direction of the dashed-dotted line A1-A2, with a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 20A , the semiconductor layer 530 preferably overlaps the conductive layer 560 at two or more locations in a plan view. That is, the semiconductor layer 530 and the conductive layer 560 have two or more overlapping regions. This structure results in multiple fin-shaped semiconductor layers 530 being formed in a cross-sectional view in the channel width direction, as shown in FIG. 20B . Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500mf functions as a multi-channel transistor. Therefore, the channel width of the transistor 500mf can be further increased. Because the transistor 500mf includes multiple fin-shaped semiconductor layers 530, it is sometimes referred to as a multi-fin structure transistor.

[0557] Although the above description has been given of a configuration in which two circumferential semiconductor layers 530 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 530 are provided may also be used. Furthermore, the circumferential semiconductor layers 530 may be joined together to form a semiconductor layer 530 having a shape with a plurality of openings.

[0558] Although the above description is directed to a circumferential semiconductor layer 530, the present invention is not limited to this. For example, the semiconductor layer 530 may have a non-circumferential configuration. For example, in the transistor 500mf shown in FIGS. 20A to 20D , the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b may intersect with the fin-shaped semiconductor layer 530 in a single region. By reducing the number of intersecting points in the fin-shaped semiconductor layer 530 between the conductive layer 540a, the insulating layer 550, the conductive layer 560, and the conductive layer 540b, the area in which the transistor is formed can be reduced, thereby reducing the area occupied by a circuit including the transistor. Note that the structure of the transistor may be referred to as a single fin structure.

[0559] <<Second Example of Cross-Sectional Configuration of Arithmetic Device>> FIG. 22 is a schematic cross-sectional view of an example of the arithmetic device CDVS shown in FIGS. 16 and 17, which is different from FIG. 18.

[0560] The arithmetic unit CDVS of FIG. 22 differs from the arithmetic unit CDVS of FIG. 18 in that the transistors included in the arithmetic layer OMAL are vertical channel transistors.

[0561] In the operation layer OMAL shown in Figure 22, the source electrode and drain electrode of each of the transistors MA_1, MA_2, MB_1, MB_2, and MC are located at different heights, and the current flowing through the semiconductor layer is configured to flow in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction), and therefore they are called vertical channel transistors. Note that each of the transistors MA_1, MA_2, MB_1, MB_2, and MC can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like, in addition to being called a vertical channel transistor.

[0562] Furthermore, as an example, the calculation layer OMAL of the calculation device CDVS in Figure 22 is configured such that transistor MA_2, transistor MC, and capacitance element CB are included in area AREa, and transistor MA_1, transistor MB_1, transistor MB_2, capacitance element CA_1, and capacitance element CA_2 are included in area AREb.

[0563] 23A shows a schematic plan view of an example of the arithmetic device CDVS, and FIG. 23B shows a schematic cross-sectional view of the arithmetic device CDVS. FIG. 22 is a schematic cross-sectional view taken along dashed line A1-A2 in FIG. 23A, and FIG. 23B is a schematic cross-sectional view taken along dashed line A3-A4 in FIG. 23A. FIG. 23B shows selected transistors included in the arithmetic layer OMAL. FIG. 24 shows a schematic perspective view of the transistor MA_2, transistor MC, and capacitor CB included in region AREa of the arithmetic layer OMAL in FIG. 22, as well as their surrounding wiring. FIG. 25 shows a schematic perspective view of the transistor MA_1, transistor MB_1, transistor MB_2, capacitor CA_1, and capacitor CA_2 included in region AREb of the arithmetic layer OMAL in FIG. 22, as well as their surrounding wiring.

[0564] The configurations of the vertical channel transistor and the capacitance element included in the arithmetic unit CDVS will be described with reference to FIG. 23B.

[0565] FIG. 23B shows a transistor MA_1, which is a vertical channel transistor, and a transistor MB_1, which is a similar vertical channel transistor located below the transistor MA_1.

[0566] As an example, the arithmetic device CDVS includes a conductive layer that functions as wiring VE1, an insulating layer IS1 that functions as an interlayer film, a conductive layer that functions as wiring IL_2, a semiconductor layer SC1 that includes a channel formation region of transistor MB_1, an insulating layer GI1 that functions as a gate insulating film of transistor MB_2, a conductive layer ME1, a conductive layer ME2, an insulating layer IS2 that functions as an interlayer film, a conductive layer ME3, a semiconductor layer SC2 that includes a channel formation region of transistor MA_1, an insulating layer GI2 that functions as a gate insulating film of transistor MA_2, a conductive layer ME4, a conductive layer that functions as wiring WSL, and an insulating layer DI that functions as a dielectric.

[0567] An insulating layer IS1 and a conductive layer functioning as wiring IL_2 are stacked in this order above the conductive layer functioning as wiring VE1. In particular, the insulating layer IS1 and the conductive layer functioning as wiring IL_2 each have an opening that they share in an area where they overlap with the conductive layer functioning as wiring VE1. A semiconductor layer SC1 is formed on the side and bottom of the opening. The semiconductor layer SC1 is also formed on the top surface of the insulating layer IS1 and the top surface of the conductive layer functioning as wiring IL_2. An insulating layer GI1 is formed on the top surface of the semiconductor layer SC1, the top and side surfaces of the conductive layer functioning as wiring IL_2, and the top surface of the insulating layer IS1. A conductive layer ME1 is formed on the top surface of the insulating layer GI1 so as to fill the opening. A conductive layer ME2 is formed on the top surface of the conductive layer ME1. An insulating layer DI is formed on the top surface of the conductive layer ME2.

[0568] Although not shown in FIG. 23B, the insulating layer DI functions as a dielectric for each of the capacitive element CA_1, the capacitive element CA_2, and the capacitive element CB.

[0569] An insulating layer IS2 and a conductive layer ME3 are formed in this order above the conductive layer ME2. An opening is formed in the insulating layer IS2 and the conductive layer ME3, and a semiconductor layer SC2 is formed on the side and bottom of the opening. The semiconductor layer SC2 is also formed on the upper surface of the conductive layer ME3. An insulating layer GI2 is formed on the upper surface of the semiconductor layer SC2, on the side of the conductive layer ME3, and above the insulating layer IS2. A conductive layer ME4 is formed on the upper surface of the insulating layer GI2 so as to fill the opening. A conductive layer functioning as wiring WSL is formed on the upper surface of the conductive layer ME4.

[0570] A part of the conductive layer serving as the wiring VE1 functions as one of the source and drain of the transistor MB_1. A part of the conductive layer serving as the wiring IL_2 functions as the other of the source and drain of the transistor MB_1. A part of the conductive layer ME1 functions as the gate of the transistor MB_1.

[0571] The conductive layer ME2 functions as one of the source and drain of the transistor MA_1, a part of the conductive layer ME3 functions as the other of the source and drain of the transistor MA_1, and a part of the conductive layer ME4 functions as the gate of the transistor MA_1.

[0572] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed, in which the channel length direction has a component in the height direction (vertical direction). The channel length of the transistor MB_1 depends on the thickness of the insulating layer IS1. The thinner the insulating layer IS1, the shorter the channel length, which allows the on-state current of the transistor MB_1 to be increased. On the other hand, the thicker the insulating layer IS1, the longer the channel length, which allows the off-state current of the transistor MB_1 to be reduced. The same applies to the transistor MB_2, which can be formed simultaneously with the transistor MB_1.

[0573] Furthermore, since the channel length of the transistor MA_1 depends on the thickness of the insulating layer IS2, similarly to the transistor MB_2, it is preferable to shorten the thickness of the insulating layer IS2 to increase the on-state current of the transistor MA_1, or to lengthen the thickness of the insulating layer IS2 to decrease the off-state current of the transistor MA_1. This also applies to the transistor MA_2 and the transistor MC, which can be formed simultaneously with the transistor MA_1.

[0574] 23A and 23B, the conductive layer that becomes the wiring IL_2 is provided along the direction of the dashed dotted line A3-A4. Although not shown in FIGS. 23A and 23B, the wiring IL_1 and the wiring WCL in FIG. 22 are also provided along the direction of the dashed dotted line A3-A4.

[0575] The wirings connecting the vertical channel transistors are not formed in the same process but in different processes. As a result, the wirings connecting the vertical channel transistors have overlapping regions in a plan view. In other words, the wirings connecting the vertical channel transistors are provided at different heights, which reduces the parasitic capacitance generated in each wiring. This increases the drive frequency of the transistors MA_1, MA_2, MB_1, MB_2, and MC, thereby increasing the drive speed of the arithmetic unit CDVS.

[0576] 18 and 22 illustrate the capacitors CA_1, CA_2, and CB included in each of the arithmetic devices CDVS and CDVS, respectively, as flat-plate capacitors, but the capacitors in the arithmetic circuit and the arithmetic device according to one embodiment of the present invention are not limited to this. For example, the structures of the capacitors CA_1, CA_2, and CB can be changed to a structure in which a pair of electrodes and a dielectric are included inside openings shared by the insulating layer ISC2 and the conductive layer MED1, respectively, as shown in FIG.

[0577] 26 includes, as an example, a part of the conductive layer MED1, a conductive layer MED2, a part of the conductive layer MEU1, and an insulating layer DIP. Note that Fig. 26 also shows an excerpt of the conductive layer MEU2, the insulating layer ISC1, the insulating layer ISC2, the insulating layer ISC3, and the insulating layer ISC4 as materials formed around the capacitive element CP.

[0578] The conductive layer MED1 functions as a wiring for connecting to one of a pair of electrodes of the capacitor CP. For the conductive layer MED1, the description of the conductive layer ME2 in FIG.

[0579] A portion of the conductive layer MED2 functions as one of a pair of electrodes of the capacitance element CP, a portion of the conductive layer MEU1 functions as the other of the pair of electrodes of the capacitance element CP, and the insulating layer DIP functions as a dielectric of the capacitance element CP. For example, the conductive layer MED1 can be made of a material that can be used for the conductive layer ME2 in FIG. 23B. For the insulating layer DIP, the description of the insulating layer DI in FIG. 23B can be referred to. For the conductive layer MED2, a material that can be used for the conductive layer ME1 or the conductive layer ME4 can be used.

[0580] Furthermore, a conductive layer MEU2 is formed on the upper part of the conductive layer MEU1. The conductive layer MEU2 functions as the wiring XCL_1 or the wiring XCL_2. For this reason, as an example, the conductive layer MEU2 is preferably provided so as to extend in a direction from the front to the back of the drawing.

[0581] The insulating layer ISC1 functions as a base film for forming the conductive layer MED1. The insulating layer ISC2 functions as an interlayer film for separating the conductive layers MED1 and MED2. The insulating layer ISC3 functions as an interlayer film for forming the conductive layer MEU2, which functions as the wiring XCL_1 or XCL_2, above the conductive layer MEU1. Note that the insulating layer ISC3 has an opening in the region where the conductive layers MEU1 and MEU2 overlap, and the conductive layers MEU1 and MEU2 are connected by this opening. The insulating layer ISC4 is an interlayer film provided above the conductive layer MEU2. Note that for each of the insulating layers ISC1 to ISC4, the description of the insulating layer IS1 or the insulating layer IS2 in FIG. 23B can be referred to.

[0582] 26 illustrates a configuration in which the upper surface of the conductive layer MED1 has a recess. The recess can be provided by forming an opening in the insulating layer ISC2. Therefore, it can be said that the bottom of the opening includes the bottom surface of the recess in the conductive layer MED1. Furthermore, the sidewall of the opening includes the side surface of the insulating layer ISC2. Note that the sidewall of the opening may also include the side surface of the recess in the conductive layer MED1.

[0583] By providing a recess in the conductive layer MED1 at a position overlapping the opening of the insulating layer ISC2, the contact area between the conductive layer MED1 and the conductive layer MED2 can be increased compared to when the recess is not provided, thereby reducing the contact resistance between the conductive layer MED1 and the conductive layer MED2 described below.

[0584] The conductive layer MED2 has a region with rounded corners within the recess of the conductive layer MED1. By having this region within the recess, electric field concentration on the insulating layer DIP near the region can be suppressed more effectively than, for example, when the recess has a right angle or an acute angle (a corner). Furthermore, the end of the conductive layer MED2 is located at a lower height from the reference plane than the top surface of the insulating layer ISC2. This allows electric field concentration on the insulating layer DIP near the end to be suppressed more effectively than when the end is located on the insulating layer ISC2. As described above, suppressing electric field concentration on the insulating layer DIP suppresses dielectric breakdown of the insulating layer DIP, thereby providing a highly reliable computing device.

[0585] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0586] Fourth Embodiment In the above-described embodiment, a calculation device capable of multiplying first data and second data has been described. Since the calculation device can also store the first data, it is sometimes called computing-in-memory (CiM) or in-memory computing (iMC). In this embodiment, a storage device capable of storing data and the relationship between the storage device and the calculation device will be described.

[0587] First, a description will be given of memory devices. Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Fig. 27 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Fig. 27, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0588] In FIG. 27 , from the top layer of the triangle, there are shown memories integrated as registers into processing devices such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an NPU (Neural Processing Unit), cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs (Dynamic Random Access Memory), and storage memories such as 3D NANDs and hard disks (also called HDDs: Hard Disk Drives).

[0589] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0590] Cache memory has the function of duplicating and storing a portion of data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the access speed to the data can be increased. Cache memory requires a smaller storage capacity than DRAM, but a faster operating speed than DRAM. Furthermore, data rewritten in cache memory is duplicated and supplied to DRAM. Note that while FIG. 27 illustrates only the L3 cache, the cache hierarchy can have four or more levels. In particular, for example, the cache located at the lowest level of the cache hierarchy may be called LLC (Last Level cache) or FLC (Final Level cache).

[0591] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0592] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0593] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0594] For example, a memory device using an oxide semiconductor (sometimes referred to as an OS memory) can retain data for a long period of time. Therefore, it can be suitably used in the region of Target 1 shown in FIG. 27 . As indicated by the diagonal hatching in FIG. 27 , Target 1 also includes a part of the cache (L1, L2, L3) and a part of the 3D NAND. In other words, Target 1 includes a boundary region between the DRAM and the 3D NAND, and a boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, a memory device using an oxide semiconductor has a high operating speed and can therefore achieve excellent write and read operations. Therefore, it can be suitably used in the region of Target 2 shown in FIG. 27 .

[0595] For example, the DRAM shown in FIG. 27 requires refresh operations and is a destructive readout storage device, resulting in higher power consumption than other storage devices. Therefore, a configuration that does not use DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or even one-thousandth of that required by a configuration that uses DRAM. Therefore, by deploying information processing devices, including supercomputers (also known as HPCs (High Performance Computers)), computers, servers, etc., that employ such a configuration throughout the world, global warming can be curbed.

[0596] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0597] When a processing device such as a CPU reads data to be processed, it accesses the register at the highest level in the hierarchy. If the data is not found, it sequentially accesses the L1 cache and storage at the lower levels. When a processing device such as a CPU processes data continuously, it writes data to a lower level such as a register for each process, which tends to lengthen the processing time including data access. Furthermore, the increased number of write and read operations related to data access increases the power consumption of the entire semiconductor device.

[0598] The arithmetic device according to one embodiment of the present invention, described in the above embodiment, has a function of retaining data in addition to a function of performing arithmetic operations, and therefore can reduce the number of data accesses. Specifically, the arithmetic device according to one embodiment of the present invention can repeatedly perform arithmetic operations using the multiplier by writing first data, which is a multiplier, to an arithmetic cell once. Therefore, by using the arithmetic device according to one embodiment of the present invention, it is possible to shorten the processing time including data access and reduce the overall power consumption of the semiconductor device.

[0599] Furthermore, when a transistor included in the arithmetic device of one embodiment of the present invention is used as an OS transistor, the arithmetic device of one embodiment of the present invention can also be treated as an OS memory. Therefore, the arithmetic device of one embodiment of the present invention can be treated as a hierarchy of the Target1 region or the Target2 region shown in FIG.

[0600] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0601] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as Data Centers (DCs)) that can use the arithmetic device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the arithmetic device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0602] [Electronic Component] Fig. 28A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 28A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that in Fig. 28A, some parts of electronic component 700 are omitted in order to show the interior of electronic component 700.

[0603] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0604] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0605] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0606] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 28B , the semiconductor device 710 includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 may be configured with a plurality of stacked memory cell arrays. The stacked drive circuit layer 715 and memory layer 716 may be configured as a monolithic stack. In a monolithic stack configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables faster operation of the interface between the processor and the memory. For example, by using the arithmetic device described in the above embodiment as the processor, the transmission of first data (e.g., weight coefficients) from the memory to the arithmetic device can be accelerated.

[0607] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0608] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0609] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0610] Next, Fig. 28C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 28C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0611] In FIG. 28C, an example of forming the electrode 733 with solder balls is shown. By providing solder balls in a matrix on the bottom of the substrate 701, BGA (Ball Grid Array) mounting can be realized. For this reason, through holes (via holes) are provided in the substrate 701, and a conductive layer 732 that functions as wiring is provided in these holes. On the substrate 701, an electrode pad 713 is provided so as to contact above the conductive layer 732, and below the substrate 701, an electrode 733 is provided so as to contact below the conductive layer 732.

[0612] Also, the electrode 733 may be formed with conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be realized.

[0613] Also, the electronic component 700A can be mounted on other substrates using various mounting methods not limited to BGA and PGA. Examples of the mounting methods include, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0614] Also, the electronic component according to one aspect of the present invention may be in the form of a SiP (System in Package) or an MCM (Multi Chip Module). For example, the electronic component 700C shown in FIG. 28D has an interposer 731 provided on a package substrate 734 (printed substrate), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0615] 28D shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0616] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0617] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0618] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0619] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0620] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using OS transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. A structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0621] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0622] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 29A . The electronic device 6500 shown in FIG. 29A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The computing device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0623] 29B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The computing device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, and the like.

[0624] The arithmetic circuit of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced. Furthermore, the speed of the operation of the artificial neural network can be increased.

[0625] [Mainframe] Next, Fig. 29C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 29C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0626] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0627] The PC card is an example of a processing board equipped with a processing device such as a CPU, a GPU, etc. For example, the electronic component 700 can be used as the processing device.

[0628] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0629] [Space Equipment] A computing device according to one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0630] The computing device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0631] Fig. 30 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 30, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0632] 30 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided fo...

Claims

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitance element, a second capacitance element, and a third capacitance element; one of a source and a drain of the first transistor is electrically connected to a first terminal of the first capacitance element and a gate of the third transistor; the other of the source and the drain of the first transistor is electrically connected to a first terminal of the second capacitance element, a gate of the fourth transistor, and one of the source and the drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to a first terminal of the third capacitance element and to one of the source and the drain of the fifth transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to the first wiring; a gate of the fifth transistor electrically connected to the first wiring; Arithmetic circuit.

2. The semiconductor device according to claim 1, wherein each of the first to fifth transistors has a channel formation region formed of an oxide semiconductor. the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Arithmetic circuit. 　 a first driving circuit, a second driving circuit, a third driving circuit, a fourth driving circuit, and a fifth driving circuit; the first driving circuit has a function of applying a first potential according to first data to the other of the source and the drain of the fifth transistor; the second driving circuit has a function of applying a second potential corresponding to second data to a second terminal of the first capacitance element, and a function of applying a third potential corresponding to third data to a second terminal of the second capacitance element; the third driving circuit has a function of transmitting a selection signal to the first wiring in order to write the first data to the arithmetic circuit; The fourth driving circuit is a function of acquiring a first current flowing through one of the source and the drain of the third transistor in accordance with the multiplication of the first data and the second data, and outputting a result of an operation of a first function using the first current as an input value; a function of acquiring a second current flowing through one of the source and the drain of the fourth transistor in accordance with the multiplication of the first data and the third data, and outputting a result of an operation of a second function using the second current as an input value; the fifth driving circuit has a function of applying a potential to a second terminal of the third capacitive element; Computing device. 　 The method according to claim 3, further comprising the steps of: the second layer is located above the first layer; the first layer has a single crystal substrate comprising silicon; the first drive circuit to the fifth drive circuit are provided on the single crystal substrate; each of the first to fifth driving circuits includes a transistor formed on the single crystal substrate; the second layer includes the arithmetic circuit; Computing device. 　 a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element; one of a source and a drain of the first transistor is electrically connected to a first terminal of the first capacitance element and a gate of the third transistor; the other of the source and the drain of the first transistor is electrically connected to a first terminal of the second capacitance element, a gate of the fourth transistor, and one of the source and the drain of the second transistor; a gate of the first transistor electrically connected to a first wiring; a gate of the second transistor electrically connected to the first wiring; Arithmetic circuit.

6. The semiconductor device according to claim 5, wherein each of the first to fourth transistors has a channel formation region formed of an oxide semiconductor. the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Arithmetic circuit. a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit; the first driving circuit has a function of applying a first potential corresponding to first data to the other of the source and the drain of the second transistor; the second driving circuit has a function of applying a second potential corresponding to second data to a second terminal of the first capacitance element, and a function of applying a third potential corresponding to third data to a second terminal of the second capacitance element; the third driving circuit has a function of transmitting a selection signal to the first wiring in order to write the first data to the arithmetic circuit; The fourth driving circuit is a function of acquiring a first current flowing through one of the source and the drain of the third transistor in accordance with the multiplication of the first data and the second data, and outputting a result of an operation of a first function using the first current as an input value; a function of acquiring a second current flowing through one of the source and the drain of the fourth transistor in accordance with the multiplication of the first data and the third data, and outputting a result of an operation of a second function using the second current as an input value; Computing device. 　 The method according to claim 7, further comprising the steps of: the second layer is located above the first layer; the first layer has a single crystal substrate comprising silicon; the first drive circuit to the fourth drive circuit are provided on the single crystal substrate; each of the first to fourth driving circuits includes a transistor formed on the single crystal substrate; the second layer includes the arithmetic circuit; Computing device. 　 An electronic device comprising the arithmetic unit according to claim 4 or 8 and a housing.

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