Variable input power control for input capacitance reduction in ac DC converters

Abstract

A Variable Input Power (VIP) control method is proposed which provides reduced capacitance values of the input capacitor. The reduced capacitance values of the input capacitor allows the use of a smaller input capacitor Cin or improve performance for a given capacitor value, thereby increasing the available system power density. Essentially, the VIP control approach is used to reallocate Pin within the AC half line cycle range. Consequently, Cin demonstrates reduced discharging power during a charging interval as compared to Pin, leading to a reduction in the required capacitance of Cin.

Description

VARIABLE INPUT POWER CONTROL FOR INPUT CAPACITANCE REDUCTION IN AC DC CONVERTERSCROSS-REFERENCE

[0001] This application is a non-provisional of, and claims all benefit, including priority to, US Application No. 63 / 551930, filed 9-Feb-2024, entitled “VARIABLE INPUT POWER CONTROL FOR INPUT CAPACITANCE REDUCTION IN AC DC CONVERTERS”, incorporated herein by reference in its entirety.FIELD

[0002] Embodiments of the present disclosure generally relate to the field of USB Power Delivery, and more specifically, embodiments relate to devices, systems and methods for improved power density of a converter system using a Variable Input Power (VIP) control.INTRODUCTION

[0003] Since 2012, the USB Power Delivery (USB PD) specification has standardized the charging protocols for a majority of consumer electronic devices. USB PD facilitates charger reusability across different devices and minimizes electronic waste. USB PD enables negotiation between the load and power source for multiple levels of power delivery. It proves to be highly advantageous in providing power to multiple devices, including smartphones, tablets, and laptops.

[0004] For USB-PD power adapters without PFC stage, it is common to adopt a single-stage architecture.

[0005] The size of the input capacitor Cin is the major power density barrier of USB- PD power adapters, which roughly takes a quarter of the converter volume. To reduce the required capacitance for Cin and improve the power density of the whole converter system, a Variable Input Power (VIP) control method is proposed.SUMMARY

[0006] A Variable Input Power (VIP) control method is proposed which provides reduced capacitance values of the input capacitor. The reduced capacitance values of the input capacitor allows the use of a smaller input capacitor Cin and thereby increasing the available system power density.

[0007] Effectively, the approach allows for a system that, when the input voltage is high, is configured to take more power from the capacitor, and conversely, when the input voltage is low, is configured to take less power from the capacitor, which helps reduce ripple. The rationale for this approach is that during a first time period when the input voltage is high, the power is likely coming from the AC source, which can be considered to provide effectively infinite power from the perspective of the device. Conversely, during a second time period, power is taken from the input capacitor Cin but since the power available is finite, less power is taken.

[0008] Essentially, the VIP control approach is used to reallocate Pin within the AC half line cycle range. Consequently, Cin demonstrates reduced discharging power during a charging interval as compared to Pin, leading to a reduction in the required capacitance of Cin.

[0009] An engineering objective of the VIP control method and corresponding circuit is that one can use the proposed approach to reduce the Vbus max and Vbus minimum ripple for the same amount of capacitor, or have a same ripple and require less of a capacitor, saving cost and size as capacitor devices can drive expense and volume.

[0010] In a first embodiment, the proposed VIP control can be implemented by maintaining a constant input current for the DC-DC converter. In this case, the input power of the DC-DC converter will exactly follow the bus voltage waveform. The input power will be higher when the bus voltage is higher and the input power will be lower when the bus voltage is lower. Other embodiments are possible, such as a second embodiment where the input current of DC-DC converter exactly follows busvoltage waveform. In a third embodiment, instead, the input current of DC-DC converter segmentally follows the bus voltage waveform. In a fourth embodiment, there is instead a segmented constant input current of DC-DC converter. All of these embodiments are potential variations of the circuit and operation that are proposed.

[0011] Experimentation was conducted using a Quasi-Resonant (QR) Flyback converter. The approach was able to achieve technical improvements during testing, for example, being able to increase a minimum bus voltage to relieve the wide gain requirement for the QR Flyback converter for a given capacitance, and also being able to reduce a required input capacitance if the designed minimum bus voltage remains fixed.

[0012] Proposed approaches are also described in relation to VIP charging control, including methodologies for controlling operation of device components to achieve a variable input power control. In particular, these methods provide improvements over conventional control where input power into the DC-DC converter is constant, and thus the required capacitance for Cin is difficult to reduce.

[0013] From a practical perspective, the proposed circuit can be configured for usage on consumer electronics chargers such as LISBC PD chargers, or other types of charging equipment, such as chargers for larger devices, such as energy storage devices, electric vehicles, among others.

[0014] A benefit of the proposed approach is that the overall cost, size, and weight of these devices can be reduced through a reduction of the required capacitance, or being able to achieve higher performance for a given capacitance relative to other approaches.

[0015] The circuit can be coupled with DC-DC converter circuitry and provided in the form of an overall charging module having various circuits disposed inside, the charging module including, for example, prongs for insertion into an outlet on one end, and having a port for connecting a cable and a load on the other (e.g., smartphone charger).

[0016] Corresponding control software and instruction sets affixed to physical machine or computer readable media is contemplated, which provide control instruction sets which when executed by a processor or a waveform generator provide a proposed VIP control approach.DESCRIPTION OF THE FIGURES

[0017] In the figures, embodiments are illustrated by way of example. It is to be expressly understood that the description and figures are only for the purpose of illustration and as an aid to understanding.

[0018] Embodiments will now be described, by way of example only, with reference to the attached figures, wherein in the figures:

[0019] FIG. 1A is a circuit diagram of a single stage architecture of an AC-DC converter.

[0020] FIG. 1B is a control diagram of a single stage architecture of an AC-DC converter.

[0021] FIG. 2 is a graph of key waveforms of voltage, current and power of a fullbridge diode rectifier with conventional constant input power control, according to some embodiments.

[0022] FIG. 3 is a graph of key waveforms of voltage, current and power a full-bridge diode rectifier with proposed VIP control, according to some embodiments.

[0023] FIG. 4 is a graph of the variation of A concerning h changes when using VIP control, according to some embodiments.

[0024] FIG. 5A is a control diagram of a constant input current of DC-DC converter.

[0025] FIG. 5B is a graph of key waveforms of voltage, current and power of a fullbridge diode rectifier of a constant input current of DC-DC converter.

[0026] FIG. 6 is a graph of correlation between capacitance reduction and bus voltage limitations of a constant input current of DC-DC converter.

[0027] FIG. 7A is a control diagram of a full-bridge diode rectifier when an input current of DC-DC converter exactly follows bus voltage waveform.

[0028] FIG. 7B is a graph of key waveforms of voltage and current of a full-bridge diode rectifier when an input current of DC-DC converter exactly follows bus voltage waveform.

[0029] FIG. 8 is a graph of correlation between capacitance reduction and bus voltage limitations when an input current of DC-DC converter exactly follows bus voltage waveform.

[0030] FIG. 9A is a control diagram of a full-bridge diode rectifier when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0031] FIG. 9B is a control diagram of a waveform modulator when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0032] FIG. 9C is a graph of key waveforms of a waveform modulator when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0033] FIG. 9D is a graph of key waveforms of voltage and current of a full-bridge diode rectifier when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0034] FIG. 10 is a graph of correlation between capacitance reduction and bus voltage limitations when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0035] FIG. 11 A is a control diagram of a full-bridge diode rectifier of a segmented constant input current of DC-DC converter.

[0036] FIG. 11 B is a control diagram of a waveform modulator of a full-bridge diode rectifier of a segmented constant input current of DC-DC converter.

[0037] FIG. 11C is a graph of key waveforms of a waveform modulator of a fullbridge diode rectifier of a segmented constant input current of DC-DC converter.

[0038] FIG. 11D is a graph of key waveforms of voltage and current of a full-bridge diode rectifier of a segmented constant input current of DC-DC converter.

[0039] FIG. 12 is a graph of correlation between capacitance reduction and bus voltage limitations of a segmented constant input current of DC-DC converter.

[0040] FIG. 13 is a graph of simulated waveforms for conventional and proposed methods, with each employing a 66 uF input capacitor, according to some embodiments.

[0041] FIG. 14 is a graph of simulated waveforms for conventional and proposed methods using different input capacitances, according to some embodiments.DETAILED DESCRIPTION

[0042] For USB-PD power adapters without PFC stage, it is common to adopt a single-stage architecture, as depicted in FIG. 1A. In FIG. 1A, the full-bridge diode rectifier 100 converts the AC input Vac into a stable bus voltage Vbus with the assistance of Cin. The subsequent DC-DC converter serves the purpose of delivering adjustable output voltages to the load. FIG. 1B illustrates the control block diagram 100B for FIG. 1A under conventional control strategy.

[0043] The output voltage Vo is sensed through the voltage sensor to generate the voltage feedback signal Vo_FB. Vo_FB is compared with the pre-set reference voltage signal Vo_Ref to generate the error signal Verror. The voltage loop compensator processes the Verror signal to generate the gate control signal Uctrl. The gate driver module converts the gate control signal Uctrl to generate the gate signal(s), Gate, to drive the switch(es) of the DC-DC converter. It is noted that depending on the types of DC_DC converter, the gate driver will produce the corresponding gate signals. For example, if a PWM (Pulse-Width-Modulation) control is used for DC-DC converter, the gate driver will produce a PWM gate drive signal with duty cycle as the control parameter, based on Uctrl. As a special case of PWM control, if constant Ton control is used, the gate driver will produce a constant onPWM gate drive signal with Ton time as the control parameter, based on gate control signal Uctrl. If a PFM (Pulse-Frequency-Modulation) control is used for the DC-DC converter, the gate driver will produce a PFM gate drive signal with switching frequency as the control parameter, based on Uctrl signal. The gate drive signal, Gate, is used to control the operation of the DC-DC converter to regulate its output voltage, Vo. It is noted that in FIG. 1B, only one gate signal is shown for the DC-DC converter. When the DC-DC converter has multiple switches, multiple gate signals are required, and the gate driver module will generate the required multiple gate drive signals.

[0044] With the conventional control method described above, as the output voltage Vo is controlled to be a constant. The output power is constant.

[0045] Therefore, the input power of the DC-DC converter is also a constant value. Therefore, the conventional control method is referred to as constant input power control in this application (specification).

[0046] As described herein, a Variable Input Power (VIP) control method is proposed which provides reduced capacitance values of the input capacitor.

[0047] Effectively, the approach allows for a system that, when the input voltage is high, is configured to take more power from the capacitor, and conversely, when the input voltage is low, is configured to take less power from the capacitor, which helps reduce ripple.

[0048] The rationale for this approach is that during a first time period when the input voltage is high, the power is likely coming from the AC source, which can be considered to provide effectively infinite power from the perspective of the device. Conversely, during a second time period, power is taken from the input capacitor Cin but since the power available is finite, less power is taken.

[0049] FIG. 2 shows key waveforms 200 of the full-bridge diode rectifier shown in FIG. 1 A with conventional constant input power control. FIG. 2 is prior art.

[0050] It can be observed that the AC input current conducts only during a portion of the AC half line cycle, which is denoted by 0 in rad. 0 represents the AC power supply angle. During [<p1, <p2], the input AC voltage simultaneously provides load power of the DC-DC converter and charges Cin. During [<p2, <p3], the load power of the DC-DC converter is supplied by Cin only and the discharging energy of Cin can be described by Equation (1):

[0052] where Fac is the AC line frequency and Pin is the input power of the DC-DC converter, which is also the is the discharging power of Cin. By defining the voltage ratio h as Equation (2).

[0054] 0 can be calculated by Equation (3).

[0056] The energy change in Cin within half line cycle of the AC voltage is calculated by Equation (4).

[0058] Combining Equations (1 )- (4), Cin can be calculated by Equation (5).

[0060] It can be observed from Equation (5) that the required capacitance for Cin is proportional to Pin for a specific voltage ripple.

[0061] With conventional control, the required capacitance for Cin can not be minimized, as the input power into the DC-DC converter is constant.

[0062] Based on this conclusion, Variable Input Power (VIP) control is proposed. Compared to the conventional method with a constant input power into the DC-DC converter, the proposed VIP control reduces Pin during [<p2, <p3], which leads to smaller capacitance of Cin and improves the power density of the AC-DC converter.

[0063] FIG. 3 shows the key waveforms 300 of the proposed VIP control, according to some embodiments. As noted herein, there are different approaches that are possible for VIP control, described in a number of embodiments in further examples.

[0064] In terms of the waveforms, Pin shown at (c) is of particular importance, as it can be observed that it shifts depending on which phase of operation is being used, as described below.

[0065] During [<p1 , <p2], the average input power of the DC-DC converter is denoted by Pin1_avg. During [<p2, <p3], the average input power of the DC-DC converter is denoted by Pin2_avg. Pin1_avg and Pin2_avg satisfy the following relationship in Equation (6).

[0067] In comparison to the conventional method employing a constant Pin within the AC half line cycle, the proposed VIP control reallocates Pin within the AC half line cycle range.

[0068] Consequently, Cin demonstrates reduced discharging power during the interval [<p2, <p3] as compared to Pin, leading to a reduction in the required capacitance of Cin. By Defining the power ratio k as seen in Equation (7), Pin2_avg can be rewritten as seen in Equation (8).

[0071] Combining Equation (5) and Equation (8), the required capacitance of Cin can be expressed as Equation (9).

[0073] Combining Equation (5), Equation (8), and Equation (9), the capacitance of ratio of Cin_new / Cin_conv can be expressed by Equation (10).

[0075] where Cin_conv represents the required capacitance of Cin when using the conventional method (i.e. , a constant Pin within the AC half line cycle).

[0076] The capacitance ratio A with respect to the bus voltage peak-to-peak ratio h (Vbus_min / Vbus_max) is plotted at plot 400 in FIG. 4.

[0077] It can be observed that a significant capacitance reduction can be achieved with a smaller voltage ratio of h (Vbus_min / Vbus_max). Also, with a fixed voltage ratio of h, the capacitance reduction increases as k 402, 404, 406, 408, and 410 increases. In other words, a smaller value of Pin2_avg corresponds to a smaller capacitance requirement for Cin. The allocations of Pin1_avg and Pin2_avg can be achieved by controlling the operation of DC-DC converter.Embodiment 1 : Constant input current of DC-DC converter

[0078] The first embodiment of the VIP control is to maintain a constant input current (iin) for the DC-DC converter.

[0079] FIG. 5A illustrates the block diagram 500A of the DC-DC converter under constant input current control. In contrast to the conventional control strategy depicted in FIG. 1B, an additional current loop is incorporated in FIG. 5A to regulate the DC-DC converter's input current to a constant value.

[0080] In FIG. 1B, the output signal of the voltage loop compensator, denoted as Uctrl, is utilized to generate the gate signal(s), Gate, to drive the switch(es) of the DC-DC Converter.

[0081] However, in FIG. 5A, the output signal of the voltage loop compensator, denoted as lin_Ref, serves as the reference current for the current loop. The input current of the DC-DC converter, iin, is sensed by Current Sensor, which produces lin_sns, that is proportional to iin. Iin_sns provides real-time information about the input current of the DC-DC converter.

[0082] By comparing lin_sns with lin_Ref, the current error signal, lerror, is generated. Subsequently, lerror is processed by the current loop compensator to produce the gate control signal Uctrl. The Gate Driver module converts the gate control signal Uctrl to generate the gate signal(s), Gate, to drive the switch(es) of the DC-DC Converter. In this dual-loop control architecture, the output voltage can be stabilized according to the reference value, and the input current can be regulated to a constant value.

[0083] The input power of the DC-DC converter is the product of its input current, iin, and the bus voltage, Vbus, Pin = iin * Vbus. When the input current (iin) of the DC- DC converter is controlled to a constant value, its input power automatically adjusts with variations in the bus voltage, Vbus. In other words, the input power of the DC- DC converter exactly follows the waveform of the bus voltage. When the bus voltage, Vbus, is higher, the input power of the DC-DC converter is higher, and vice versa. Consequently, the VIP control strategy #1 is automatically achieved.

[0084] FIG. 5B shows the key waveforms 500B of full-bridge diode rectifier of a constant input current of DC-DC converter.

[0085] As depicted in FIG. 5B, the input power shown in (d) Pin will be higher when the bus voltage is higher and the input power will be lower when the bus voltage is lower.

[0086] During [<p1 , <p2], the average input power of DC-DC converter can be expressed by Equation (11).

[0088] During [<p2, <p3], the average input power of DC-DC converter can be expressed by Equation (12).

[0090] Hence, k can be calculated by Equation (13).

[0092] Based on Equation (10) and Equation (13), the capacitance of ratio ofCin_new / Cin_conv can be recalculated by Equation (14).

[0094] Based on Equation (14), the capacitance ratio A with respect to the bus voltage peak-to-peak ratio h (Vbus_min / Vbus_max) is plotted at plot 600 in FIG. 6.

[0095] It can be observed that A 602 monotonically decreases as h decreases. When h = 0.6 (or the minimum voltage is 60% of the maximum voltage), the needed capacitance for Cin can be reduced by 2.3%. When h = 0.5, the needed capacitance for Cin can be reduced by 3.2%.Embodiment 2: Input current of DC-DC converter exactly follows bus voltage waveform

[0096] The second embodiment of the VIP control is to regulate (or to control) the input current of the DC-DC converter to exactly follow the bus voltage waveform, Vbus. FIG. 7A shows the control block diagram 700A that can be implemented to achieve this embodiment.

[0097] In contrast to the dual-loop control architecture depicted in FIG. 5A, FIG. 7A introduces an additional bus voltage feedforward loop. In FIG. 5A, the output signal of the voltage loop compensator, denoted as I in_Ref, serves as the reference current for the current loop.

[0098] However, in FIG. 7A, the reference current for the current loop ( I in_Ref 1 ) is generated by adding lin_Ref and Vbus_flt, I in_ref 1 = I in_ref + Vbus_flt. Here, Vbus_flt represents the feedforward signal obtained by processing the bus voltage, Vbus, through a band pass filter. The band pass filter removes the DC component from the bus voltage, and retains only the AC component, or the ripple voltagecontained in Vbus. It is noted that Vbus_flt contains only AC voltage and its DC value (or average value) is zero.

[0099] Thus, in FIG. 7A, the real-time value of lin_Ref1 varies with changes in the bus voltage, Vbus, while ensuring that its average remains equal to lin_Ref. In other words, the input current of the DC-DC converter is controlled to dynamically follow the bus voltage variation in real-time, while ensuring the stability of the output voltage.

[0100] The input power of the DC-DC converter is determined by the product of its input current, iin, and the bus voltage, Vbus, expressed as Pin = iin * Vbus. When the input current (iin) of the DC-DC converter is precisely controlled to track the bus voltage waveform, its input power automatically adjusts with variations in the bus voltage, Vbus. When the bus voltage, Vbus, is higher, the input power of the DC-DC converter is higher, and vice versa. Consequently, the VIP control strategy #2 is automatically achieved.

[0101] FIG. 7B shows the key waveforms 700B of full-bridge diode rectifier when an input current of DC-DC converter exactly follows bus voltage waveform.

[0102] It can be observed that Input current of DC-DC converter exactly follows bus voltage waveform. In other words, within the intervals [<p1 , <p2], the input current sinusoidally increases from lin_min to lin_max. Subsequently, during [<p2, <p3], the input current linearly decreases from lin_max to lin_min.

[0103] Fix-frequency DCM (Discontinuous Conduction Mode) Flyback converters are widely used for both AC-DC and DC-DC power conversion applications. In DCM, the energy stored in the transformer is completely transferred to the secondary. During the ON time of the main switch, the Flyback input current undergoes a linear increase from zero. With constant ON time control, the average input current within a switching cycle is expressed by Equation (15).

[0105] where Vbus is the instantaneous bus voltage, Ton is the ON time of the main switch, L is Flyback inductance, Ts is the switching cycle of the Flyback converter. It can be observed that lin_avg_Ts is proportional to the instantaneous bus voltage.

[0106] In other words, with the constant ON time, the input current variation ofDCM Flyback converter exactly follows the variation of the bus voltage. The conclusion is the same for QR (Quasi Resonant) Flyback converter, as it is simply a DCM Flyback having a valley switching turn ON.

[0107] During [<p1 , <p2], the average input power of DC-DC converter is expressed by Equation (16).

[0109] During [<p2, <p3], the average input power of DC-DC converter is expressed by Equation (17).

[0111] Hence, k can be calculated by Equation (18).

[0113] Based on Equation (10) and Equation (18), the capacitance of ratio ofCin_new / Cin_conv can be recalculated by Equation (19).

[0115] Based on Equation (19), the capacitance ratio A with respect to the bus voltage peak-to-peak ratio h (Vbus_min / Vbus_max) is plotted in plot 800 in FIG. 8.

[0116] It can be observed that A 802 monotonically decreases as h decreases.When h = 0.6, the needed capacitance for Cin can be reduced by 5%. When h = 0.5, the needed capacitance for Cin can be reduced by around 8%.Embodiment 3: Input current of DC-DC converter segmentally follows bus voltage waveform

[0117] The third embodiment of the VIP control aims to regulate the input current of the DC-DC converter to segmentally follow the bus voltage waveform, Vbus.

[0118] FIG. 9A illustrates the control block diagram 900A for implementing this embodiment. In contrast to the control architecture shown in FIG. 7A, FIG. 9A introduces an additional waveform modulator #1. The purpose of this waveform modulator #1 is to convert the sensed Vbus waveform into Vbus_mod waveform. It's noted that the Vbus_mod waveform segmentally follows the bus voltage waveform. By feeding Vbus_mod to the band pass filter, the DC component of Vbus_mod is removed, resulting in Vbus_flt containing only the AC component of Vbus_mod, with its DC value (or average value) to be zero. As depicted in FIG. 9A, lin_Ref1 isobtained by adding Vbus_mod and lin_Ref (a constant value), lin_Ref1 = Vbus_mod + lin_Ref. Therefore, lin_Ref1 segmentally follows the bus voltage waveform, Vbus. Consequently, under closed-loop control, the input current of the DC-DC converter (lin) follows lin_Ref1. In other words, the input current of the DC-DC converter segmentally follows the bus voltage waveform. The VIP control strategy #3 has therefore been achieved.

[0119] Generally, waveform modulator #1 needs to accomplish two tasks. Firstly, it must distinguish the AC power conduction angle, denoted as 9, from the Vbus waveform, as depicted in FIG. 9A. Secondly, it needs to segmentally multiply the Vbus waveform by different scaling factors. For instance, when the Vbus waveform is within the AC power conduction angle 6, it is multiplied by the scaling factor K1 . When the Vbus waveform is not within the AC power conduction angle 6, it is multiplied by the scaling factor K2. The value of K1 should be larger than K2. When K1 equals K2, the third embodiment of VIP control will be identical to the second embodiment of the VIP control.

[0120] It is noted that the waveform modulator #1 can be implemented using various analog or digital circuits.

[0121] FIG. 9B provides a block diagram 900B to implement waveform modulator #1 . This block diagram mainly consists of two circuit parts, referred to as Circuit A and Circuit B.

[0122] The objective of Circuit A is to accomplish the previously mentioned task 1 , which is to distinguish the AC power conduction angle from the Vbus waveform. Circuit A includes a voltage sensor to sense the bus voltage Vbus, denoted as Vbus_sns. The sensed Vbus_sns is compared with two reference values, Vrefl and Vref2, using two comparators. Vrefl and Vref2 are pre-set constants. The output signals of the comparators are fed to the input of a set-reset flip-flop (triggered by the rising edge) to generate the control signal Vsel for Circuit B.

[0123] The objective of Circuit B is to fulfill the previously mentioned task 2, which is to segmentally multiply the Vbus waveform by different scaling factors. Circuit B consists of a multiplexer. The two input signals of the multiplexer correspond to two different scaling factors, K1 and K2. The output signal of the multiplexer, denoted as Y, is multiplied by Vbus_sns to obtain the Vbus_mod signal. The truth table of the multiplexer is provided in Table I of FIG. 9B. It can be observed that when Vsel is 0, Vbus_sns is multiplied by K2, and when Vsel is 1 , Vbus_sns is multiplied by K1.

[0124] FIG. 9C illustrates the key waveforms 900C of the block diagram shown in FIG. 9B. At time to, when Vbus_sns is just below Vrefl , the signal V1 goes high, generating a rising edge. This rising edge causes the output signal Vsel of the setreset flip-flop to to transition to its high level (i.e., 1 ).

[0125] At time t1 , when Vbus_sns is just above Vref2, the signal V2 goes high, generating another rising edge. This rising edge causes the output signal Vsel of the set-reset flip-flop to transition to its low level (i.e., 0). Therefore, during the AC power conduction angle 9 (i.e., during the time interval [to, t1 ]), the Vsel signal remains high (i.e., 1 ). When the Vbus waveform is not within the AC power conduction angle 6 (i.e., during the time interval [t1 , t2]), the Vsel signal remains low (i.e., 0). Thus, during the time interval [to, t1], Vbus_sns is multiplied by K1 , and during the time interval [t1 , t2], Vbus_sns is multiplied by K2.

[0126] FIG. 9D shows the key waveforms 900D of full-bridge diode rectifier when an input current of DC-DC converter segmentally follows bus voltage waveform.

[0127] During the interval [<p1, <p2], the input current sinusoidally increases from Iin_min1 to Iin_max1. During the interval [<P2, <p3], the input current linearly decreases from Iin_max2 to Iin_min2. <p1 and <p2 represent the transition nodes of the control modes for the DC-DC converter. For DCM Flyback converter, this control can be accomplished by employing different Ton values corresponding to the time durations of 0 and ir-0.

[0128] It is noted that during time interval <p1 to <p2, the diode bridge is turned on and the input AC voltage is used to charge the input capacitor, Cin, and to provide the input power of the DC-DC converter, Pin. Therefore, it is desirable to increase the input current, iin, and therefore, the input power Pin, of the DC-DC converter during this time interval.

[0129] Since the total power that the DC-DC converter will consume over one half AC line, from <p1 to <p3, as shown in FIG. 9D, is consistent, when the input power of DC-DC converter during time interval <p1 to <p2 is higher, the input power during time interval <p2 to <p3 will be lower. It is noted that during <p2 to <p3, the input capacitor, Cin, discharges to provide the power to DC-DC converter. When Cin is required to provide less power, the capacitor value can be reduced.

[0130] Assuming Toni and Ton2 are used to control the conduction time of the main switch during intervals [<p1 , <p2] and [<p2, <p3], then the input current of the DCM Flyback converter can be expressed as Equation (20).

[0132] Since Toni and Ton2 are constant values, the input current of the DCMFlyback converter will segmentally follow the bus voltage waveform Vbus(<p).

[0133] During [<p1 , <p2], the average input power of DC-DC converter is expressed as Equation (21).

[0135] During [<p2, <p3], the average input power of DC-DC converter is expressed as Equation (22).

[0137] Hence, k can be calculated by Equation (23).

[0139] Based on Equation (10) and Equation (23), the capacitance of ratio of Cin_new / Cin_conv can be recalculated by Equation (24).

[0141] Based on Equation (24), the capacitance ratio A with respect to the bus voltage peak-to-peak ratio h (Vbus_min / Vbus_max) is plotted in plot 1000 in FIG. 10

[0142] It can be observed that A 1002, 1004, 1006, 1008, 1010 and 1012 monotonically decreases as h decreases. Also, with a fixed h, the capacitance reduction increases as Iin_max1 / lin_max2 increases. In other words, a larger value of Iin_max1 / lin_max2 corresponds to a smaller capacitance requirement for Cin.Embodiment 4: Segmented constant input current of DC-DC converter

[0143] The fourth embodiment of the VIP control aims to regulate the input current of the DC-DC converter to maintain a segmented constant input current.

[0144] FIG. 11A illustrates the control block diagram 1100A for implementing this embodiment.

[0145] The difference between embodiment #4 (as shown in FIG. 11 A) and embodiment #3 (as shown in FIG. 9A) lies in the waveform variation of Vbus_mod.

[0146] When the Vbus waveform is within the AC power conduction angle 9, Vbus_mod is set to a higher level, Vbus_mod_H. When the Vbus waveform is not within the AC power conduction angle 6, Vbus_mod is set to a lower level, Vbus_mod_L.

[0147] Both levels (Vbus_mod_H and Vbus_mod_L) are constant values. Consequently, lin_Ref1 maintains a higher constant value during 6, resulting in an increased input power of the DC-DC converter during this angle. This leads to the automatic realization of VIP control strategy #4.

[0148] FIG. 11B shows a block diagram 1100B to implement Waveform Modulator #2, as shown in FIG. 11 A. In FIG. 11 B, there are two circuits: Circuit A and Circuit B. The Circuit A in FIG. 11B exhibits the same structure and function as the Circuit A in FIG. 9B.

[0149] The distinction between FIG. 11B and FIG. 9B lies in Circuit B. In Circuit B of FIG. 11 B, the two input signals of the multiplexer correspond to the high-level signal of Vbus_mod, denoted as Vbus_mod_H, and the low-level signal of Vbus_mod, denoted as Vbus_mod_L. The truth table of the multiplexer is provided in Table II of FIG. 11B. It can be observed that when the Vsel signal is 0, the output of the multiplexer is Vbus_mod_L. When the Vsel signal is 1 , the output of the multiplexer is Vbus_mod_H.FIG. 11C illustrates the key waveforms 1100C of the block diagram depicted in FIG. 11B. It can be observed that during the AC power conduction angle 6 (i.e., during the time interval [to, t1 ]), the Vsel signal remains high (i.e., 1). When the Vbus waveform is not within the AC power conduction angle 6 (i.e., during the time interval [t1 , t2]),the Vsel signal remains low (i.e., 0). Thus, during the time interval [to, t11, the output of Waveform Modulator #2 is Vbus_mod_H, and during the time interval [t1 , t2], the output of Waveform Modulator #2 is Vbus_mod_L.

[0150] FIG. 11 D shows the key waveforms 1100D of full-bridge diode rectifier of a segmented constant input current of DC-DC converter.

[0151] Within the intervals [<p1 , <p2] and [<p2, <p3], the input current of the DC-DC converter is consistently set at Iin1 and Iin2 (Iin1> Iin2). Achieving this segmented constant input current for the DC-DC converter involves utilizing different current reference values that align with the time durations of 0 and ir-0. As depicted in FIG. 11 A, the current reference value for the DC-DC converter during 9 (from <p1 to <p2 as shown in FIG. 11D) is set to lin_Ref1_H, while during TT-6 (from <p2, <p3 as shown in FIG. 11 D), it is set to lin_Ref1_L. Since lin_Ref1_H is higher than lin_Ref1_L, the input current of the DC-DC converter, Iin1 , during 6 under closed-loop control will be higher than its input current Iin2 during TT-6. It is noted that the ratio of lin_Ref1_H to lin_Ref1_L is equal to the ratio of Iin1 to Iin2. A larger value of lin_Ref1_H to lin_Ref1_L (i.e., Iin1 to Iin2) leads to a larger reduction in the capacitance of Cin.

[0152] During [<p1 , <p2], the average input power of DC-DC converter is expressed as Equation (25).

[0154] During [<p2, <p3], the average input power of DC-DC converter is expressed as Equation (26).

[0156] Hence, k can be calculated by Equation (27).

[0158] Based on Equation (10) and Equation (27), the capacitance of ratio ofCin_new / Cin_conv can be recalculated by Equation (28).

[0160] Based on Equation (28), the capacitance ratio A with respect to the bus voltage peak-to-peak ratio h (Vbus_min / Vbus_max) is plotted in plot 1200 in FIG. 12

[0161] It can be observed that A 1202, 1204, 1206, 1208, 1210 and 1212 monotonically decreases as h decreases. Also, with a fixed h, the capacitance reduction increases as Iin1 / lin2 increases. In other words, a larger value of Iin1 / lin2 corresponds to a smaller capacitance requirement for Cin.

[0162] A QR Flyback converter is used here as an example to illustrate the performance comparison between the conventional constant input power control and the proposed VIP control. The QR Flyback converter is widely used in low power SMPS (Switch Mode Power Supply) applications such as chargers, USB-PD adapters and auxiliary supplies. In a QR Flyback, ON-time Ton of the main power switch is used to control the output voltage. Different Ton will produce different output voltages. The specifications of the QR Flyback converter employed in the PSIM simulation are summarized as follows:1 . 90 Vac / 60 Hz input, and 22 Vdc, 2.95 A (65 W) output.2. 0.7 Vdc constant forward voltage drop of the diodes used in the full bridge rectifier.3. 0.7 Vdc constant forward voltage drop of the secondary diode rectifier.4. The transformer turns ratio is 26:5. The Magnetizing inductance is 140 uH. Ignoring the leakage inductance.5. The secondary output capacitance is 1700 uF.

[0163] The proposed VIP control is implemented following the control strategy shown in Embodiment 2, wherein the input current of the QR Flyback converter exactly follows the bus voltage waveform. This implementation can be conveniently achieved by utilizing a constant Ton for the main power switch. In practical circuits, maintaining a constant Ton for the main power switch can be accomplished by reducing the bandwidth of the voltage feedback loop.

[0164] If the same input capacitance is used, then the minimum bus voltage can be increased to relieve the wide gain requirement for the QR Flyback converter.

[0165] FIG. 13 shows the simulated waveforms 1300 for the conventional and proposed methods, with each employing a 66 uF input capacitor.

[0166] Table I summarizes the circuit performance. It can be observed that the proposed VIP control exhibits superior performance in terms of the minimum bus voltage, input RMS current, and output RMS current. This suggests that the VIP control method enables the QR Flyback converter to achieve higher conversion efficiency.

[0167] However, the utilization of VIP control introduces an increased 120-Hz voltage ripple on the output capacitor. This is attributed to the fundamental nature of VIP control, which modulates the power processed by the QR Flyback converter at a frequency of 120 Hz.

[0168] Consequently, the charging power of the output capacitor also varies at 120 Hz. Given that the discharging power of the output capacitor always equals the output power, the variation in charging power at 120 Hz manifests as an amplified 120-Hz voltage ripple on the output voltage.Table I: Performance Comparison (66 uF input capacitance)

[0169] If the designed remains fixed, the proposed VIP control can be employed to reduce the required input capacitance.

[0170] FIG. 14 shows simulated waveforms 1400 for the conventional and proposed methods using different input capacitances.

[0171] Table II presents the summary of the circuit performance. With the proposed VIP control, the same 69 Vdc minimum bus voltage can be achieved with a reduced input capacitance of 61.2 uF. The capacitance reduction is around (66- 61 ,2) / 66=7.3%. The input RMS current can be lowered to 1.06 / 1.09=97%, corresponding to a reduction of primary conduction losses by (1-0.972)=6%.

[0172] However, the secondary output current increases by (5.21- 5.15) / 5.15=1 .2%, leading to a 1.0122=2% increase in secondary conduction losses. The 120-Hz output voltage ripple increases to 1 .75 V (peak-to-peak value).Table II: Performance Comparison (different input capacitance)

[0173] The proposed VIP control can be employed to reduce the capacitance value of the input capacitor, allowing the use of a smaller input capacitor to increase the system power density.

[0174] It is noted that with the proposed variable input power (VIP) control, the input power to the DC-DC converter is not a constant value. On the other hand, the power consumed by the load of the DC-DC converter, is generally a constant value. Therefore, the difference between the input power and output power will create a 120Hz ripple at the output of the DC-DC converter. This 120Hz ripple can be observed in FIG. 13 and FIG. 14. Therefore, a 120Hz ripple voltage will present at the output of the DC-DC converter when the proposed Variable Input Power (VIP) control is used. Generally speaking, if the more reduction for input capacitor, the larger the 120Hz ripple will be present. However, additional 120-Hz current stress induced by the proposed VIP control should be taken into account during the design of the output capacitor and for the system design. In some cases, such as PD adapter, a second stage Buck converter (not shown in this application) is added to regulate the actual output voltage that will be applied to the devices, such as smart phone, notebook computer, this 120Hz can be removed by the second stage Buck converter and this 120Hz ripple voltage does not have any impact on the power adapter.

[0175] The proposed VIP control is suitable for the QR Flyback converter when operating at low input AC voltage, such as 90 Vac. Under normal operation at 120 Vac, the bus voltage is consistently higher than the designed Vbus_min. Consequently, there is no need to implement this control. In other words, we can disable the operation of the VIP control strategy when the input AC voltage is above a certain level, such as at 120V.

[0176] Applicant notes that the described embodiments and examples are illustrative and non-limiting. Practical implementation of the features may incorporate a combination of some or all of the aspects, and features described herein should not be taken as indications of future or existing product plans. Applicant partakes in both foundational and applied research, and in some cases, the features described are developed on an exploratory basis.

[0177] The term “connected” or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[0178] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.

[0179] As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0180] As can be understood, the examples described above and illustrated are intended to be exemplary only.

Claims

WHAT IS CLAIMED IS:

1. A variable input power control device for use with an DC-DC converter, the variable input power control device including at least: a full-bridge diode rectifier circuit coupled to an AC voltage source, the rectifier circuit including a diode bridge and at least a capacitor Cin, the rectifier circuit providing a rectified current irec to the capacitor Cin and the DC-DC converter, a bus voltage Vbus, an input current lin and a corresponding power Pin to the DC-DC converter, the DC-DC converter configured to deliver power to a load; the rectifier circuit configured such that the power Pin operates within a range corresponding to an AC half line cycle range, increasing the power Pin during a first phase when the AC voltage source is coupled to the DC-DC converter through the diode bridge, and decreasing the power Pin during a second phase when the capacitor Cin is coupled to the DC-DC converter.

2. The device of claim 1, wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining a constant input current for the DC- DC converter such that the input power Pin follows a bus voltage waveform.

3. The device of claim 2 operates through controlling phase operation of the rectifier circuit by controlling a value of the AC power supply angle 0.

4. The device of claim 2, further comprising an additional current loop that is configured to regulate the DC-DC converter's input current value to a constant value.

5. The device of claim 1, wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining an input current for the DC-DC converter that follows a bus voltage waveform by further including a bus voltage feedforward loop.

6. The device of claim 5, wherein the input current for the DC-DC converter that follows the bus voltage waveform is implemented through controlling operation of a flyback converter and a flyback input current.

7. The device of claim 1, wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining an input current for the DC-DC converter that segmentally follows a bus voltage waveform.

8. The device of claim 7, wherein maintaining of the input current for the DC-DC converter that segmentally follows the bus voltage waveform is conducted through using different Ton values corresponding to the time durations of 0 and TT-0 on a flyback converter operating in discontinuous mode.

9. The device of claim 1, wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining a segmented constant input current for the DC-DC converter by different Ton values that align with the time durations of 0 and TT-0.

10. The device of any one of claims 1-9, wherein the device is incorporated into a charger for consumer electronic devices that is configured to deliver an adjustable output voltage to the load, the variable input power control utilized to reduce a required capacitance for the capacitor Cin.

11. A variable input power control method for use with an DC-DC converter, the variable input power control method including at least: operating a full-bridge diode rectifier circuit coupled to an AC voltage source, the rectifier circuit including a diode bridge and at least a capacitor Cin, the rectifier circuit providing a rectified current irec to the capacitor Cin and the DC-DC converter, a bus voltage Vbus, an input current I in and a corresponding power Pin to the DC-DC converter, the DC-DC converter configured to deliver power to a load, such that the power Pin operates within a range corresponding to an AC half line cycle range, increasing the power Pin during a first phase when the AC voltage source is coupled to the DC-DC converter through the diode bridge, and decreasing the power Pin during a second phase when the capacitor Cin is coupled to the DC-DC converter.

12. The method of claim 11 , wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining a constant input current for the DC- DC converter such that the input power Pin follows a bus voltage waveform.

13. The method of claim 12 wherein controlling phase operation of the rectifier circuit is conducted by controlling a value of the AC power supply angle 0.

14. The method of claim 12, wherein an additional current loop that is utilized to regulate the DC-DC converter's input current value to a constant value.

15. The method of claim 11 , wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining an input current for the DC-DC converter that follows a bus voltage waveform by further including a bus voltage feedforward loop.

16. The method of claim 15, wherein the input current for the DC-DC converter that follows the bus voltage waveform is implemented through controlling operation of a flyback converter and a flyback input current.

17. The method of claim 11 , wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining an input current for the DC-DC converter that segmentally follows a bus voltage waveform.

18. The method of claim 17, wherein maintaining of the input current for the DC-DC converter that segmentally follows the bus voltage waveform is conducted through using different Tonvalues corresponding to the time durations of 0 and TT-0 on a flyback converter operating in discontinuous mode.

19. The method of claim 11 , wherein operation of the rectifier circuit is controlled to provide variable input power control through maintaining a segmented constant input current for the DC-DC converter by different Ton values that align with the time durations of 0 and TT-0.

20. The method of any one of claims 11-19, wherein the method is operated by a charger for consumer electronic devices that is configured to deliver an adjustable output voltage to the load, the variable input power control utilized to reduce a required capacitance for the capacitor Cin.

21. A non-transitory machine readable medium, storing machine interpretable instruction sets, which when executed by a processor, cause the processor to execute a variable input power control method, the method comprising any one of the methods of claims 11-20.

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