Display panel and display device

Abstract

Disclosed are a display panel (100) and a display device. A pixel driving circuit (211a) included in the display panel (100) comprises a switching transistor (T2), a driving transistor (T1), a compensation transistor (T3), a first reset transistor (T8) and a first capacitor (C1), which are connected to each other, wherein a first electrode of the first reset transistor (T8) is connected to a first reset signal line (Vi3); and a first plate of the first capacitor (C1) is connected to the first reset signal line (Vi3), and a second plate of the first capacitor (C1) is connected to a first high potential line (VDD1).

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention for its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of the OLED display panel usually includes a switching transistor, a driving transistor, a compensation transistor and a reset transistor. The drain of the switching transistor is connected to the data line, and the drain end of the reset transistor is connected to the reset signal line. There is an overlapping area between the data line and the reset signal line. When the voltage input by the data line changes, the coupling capacitance between the data line and the reset signal line causes the voltage signal on the reset signal line to change, causing the output voltage of the source end of the reset transistor to change, and thus the voltage of the reset node is not reset to the reference voltage, resulting in abnormal display of the display panel. SUMMARY OF THE INVENTION

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] The present application provides a display panel comprising a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit comprises:

[0007] a switch transistor, wherein a first electrode of the switch transistor is connected to the first data signal line, and a second electrode of the switch transistor is connected to the first node;

[0008] a driving transistor, wherein a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to a third node;

[0009] a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third node, and a second electrode of the compensation transistor is connected to the second node;

[0010] a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first node; and

[0011] A first capacitor, wherein a first plate of the first capacitor is connected to the first reset signal line, and a second plate of the first capacitor is connected to the first high potential line.

[0012] The present application further provides a display device, comprising a display panel, wherein the display panel comprises a plurality of sub-pixel units, each of the sub-pixel units being provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit comprises:

[0013] a switch transistor, wherein a first electrode of the switch transistor is connected to the first data signal line, and a second electrode of the switch transistor is connected to the first node;

[0014] a driving transistor, wherein a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to a third node;

[0015] a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third node, and a second electrode of the compensation transistor is connected to the second node;

[0016] a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first node; and

[0017] A first capacitor, wherein a first plate of the first capacitor is connected to the first reset signal line, and a second plate of the first capacitor is connected to the first high potential line. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a simplified structural diagram of the display panel of the present application;

[0019] FIG2 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

[0020] FIG3 is a schematic diagram of the film layer in the display panel of the present application;

[0021] FIG4 is a film layer diagram of the first gate layer in the display panel of the present application;

[0022] FIG5 is a film diagram of the first active layer in the display panel of the present application;

[0023] FIG6 is a diagram showing a stack of film layers of a first gate layer and a first active layer in a display panel of the present application;

[0024] FIG7 is a film layer diagram of the second gate layer in the display panel of the present application;

[0025] FIG8 is a diagram showing a stack of first and second gate layers in a display panel of the present application;

[0026] FIG9 is a film diagram of the second active layer in the display panel of the present application;

[0027] FIG10 is a film layer diagram of the third gate layer in the display panel of the present application;

[0028] FIG11 is a film layer diagram of the first active layer, the second active layer, the second gate layer and the third gate layer in the display panel of the present application;

[0029] FIG12 is a film diagram of the first source and drain electrode layer in the display panel of the present application;

[0030] FIG13 is a film layer diagram of the first gate layer, the third gate layer, the first active layer, the second active layer and the first source and drain layer in the display panel of the present application;

[0031] FIG14 is a film layer diagram of the second active layer, the second gate layer, and the first source and drain layer in the display panel of the present application;

[0032] FIG15 is a film layer diagram of the first gate layer, the second gate layer, the third gate layer, the first active layer, the second active layer, and the first source and drain layer in the display panel of the present application;

[0033] FIG16 is a first film layer diagram of the second source and drain electrode layer in the display panel of the present application;

[0034] FIG17 is a diagram showing a first type of film layer superposition of a first gate layer, a first source / drain electrode layer, and a second source / drain electrode layer in a display panel of the present application;

[0035] FIG18 is a diagram showing a first type of film layer stacking of a pixel driving circuit of the present application;

[0036] FIG19 is a connection diagram of different sub-pixel units and different data lines of the display panel of the present application;

[0037] FIG20 is a second film layer diagram of the second source and drain layer in the display panel of the present application;

[0038] FIG21 is a second film layer superposition diagram of the first gate layer, the first source-drain electrode layer, and the second source-drain electrode layer in the display panel of the present application;

[0039] FIG22 is a film diagram of the third source and drain electrode layer in the display panel of the present application;

[0040] FIG23 is a diagram showing the superimposed film layers of the second source-drain electrode layer and the third source-drain electrode layer in the display panel of the present application;

[0041] FIG24 is a fourth film layer stacking diagram of the pixel driving circuit of the present application;

[0042] FIG25 is a film layer diagram of the third source and drain electrode layer in multiple sub-pixel units in the display panel of the present application;

[0043] FIG26 is a diagram showing the connection relationship among the third reset signal line, the second reset signal line, the first reset signal line, and the fourth reset signal line in the display panel of the present application;

[0044] FIG27 is a diagram showing the superposition of the film layers of the third source and drain electrode layer, the data signal line, and the anode of the light-emitting device in the display panel of the present application. Modes for Carrying Out the Invention

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0046] Referring to Figures 1 to 26 , the present application provides a display panel 100 . The display panel 100 may include a display portion 200 and a gate driving circuit 300 located on one side of the display portion 200 . The gate driving circuit 300 is used to input a control signal to the display portion 200 .

[0047] In this embodiment, referring to FIG1 , the display portion 200 includes a plurality of sub-pixel rows 210 , each sub-pixel row 210 includes a plurality of sub-pixel units 211 , each sub-pixel unit 211 is provided with a light-emitting device 211 b and a pixel driving circuit 211 a connected to the light-emitting device 211 b , and the gate driving circuit 300 is used to input a gate control signal to the transistor in the pixel driving circuit 211 a .

[0048] In this embodiment, the pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first reset transistor T8 connected to each other. A first electrode of the switching transistor T2 is connected to the first data signal line Data1, a second electrode of the switching transistor T2 is connected to the first node A, a first electrode of the driving transistor T1 is connected to the first node A, a second electrode of the driving transistor T1 is connected to the second node B, a driving gate T1G of the driving transistor T1 is connected to the third node Q, a first electrode of the compensation transistor T3 is connected to the third node Q, a second electrode of the compensation transistor T3 is connected to the second node B, a compensation gate T3G of the compensation transistor T3 is connected to the first scan signal line Nscan1, a first electrode of the first reset transistor T8 is connected to the first reset signal line Vi3, and a second electrode of the first reset transistor is connected to the first node A.

[0049] In this embodiment, the pixel driving circuit 211 a further includes a first capacitor C1 , a first plate of the first capacitor C1 is connected to the first reset signal line Vi3 , and a second plate of the first capacitor C1 is connected to the first high potential line VDD1 .

[0050] The present application sets a first capacitor C1 between the first reset signal line Vi3 and the first high potential line VDD1, and improves the anti-coupling capability of the first reset signal line Vi3 by utilizing the high potential of the first high potential line VDD1, thereby improving the stability of the reset signal transmitted by the first reset signal line Vi3. The output voltage of the output end of the first reset transistor Vi3 is abnormal, which ensures that the voltage of the reset node between the switching transistor T2 and the first reset transistor T8 is reset to the reference potential, thereby improving the technical problem of abnormal display of the display panel.

[0051] It should be noted that the light-emitting device 211b of the present application can be an organic light-emitting diode, Mini LED, Micro LED, a regular-sized LED or other light-emitting source.

[0052] The technical solution of this application is now described in conjunction with specific embodiments.

[0053] Referring to Figure 1 , the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA. A display portion 200 is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the region within the display panel 100 used for display functions, and is provided with a plurality of sub-pixel units 211 therein to implement these functions. The non-display area NA may be a border region of the display panel 100, and may contain functional components that assist the sub-pixel units 211 within the display area AA in performing display functions.

[0054] Referring to Figure 1 , the lower side of the display area AA is provided with a bonding terminal 400. The bonding terminal 400 can be connected to an external circuit and transmits signals input from the external circuit to the data traces, thereby driving the display panel 100 to display an image. For example, the bonding terminal 400 can be bonded to a chip or a chip-on-film to provide power and drive signals to the display panel 100.

[0055] In this embodiment, the gate driving circuit 300 is arranged in the non-display area NA, and the gate driving circuit 300 can be arranged on both sides of the display area AA; the gate driving circuit 300 may include a plurality of cascaded gate driving units, and the plurality of gate driving units may be arranged along the first direction X. The structure of the gate driving unit is not specifically limited in this application.

[0056] In this embodiment, a plurality of light-emitting devices 211b and a pixel driving circuit 211a for driving the light-emitting devices 211b may be arranged in an array in the display area AA. The pixel driving circuit 211a may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 211a. The following embodiment will be described using the 8T3C pixel driving circuit 211a as an example.

[0057] Referring to Figure 2, the pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a third reset transistor T4, a second reset transistor T7, a first reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a first capacitor C1, a boost capacitor Cboost and a storage capacitor Cst, the first capacitor C1 includes a first plate and a second plate, the storage capacitor Cst includes a third plate Cst1 and a fourth plate Cst2, and the boost capacitor Cboost includes a fifth plate and a sixth plate.

[0058] Please refer to Figure 2. The first electrode of the switching transistor T2 is connected to the first data signal line Data1, the second electrode of the switching transistor T2 is connected to the first node A, and the switch gate T2G of the switching transistor T2 is connected to the second scan signal line Pscan1; the first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the drive gate T1G of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3 of the compensation transistor T3 is connected to the third node Q. G is connected to the first scan signal line Nscan1; the first electrode of the third reset transistor T4 is connected to the third reset signal line Vi1, the second electrode of the third reset transistor T4 is connected to the third node Q, and the third reset gate T4G of the third reset transistor T4 is connected to the third scan signal line Nscan2; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is connected to the anode of the light emitting device 211b, and the second reset gate T7G of the second reset transistor T7 is connected to the fourth scan signal line Pscan2; the first electrode of the first reset transistor T8 is connected to the third reset signal line Vi1, the second electrode of the third reset transistor T4 is connected to the third node Q, and the third reset gate T4G of the third reset transistor T4 is connected to the third scan signal line Nscan2; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is connected to the anode of the light emitting device 211b, and the second reset gate T7G of the second reset transistor T7 is connected to the fourth scan signal line Pscan2 The first reset signal line Vi3 is connected to the first reset signal line Vi3, the second electrode of the first reset transistor T8 is connected to the first node A, and the first reset gate T8G of the first reset transistor T8 is connected to the fourth scan signal line Pscan2; the first electrode of the first light-emitting transistor T5 is connected to the first high potential line VDD1, the second electrode of the first light-emitting transistor T5 is connected to the first node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting signal line EM; the first electrode of the second light-emitting transistor T6 is connected to the second node B, the second electrode of the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b, and the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b. The second light-emitting gate T6G of the body transistor T6 is connected to the light-emitting signal line EM; the fifth plate of the boost capacitor Cboost is connected to the third node Q, and the sixth plate of the boost capacitor Cboost is connected to the second scan signal line Pscan1; the third plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the fourth plate Cst2 of the storage capacitor Cst is connected to the first high potential line VDD1; the first plate of the first capacitor C1 is connected to the first reset signal line Vi3, and the second plate of the first capacitor C1 is connected to the first high potential line VDD1; the cathode of the light-emitting device 211b is connected to the first low potential line VSS.

[0059] It should be noted that the switch transistors T2 in different sub-pixel units 211 are connected to different data signal lines, and this application only takes one of them as an example for description.

[0060] In this embodiment, the first high potential line VDD1 is used to provide a constant high voltage to the pixel driving circuit 211 a , and the first low potential line VSS is used to provide a constant low voltage to the pixel driving circuit 211 a .

[0061] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the first reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 may be one of P-type transistors or N-type transistors, and the compensation transistor T3 and the third reset transistor T4 may be the other of P-type transistors or N-type transistors; this application is described by taking the switching transistor T2, the driving transistor T1, the second reset transistor T7, the first reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the third reset transistor T4 as N-type transistors as an example.

[0062] In this embodiment, the capacitance of the first capacitor C1 is smaller than that of the storage capacitor Cst, and the capacitance of the boost capacitor Cboost is smaller than that of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is primarily used to maintain the stability of the potential of the third node Q. Therefore, the capacitance of the storage capacitor Cst is relatively large. For example, the capacitance of the storage capacitor Cst may range from 45 fF to 55 fF, and the capacitance of the boost capacitor Cboost and the first capacitor Cst may range from 5 fF to 15 fF.

[0063] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0064] In the following embodiments, the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0065] The following describes the film layer structure of the pixel driving circuit 211 a of the present application with reference to the structure of FIG. 2 .

[0066] Referring to Figure 3 , the display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer (not shown) disposed on the array drive layer 120, a light-emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following primarily describes the film layer structure within the display area AA.

[0067] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0068] In this embodiment, the base substrate 110 is used to support the various film layers provided thereon. The base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0069] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0070] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a supporting substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material. The second flexible substrate 113 is formed by the same method as the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby eliminating such defects.

[0071] Referring to FIG3 , the array drive layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, or other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein the thin film transistor in FIG3 does not represent the structural diagram of any transistor in FIG2 , but is only a schematic diagram of the various film layers of the display panel 100 of the present application.

[0072] 3 , the array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, and a second active layer 129 disposed on the third gate insulating layer 128. , a fourth gate insulating layer 130 arranged on the second active layer 129, a third gate layer 131 arranged on the fourth gate insulating layer 130, a first interlayer insulating layer 132 arranged on the third gate layer 131, a first source-drain layer 133 arranged on the first interlayer insulating layer 132, a second interlayer insulating layer 134 arranged on the first source-drain layer 133, a second source-drain layer 135 arranged on the second interlayer insulating layer 134, a third interlayer insulating layer 136 arranged on the second source-drain layer 135, a third source-drain layer 137 arranged on the third interlayer insulating layer 136, and a planarization layer 138 arranged on the third source-drain layer 137.

[0073] 3 , a light shielding layer 121 is provided on the second barrier layer 114 . The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The light shielding layer 121 may be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0074] Please refer to Figure 3. The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0075] Referring to Figure 3, the first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0076] Please refer to Figure 3. The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the material of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0077] 3 , the first gate layer 125 , the second gate layer 127 and the third gate layer 131 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 , the second gate layer 127 and the third gate layer 131 may be copper, molybdenum or molybdenum-titanium alloy.

[0078] Please refer to Figure 3, the first source and drain layer 133 is arranged on the first interlayer insulating layer 132, the second source and drain layer 135 is arranged on the second interlayer insulating layer 134, and the third source and drain layer 137 is arranged on the third interlayer insulating layer 136. The materials of the first source and drain layer 133, the second source and drain layer 135, and the third source and drain layer 137 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal, etc.

[0079] 3 , the planarization layer 138 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120 . The material of the planarization layer 138 can be an inorganic material composed of nitride oxide and silicon, or an organic material with flatness.

[0080] Referring to Figure 4, the first gate layer 125 includes a light-emitting signal line EM, a third reset signal line Vi1, a first reset signal line Vi3, and a fourth scan signal line Pscan2. The light-emitting signal line EM, the third reset signal line Vi1, the first reset signal line Vi3, and the fourth scan signal line Pscan2 all extend along the first direction X, and the first reset signal line Vi3, the fourth scan signal line Pscan2, the light-emitting signal line EM, and the third reset signal line Vi1 are arranged at intervals along the second direction Y.

[0081] Please refer to Figure 4. The first gate layer 125 also includes a switch gate T2G and a third electrode plate Cst1 of the storage capacitor Cst, which are arranged between the light-emitting signal line EM and the third reset signal line Vi1. The switch gate T2G and the third electrode plate Cst1 are arranged at intervals in the second direction Y, and the third electrode plate Cst1 is close to the light-emitting signal line EM, and the switch gate T2G is arranged away from the light-emitting signal line EM.

[0082] In this embodiment, the light emitting signal line EM can directly serve as the first light emitting gate T5G and the second light emitting gate T6G, and the fourth scanning signal line Pscan2 can directly serve as the second reset gate T7G and the first reset gate T8G.

[0083] Referring to FIG. 4 , the switch gate T2G and the third electrode plate Cst1 may be in the shape of a rectangle, and the four corners of the third electrode plate Cst1 may be chamfered.

[0084] 5 , the first active layer 123 includes a switch active portion T2A of the switch transistor T2, a drive active portion T1A of the drive transistor T1, a second reset active portion T7A of the second reset transistor T7, a first reset active portion T8A of the first reset transistor T8, a first light emitting active portion T5A of the first light emitting transistor T5, and a second light emitting active portion T6A of the second light emitting transistor T6.

[0085] Please refer to Figure 5. The switch active portion T2A, the driving active portion T1A, the second reset active portion T7A, the first light-emitting active portion T5A, and the second light-emitting active portion T6A are connected to each other. The first reset active portion T8A is arranged separately from the other active portions. The switch active portion T2A, the second reset active portion T7A, the first reset active portion T8A, the first light-emitting active portion T5A, and the second light-emitting active portion T6A are all long strips and extend along the second direction Y. The driving active portion T1A is in a "X" shape and is arranged between the first light-emitting active portion T5A and the second light-emitting active portion T6A. The first end of the switch active portion T2A, the first end of the driving active portion T1A, and the first end of the first light-emitting active portion T5A are connected to the first connection point P1. The second end of the driving active portion T1A and the first end of the second light-emitting active portion T6A are connected to the second connection point P2. The first end of the second reset active portion T7A and the second end of the second light-emitting active portion T6A are connected to the third connection point P3.

[0086] In this embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third node Q is the location of the anode of the light emitting device 211 b.

[0087] Please refer to Figure 6. The light-emitting signal line EM and the first light-emitting active portion T5A partially overlap, and the overlapping portion is the channel of the first light-emitting active portion T5A; the light-emitting signal line EM and the second light-emitting active portion T6A partially overlap, and the overlapping portion is the channel of the second light-emitting active portion T6A; the switch gate T2G and the switch active portion T2A partially overlap, and the overlapping portion is the channel of the switch active portion T2A; the fourth scan signal line Pscan2 and the second reset active portion T7A partially overlap, and the overlapping portion is the channel of the second reset active portion T7A; the fourth scan signal line Pscan2 and the first reset active portion T8A partially overlap, and the overlapping portion is the channel of the first reset active portion T8A; the driving active portion T1A and the third electrode plate Cst1 partially overlap, and the overlapping portion is the channel of the driving active portion T1A. The third electrode plate Cst1 of the present application is multiplexed as the driving gate T1G of the driving transistor T1.

[0088] Referring to Figures 7 and 8, the second gate layer 127 includes a fourth plate Cst2 of the storage capacitor Cst arranged along the second direction Y, a first light shielding unit T3S of the compensation transistor T3, and a second light shielding unit T4S of the third reset transistor T4. The fourth plate Cst2, the first light shielding unit T3S and the second light shielding unit T4S are located between the light-emitting signal line EM and the third reset signal line Vi1. The third plate Cst1 is located close to the light-emitting signal line EM, the second light shielding unit T4S is located close to the third reset signal line Vi1, and the first light shielding unit T3S is located between the second light shielding unit T4S and the fourth plate Cst2.

[0089] 7 and 8 , the area of ​​the fourth plate Cst2 is larger than that of the third plate Cst1 , and the orthographic projection of the third plate Cst1 on the fourth plate Cst2 is located within the fourth plate Cst2 . A first through hole HL0 is defined on the fourth plate Cst2 to expose a portion of the third plate Cst1 .

[0090] Referring to FIG. 8 , the first light shielding unit T3S, the second light shielding unit T4S, and the fourth electrode plate Cst2 may be rectangular in shape, and at least part of their top corners may be chamfered.

[0091] Referring to FIG. 8 , the second gate layer 127 further includes first electrical connection segments 311 disposed on both sides of the fourth electrode plate Cst2. The two first electrical connection segments 311 extend along the first direction X. In two adjacent sub-pixel units 211 disposed along the first direction X, the fourth electrodes Cst2 in the two sub-pixel units 211 are electrically connected via the first electrical connection segments 311. In this embodiment, the fourth electrode plate Cst2 is connected to the first high potential line VDD1. To reduce the impedance on the fourth electrode plate Cst2, the present application may connect the fourth electrodes Cst2 in the sub-pixel units 211 disposed along the first direction X to each other and to be disposed in parallel with the first high potential line VDD1 of the upper layer, thereby reducing the impedance between the first high potential line VDD1 and the fourth electrode plate Cst2.

[0092] Referring to Figures 9 and 11, the second active layer 129 includes a compensation active portion T3A of the compensation transistor T3 and a third reset active portion T4A of the third reset transistor T4. The compensation active portion T3A and the third reset active portion T4A both extend along the second direction Y. A first end of the compensation active portion T3A and a first end of the third reset active portion T4A are connected to a fourth connection point P4. A second end of the compensation active portion T3A extends toward the second connection point P2 and is separated from the second connection point P2. A second end of the third reset active portion T4A extends toward the third reset signal line Vi1 and overlaps with the third reset signal line Vi1.

[0093] In this embodiment, the fourth connection point P4 may be the third node Q.

[0094] 9 and 11 , the second active layer 129 further includes a first extension segment 321 connected to the fourth connection point P4 and a second extension segment 322 connected to the second end of the third reset active portion T4A. The first extension segment 321 extends along the second direction Y toward the storage capacitor Cst, and is separated from the storage capacitor Cst. The second extension segment 322 extends along the first direction X, and at least partially overlaps with the third reset signal line Vi1.

[0095] Referring to Figures 10 and 11, the third gate layer 131 includes a compensation gate T3G and a third reset gate T4G of the third reset transistor T4. The area of ​​the compensation gate T3G is smaller than the area of ​​the first light-shielding unit T3S, and the orthographic projection of the compensation gate T3G on the first light-shielding unit T3S is located within the first light-shielding unit T3S. The area of ​​the third reset gate T4G is smaller than the area of ​​the second light-shielding unit T4S, and the orthographic projection of the third reset gate T4G on the second light-shielding unit T4S is located within the second light-shielding unit T4S.

[0096] 10 and 11 , the third reset gate T4G and the third reset active portion T4A partially overlap, and the overlapping portion is the channel of the third reset active portion T4A; the compensation active portion T3A and the compensation active portion T3A partially overlap, and the overlapping portion is the channel of the compensation active portion T3A.

[0097] 10 and 11 , the third reset gate T4G and the compensation gate T3G may both be rectangular in shape, and some of the top corners of the third reset gate T4G and the compensation gate T3G may be chamfered.

[0098] 10 and 11 , the third gate layer 131 further includes a first conductive segment 331 connected to the compensation gate T3G and a second conductive segment 332 connected to the third reset gate T4G. The first conductive segment 331 extends along the second direction Y toward a side away from the compensation gate T3G, and the second conductive segment 332 extends along the second direction Y toward a side away from the third reset gate T4G.

[0099] Referring to Figures 7 and 11 , the second gate layer 127 further includes a third conductive segment 333 connected to the first light shielding unit T3S, and a fourth conductive segment 334 connected to the second light shielding unit T4S. The third conductive segment 333 extends along the second direction Y toward a side away from the compensation gate T3G. The line width of the first conductive segment 331 can be less than or equal to the line width of the third conductive segment 333, and the orthographic projection of the first conductive segment 331 on the third conductive segment 333 can be located within the third conductive segment 333. The fourth conductive segment 334 can first extend along the second direction Y toward a side away from the third reset gate T4G, and then extend along the first direction X toward a side away from the compensation transistor T3. The ends of the second conductive segment 332 and the fourth conductive segment 334 away from the third reset gate T4G can be co-located.

[0100] Please refer to Figure 12, the first source and drain layer 133 includes a second reset signal line Vi2, a fifth scan signal line Nscan3, a second high potential line VDD2, a second scan signal line Pscan1, a first scan signal line Nscan1, and a third scan signal line Nscan2 arranged along the second direction Y. The second reset signal line Vi2, the fifth scan signal line Nscan3, the second high potential line VDD2, the second scan signal line Pscan1, the first scan signal line Nscan1, and the third scan signal line Nscan2 can all extend along the first direction X.

[0101] Please refer to Figures 12 to 15, the second reset signal line Vi2 is arranged between the first reset signal line Vi3 and the first scan signal line Nscan1, the fifth scan signal line Nscan3 and the fourth scan signal line Pscan2 partially overlap, the second high potential line VDD2 is arranged between the light-emitting signal line EM and the first electrical connection segment 311, the second scan signal line Pscan1, the first scan signal line Nscan1 and the third scan signal line Nscan2 are arranged between the first electrical connection segment 311 and the third reset signal line Vi1, and the second scan signal line Pscan1 is arranged close to the first electrical connection segment 311, the third scan signal line Nscan2 is arranged close to the third reset signal line Vi1, and the first scan signal line Nscan1 is arranged between the second scan signal line Pscan1 and the third scan signal line Nscan2.

[0102] Referring to Figures 12 to 15, the first source-drain layer 133 also includes a second electrical connection segment 312 arranged between the second reset signal line Vi2 and the first reset signal line Vi3. The first end of the second electrical connection segment 312 is electrically connected to the first reset signal line Vi3 through the first via HL1, and the second end of the second electrical connection segment 312 is electrically connected to the first end of the first reset active portion T8A through the second via HL2. The first reset signal line Vi3 transmits the reference voltage to the first reset transistor T8 through the second electrical connection segment 312.

[0103] In this embodiment, the first via hole HL1 passes through the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interlayer insulation layer 132 , and the second via hole HL2 passes through the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interlayer insulation layer 132 .

[0104] Referring to Figures 12 to 15, the first source and drain layer 133 also includes a third extension segment 323, a third electrical connection segment 313 and a fourth electrical connection segment 314 arranged between the second high potential line VDD2 and the fifth scan signal line Nscan3. The third extension segment 323 and the third electrical connection segment 313 both extend along the second direction Y, and the fourth electrical connection segment 314 extends along the first direction X.

[0105] In this embodiment, the first end of the third extension section 323 is electrically connected to the second high potential line VDD2, the second end of the third extension section 323 extends to a side away from the second high potential line VDD2, and the third extension section 323 overlaps with a portion of the first light emitting active portion T5A, and the second end of the third extension section 323 passes through the third via hole HL3 and is electrically connected to the second end of the first light emitting active portion T5A; the first end of the third electrical connection section 313 passes through the fourth via hole HL4 and is electrically connected to the second end of the first reset active portion T8A, and the first active layer 123 further includes a fourth extension section connected to the first light emitting active portion T5A. 324, the fourth extension segment 324 extends along the first direction X, the second end of the third electrical connection segment 313 passes through the fifth via HL5 and is electrically connected to the fourth extension segment 324, the first reset signal line Vi3 transmits the reference voltage to the first connection point P1 through the second electrical connection segment 312, the third electrical connection segment 313 and the fourth extension segment 324 to reset the potential of the first node A; one end of the fourth electrical connection segment 314 passes through a via and is electrically connected to the third connection point P3 in the first active layer 123, and the other end of the fourth electrical connection segment 314 passes through another via and is electrically connected to the conductive layer in the second source and drain layer 135.

[0106] In this embodiment, the third via hole HL3 passes through the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interlayer insulation layer 132, and the fourth via hole HL4 and the fifth via hole HL5 both pass through the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interlayer insulation layer 132.

[0107] 12 to 15 , the first source-drain layer 133 further includes a fifth electrical connection segment 315 and a sixth electrical connection segment 316 disposed between the second high potential line VDD2 and the second scan signal line Pscan1 . Both the fifth electrical connection segment 315 and the sixth electrical connection segment 316 extend along the second direction Y.

[0108] In this embodiment, the first end of the fifth electrical connection segment 315 passes through the sixth via hole HL6 and is electrically connected to the end of the first extension segment 321 away from the second scan signal line Pscan1. The second end of the fifth electrical connection segment 315 extends into the storage capacitor Cst and is electrically connected to the third electrode plate Cst1 of the storage capacitor Cst through the seventh via hole HL7. In the structure of Figure 14, the seventh via hole HL7 passes through the first through hole HL0 on the fourth electrode plate Cst2. The center of the first through hole HL0 and the center of the seventh through hole HL7 can be located on the same straight line perpendicular to the light-emitting surface of the display panel 100; the first end of the sixth electrical connection segment 316 passes through the eighth through hole HL8 and is electrically connected to the second connection point P2 in the first active layer 123, and the second end of the sixth electrical connection segment 316 passes through the ninth through hole HL9 and is electrically connected to the second end in the compensation active portion T3A.

[0109] In this embodiment, the sixth via hole HL6 and the ninth via hole HL9 penetrate the fourth gate insulation layer 130 and the first interinsulation layer 132 , and the seventh via hole HL7 and the eighth via hole HL8 penetrate the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interinsulation layer 132 .

[0110] Referring to Figures 12 to 15, the first source-drain layer 133 further includes a fifth extension segment 325, one end of the fifth extension segment 325 being electrically connected to the first scan signal line Nscan1, and the fifth extension segment 325 extending along the second direction Y and toward a side away from the first scan signal line Nscan1; the end of the fifth extension segment 325 away from the first scan signal line Nscan1 passes through the tenth via HL10 and is electrically connected to the first conductive segment 331, and the first scan signal line Nscan1 transmits the scan signal to the compensation gate T3G of the compensation transistor T3 through the fifth extension segment 325 and the first conductive segment 331; at the same time, the end of the second conductive segment 332 away from the third reset gate T4G overlaps with the third scan signal line Nscan2, and is electrically connected to the third scan signal line Nscan2 through the eleventh via HL11, and the third scan signal line Nscan2 transmits the scan signal to the third reset gate T4G of the third reset transistor T4 through the second conductive segment 332.

[0111] In this embodiment, both the tenth via hole HL10 and the eleventh via hole HL11 pass through the first interlayer insulating layer 132 .

[0112] Please refer to Figures 12 to 15. The third conductive segment 333 overlaps with the first conductive segment 331 and the third conductive segment 333, and the third conductive segment 333 passes through the twelfth via HL12 and is electrically connected to the first scan signal line Nscan1. The first scan signal line Nscan1 transmits the scan signal to the first light shielding unit T3S through the third conductive segment 333. That is, the first light shielding unit T3S can be reused as the bottom gate of the compensation transistor T3, and the compensation gate T3G is the top gate of the compensation transistor T3. The arrangement of the first light shielding unit T3S and the compensation gate T3G can increase the conduction rate of the compensation transistor T3 and improve the compensating transistor T3. Device effect; the fourth conductive segment 334 overlaps with a portion of the third scan signal line Nscan2, and is electrically connected to the third scan signal line Nscan2 through the thirteenth through hole HL13. The third scan signal line Nscan2 transmits the scan signal to the second shading unit T4S through the fourth conductive segment 334, that is, the second shading unit T4S can be reused as the bottom gate of the third reset transistor T4, and the third reset gate T4G is the top gate of the third reset transistor T4. The setting of the second shading unit T4S and the third reset gate T4G can increase the conduction rate of the third reset transistor T4 and improve the device effect of the third reset transistor T4.

[0113] In this embodiment, the twelfth via hole HL12 and the thirteenth via hole HL13 both penetrate the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first interlayer insulating layer 132 .

[0114] It should be noted that the third conductive segment 333 may be insulated from the first scan signal line Nscan1 , and the fourth conductive segment 334 may be insulated from the third scan signal line Nscan2 .

[0115] 12 to 15 , the fifth scan signal line Nscan3 can pass through the fourteenth via hole HL14 and be connected in parallel with the fourth scan signal line Pscan2 , that is, the fifth scan signal and the fourth scan signal line Pscan2 are arranged in parallel, thereby reducing the impedance of the fifth scan signal line Nscan3 and the fourth scan signal line Pscan2 .

[0116] In this embodiment, the fourteenth via hole HL14 passes through the second gate insulating layer 126 , the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first interlayer insulating layer 132 .

[0117] Please refer to Figures 12 to 15. The first scan signal line Nscan1 and the third reset active portion T4A partially overlap, the second scan signal line Pscan1 and the first extension segment 321 partially overlap, and the second scan signal line Pscan1 and the compensation active portion T3A partially overlap. The third scan signal line Nscan2 and the third reset active portion T4A partially overlap. The four overlapping areas are all overlapped by the material of the second active layer 129 and the material of the first source and drain layer 133. The fourth gate insulating layer 130 and the first interlayer insulating layer 132 are interposed between the first source and drain layer 133 and the second active layer 129, and the material of the third gate layer 131 is not provided in between, thereby avoiding the technical problem that the third gate layer 131 is easily short-circuited with the first source and drain layer 133.

[0118] Please refer to Figures 12 to 15. The overlapping portion of the second scanning signal line Pscan1 and the first extension section 321 is the boost capacitor Cboost of the present application. The fifth plate of the boost capacitor Cboost can be the portion of the first extension section 321 that overlaps with the second scanning signal line Pscan1. The sixth plate of the boost capacitor Cboost can be the portion of the second scanning signal line Pscan1 that overlaps with the first extension section 321.

[0119] Please refer to Figures 12 to 15. The first source and drain layer 133 also includes a seventh electrical connection segment 317 arranged between the second reset signal line Vi2 and the third scan signal line Nscan2. The seventh electrical connection segment 317 extends along the second direction Y and toward a side away from the second reset signal line Vi2. The seventh electrical connection segment 317 and the second extension segment 322 are arranged in an overlapping manner, which is equivalent to forming a capacitor between the third reset signal line Vi1 and the second reset signal line Vi2, thereby ensuring the stability of the voltage on the third reset signal line Vi1 and the second reset signal line Vi2.

[0120] Referring to Figure 16, the second source-drain layer 135 includes a first data signal line Data1, a second data signal line Data2, and a first high potential line VDD1. The second data signal line Data2, the first data signal line Data1, and the first high potential line VDD1 are arranged along a first direction X and extend along a second direction Y. The first data signal line Data1 is disposed between the second data signal line Data2 and the first high potential line VDD1.

[0121] Please refer to Figures 17 to 19. The first source and drain layer 133 includes an eighth electrical connection segment 318 arranged between the first scan signal line Nscan1 and the second scan signal line Pscan1. One end of the eighth electrical connection segment 318 is electrically connected to the second end of the switch active portion T2A, and the other end of the eighth electrical connection segment 318 is electrically connected to the first data signal line Data1. The first data signal line Data1 transmits the data signal to the switching transistor T2 through the eighth electrical connection segment 318.

[0122] In the structure of Figure 19, this application lists 6 sub-pixel units 211. The sub-pixel units 211 located in the first row are all connected to the first data signal line Data1, and the sub-pixel units 211 located in the second row are all connected to the second data signal line Data2. The sub-pixel units 211 listed in Figures 17 and 18 of this application are the sub-pixel units 211 in the first row in Figure 19.

[0123] In this embodiment, the structure of each pixel driving circuit 211a of the present application is the same, that is, the input end of the switch active part T2A equivalent to the switch transistor T2 is arranged on the same side. If the first data signal line Data1 and the second data signal line Data2 are arranged on both sides of the pixel driving circuit 211a, for example, when the first data signal line Data1 is arranged on the left side of the pixel driving circuit 211a and the second data signal line Data2 is arranged on the right side of the pixel driving circuit 211a, then the input end of the switch active part T2A of the sub-pixel unit 211 of the first row is adjacent to the first data signal line Data1, and the input end of the switch active part T2A of the sub-pixel unit 211 of the second row is adjacent to the second data signal line Data1. The spacing between the data signal lines Data2 is the width of a sub-pixel unit 211, that is, a connecting line across the sub-pixel unit 211 is required to electrically connect the second data signal line Data2 and the switch active part T2A of the sub-pixel unit 211 of the second row. The connecting line overlaps with multiple structures in the pixel driving circuit 211a, and the coupling capacitance increases, resulting in poor stability of the pixel driving circuit 211a; please refer to Figure 19. The present application reduces the connection distance between the data signal line and the switch active part T2A in the sub-pixel unit 211 by setting the two data signal lines on the same side of the pixel driving circuit 211a, reduces the coupling capacitance inside the pixel driving circuit 211a, and improves the stability of the pixel driving circuit 211a.

[0124] 16 to 18 , the first high potential line VDD1 includes a first sub-plate 341, a second sub-plate 342, a third sub-plate 343, a fourth sub-plate 344, and a fifth sub-plate 345. The third sub-plate 343, the first sub-plate 341, the fourth sub-plate 344, the fifth sub-plate 345, and the second sub-plate 342 are arranged along the second direction Y. The first sub-plate 341 is arranged between the third sub-plate 343 and the fourth sub-plate 344, the fourth sub-plate 344 is arranged between the third sub-plate 343 and the fifth sub-plate 345, and the second sub-plate 342 is arranged on a side of the fifth sub-plate 345 away from the fourth sub-plate 344. In the first direction X, the width of the first sub-plate 341 is smaller than the width of the fifth sub-plate 345, the width of the first sub-plate 341 may be greater than the width of the fourth sub-plate 344, and the width of the fourth sub-plate 344 may be greater than or equal to the widths of the third sub-plate 343 and the second sub-plate 342.

[0125] In this embodiment, since the potential of the driving gate T1G is the potential of the third node Q, the potential change of the third node Q directly affects the working current of the light-emitting device 211b, so this application needs to ensure the stability of the potential of the third node Q; this application can make the positive projection of the driving gate T1G on the first high potential line VDD1 located within the first sub-plate 341, which is equivalent to using the first sub-plate 341 as a shielding layer to maintain the stability of the potential of the third node Q, so this application needs to increase the lateral width of the first sub-plate 341 so that the first sub-plate 341 fully covers the driving gate T1G, and the third plate Cst1 of the storage capacitor Cst is reused as the driving gate T1G, that is, the positive projection of the third plate Cst1 on the first high potential line VDD1 can be located within the first sub-plate 341, so the width of the first sub-plate 341 of this application can be greater than the widths of the third sub-plate 343, the fourth sub-plate 344 and the second sub-plate 342.

[0126] In this embodiment, the fifth electrical connection section 315 and the first extension section 321 are both electrically connected to the driving gate T1G, so changes in the potential on the fifth electrical connection section 315 and the first extension section 321 will also affect the potential of the driving gate T1G. Therefore, the present application can increase the width of the fourth sub-plate 344 to fully cover the fifth electrical connection section 315 and the first extension section 321. Therefore, the lateral width of the fourth sub-plate 344 of the present application can be greater than the lateral width of the third sub-plate 343 and the second sub-plate 342.

[0127] Please refer to Figures 12, 17 and 18. The second electrically connecting segment 312 can serve as the first sub-portion of the first electrode plate, one end of the first sub-portion is electrically connected to the first reset signal line Vi3, the other end of the first sub-portion is connected to the active portion of the first reset transistor T8, the orthographic projection of the first sub-portion on the second source-drain layer 135 is at least partially located within the first high potential line VDD1, and the second sub-plate 342 can serve as the second electrode plate of the first capacitor C1.

[0128] In the present application, the second electrical connection section 312 and part of the first high-potential line VDD1 are overlapped, the second electrical connection section 312 serves as a first plate, the second sub-plate 342 serves as a second plate, the first plate and the second plate form a first capacitor C1, and the constant high potential on the second plate improves the anti-coupling capability of the first reset signal line Vi3, thereby improving the stability of the reset signal transmitted by the first reset signal line Vi3, avoiding abnormal output voltage at the output end of the first reset transistor T8, ensuring that the voltage of the reset node between the switching transistor T2 and the first reset transistor T8 is reset to the reference potential, and improving the technical problem of abnormal display of the display panel 100.

[0129] Referring to Figures 12, 17 and 18, the second electrical connection section 312 can be in the form of a right triangle, with the two acute angles of the second electrical connection section 312 located at the positions of the first via HL1 and the second via HL2 respectively. In the prior art, the second electrical connection section 312 only needs to be along the straight line segment from the first via HL1 to the second via HL2. However, in the present application, by setting the shape of the second electrical connection section 312 to a right triangle, overlapping the second electrical connection section 312 and part of the first reset signal line Vi3, and separating the second electrical connection section 312 and the second reset signal line Vi2, the longitudinal width and lateral width of the second electrical connection section 312 are increased, which is equivalent to increasing the area of ​​the second electrical connection section 312, thereby increasing the overlapping area of ​​the second electrical connection section 312 and the first high potential line VDD1, increasing the capacitance value of the first capacitor C1, and further improving the stability of the reset signal transmitted by the first reset signal line Vi3.

[0130] In this embodiment, in order to avoid interference between the second electrical connection section 312 and the second reset signal line Vi2, the second reset signal line Vi2 is designed to be sunken at the position corresponding to the second electrical connection section 312, that is, the signal line in this area is offset to the side away from the first reset signal line Vi3; at the same time, in order to ensure the line distance between the fifth scan signal line Nscan3 and the second reset signal line Vi2, the fifth scan signal line Nscan3 is also designed to be sunken.

[0131] Referring to Figures 12, 17, and 18, the second reset signal line Vi2 includes a transverse segment Vi2a, an inclined segment Vi2b, and a relief segment Vi2c. The relief segment Vi2c is connected to one of the inclined segments Vi2b at each end, and the end of the inclined segment Vi2b distal from the relief segment Vi2c is connected to the transverse segment Vi2a. The spacing between the transverse segment Vi2a and the first reset signal line Vi3 is smaller than the spacing between the relief segment Vi2c and the second reset signal line Vi2. The relief segment Vi2c is aligned with the first sub-section. Specifically, the distance that the relief segment Vi2c is sunken relative to the second reset signal line Vi2 can be set based on the longitudinal spacing between the transverse segment Vi2a and the first reset signal line Vi3. For example, the longitudinal spacing between the second via HL2 in the second electrical connection segment 312 and the relief segment Vi2c is close to the longitudinal spacing between the transverse segment Vi2a and the first reset signal line Vi3.

[0132] Referring to Figures 12, 17, and 18, the first sub-section has a first inclined surface M1 facing the second reset signal line Vi2, and the inclined section Vi2b has a second inclined surface M2 facing the first sub-section, with the first inclined surface M1 and the second inclined surface M2 being parallel. By aligning the first inclined surface M1 of the second electrical connection section 312 and the second inclined surface M2 of the inclined section Vi2b, the present application ensures equal spacing between the second electrical connection section 312 and the inclined section Vi2b. This allows for a compact arrangement of the film structure while insulating the second reset signal line Vi2 from the second electrical connection section 312.

[0133] Please refer to Figures 20 and 21. Compared with the structure of Figure 16, the present application can increase the width of the second sub-plate 342 in the first high-potential line VDD1 so that the second electrical connection segment 312 is located inside the second sub-plate 342 on the first high-potential line VDD1. The increase in the lateral width of the second sub-plate 342 is equivalent to increasing the overlapping area between the second sub-plate 342 and the second electrical connection segment 312, thereby increasing the capacitance value of the first capacitor C1, that is, improving the anti-coupling capability of the first reset signal line Vi3, and further improving the stability of the reset signal transmitted by the first reset signal line Vi3.

[0134] In this embodiment, the increase in the lateral width of the second sub-board 342 makes the second sub-board 342 closer to the first data signal line Data1, and the distance between the first sub-board 341 and the first data signal line Data1 is greater than the distance between the second sub-board 342 and the first data signal line Data1.

[0135] Referring to Figure 21 , a portion of the first reset signal line Vi3 is multiplexed into the second sub-portion Vi3a of the first plate. The orthographic projection of the second sub-portion Vi3a on the first source / drain layer 133 does not overlap with the first sub-portion, and the orthographic projection of the second sub-portion Vi3a on the second source / drain layer 135 lies within the first high-potential line VDD1. The increased lateral width of the second sub-plate 342 allows it to overlap with a portion of the first reset signal line Vi3. This portion of the first reset signal line Vi3 can serve as the second sub-plate 342 of the first plate. This effectively increases the area of ​​the first plate, thereby increasing the relative area between the first and second plates and increasing the capacitance of the first capacitor C1, thereby improving the anti-coupling capability of the first reset signal line Vi3.

[0136] It should be noted that, in the prior art, there is a small area of ​​overlap between the first reset signal line Vi3 and the first high potential line VDD1, and the first capacitance C1 between the two can be 7.3fF, while the second capacitance between the data line and the first reset signal line Vi3 is 0.68fF; taking the second source and drain layer 135 in Figures 16 to 18 as an example, the first capacitance C1 between the first high potential line VDD1 and the first reset signal line Vi3 is increased to 18.5fF, and the second capacitance between the data line and the first reset signal line Vi3 is still 0.68fF; therefore, compared with the prior art, the quotient of the second capacitance value and the first capacitance C1 value of the present application is reduced from 9.3% to 3.7%, thereby improving the anti-coupling capability of the first reset signal line Vi3, and thereby improving the stability of the reset signal transmitted by the first reset signal line Vi3.

[0137] 22 and 24 , the third source-drain layer 137 may include a third high potential line VDD3 extending along the second direction Y, the third high potential line VDD3 being electrically connected to the second high potential line VDD2, and the third high potential line VDD3 being provided mainly to reduce the impedance of the conductor that transmits a constant voltage high level.

[0138] It should be noted that in Figures 16 to 22, the first high potential line VDD1 of the present application can be electrically connected to the second high potential line VDD2, and then the second high potential line VDD2 is electrically connected to the fourth plate Cst2 of the storage capacitor Cst, and the fourth plate Cst2 located in the same row is electrically connected through the first electrical connection section 311; therefore, the wire for transmitting a constant voltage high level in the present application has four layers of metal, namely, the fourth plate Cst2 and the first electrical connection section 311 located in the second gate layer 127, the second high potential line VDD2 located in the first source and drain layer 133, and the fourth plate Cst2 located in the same row. The bit line VDD2, the first high potential line VDD1 located in the second source and drain layer 135, the third high potential line VDD3 located in the third source and drain layer 137, the fourth electrode plate Cst2, the first electrical connection section 311, and the second high potential line VDD2 all extend along the first direction X, and the first high potential line VDD1 and the third high potential line VDD3 all extend along the second direction Y. Therefore, the present application uses four layers of metal to transmit a constant voltage high level to form a metal mesh that is crisscrossed horizontally and vertically in a mesh shape to reduce the impedance of the wire, thereby reducing the loss of the constant voltage high level on the transmitted wire.

[0139] Please refer to Figure 25. The third source-drain layer 137 of the present application includes a plurality of repeating units 137a. Each repeating unit 137a corresponds to three adjacent sub-pixel units 211 arranged along the first direction X. For example, the three sub-pixel units 211 are the first sub-pixel unit 212, the second sub-pixel unit 213, and the third sub-pixel unit 214. For example, each repeating unit 137a may include a first third high potential line VDD3 corresponding to the first sub-pixel unit 212, a third third high potential line VDD3 corresponding to the third sub-pixel unit 214, a second high potential line and a fourth reset signal line Vi4 corresponding to the second sub-pixel unit 213. The structures of the first third high potential line VDD3 and the third third high potential line VDD3 may be the same, and the structures of the second third high potential line VDD3 and the third third high potential line VDD3 are different. In addition, the lateral width of the second third high potential line VDD3 is smaller than the lateral width of the third third high potential line VDD3.

[0140] Please refer to Figure 25. Each repeating unit 137a is provided with a longitudinal reset signal line and three transverse reset signal lines. In order to reduce the impedance of the reset signal line, the longitudinal reset signal line can be electrically connected to one of the three transverse reset signal lines. For example, there are three rows of repeating units 137a in Figure 26, and each row of repeating units 137a includes three repeating units 137a. Each repeating unit 137a is provided with a fourth reset signal line Vi4. The fourth reset signal line Vi4 in the first repeating unit 137a can be electrically connected to the third reset signal line Vi1 of each row, the fourth reset signal line Vi4 in the second repeating unit 137a can be electrically connected to the second reset signal line Vi2 of each row, and the fourth reset signal line Vi4 in the third repeating unit 137a can be electrically connected to the first reset signal line Vi3 of each row, so that each transverse reset signal line and the fourth reset signal line Vi4 are electrically connected to form a metal mesh that is crisscrossed horizontally and vertically, thereby reducing the impedance of the reset signal line.

[0141] It should be noted that the first sub-pixel unit 212, the second sub-pixel unit 213 and the third sub-pixel unit 214 in Figure 25 only represent the position of the pixel driving circuit 211a of the corresponding sub-pixel unit 211, and the position of the anode in the sub-pixel unit 211 may not be in the corresponding area; for example, please refer to Figure 27, the pixel driving circuit 211a in the first sub-pixel unit 212 of the present application is electrically connected to the first anode 211b1, and the pixel driving circuit 211a in the second sub-pixel unit 213 is electrically connected to the second anode 211b2, the first anode 211b1 and the second anode 211b2 are arranged along the second direction Y, and the first anode 211b1 and the second anode 211b2 both span the first sub-pixel unit 212 and the second sub-pixel unit 213.

[0142] It should be noted that, in FIG27 , the third source-drain electrode layer 137 may further include a ninth electrical connection segment 319 and a tenth electrical connection segment 320, the ninth electrical connection segment 319 being disposed between the fourth reset signal line Vi4 and the second third high potential line VDD3, the tenth electrical connection segment 320 being disposed on one side of the first third high potential line VDD3 and the third third high potential line VDD3, the tenth electrical connection segment 320 corresponding to the fourth electrical connection segment 314; the second source-drain electrode layer 135 may further include an eleventh electrical connection segment 321, and the second anode 211b2 may be connected to the ninth electrical connection segment 321 of the second sub-pixel unit 213. Segment 319, the eleventh electrical connection segment 321, the fourth electrical connection segment 314 and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the second sub-pixel unit 213 are electrically connected; similarly, the first anode 211b1 can be electrically connected through the tenth electrical connection segment 320, the eleventh electrical connection segment 321, the fourth electrical connection segment 314 and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the first sub-pixel unit 212; similarly, the connection method of the anode in the third sub-pixel unit 314 is the same as the connection method of the first anode 211b1.

[0143] The present application also provides a display device, comprising the above-mentioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0144] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] The above is a detailed introduction to a spliced ​​display module, a preparation method, and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit comprises: a switch transistor, wherein a first electrode of the switch transistor is connected to the first data signal line, and a second electrode of the switch transistor is connected to the first node; a driving transistor, wherein a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to a third node; a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third node, and a second electrode of the compensation transistor is connected to the second node; a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first node; as well as A first capacitor, wherein a first plate of the first capacitor is connected to the first reset signal line, and a second plate of the first capacitor is connected to the first high potential line.

2. The display panel according to claim 1, wherein The display panel includes: substrate; A first gate layer is provided on one side of the base substrate; a second gate layer, disposed on a side of the first gate layer away from the base substrate; a third gate layer, disposed on a side of the second gate layer away from the first gate layer; a first source-drain electrode layer, disposed on a side of the third gate layer away from the second gate layer; a second source-drain electrode layer, disposed on a side of the first source-drain electrode layer away from the third gate layer; The first electrode plate is disposed on at least one of the first gate layer and the first source-drain layer, and the second electrode plate is disposed on the second source-drain layer.

3. The display panel according to claim 2, wherein: The second source-drain layer includes a plurality of the first high-potential lines arranged along a first direction and extending along a second direction, the first source-drain layer includes a first sub-portion of the first electrode plate, one end of the first sub-portion is electrically connected to the first reset signal line, and the other end of the first sub-portion is connected to the active portion of the first reset transistor; The orthographic projection of the first sub-portion on the second source-drain layer is at least partially located within the first high-potential line, and the angle between the first direction and the second direction is greater than 0 degree and less than or equal to 90 degrees.

4. The display panel according to claim 3, wherein: The first gate layer includes the first reset signal line extending along the first direction, the first source-drain layer includes the second reset signal line extending along the first direction, and the second reset signal line and the first reset signal line are spaced apart in the second direction; The first sub-section and a portion of the first reset signal line are overlapped, and the first sub-section and the second reset signal line are separated.

5. The display panel according to claim 4, wherein: The second reset signal line includes a transverse section, an inclined section, and an avoidance section, wherein both ends of the avoidance section are respectively connected to one of the inclined sections, and one end of the inclined section away from the avoidance section is connected to the transverse section; The distance between the transverse section and the first reset signal line is smaller than the distance between the avoidance section and the second reset signal line, and the avoidance section is aligned with the first sub-section. The display panel according to claim 5 , wherein: The first sub-portion has a first inclined surface facing the second reset signal line, and the inclined section has a second inclined surface facing the first sub-portion. The first inclined surface and the second inclined surface are parallel.

7. The display panel according to claim 3, wherein: Part of the first reset signal line is multiplexed as the second sub-portion of the first electrode plate, the orthographic projection of the second sub-portion on the first source and drain layer does not overlap with the first sub-portion, and the orthographic projection of the second sub-portion on the second source and drain layer is located within the first high potential line.

8. The display panel according to claim 2, wherein: The first high-potential line includes a first sub-plate and a second sub-plate arranged along the second direction, the orthographic projection of the driving gate on the first high-potential line is located within the first sub-plate, and the orthographic projection of the first electrode plate on the first high-potential line is at least partially located within the second sub-plate; The second source-drain layer further includes the first data signal line extending along the second direction, and the distance between the first sub-board and the first data signal line is greater than the distance between the second sub-board and the first data signal line.

9. The display panel according to claim 1, wherein: The pixel driving circuit further includes a storage capacitor, the storage capacitor including a third plate and a fourth plate, the third plate is connected to the third node, and the fourth plate is connected to the first high potential line; a second reset transistor, wherein a first electrode of the second reset transistor is connected to a second reset signal line, and a second electrode of the second reset transistor is connected to an anode of the light emitting device; a third reset transistor, wherein a first electrode of the third reset transistor is connected to a third reset signal line, and a second electrode of the third reset transistor is connected to the third node; a first light-emitting transistor, wherein a first electrode of the first light-emitting transistor is connected to the first high-potential line, a second electrode of the first light-emitting transistor is connected to the first node, and a gate of the first light-emitting transistor is connected to a light-emitting signal line; a second light emitting transistor, wherein a first electrode of the second light emitting transistor is connected to the second node, a second electrode of the second light emitting transistor is connected to the anode of the light emitting device, and a gate of the second light emitting transistor is connected to the light emitting signal line; A boost capacitor includes a fifth plate and a sixth plate, wherein the fifth plate is connected to the third node, and the sixth plate is connected to the second scanning signal line.

10. The display panel according to claim 9, wherein: The capacitance value of the first capacitor is smaller than the capacitance value of the storage capacitor, and the capacitance value of the boost capacitor is smaller than the capacitance value of the storage capacitor.

11. The display panel according to claim 9, wherein: The first gate layer of the display panel includes a light-emitting signal line, a third reset signal line, a first reset signal line, and a fourth scan signal line. The light-emitting signal line, the third reset signal line, the first reset signal line, and the fourth scan signal line all extend along a first direction, and the first reset signal line, the fourth scan signal line, the light-emitting signal line, and the third reset signal line are arranged at intervals along a second direction.

12. The display panel according to claim 11, wherein: The first active layer of the display panel includes a switching active portion of the switching transistor, a driving active portion of the driving transistor, a second reset active portion of the second reset transistor, a first reset active portion of the first reset transistor, a first light emitting active portion of the first light emitting transistor, and a second light emitting active portion of the second light emitting transistor; Among them, the switch active part, the driving active part, the second reset active part, the first light-emitting active part, and the second light-emitting active part are connected to each other, the switch active part, the second reset active part, the first reset active part, the first light-emitting active part, and the second light-emitting active part extend along the second direction, and the driving active part is arranged between the first light-emitting active part and the second light-emitting active part.

13. The display panel according to claim 12, wherein: The second gate layer of the display panel includes a fourth plate of the storage capacitor arranged along the second direction, a first shading unit of the compensation transistor, and a second shading unit of the third reset transistor. The fourth plate, the first shading unit and the second shading unit are located between the light-emitting signal line and the third reset signal line. The third plate is arranged close to the light-emitting signal line, the second shading unit is arranged close to the third reset signal line, and the first shading unit is located between the second shading unit and the fourth plate.

14. The display panel according to claim 13, wherein: The second gate layer also includes first electrical connection segments arranged on both sides of the fourth electrode plate, and the two first electrical connection segments both extend along the first direction. In two adjacent sub-pixel units arranged along the first direction, the fourth electrodes in the two sub-pixel units are electrically connected through the first electrical connection segments.

15. The display panel according to claim 13, wherein: The second active layer of the display panel includes a compensation active portion of the compensation transistor and a third reset active portion of the third reset transistor, the compensation active portion and the third reset active portion both extend along the second direction, a first end of the compensation active portion is connected to a first end of the third reset active portion, and a second end of the third reset active portion extends toward the third reset signal line and overlaps with the third reset signal line.

16. The display panel according to claim 15, wherein: The second active layer also includes a first extension segment and a second extension segment connected to the second end of the third reset active portion, the first extension segment extends along the second direction and extends toward the location of the storage capacitor, the first extension segment is separated from the storage capacitor, the second extension segment extends along the first direction, and the second extension segment and the third reset signal line at least partially overlap.

17. The display panel according to claim 15, wherein: The third gate layer of the display panel includes a compensation gate of the compensation transistor and a third reset gate of the third reset transistor, an area of the compensation gate is smaller than an area of the first shading unit, and an orthographic projection of the compensation gate on the first shading unit is located within the first shading unit. An area of the third reset gate is smaller than an area of the second shading unit, and an orthographic projection of the third reset gate on the second shading unit is located within the second shading unit.

18. The display panel according to claim 17, wherein: The third gate layer further includes a first conductive segment connected to the compensation gate and a second conductive segment connected to the third reset gate, wherein the first conductive segment extends along the second direction and toward a side away from the compensation gate, and the second conductive segment extends along the second direction and toward a side away from the third reset gate.

19. The display panel according to claim 18, wherein: The first source and drain layer of the display panel includes a second reset signal line, a fifth scan signal line, a second high potential line, a second scan signal line, a first scan signal line, and a third scan signal line arranged along the second direction, and the second reset signal line, the fifth scan signal line, the second high potential line, the second scan signal line, the first scan signal line, and the third scan signal line all extend along the first direction.

20. A display device comprising a display panel, the display panel comprising a plurality of sub-pixel units, each of the sub-pixel units being provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, the pixel driving circuit comprising: a switch transistor, wherein a first electrode of the switch transistor is connected to the first data signal line, and a second electrode of the switch transistor is connected to the first node; a driving transistor, wherein a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to a third node; a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third node, and a second electrode of the compensation transistor is connected to the second node; a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first node; as well as A first capacitor, wherein a first plate of the first capacitor is connected to the first reset signal line, and a second plate of the first capacitor is connected to the first high potential line.

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