Display panel and display apparatus

Abstract

A display panel (100) and a display apparatus. A pixel driving circuit (211a) of the display panel (100) comprises a driving portion (220), a first capacitor (C1), and a second capacitor (C2); a first electrode sheet of the first capacitor (C1) is connected to an anode of a light-emitting device, and a second electrode sheet of the first capacitor (C1) is connected to a high-potential line (VDD); a first electrode sheet of the second capacitor (C2) is connected to a data signal line (Data), and a second electrode sheet of the second capacitor (C2) is connected to the high-potential line (VDD).

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention for its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In related technologies, the data line in the OLED display panel overlaps with the anode of the light-emitting device, and there is a coupling capacitor between the data line and the light-emitting device. When the data signal of the data line jumps, the voltage signal at the anode point changes due to the existence of the coupling capacitor, resulting in abnormal display of the display panel. Summary of the Invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] The present application provides a display panel comprising a plurality of sub-pixel units and a plurality of data signal lines, wherein the data signal lines are provided between two adjacent sub-pixel units, the sub-pixel units comprising light-emitting devices and a pixel driving circuit connected to the light-emitting devices, the pixel driving circuit comprising:

[0007] a driving unit connected to the data signal line at a first control node, connected to the high potential line at a second control node, and connected to the light emitting device at a third control node; and

[0008] a first capacitor, wherein a first plate of the first capacitor is connected to the third control node, and a second plate of the first capacitor is connected to the high potential line;

[0009] A second capacitor, wherein a first plate of the second capacitor is connected to the data signal line, and a second plate of the second capacitor is connected to the high potential line.

[0010] The present application also proposes a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a simplified structural diagram of the display panel of the present application;

[0012] FIG2 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

[0013] FIG3 is a schematic diagram of the film layer in the display panel of the present application;

[0014] FIG4 is a film layer diagram of the first gate layer in the display panel of the present application;

[0015] FIG5 is a film diagram of the first active layer in the display panel of the present application;

[0016] FIG6 is a diagram showing a stack of film layers of a first gate layer and a first active layer in a display panel of the present application;

[0017] FIG7 is a film layer diagram of the second gate layer in the display panel of the present application;

[0018] FIG8 is a diagram showing a stack of first and second gate layers in a display panel of the present application;

[0019] FIG9 is a film diagram of the second active layer in the display panel of the present application;

[0020] FIG10 is a film layer diagram of the third gate layer in the display panel of the present application;

[0021] FIG11 is a film layer diagram of the first active layer, the second active layer, the second gate layer and the third gate layer in the display panel of the present application;

[0022] FIG12 is a film diagram of the first source and drain electrode layer in the display panel of the present application;

[0023] FIG13 is a film layer diagram of the first gate layer, the third gate layer, the first active layer, the second active layer and the first source and drain layer in the display panel of the present application;

[0024] FIG14 is a film layer diagram of the second active layer, the second gate layer, and the first source and drain layer in the display panel of the present application;

[0025] FIG15 is a film layer diagram of the first gate layer, the second gate layer, the third gate layer, the first active layer, the second active layer, and the first source and drain layer in the display panel of the present application;

[0026] FIG16 is a film diagram of the second source and drain electrode layer in the display panel of the present application;

[0027] FIG17 is a diagram showing the superposition of the first active layer, the second active layer, the third gate layer, the first source-drain electrode layer, and the second source-drain electrode layer in the display panel of the present application;

[0028] FIG18 is a diagram showing the film layer stacking of the pixel driving circuit of the present application;

[0029] FIG19 is a connection diagram of different sub-pixel units and different data lines of the display panel of the present application;

[0030] FIG20 is a film diagram of the third source and drain layer in the display panel of the present application;

[0031] FIG21 is a diagram showing the superimposed film layers of the second source-drain electrode layer and the third source-drain electrode layer in the display panel of the present application;

[0032] FIG22 is a fourth film layer stacking diagram of the pixel driving circuit of the present application;

[0033] FIG23 is a film layer diagram of the third source and drain electrode layer in multiple sub-pixel units in the display panel of the present application;

[0034] FIG24 is a diagram showing the connection relationship between the first reset signal line, the second reset signal line, the third reset signal line, and the fourth reset signal line in the display panel of the present application;

[0035] FIG25 is a diagram of a first type of film layer in which a third source / drain electrode layer and a second source / drain electrode layer are superimposed in a display panel of the present application;

[0036] FIG26 is a diagram of a first type of film layer in which a third source / drain electrode layer, a second source / drain electrode layer, and an anode layer are stacked in the display panel of the present application;

[0037] FIG27 is a second film layer diagram of the third source-drain electrode layer and the second source-drain electrode layer superimposed in the display panel of the present application;

[0038] FIG28 is a second film layer diagram of the third source-drain electrode layer, the second source-drain electrode layer, and the anode layer stacked in the display panel of the present application. Modes for Carrying Out the Invention

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application and are not intended to limit the present application.

[0040] In the description of this application, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, and "at least one" means one, two, or more, unless otherwise specifically defined.

[0042] Referring to Figures 1 to 28, the present application provides a display panel 100. The display panel 100 may include a display portion 200 and a gate driving circuit 300 located on one side of the display portion 200. The gate driving circuit 300 is used to input a control signal to the display portion 200.

[0043] In this embodiment, referring to FIG1 , the display portion 200 includes a plurality of sub-pixel rows 210 , each sub-pixel row 210 includes a plurality of sub-pixel units 211 , each sub-pixel unit 211 includes a light-emitting device 211 b and a pixel driving circuit 211 a connected to the light-emitting device 211 b , and the gate driving circuit 300 is used to input a gate control signal to the transistor in the pixel driving circuit 211 a .

[0044] In this embodiment, referring to FIG. 2 , the pixel driving circuit 211 a includes a driving unit 220 and a first capacitor C1 and a second capacitor C2 electrically connected to the driving unit 220; the driving unit 220 is connected to the data signal line Data at the first control node N1, is connected to the high potential line VDD at the second control node N2, and is connected to the light-emitting device 211 b at the third control node N3; the first plate of the first capacitor C1 is connected to the third control node N3, and the second plate of the first capacitor C1 is connected to the high potential line VDD; the first plate of the second capacitor C2 is connected to the data signal line Data, and the second plate of the second capacitor C2 is connected to the high potential line VDD.

[0045] The present application provides a first capacitor C1 connected to the anode of the light-emitting device 211b and the high potential line VDD and a second capacitor C2 connected to the high potential line VDD and the data signal line Data in the pixel driving circuit 211a, thereby shielding the coupling capacitance between the data signal line Data and the high potential line VDD, thereby avoiding changes in the voltage signal at the anode point in the light-emitting device 211b when the data signal of the data signal line Data jumps, improving the potential stability of the anode point, and eliminating the technical problem of abnormal display of the display panel 100.

[0046] It should be noted that the light-emitting device 211b of the present application can be an organic light-emitting diode, Mini LED, Micro LED, a regular-sized LED or other light-emitting source.

[0047] The technical solution of this application is now described in conjunction with specific embodiments.

[0048] Referring to Figure 1 , the display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA. A display portion 200 is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the region within the display panel 100 used for display functions, and is provided with a plurality of sub-pixel units 211 therein to implement these functions. The non-display area NA may be a border region of the display panel 100, and may contain functional components that assist the sub-pixel units 211 within the display area AA in performing display functions.

[0049] Referring to Figure 1 , the lower side of the display area AA is provided with a bonding terminal 400. The bonding terminal 400 can be connected to an external circuit and transmits signals input from the external circuit to the data traces, thereby driving the display panel 100 to display an image. For example, the bonding terminal 400 can be bonded to a chip or a chip-on-film to provide power and drive signals to the display panel 100.

[0050] In this embodiment, the gate driving circuit 300 is arranged in the non-display area NA, and the gate driving circuit 300 can be arranged on both sides of the display area AA; the gate driving circuit 300 may include a plurality of cascaded gate driving units, and the plurality of gate driving units may be arranged along the first direction X. The structure of the gate driving unit is not specifically limited in this application.

[0051] In this embodiment, a plurality of light-emitting devices 211b and a pixel driving circuit 211a for driving the light-emitting devices 211b may be arranged in an array in the display area AA. The pixel driving circuit 211a may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 211a. The following embodiment will be described using the 8T4C pixel driving circuit 211a as an example.

[0052] Referring to Figure 2, the pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boost capacitor Cboost and a storage capacitor Cst, the storage capacitor Cst includes a fifth plate Cst1 and a sixth plate Cst2, and the boost capacitor Cboost includes a seventh plate and an eighth plate.

[0053] Please refer to Figure 2. The first electrode of the switching transistor T2 is connected to the data signal line Data, the second electrode of the switching transistor T2 is connected to the first internal node A, and the switching gate T2G of the switching transistor T2 is connected to the second control signal line Pscan1; the first electrode of the driving transistor T1 is connected to the first internal node A, the second electrode of the driving transistor T1 is connected to the second internal node B, and the driving gate T1G of the driving transistor T1 is connected to the third internal node Q; the first electrode of the compensation transistor T3 is connected to the third internal node Q, the second electrode of the compensation transistor T3 is connected to the second internal node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control signal line Nscan1; the first electrode of the first reset transistor T4 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T4 is connected to the third internal node Q, and the first reset gate T4G of the first reset transistor T4 is connected to the third control signal line Nscan2; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is connected to the anode of the light emitting device 211b, and the The second reset gate T7G is connected to the fourth control signal line Pscan2; the first electrode of the third reset transistor T8 is connected to the third reset signal line Vi3, the second electrode of the third reset transistor T8 is connected to the first internal node A, and the third reset gate T8G of the third reset transistor T8 is connected to the fourth control signal line Pscan2; the first electrode of the first light-emitting transistor T5 is connected to the high potential line VDD, the second electrode of the first light-emitting transistor T5 is connected to the first internal node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting signal line EM; the first electrode of the second light-emitting transistor T6 is connected to the second internal node B, the second electrode of the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b, and the second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting signal line EM; the seventh plate of the boost capacitor Cboost is connected to the third internal node Q, and the eighth plate of the boost capacitor Cboost is connected to the second control signal line Pscan1; the fifth plate Cst1 of the storage capacitor Cst is connected to the third internal node Q, and the sixth plate Cst2 of the storage capacitor Cst is connected to the high potential line VDD.

[0054] It should be noted that the switch transistors T2 in different sub-pixel units 211 are connected to different data signal lines, and this application only takes one of them as an example for description.

[0055] In this embodiment, the first high potential line VDD1 is used to provide a constant high voltage to the pixel driving circuit 211a, and the low potential line VSS is used to provide a constant low voltage to the pixel driving circuit 211a. The low potential line VSS is electrically connected to the cathode of the light emitting device 211b.

[0056] In this embodiment, the first control node is where the first electrode of the switch transistor T2 is located, the second control node is where the first electrode of the first light emitting transistor T5 is located, and the third control node is where the anode of the light emitting device is located.

[0057] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 may be one of P-type transistors or N-type transistors, and the compensation transistor T3 and the first reset transistor T4 may be the other of P-type transistors or N-type transistors; this application is described by taking the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0058] In this embodiment, the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the boost capacitor Cboost are smaller than the capacitance value of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is primarily used to maintain the stability of the potential of the third internal node Q. Therefore, the capacitance of the storage capacitor Cst is relatively large. For example, the capacitance value of the storage capacitor Cst may range from 45fF to 55fF, the capacitance value of the boost capacitor Cboost may range from 5fF to 15fF, and the capacitance value of the first capacitor C1 and the second capacitor C2 may range from 1fF to 30fF.

[0059] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0060] In the following embodiments, the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0061] The following describes the film layer structure of the pixel driving circuit 211 a of the present application with reference to the structure of FIG. 2 .

[0062] Referring to Figure 3 , the display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer (not shown) disposed on the array drive layer 120, a light-emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following primarily describes the film layer structure within the display area AA.

[0063] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0064] In this embodiment, the base substrate 110 is used to support the various film layers provided thereon. The base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0065] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0066] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a supporting substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material. The second flexible substrate 113 is formed by the same method as the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby eliminating such defects.

[0067] Referring to FIG3 , the array drive layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, or other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein the thin film transistor in FIG3 does not represent the structural diagram of any transistor in FIG2 , but is only a schematic diagram of the various film layers of the display panel 100 of the present application.

[0068] 3 , the array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, and a second active layer 129 disposed on the third gate insulating layer 128. , a fourth gate insulating layer 130 arranged on the second active layer 129, a third gate layer 131 arranged on the fourth gate insulating layer 130, a first interlayer insulating layer 132 arranged on the third gate layer 131, a first source-drain layer 133 arranged on the first interlayer insulating layer 132, a second interlayer insulating layer 134 arranged on the first source-drain layer 133, a second source-drain layer 135 arranged on the second interlayer insulating layer 134, a third interlayer insulating layer 136 arranged on the second source-drain layer 135, a third source-drain layer 137 arranged on the third interlayer insulating layer 136, and a planarization layer 138 arranged on the third source-drain layer 137.

[0069] 3 , a light shielding layer 121 is provided on the second barrier layer 114 . The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The light shielding layer 121 may be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0070] Please refer to Figure 3. The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0071] Referring to Figure 3, the first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0072] Please refer to Figure 3. The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the material of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0073] Please refer to Figure 3. The first gate layer 125, the second gate layer 127 and the third gate layer 131 are respectively arranged on the corresponding insulating layers. The materials of the first gate layer 125, the second gate layer 127 and the third gate layer 131 can be copper, molybdenum or molybdenum-titanium alloy, etc. The material of the three gate layers of the present application can be molybdenum.

[0074] Please refer to Figure 3, the first source and drain layer 133 is arranged on the first interlayer insulating layer 132, the second source and drain layer 135 is arranged on the second interlayer insulating layer 134, and the third source and drain layer 137 is arranged on the third interlayer insulating layer 136. The materials of the first source and drain layer 133, the second source and drain layer 135, and the third source and drain layer 137 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal, etc. The material of the three-layer source and drain layer of the present application can be titanium-aluminum-titanium.

[0075] 3 , the planarization layer 138 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120 . The material of the planarization layer 138 can be an inorganic material composed of nitride oxide and silicon, or an organic material with flatness.

[0076] Referring to Figure 4, the first gate layer 125 includes a light-emitting signal line EM, a first reset signal line Vi1, a third reset signal line Vi3, and a fourth control signal line Pscan2. The light-emitting signal line EM, the first reset signal line Vi1, the third reset signal line Vi3, and the fourth control signal line Pscan2 all extend along the first direction X, and the third reset signal line Vi3, the fourth control signal line Pscan2, the light-emitting signal line EM, and the first reset signal line Vi1 are arranged at intervals along the second direction Y.

[0077] Please refer to Figure 4. The first gate layer 125 also includes a switch gate T2G and a fifth electrode plate Cst1 of the storage capacitor Cst, which are arranged between the light-emitting signal line EM and the first reset signal line Vi1. The switch gate T2G and the fifth electrode plate Cst1 are arranged at intervals in the second direction Y, and the fifth electrode plate Cst1 is arranged close to the light-emitting signal line EM, and the switch gate T2G is arranged away from the light-emitting signal line EM.

[0078] In this embodiment, the light emitting signal line EM can directly serve as the first light emitting gate T5G and the second light emitting gate T6G, and the fourth control signal line Pscan2 can directly serve as the second reset gate T7G and the third reset gate T8G.

[0079] Referring to FIG. 4 , the switch gate T2G and the fifth electrode plate Cst1 may be in the shape of a rectangle, and the four corners of the fifth electrode plate Cst1 may be chamfered.

[0080] 5 , the first active layer 123 includes a switch active portion T2A of the switch transistor T2, a drive active portion T1A of the drive transistor T1, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first light emitting active portion T5A of the first light emitting transistor T5, and a second light emitting active portion T6A of the second light emitting transistor T6.

[0081] Please refer to Figure 5. The switch active portion T2A, the driving active portion T1A, the second reset active portion T7A, the first light-emitting active portion T5A, and the second light-emitting active portion T6A are connected to each other, and the third reset active portion T8A is arranged separately from the other active portions. The switch active portion T2A, the second reset active portion T7A, the third reset active portion T8A, the first light-emitting active portion T5A, and the second light-emitting active portion T6A are all long strips and extend along the second direction Y. The driving active portion T1A is in a "X" shape and is arranged between the first light-emitting active portion T5A and the second light-emitting active portion T6A. The first end of the switch active portion T2A, the first end of the driving active portion T1A, and the first end of the first light-emitting active portion T5A are connected to the first connection point P1. The second end of the driving active portion T1A and the first end of the second light-emitting active portion T6A are connected to the second connection point P2. The first end of the second reset active portion T7A and the second end of the second light-emitting active portion T6A are connected to the third connection point P3.

[0082] In this embodiment, the first connection point P1 is the first internal node A, the second connection point P2 is the second internal node B, and the third connection point P3 is the location of the anode of the light emitting device 211 b.

[0083] Please refer to Figure 6. The light-emitting signal line EM and the first light-emitting active portion T5A partially overlap, and the overlapping portion is the channel of the first light-emitting active portion T5A; the light-emitting signal line EM and the second light-emitting active portion T6A partially overlap, and the overlapping portion is the channel of the second light-emitting active portion T6A; the switch gate T2G and the switch active portion T2A partially overlap, and the overlapping portion is the channel of the switch active portion T2A; the fourth control signal line Pscan2 and the second reset active portion T7A partially overlap, and the overlapping portion is the channel of the second reset active portion T7A; the fourth control signal line Pscan2 and the third reset active portion T8A partially overlap, and the overlapping portion is the channel of the third reset active portion T8A; the driving active portion T1A and the fifth electrode plate Cst1 partially overlap, and the overlapping portion is the channel of the driving active portion T1A. The fifth electrode plate Cst1 of the present application is multiplexed as the driving gate T1G of the driving transistor T1.

[0084] Please refer to Figures 7 and 8. The second gate layer 127 includes a sixth plate Cst2 of the storage capacitor Cst arranged along the second direction Y, a first shading unit T3S of the compensation transistor T3, and a second shading unit T4S of the first reset transistor T4. The sixth plate Cst2, the first shading unit T3S and the second shading unit T4S are located between the light-emitting signal line EM and the first reset signal line Vi1. The fifth plate Cst1 is arranged close to the light-emitting signal line EM, the second shading unit T4S is arranged close to the first reset signal line Vi1, and the first shading unit T3S is located between the second shading unit T4S and the sixth plate Cst2.

[0085] 7 and 8 , the area of ​​the sixth plate Cst2 is larger than that of the fifth plate Cst1 , and the orthographic projection of the fifth plate Cst1 on the sixth plate Cst2 is located within the sixth plate Cst2 . A first through hole HL0 is defined in the sixth plate Cst2 to expose a portion of the fifth plate Cst1 .

[0086] Referring to FIG. 8 , the first light shielding unit T3S, the second light shielding unit T4S, and the sixth electrode plate Cst2 may be rectangular in shape, and at least part of their top corners may be chamfered.

[0087] Referring to FIG. 8 , the second gate layer 127 further includes first electrical connection segments 311 disposed on both sides of the sixth electrode plate Cst2. The two first electrical connection segments 311 extend along the first direction X. In addition, in two adjacent sub-pixel units 211 disposed along the first direction X, the sixth electrodes Cst2 in the two sub-pixel units 211 are electrically connected via the first electrical connection segments 311. In this embodiment, the sixth electrode plate Cst2 is connected to the first high potential line VDD1. In order to reduce the impedance on the sixth electrode plate Cst2, the present application may connect the sixth electrodes Cst2 in the sub-pixel units 211 disposed along the first direction X to each other and to be disposed in parallel with the first high potential line VDD1 of the upper layer, thereby reducing the impedance of the first high potential line VDD1 and the sixth electrode plate Cst2.

[0088] Referring to Figures 9 and 11, the second active layer 129 includes a compensation active portion T3A of the compensation transistor T3 and a first reset active portion T4A of the first reset transistor T4. The compensation active portion T3A and the first reset active portion T4A both extend along the second direction Y. A first end of the compensation active portion T3A and a first end of the first reset active portion T4A are connected to a fourth connection point P4. A second end of the compensation active portion T3A extends toward the second connection point P2 and is separated from the second connection point P2. A second end of the first reset active portion T4A extends toward the first reset signal line Vi1 and overlaps with the first reset signal line Vi1.

[0089] In this embodiment, the fourth connection point P4 may be the third internal node Q.

[0090] 9 and 11 , the second active layer 129 further includes a first extension segment 321 connected to the fourth connection point P4 and a second extension segment 322 connected to the second end of the first reset active portion T4A. The first extension segment 321 extends along the second direction Y toward the location of the storage capacitor Cst, and is separated from the storage capacitor Cst. The second extension segment 322 extends along the first direction X, and at least partially overlaps with the first reset signal line Vi1.

[0091] Referring to Figures 10 and 11, the third gate layer 131 includes a compensation gate T3G and a first reset gate T4G of the first reset transistor T4. The area of ​​the compensation gate T3G is smaller than the area of ​​the first light-shielding unit T3S, and the orthographic projection of the compensation gate T3G on the first light-shielding unit T3S is located within the first light-shielding unit T3S. The area of ​​the first reset gate T4G is smaller than the area of ​​the second light-shielding unit T4S, and the orthographic projection of the first reset gate T4G on the second light-shielding unit T4S is located within the second light-shielding unit T4S.

[0092] 10 and 11 , the first reset gate T4G and the first reset active portion T4A partially overlap, and the overlapping portion is the channel of the first reset active portion T4A; the compensation gate T3G and the compensation active portion T3A partially overlap, and the overlapping portion is the channel of the compensation active portion T3A.

[0093] 10 and 11 , the first reset gate T4G and the compensation gate T3G may both be rectangular in shape, and part of the top corners of the first reset gate T4G and the compensation gate T3G may be chamfered.

[0094] 10 and 11 , the third gate layer 131 further includes a first conductive segment 331 connected to the compensation gate T3G and a second conductive segment 332 connected to the first reset gate T4G. The first conductive segment 331 extends along the second direction Y toward a side away from the compensation gate T3G, and the second conductive segment 332 extends along the second direction Y toward a side away from the first reset gate T4G.

[0095] Referring to Figures 7 and 11 , the second gate layer 127 further includes a third conductive segment 333 connected to the first light shielding unit T3S, and a fourth conductive segment 334 connected to the second light shielding unit T4S. The third conductive segment 333 extends along the second direction Y toward a side away from the compensation gate T3G. The line width of the first conductive segment 331 can be less than or equal to the line width of the third conductive segment 333, and the orthographic projection of the first conductive segment 331 on the third conductive segment 333 can be located within the third conductive segment 333. The fourth conductive segment 334 can first extend along the second direction Y toward a side away from the first reset gate T4G, and then extend along the first direction X toward a side away from the compensation transistor T3. The ends of the second conductive segment 332 and the fourth conductive segment 334 away from the first reset gate T4G can be co-located.

[0096] Please refer to Figure 12, the first source and drain layer 133 includes a second reset signal line Vi2, a fifth control signal line Nscan3, a second high potential line VDD2, a second control signal line Pscan1, a first control signal line Nscan1, and a third control signal line Nscan2 arranged along the second direction Y. The second reset signal line Vi2, the fifth control signal line Nscan3, the second high potential line VDD2, the second control signal line Pscan1, the first control signal line Nscan1, and the third control signal line Nscan2 can all extend along the first direction X.

[0097] Please refer to Figures 12 to 15, the second reset signal line Vi2 is arranged between the third reset signal line Vi3 and the first control signal line Nscan1, the fifth control signal line Nscan3 and the fourth control signal line Pscan2 partially overlap, the second high potential line VDD2 is arranged between the light-emitting signal line EM and the first electrical connection section 311, the second control signal line Pscan1, the first control signal line Nscan1 and the third control signal line Nscan2 are arranged between the first electrical connection section 311 and the first reset signal line Vi1, and the second control signal line Pscan1 is arranged close to the first electrical connection section 311, the third control signal line Nscan2 is arranged close to the first reset signal line Vi1, and the first control signal line Nscan1 is arranged between the second control signal line Pscan1 and the third control signal line Nscan2.

[0098] Referring to Figures 12 to 15, the first source-drain layer 133 also includes a second electrical connection segment 312 arranged between the second reset signal line Vi2 and the third reset signal line Vi3. The first end of the second electrical connection segment 312 is electrically connected to the third reset signal line Vi3 through the first via HL1, and the second end of the second electrical connection segment 312 is electrically connected to the first end of the third reset active portion T8A through the second via HL2. The third reset signal line Vi3 transmits the reference voltage to the third reset transistor T8 through the second electrical connection segment 312.

[0099] In this embodiment, the first via hole HL1 passes through the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interlayer insulation layer 132 , and the second via hole HL2 passes through the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interlayer insulation layer 132 .

[0100] In this embodiment, in order to avoid interference between the second electrical connection section 312 and the second reset signal line Vi2, the second reset signal line Vi2 is designed to be sunken at the position corresponding to the second electrical connection section 312, that is, the signal line in this area is offset to the side away from the third reset signal line Vi3; at the same time, in order to ensure the line distance between the fifth control signal line Nscan3 and the second reset signal line Vi2, the fifth control signal line Nscan3 is also designed to be sunken.

[0101] Referring to Figures 12 to 15, the first source and drain layer 133 also includes a third extension segment 323, a third electrical connection segment 313 and a fourth electrical connection segment 314 arranged between the second high potential line VDD2 and the fifth control signal line Nscan3. The third extension segment 323 and the third electrical connection segment 313 both extend along the second direction Y, and the fourth electrical connection segment 314 extends along the first direction X.

[0102] In this embodiment, a first end of the third extension section 323 is electrically connected to the second high potential line VDD2, a second end of the third extension section 323 extends toward a side away from the second high potential line VDD2, and the third extension section 323 overlaps with a portion of the first light emitting active portion T5A, and a second end of the third extension section 323 passes through the third via hole HL3 and is electrically connected to the second end of the first light emitting active portion T5A; a first end of the third electrical connection section 313 passes through the fourth via hole HL4 and is electrically connected to the second end of the third reset active portion T8A, and the first active layer 123 further includes a fourth extension section 313 connected to the first light emitting active portion T5A. 24, the fourth extension segment 324 extends along the first direction X, the second end of the third electrical connection segment 313 passes through the fifth via HL5 and is electrically connected to the fourth extension segment 324, and the third reset signal line Vi3 transmits the reference voltage to the first connection point P1 through the second electrical connection segment 312, the third electrical connection segment 313, and the fourth extension segment 324 to reset the potential of the first internal node A; one end of the fourth electrical connection segment 314 passes through a via and is electrically connected to the third connection point P3 in the first active layer 123, and the other end of the fourth electrical connection segment 314 passes through another via and is electrically connected to the conductive layer in the second source-drain layer 135.

[0103] In this embodiment, the third via hole HL3 passes through the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interlayer insulation layer 132, and the fourth via hole HL4 and the fifth via hole HL5 both pass through the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interlayer insulation layer 132.

[0104] 12 to 15 , the first source-drain layer 133 further includes a fifth electrical connection segment 315 and a sixth electrical connection segment 316 disposed between the second high potential line VDD2 and the second control signal line Pscan1 . Both the fifth electrical connection segment 315 and the sixth electrical connection segment 316 extend along the second direction Y.

[0105] In this embodiment, a first end of the fifth electrical connection segment 315 passes through the sixth via HL6 and is electrically connected to an end of the first extension segment 321 away from the second control signal line Pscan1. A second end of the fifth electrical connection segment 315 extends into the storage capacitor Cst and is electrically connected to the fifth plate Cst1 of the storage capacitor Cst through the seventh via HL7. In the structure of Figure 14, the seventh via HL7 passes through the first through hole HL0 on the sixth plate Cst2. The center of the first through hole HL0 and the center of the seventh through hole HL7 can be located on the same straight line perpendicular to the light emitting surface of the display panel 100. The fifth electrical connection segment 315 of the present application serves as an electrical connection component, one end of which passes through the sixth via HL6 and is electrically connected to the first extension segment 321, and the other end passes through the seventh via HL7 and is electrically connected to the fifth plate Cst1 of the storage capacitor Cst, that is, the conductive lines of the third internal node Q in the first gate layer 125 and the second active layer 129 are electrically connected through the metal of the first source-drain layer 133.

[0106] In this embodiment, a first end of the sixth electrical connection segment 316 passes through the eighth via hole HL8 and is electrically connected to the second connection point P2 in the first active layer 123 , and a second end of the sixth electrical connection segment 316 passes through the ninth via hole HL9 and is electrically connected to the second end in the compensation active portion T3A.

[0107] In this embodiment, the sixth via hole HL6 and the ninth via hole HL9 penetrate the fourth gate insulation layer 130 and the first interinsulation layer 132 , and the seventh via hole HL7 and the eighth via hole HL8 penetrate the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first interinsulation layer 132 .

[0108] Referring to Figures 12 to 15, the first source-drain layer 133 further includes a fifth extension segment 325, one end of the fifth extension segment 325 being electrically connected to the first control signal line Nscan1, and the fifth extension segment 325 extending along the second direction Y and toward a side away from the first control signal line Nscan1; the end of the fifth extension segment 325 away from the first control signal line Nscan1 passes through the tenth via HL10 and is electrically connected to the first conductive segment 331, and the first control signal line Nscan1 transmits the control signal to the compensation gate T3G of the compensation transistor T3 through the fifth extension segment 325 and the first conductive segment 331; at the same time, the end of the second conductive segment 332 away from the first reset gate T4G overlaps with the third control signal line Nscan2, and is electrically connected to the third control signal line Nscan2 through the eleventh via HL11, and the third control signal line Nscan2 transmits the control signal to the first reset gate T4G of the first reset transistor T4 through the second conductive segment 332.

[0109] In this embodiment, both the tenth via hole HL10 and the eleventh via hole HL11 pass through the first interlayer insulating layer 132 .

[0110] Please refer to Figures 12 to 15. The third conductive segment 333 overlaps with the first conductive segment 331 and the third conductive segment 333, and the third conductive segment 333 passes through the twelfth via HL12 and is electrically connected to the first control signal line Nscan1. The first control signal line Nscan1 transmits the control signal to the first light shielding unit T3S through the third conductive segment 333. That is, the first light shielding unit T3S can be reused as the bottom gate of the compensation transistor T3, and the compensation gate T3G is the top gate of the compensation transistor T3. The arrangement of the first light shielding unit T3S and the compensation gate T3G can increase the conduction rate of the compensation transistor T3 and improve the compensating transistor T3. Device effect; the fourth conductive segment 334 overlaps with a portion of the third control signal line Nscan2, and is electrically connected to the third control signal line Nscan2 through the thirteenth through-hole HL13. The third control signal line Nscan2 transmits the control signal to the second shading unit T4S through the fourth conductive segment 334, that is, the second shading unit T4S can be reused as the bottom gate of the first reset transistor T4, and the first reset gate T4G is the top gate of the first reset transistor T4. The setting of the second shading unit T4S and the first reset gate T4G can increase the conduction rate of the first reset transistor T4 and improve the device effect of the first reset transistor T4.

[0111] In this embodiment, the twelfth via hole HL12 and the thirteenth via hole HL13 both penetrate the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first interlayer insulating layer 132 .

[0112] It should be noted that the third conductive segment 333 may be insulated from the first control signal line Nscan1 , and the fourth conductive segment 334 may be insulated from the third control signal line Nscan2 .

[0113] 12 to 15 , the fifth control signal line Nscan3 can pass through the fourteenth via HL14 and be connected in parallel with the fourth control signal line Pscan2 , that is, the fifth control signal and the fourth control signal line Pscan2 are set in parallel, thereby reducing the impedance of the fifth control signal line Nscan3 and the fourth control signal line Pscan2 .

[0114] In this embodiment, the fourteenth via hole HL14 passes through the second gate insulating layer 126 , the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first interlayer insulating layer 132 .

[0115] Please refer to Figures 12 to 15. The first control signal line Nscan1 partially overlaps with the first reset active portion T4A, the second control signal line Pscan1 partially overlaps with the first extension segment 321, and the second control signal line Pscan1 partially overlaps with the compensation active portion T3A. The third control signal line Nscan2 partially overlaps with the first reset active portion T4A. The four overlapping areas are all overlapped by the material of the second active layer 129 and the material of the first source and drain layer 133. The fourth gate insulating layer 130 and the first interlayer insulating layer 132 are interposed between the first source and drain layer 133 and the second active layer 129, and the material of the third gate layer 131 is not provided in between, thereby avoiding the technical problem that the third gate layer 131 is easily short-circuited with the first source and drain layer 133.

[0116] Please refer to Figures 12 to 15. The overlapping portion of the second control signal line Pscan1 and the first extension section 321 is the boost capacitor Cboost of the present application. The seventh plate of the boost capacitor Cboost can be the portion of the first extension section 321 that overlaps with the second control signal line Pscan1. The eighth plate of the boost capacitor Cboost can be the portion of the second control signal line Pscan1 that overlaps with the first extension section 321.

[0117] Please refer to Figures 12 to 15. The first source and drain layer 133 also includes a seventh electrical connection segment 317 arranged between the second reset signal line Vi2 and the third control signal line Nscan2. The seventh electrical connection segment 317 extends along the second direction Y and toward a side away from the second reset signal line Vi2. The seventh electrical connection segment 317 and the second extension segment 322 are arranged in an overlapping manner, which is equivalent to forming a capacitor between the first reset signal line Vi1 and the second reset signal line Vi2, thereby ensuring the stability of the voltage on the first reset signal line Vi1 and the second reset signal line Vi2.

[0118] In this embodiment, the fifth electrical connection section 315 and the first extension section 321 are both wires in the area where the third internal node of the present application is located, that is, the potential on the fifth electrical connection section 315 and the first extension section 321 is the potential of the third internal node Q; at the same time, the second control signal line Pscan1 and the first extension section 321 are overlapped in the first area M1, that is, the first extension section 321 of the present application is in the second active layer 129, and the second control signal line Pscan1 is in the first source and drain layer 133. Part of the wires in the area where the third internal node Q is located are replaced from the original third gate layer 131 to the second active layer 129 of the present application, thereby avoiding the technical problem of cracks in the upper insulating layer, and at the same time avoiding the technical problem of the horizontally arranged second control signal line Pscan1 being short-circuited with the lower wire in the first area M1.

[0119] At the same time, the first control signal line Nscan1 and the compensation active portion T3A are overlapped in the second region M2, the second control signal line Pscan1 and the first reset active portion T4A are overlapped in the third region M3, and the third control signal line Nscan2 and the first reset active portion T4A are overlapped in the fourth region M4; that is, the compensation active portion T3A and the first reset active portion T4A of the present application are both in the second active layer 129, the first control signal line Nscan1 and the third control signal line Nscan2 are both in the first source and drain layer 133, so that the first control signal line Nscan1 n1, the second control signal line Pscan1 and the third control signal line Nscan2 are replaced from the gate layer with larger impedance to the first source and drain layer 133 with smaller impedance, for example, the original metal molybdenum is replaced with the titanium aluminum titanium of the present application, thereby reducing the impedance of the three control signal lines; secondly, since there is a risk of short circuit due to the overlap of the first source and drain layer 133 and the third gate layer 131, the present application replaces the wires in the area where the third internal node Q is located from the third gate layer 131 to the second active layer 129 to avoid short circuit between the wires in the area where the third internal node Q is located and the first source and drain layer 133.

[0120] Referring to Figure 16, the second source-drain layer 135 includes a first data signal line Data1, a second data signal line Data2, and a first high potential line VDD1. The second data signal line Data2, the first data signal line Data1, and the first high potential line VDD1 are arranged along a first direction X and extend along a second direction Y. The first data signal line Data1 is disposed between the second data signal line Data2 and the first high potential line VDD1.

[0121] Please refer to Figures 17 to 19. The first source and drain layer 133 includes an eighth electrical connection segment 318 arranged between the first control signal line Nscan1 and the second control signal line Pscan1. One end of the eighth electrical connection segment 318 is electrically connected to the second end of the switch active portion T2A, and the other end of the eighth electrical connection segment 318 is electrically connected to the first data signal line Data1. The first data signal line Data1 transmits the data signal to the switching transistor T2 through the eighth electrical connection segment 318.

[0122] In the structure of Figure 19, this application lists 6 sub-pixel units 211. The sub-pixel units 211 located in the first row are all connected to the first data signal line Data1, and the sub-pixel units 211 located in the second row are all connected to the second data signal line Data2. The sub-pixel units 211 listed in Figures 17 and 18 of this application are the sub-pixel units 211 in the first row in Figure 19.

[0123] In this embodiment, the structure of each pixel driving circuit 211a of the present application is the same, that is, the input end of the switch active portion T2A equivalent to the switch transistor T2 is arranged on the same side. If the first data signal line Data1 and the second data signal line Data2 are arranged on both sides of the pixel driving circuit 211a, for example, when the first data signal line Data1 is arranged on the left side of the pixel driving circuit 211a and the second data signal line Data2 is arranged on the right side of the pixel driving circuit 211a, then the input end of the switch active portion T2A of the sub-pixel unit 211 of the first row is adjacent to the first data signal line Data1, and the input end of the switch active portion T2A of the sub-pixel unit 211 of the second row is adjacent to the second data signal line Data1. The spacing of Data2 is the width of a sub-pixel unit 211, that is, a connecting line across the sub-pixel unit 211 is required to electrically connect the second data signal line Data2 and the switch active part T2A of the sub-pixel unit 211 of the second row. The connecting line overlaps with multiple structures in the pixel driving circuit 211a, and the coupling capacitance increases, resulting in poor stability of the pixel driving circuit 211a; for example, in the structure of Figure 19, the present application reduces the connection distance between the data signal line and the switch active part T2A in the sub-pixel unit 211 by setting the two data signal lines on the same side of the pixel driving circuit 211a, reduces the coupling capacitance inside the pixel driving circuit 211a, and improves the stability of the pixel driving circuit 211a.

[0124] 16 to 18 , the first high potential line VDD1 includes a first sub-plate 341, a second sub-plate 342, a third sub-plate 343, a fourth sub-plate 344, and a fifth sub-plate 345. The third sub-plate 343, the first sub-plate 341, the fourth sub-plate 344, the second sub-plate 342, and the fifth sub-plate 345 are arranged along the second direction Y. The first sub-plate 341 is arranged between the third sub-plate 343 and the fourth sub-plate 344, and the second sub-plate 342 is arranged between the fourth sub-plate 344 and the fifth sub-plate 345. In the first direction X, the width of the first sub-plate 341 is smaller than the width of the second sub-plate 342, the width of the first sub-plate 341 may be greater than the width of the fourth sub-plate 344, and the width of the fourth sub-plate 344 may be greater than or equal to the widths of the third sub-plate 343 and the fifth sub-plate 345.

[0125] In this embodiment, since the potential of the driving gate T1G is the potential of the third internal node Q, the potential change of the third internal node Q directly affects the operating current of the light-emitting device 211b, so this application needs to ensure the stability of the potential of the third internal node Q; this application can make the positive projection of the driving gate T1G on the first high potential line VDD1 located within the first sub-plate 341, which is equivalent to using the first sub-plate 341 as a shielding layer to maintain the stability of the potential of the third internal node Q, so this application needs to increase the lateral width of the first sub-plate 341 so that the first sub-plate 341 fully covers the driving gate T1G, and the fifth plate Cst1 of the storage capacitor Cst is reused as the driving gate T1G, that is, the positive projection of the fifth plate Cst1 on the first high potential line VDD1 can be located within the first sub-plate 341, so the width of the first sub-plate 341 of this application can be greater than the widths of the third sub-plate 343, the fourth sub-plate 344 and the fifth sub-plate 345.

[0126] In this embodiment, the fifth electrical connection section 315 and the first extension section 321 are both electrically connected to the driving gate T1G, so changes in the potential on the fifth electrical connection section 315 and the first extension section 321 will also affect the potential of the driving gate T1G. Therefore, the present application can increase the width of the fourth sub-plate 344 to fully cover the fifth electrical connection section 315 and the first extension section 321. Therefore, the lateral width of the fourth sub-plate 344 of the present application can be greater than the lateral width of the third sub-plate 343 and the fifth sub-plate 345.

[0127] Please refer to Figures 16 and 17. The positive projection of the compensation gate T3G on the first high potential line VDD1 is located in the second sub-board 342. Part of the first high potential line VDD1 overlaps with the compensation gate T3G and part of the first control signal line Nscan1. The two can form a capacitor, thereby improving the anti-coupling capability of the first control signal line Nscan1, thereby improving the stability of the control signal transmitted by the first control signal line Nscan1, avoiding abnormal start-up of the compensation transistor T3, and ensuring the stability of the potential of the gate of the driving transistor T1.

[0128] 20 and 22 , the third source-drain layer 137 may include a third high potential line VDD3 extending along the second direction Y, the third high potential line VDD3 being electrically connected to the second high potential line VDD2, and the third high potential line VDD3 being provided mainly to reduce the impedance of the conductor transmitting a constant voltage high level.

[0129] It should be noted that in Figures 16 to 20, the first high potential line VDD1 of the present application can be electrically connected to the second high potential line VDD2, and then the second high potential line VDD2 is electrically connected to the sixth plate Cst2 of the storage capacitor Cst, and the sixth plate Cst2 located in the same row is electrically connected through the first electrical connection section 311; therefore, the wire for transmitting a constant voltage high level in the present application has four layers of metal, namely, the sixth plate Cst2 and the first electrical connection section 311 located in the second gate layer 127, the second high potential line VDD2 located in the first source and drain layer 133, and the sixth plate Cst2 located in the same row. The bit line VDD2, the first high potential line VDD1 located in the second source and drain layer 135, the third high potential line VDD3 located in the third source and drain layer 137, the sixth electrode plate Cst2, the first electrical connection section 311, and the second high potential line VDD2 all extend along the first direction X, and the first high potential line VDD1 and the third high potential line VDD3 all extend along the second direction Y. Therefore, the present application uses four layers of metal to transmit a constant voltage high level to form a metal mesh that is crisscrossed horizontally and vertically in a mesh shape to reduce the impedance of the wire, thereby reducing the loss of the constant voltage high level on the transmitted wire.

[0130] Please refer to Figure 23. The third source-drain layer 137 of the present application includes a plurality of repeating units 137a. Each repeating unit 137a corresponds to three adjacent sub-pixel units 211 arranged along the first direction X. For example, the three sub-pixel units 211 are respectively the first sub-pixel unit 212, the second sub-pixel unit 213 and the third sub-pixel unit 214. For example, each repeating unit 137a may include a first sub-high potential line VDD31 corresponding to the first sub-pixel unit 212, a second sub-high potential line VDD32 and a fourth reset signal line Vi4 corresponding to the second sub-pixel unit 214, and a third sub-high potential line VDD33 corresponding to the third sub-pixel unit 214. The patterns of the first sub-high potential line VDD31 and the third sub-high potential line VDD33 may be the same, the patterns of the third sub-high potential line VDD32 and the first sub-high potential line VDD31 may be different, and the maximum lateral width of the second sub-high potential line VDD32 is smaller than the maximum lateral width of the first sub-high potential line VDD31.

[0131] It should be noted that, in the present application, the first sub-high potential line VDD31 , the second sub-high potential line VDD32 and the third sub-high potential line VDD33 are all third high potential lines VDD3 .

[0132] It should be noted that the first sub-high potential line VDD31, the second sub-high potential line VDD32, the third sub-high potential line VDD33 and other high potential lines, as well as other data signal lines such as the first data signal line Data1 and the second data signal line Data2 are all arranged along the first direction X and extend along the second direction Y.

[0133] Please refer to Figure 23. Each repeating unit 137a is provided with a longitudinal reset signal line and three transverse reset signal lines, that is, each repeating unit 137a can also include a fourth reset signal line Vi4 located in the second sub-pixel unit 213. The fourth reset signal line Vi4 in each repeating unit 137a is electrically connected to one of the first reset signal line Vi1, the second reset signal line Vi2 and the third reset signal line Vi3, and the reset signal lines connected to the fourth reset signal line Vi4 in three adjacent repeating units 137a are different.

[0134] In order to reduce the impedance of the reset signal line, the present application provides that the vertically arranged reset signal line can be electrically connected to one of the three horizontal reset signal lines; for example, three rows of repeating units 137a are provided in FIG24 , and each row of repeating units 137a includes three repeating units 137a, and each repeating unit 137a is provided with a fourth reset signal line Vi4, the fourth reset signal line Vi4 in the first repeating unit 137a can be electrically connected to the first reset signal line Vi1 of each row, the fourth reset signal line Vi4 in the second repeating unit 137a can be electrically connected to the second reset signal line Vi2 of each row, and the fourth reset signal line Vi4 in the third repeating unit 137a can be electrically connected to the third reset signal line Vi3 of each row, thereby electrically connecting each horizontally arranged reset signal line to the fourth reset signal line Vi4 to form a metal mesh that is crisscrossed horizontally and vertically, thereby reducing the impedance of the reset signal line.

[0135] 25 and 26 , the display panel 100 further includes a first anode 211 b 1 corresponding to the first sub-pixel unit 212 and a second anode 211 b 2 corresponding to the second sub-pixel unit 213 . The first anode 211 b 1 and the second anode 211 b 2 are arranged in the second direction.

[0136] It should be noted that the first sub-pixel unit 212, the second sub-pixel unit 213 and the third sub-pixel unit 214 in Figures 25 and 26 only represent the position of the pixel driving circuit 211a of the corresponding sub-pixel unit 211, and the position of the anode in the sub-pixel unit 211 may not be in the corresponding area. For example, the first anode 211b1 and the second anode 211b2 of the present application both span the first sub-pixel unit 212 and the second sub-pixel unit 213.

[0137] It should be noted that the third source-drain layer 137 may further include a ninth electrical connection segment 319 arranged between the fourth reset signal line Vi4 and the second sub-high potential line VDD32, and the second anode 211b2 may be electrically connected to the pixel driving circuit 211a in the second sub-pixel unit 213 through the ninth electrical connection segment 319.

[0138] In this embodiment, the display panel 100 may include an electrical connection portion 40 connected to the high potential line VDD and extending along the first direction X. The electrical connection portion 40 has an overlapping portion with the data signal line Data and the electrical connection portion 40 has an overlapping portion with the anode of the light emitting device.

[0139] For example, in Figures 25 and 26, the electrical connection part 40 includes a first electrical connection component 410, one end of the first electrical connection component 410 is electrically connected to the first sub-high potential line VDD31, and the other end of the first electrical connection component 410 is electrically connected to the second sub-high potential line VDD32, and the anode is overlapped with the first electrical connection component 410, part of the first sub-high potential line VDD31 and part of the second sub-high potential line VDD32, that is, the first electrical connection component 410, part of the first sub-high potential line VDD31 and part of the second sub-high potential line VDD32 are equivalent to the second plate of the first capacitor C1, and the anode is equivalent to the first plate of the first capacitor C1; at the same time, the first electrical connection component 410 is overlapped with the first data signal line Data1 and the second data signal line Data2, that is, the first electrical connection component 410 is equivalent to the fourth plate of the second capacitor C2, and part of the first data signal line Data1 and part of the second data signal line Data2 are equivalent to the third plate of the second capacitor C2.

[0140] Please refer to Figures 27 and 28. The electrical connection part 40 may further include a second electrical connection component 420, one end of which is electrically connected to one of the first sub-high potential line VDD31 or the second sub-high potential line VDD32, and the second electrical connection component 420 is separated from the other of the first sub-high potential line VDD31 or the second sub-high potential line VDD32; the second electrical connection component 420 has an overlapping portion with the data signal line of the high potential line electrically connected to the second electrical connection component 420.

[0141] For example, in the structures of Figures 27 and 28, the second electrical connection member 420 is electrically connected to the second sub-high potential line VDD32, the second electrical connection member 420 and the first sub-high potential line VDD31 are separated, and the second electrical connection member 420 is only overlapped with the first data signal line Data1; in other embodiments, the second electrical connection member 420 can be electrically connected only to the first sub-high potential line VDD31, separated from the second sub-high potential line VDD32, and the second electrical connection member 420 is only overlapped with the second data signal line Data2.

[0142] Please refer to Figures 26 and 28. Since the luminous efficiency of sub-pixels of different colors is different, in order to ensure that the luminous life of sub-pixels of different colors is consistent, the present application can differentiate the luminous areas of sub-pixels of different colors. For example, the area of ​​the first anode 211b1 can be smaller than the area of ​​the second anode 211b2, that is, the luminous area of ​​the first sub-pixel unit 212 can be smaller than the luminous area of ​​the second sub-pixel unit 213. The first sub-pixel unit 212 can be a red sub-pixel unit or a green sub-pixel unit, and the second sub-pixel unit 213 can be a blue sub-pixel unit.

[0143] In this embodiment, since the area of ​​the first anode 211b1 can be smaller than the area of ​​the second anode 211b2, the overlapping area between the second anode 211b2 and the first data signal line Data1 or / and the second data signal line Data2 is larger than the overlapping area between the first anode 211b1 and the first data signal line Data1 or / and the second data signal line Data2. Therefore, the coupling capacitance between the second anode 211b2 and the data signal line is the same as the coupling capacitance between the first anode 211b1 and the data signal line. Therefore, the present application can make the overlapping area between the second electrical connection member 420 and the first data signal line Data1 larger than the overlapping area between the first electrical connection member 410 and the first data signal line Data1, so that the shielding area of ​​the second electrical connection member 420 for the second anode 211b2 is larger than the shielding area of ​​the first electrical connection member 410 for the first anode 211b1, thereby making the coupling capacitance between the second anode 211b2 and the first data signal line Data1 close to the coupling capacitance between the first anode 211b1 and the first data signal line Data1.

[0144] It should be noted that the coupling capacitances between different data signal lines and the anodes are different, so it is not necessary to make the overlapping areas between the electrical connection portion 40 and the different data signal lines equal.

[0145] It should be noted that since the second anode 211b2 and the first anode 211b1 in the second sub-pixel unit 213 are arranged along the second direction Y, no anode is set between the second sub-high potential line VDD32 and the third sub-high potential line VDD33, that is, the two data signal lines between the second sub-high potential line VDD32 and the third sub-high potential line VDD33 do not overlap with the anode, that is, there is no coupling capacitance between the data signal line and the anode in this area, and therefore there is no need to set an electrical connection part 40 between the second sub-high potential line VDD32 and the third sub-high potential line VDD33.

[0146] The present application also provides a display device, comprising the above-mentioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0147] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0148] The above is a detailed introduction to the technical solutions provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, wherein: The invention comprises a plurality of sub-pixel units and a plurality of data signal lines, wherein the data signal lines are provided between two adjacent sub-pixel units, the sub-pixel units include light-emitting devices and a pixel driving circuit connected to the light-emitting devices, and the pixel driving circuit includes: a driving unit connected to the data signal line at a first control node, connected to the high potential line at a second control node, and connected to the light emitting device at a third control node; and a first capacitor, wherein a first plate of the first capacitor is connected to the third control node, and a second plate of the first capacitor is connected to the high potential line; A second capacitor, wherein a first plate of the second capacitor is connected to the data signal line, and a second plate of the second capacitor is connected to the high potential line.

2. The display panel according to claim 1, wherein The high potential line and the data signal line are arranged along a first direction and extend along a second direction; The display panel includes an electrical connection portion connected to the high potential line and extending along the first direction, the electrical connection portion has an overlapping portion with the data signal line, and the electrical connection portion has an overlapping portion with the anode of the light emitting device.

3. The display panel according to claim 2, wherein: The plurality of sub-pixel units include a first sub-pixel unit and a second sub-pixel unit, wherein the first sub-pixel unit and the second sub-pixel unit are adjacently arranged and arranged along the first direction; The plurality of data signal lines include a first data signal line and a second data signal line disposed between the first sub-pixel unit and the second sub-pixel unit, and the electrical connection portion has an overlapping portion with at least one of the first data signal line and the second data signal line.

4. The display panel according to claim 3, wherein: The high potential line includes a first sub-high potential line corresponding to the first sub-pixel unit and a second sub-high potential line corresponding to the second sub-pixel unit; The electrical connection portion includes a first electrical connection member, one end of the first electrical connection member is electrically connected to the first sub-high potential line, and the other end of the first electrical connection member is electrically connected to the second sub-high potential line.

5. The display panel according to claim 4, wherein: The electrical connection portion includes a second electrical connection member, one end of the second electrical connection member is electrically connected to one of the first sub-high potential line or the second sub-high potential line, and the second electrical connection member is provided separately from the other of the first sub-high potential line or the second sub-high potential line; The second electrical connection member has an overlapping portion with a data signal line close to a high potential line electrically connected to the second electrical connection member. The display panel according to claim 5 , wherein: The area of the anode of the first sub-pixel unit is smaller than the area of the anode of the second sub-pixel unit; One end of the second electrical connection member is electrically connected to one of the second sub-high potential lines, the second electrical connection member is separated from the first sub-high potential line, and the second electrical connection member has an overlapping portion with the first data signal line.

7. The display panel according to claim 6, wherein: The first electrical connection member and the first data signal line have an overlapping portion, and an overlapping area between the second electrical connection member and the first data signal line is larger than an overlapping area between the first electrical connection member and the first data signal line.

8. The display panel according to claim 4, wherein: A pattern of the first sub-high potential line is different from a pattern of the second sub-high potential line, and a maximum width of the first sub-high potential line is greater than a maximum width of the second sub-high potential line.

9. The display panel according to claim 8, wherein: The plurality of sub-pixel units further include a third sub-pixel unit disposed adjacent to the second sub-pixel unit, and the display panel further includes a third sub-high potential line corresponding to the third sub-pixel unit; The pattern of the third sub-high potential line is the same as the pattern of the first sub-high potential line.

10. The display panel according to any one of claims 1 to 9, wherein: The driving unit includes: a switch transistor, wherein a first electrode of the switch transistor is connected to the data signal line, a second electrode of the switch transistor is connected to a first internal node, and a switch gate of the switch transistor is connected to a second control signal line; a driving transistor, wherein a first electrode of the driving transistor is connected to the first internal node, a second electrode of the driving transistor is connected to the second internal node, and a driving gate of the driving transistor is connected to a third internal node; a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third internal node, a second electrode of the compensation transistor is connected to the second internal node, and a compensation gate of the compensation transistor is connected to the first control signal line; a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to the third internal node, and a first reset gate of the first reset transistor is connected to a third control signal line; a second reset transistor, wherein a first electrode of the second reset transistor is connected to a second reset signal line, a second electrode of the second reset transistor is connected to the third control node, and a second reset gate of the second reset transistor is connected to a fourth control signal line; a third reset transistor, wherein a first electrode of the third reset transistor is connected to a third reset signal line, a second electrode of the third reset transistor is connected to the first internal node, and a third reset gate of the third reset transistor is connected to the fourth control signal line; a first light emitting transistor, wherein a first electrode of the first light emitting transistor is connected to the first high potential line, a second electrode of the first light emitting transistor is connected to the first internal node, and a first light emitting gate of the first light emitting transistor is connected to a light emitting signal line; a second light emitting transistor, wherein a first electrode of the second light emitting transistor is connected to the second internal node, a second electrode of the second light emitting transistor is connected to the third control node, and a second light emitting gate of the second light emitting transistor is connected to the light emitting signal line; a storage capacitor, the storage capacitor comprising a fifth plate and a sixth plate, the fifth plate being connected to the third internal node, and the sixth plate being connected to the high potential line; A boost capacitor includes a seventh plate and an eighth plate, the seventh plate is connected to the third internal node, and the eighth plate is connected to the second control signal line.

11. The display panel according to claim 10, wherein: The first gate layer of the display panel includes the light-emitting signal line, the first reset signal line, the third reset signal line, and the fourth control signal line. The light-emitting signal line, the first reset signal line, the third reset signal line, and the fourth control signal line all extend along the first direction, and the third reset signal line, the fourth control signal line, the light-emitting signal line, and the first reset signal line are arranged at intervals along the second direction.

12. The display panel according to claim 11, wherein: The first gate layer also includes a switch gate arranged between the light-emitting signal line and the first reset signal line and a fifth plate of the storage capacitor. The switch gate and the fifth plate are arranged at intervals in the second direction, and the fifth plate is arranged close to the light-emitting signal line, and the switch gate is arranged away from the light-emitting signal line.

13. The display panel according to claim 12, wherein: The first active layer of the display panel includes a switch active portion of the switch transistor, a drive active portion of the drive transistor, a second reset active portion of the second reset transistor, a third reset active portion of the third reset transistor, a first light emitting active portion of the first light emitting transistor, and a second light emitting active portion of the second light emitting transistor; The switch active portion, the driving active portion, the second reset active portion, the first light-emitting active portion, and the second light-emitting active portion are connected to each other, the switch active portion, the second reset active portion, the third reset active portion, the first light-emitting active portion, and the second light-emitting active portion all extend along the second direction, and the driving active portion is arranged between the first light-emitting active portion and the second light-emitting active portion.

14. The display panel according to claim 13, wherein: The second gate layer of the display panel includes a sixth plate of the storage capacitor arranged along the second direction, a first shading unit of the compensation transistor, and a second shading unit of the first reset transistor. The sixth plate, the first shading unit and the second shading unit are located between the light-emitting signal line and the first reset signal line. The fifth plate is arranged close to the light-emitting signal line, the second shading unit is arranged close to the first reset signal line, and the first shading unit is located between the second shading unit and the sixth plate.

15. The display panel according to claim 14, wherein: The area of the sixth electrode plate is greater than that of the fifth electrode plate, and the orthographic projection of the fifth electrode plate on the film layer where the sixth electrode plate is located is located inside the sixth electrode plate.

16. The display panel according to claim 15, wherein: The second active layer of the display panel includes a compensation active portion of the compensation transistor and a first reset active portion of the first reset transistor, the compensation active portion and the first reset active portion both extend along the second direction, a first end of the compensation active portion is connected to a first end of the first reset active portion, and a second end of the first reset active portion extends toward the first reset signal line and overlaps with the first reset signal line.

17. The display panel according to claim 16, wherein: The third gate layer of the display panel includes the compensation gate and the first reset gate of the first reset transistor; In which, the area of the compensation gate is smaller than the area of the first shading unit, and the orthographic projection of the compensation gate on the film layer where the first shading unit is located is located within the first shading unit. The area of the first reset gate is smaller than the area of the second shading unit, and the orthographic projection of the first reset gate on the film layer where the second shading unit is located is located within the second shading unit.

18. The display panel according to claim 17, wherein: The first source and drain layer of the display panel includes the second reset signal line, the second control signal line, the first control signal line, and the third control signal line arranged along the second direction, and the second reset signal line, the second control signal line, the first control signal line, and the third control signal line all extend along the first direction.

19. The display panel according to claim 18, wherein: The display panel further includes a second source-drain electrode layer and a third source-drain electrode layer located on a side of the first source-drain electrode layer away from the third gate layer; Among them, the high potential line includes a first high potential line, a second high potential line and a third high potential line that are electrically connected. The first high potential line is located in the second source and drain layer, the second high potential line is located in the first source and drain layer, and the electrical connection part and the third high potential line are both located in the third source and drain layer.

20. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 19.

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