Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base, and at least one transistor located on one side of the base, wherein the at least one transistor comprises an active layer (116) and a gate electrode; the active layer (116) comprises a first region (116-1), a second region (116-2), and a compensation region (120) located between the first region (116-1) and the second region (116-2); and the orthographic projection of the compensation region (120) on a plane where the base is located does not overlap with the orthographic projection of the gate electrode on the plane where the base is located. The display substrate further comprises a compensation structure (118), wherein the orthographic projection of the compensation structure (118) on the plane where the base is located at least partially overlaps with the orthographic projection of the compensation region (120) on the plane where the base is located, and the compensation structure (118) is connected to the gate electrode.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 7, 2024, with application number 202410175735.1 and invention name “A display substrate and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising a substrate and at least one transistor located on one side of the substrate, wherein the at least one transistor includes an active layer and a gate electrode, the active layer includes a first region, a second region, and a compensation region located between the first region and the second region; the orthographic projection of the compensation region on the plane where the substrate is located does not overlap with the orthographic projection of the gate electrode on the plane where the substrate is located; the display substrate also includes a compensation structure, the orthographic projection of the compensation structure on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation region on the plane where the substrate is located, and the compensation structure is connected to the gate electrode.

[0007] In some exemplary embodiments, the compensation structure includes at least one of a first compensation portion and a second compensation portion, and the orthographic projection of the first compensation portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation area on the plane where the substrate is located, and the orthographic projection of the second compensation portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation area on the plane where the substrate is located.

[0008] In some exemplary embodiments, an orthographic projection of the first compensation portion on the plane where the substrate is located is located between the first region and an orthographic projection of the gate electrode on the plane where the substrate is located.

[0009] In some exemplary embodiments, the compensation structure further includes a connecting portion, the orthographic projection of the connecting portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the gate electrode on the plane where the substrate is located, the connecting portion is connected to the gate electrode, and the first compensation portion is connected to the connecting portion.

[0010] In some exemplary embodiments, the first compensation portion and the connecting portion are an integral structure connected to each other.

[0011] In some exemplary embodiments, an orthographic projection of the second compensation portion on the plane where the substrate is located is located between the second region and an orthographic projection of the gate electrode on the plane where the substrate is located.

[0012] In some exemplary embodiments, the compensation structure further includes a connecting portion, the orthographic projection of the connecting portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the gate electrode on the plane where the substrate is located, the connecting portion is connected to the gate electrode, and the second compensation portion is connected to the connecting portion.

[0013] In some exemplary embodiments, the second compensation portion and the connecting portion are an integral structure connected to each other.

[0014] In some exemplary embodiments, the first compensation portion and the second compensation portion are interconnected integral structures, and an orthographic projection of the compensation structure on the plane where the substrate is located at least partially overlaps with an orthographic projection of the gate electrode on the plane where the substrate is located.

[0015] In some exemplary embodiments, in a plane perpendicular to the substrate, the display substrate further includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer sequentially located on one side of the substrate; the active layer is located in the semiconductor layer, and the gate electrode and the compensation structure are located in different conductive layers.

[0016] In some exemplary embodiments, the gate electrode is located in the second conductive layer, and the compensation structure is located in the third conductive layer.

[0017] In some exemplary embodiments, the at least one transistor further includes a bottom gate electrode, the bottom gate electrode being located in the first conductive layer, and the orthographic projection of the bottom gate electrode on the plane where the substrate is located at least partially overlaps with the orthographic projection of the active layer on the plane where the substrate is located.

[0018] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate described in any of the aforementioned embodiments.

[0019] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0020] Summary of the Figures

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0022] FIG1 is a schematic structural diagram of a display device;

[0023] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0024] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0025] FIG4 is a partial top view of a display substrate according to an embodiment of the present disclosure;

[0026] FIG4A is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0027] FIG5 is a schematic diagram showing a substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0028] 6A and 6B are schematic diagrams showing a substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0029] 7A and 7B are schematic diagrams showing a substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0030] FIG8 is a schematic diagram showing a substrate after a third insulating layer pattern is formed according to an embodiment of the present disclosure;

[0031] 9A and 9B are schematic diagrams showing a substrate after a third conductive layer pattern is formed according to an embodiment of the present disclosure;

[0032] FIG10 is a partial top view of a display substrate according to another embodiment of the present disclosure;

[0033] FIG10A is a schematic partial cross-sectional view of a display substrate according to another embodiment of the present disclosure.

[0034] Details

[0035] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0036] In the drawings, the size of one or more components, layer thicknesses, or regions are exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0037] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0038] In this disclosure, the use of words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," to illustrate the positional relationships of constituent elements with reference to the accompanying drawings is intended solely for the convenience of describing this specification and to simplify the description. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this disclosure. The positional relationships of constituent elements may be appropriately modified depending on the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced depending on the circumstances.

[0039] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0040] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0041] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0042] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0043] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0044] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0045] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0046] An embodiment of the present disclosure provides a display substrate, which includes a substrate and at least one transistor located on one side of the substrate, the at least one transistor including an active layer and a gate electrode, the active layer including a first region, a second region, and a compensation region located between the first region and the second region; the orthographic projection of the compensation region on the plane where the substrate is located does not overlap with the orthographic projection of the gate electrode on the plane where the substrate is located; the display substrate also includes a compensation structure, the orthographic projection of the compensation structure on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation region on the plane where the substrate is located, and the compensation structure is connected to the gate electrode.

[0047] The display substrate provided in the embodiment of the present disclosure has a compensation structure. When the transistor is powered on, an additional current channel is formed between the compensation structure and the active layer. The additional current channel promotes conduction between the first and second electrodes of the transistor, thereby improving the current conduction efficiency of the transistor.

[0048] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0049] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0050] In some exemplary embodiments, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In one example, the subpixels may be rectangular, diamond, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0051] In some exemplary embodiments, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0052] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels within the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may also include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0053] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0054] In some exemplary embodiments, the substrate 101 may be a flexible substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The semiconductor layer may be made of amorphous silicon (a-Si).

[0055] In some exemplary embodiments, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit, which may include at least one transistor and at least one capacitor. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device, which may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode.

[0056] In some exemplary embodiments, the pixel driving circuit may include at least one transistor and at least one capacitor. For example, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the pixel driving circuit, and the number before C represents the number of capacitors in the pixel driving circuit. In some examples, the multiple transistors in the pixel driving circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the multiple transistors in the pixel driving circuit may include P-type transistors and N-type transistors.

[0057] In some exemplary embodiments, a plurality of transistors in a pixel driving circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, while oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0058] In some exemplary embodiments, the light-emitting device may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc.

[0059] In some exemplary embodiments, the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0060] In some exemplary embodiments, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0061] Figure 4 is a partial top view of a display substrate according to an embodiment of the present disclosure. Figure 4A is a partial cross-sectional view of the display substrate according to an embodiment of the present disclosure. Figure 4A is a cross-sectional view taken along the line AA in Figure 4. As shown in Figures 4 and 4A, the display substrate may include a first conductive layer 111, a semiconductor layer 114, a second conductive layer 112, and a third conductive layer 113, sequentially located on one side of a substrate 101. The first conductive layer 111 may include at least a bottom gate electrode 115 of a transistor, the semiconductor layer 114 may include at least an active layer 116 of the transistor, the second conductive layer 112 may include at least a top gate electrode 117 of the transistor, and the third conductive layer 113 may include at least a first connecting electrode 121 and a second connecting electrode 122. The first connecting electrode 121 is configured to connect to the first electrode of the transistor via a first via K1, and the second connecting electrode 122 is configured to connect to the second electrode of the transistor via a second via K2. The first electrode may be either a drain electrode or a source electrode, and the second electrode may be the other of the drain and source electrodes. In the embodiments of the present disclosure, the top gate electrode may also be referred to as the gate electrode of the transistor.

[0062] As shown in FIG4 , the active layer 116 may further include a compensation region 120 . The orthographic projection of the compensation region 120 on the plane of the substrate 101 does not overlap with the orthographic projection of the top gate electrode 117 on the plane of the substrate 101 . For example, the compensation region 120 is shown within the dashed box in FIG4 . As shown in FIG4 and FIG4A , the active layer 116 may include a first region 116-1, a second region 116-2, and a channel region 116-3 located between the first region 116-1 and the second region 116-2. The first region 116-1 may function as a first electrode or a second electrode of a transistor. The second region 116-2 may function as a second electrode or a first electrode of a transistor.

[0063] As shown in Figures 4 and 4A, the third conductive layer 113 may further include a compensation structure 118. The orthographic projection of the compensation structure 118 on the plane of the substrate 101 is located between the orthographic projections of the first region 116-1 and the second region 116-2 on the plane of the substrate 101. The compensation structure 118 is electrically connected to the top gate electrode 117, and the orthographic projection of the compensation structure 118 on the plane of the substrate 101 at least partially overlaps with the orthographic projection of the compensation region 120 on the plane of the substrate 101. In the embodiment of the present disclosure, by providing the compensation structure, an external electric field can be formed in the transistor during the turn-on phase, stimulating the number of electrons between the first and second electrodes of the transistor, thereby improving the uniformity of the transistor and enhancing the conduction efficiency of the transistor current.

[0064] In some exemplary embodiments, the orthographic projection of the compensation structure 118 on the plane where the substrate 101 is located at least partially overlaps with the orthographic projection of the top gate electrode 117 on the plane where the substrate 101 is located. For example, the orthographic projection of the compensation structure 118 on the plane where the substrate 101 is located includes the orthographic projection of the top gate electrode 117 on the plane where the substrate 101 is located, and the orthographic projection area of ​​the compensation structure 118 on the plane where the substrate 101 is located is greater than the orthographic projection area of ​​the top gate electrode 117 on the plane where the substrate 101 is located.

[0065] In some exemplary embodiments, as shown in Figure 4, within the plane where the display substrate is located, and in the direction of a line perpendicular to the center of the orthographic projection of the first area 116-1 on the plane where the substrate 101 is located and the center of the orthographic projection of the second area 116-2 on the plane where the substrate 101 is located, the compensation structure 118 has a first minimum width W1, and the portion of the active layer 116 located between the first area 116-1 and the second area 116-2 has a second minimum width W2. The first minimum width W1 can be greater than the second minimum width W2, so as to facilitate the formation of an additional current channel between the compensation structure 118 and the active layer 116.

[0066] As shown in FIG4 , there is a non-overlapping area between the orthographic projection of the active layer 116 on the plane where the substrate 101 is located and the orthographic projection of the top gate electrode 117 on the plane where the substrate 101 is located. During the process of conducting the active layer 116, since only a part of the non-overlapping area is conducted, the current conduction resistance between the first area 116-1 and the second area 116-2 is large. During the performance test of the transistor, the electron mobility and the average on-state current of the transistor are low, and the on-state current uniformity is poor. As shown in FIG4 , by providing the compensation structure 118, when the voltage of the compensation structure 118 is greater than zero volts, a large amount of positive charge will accumulate on the compensation structure 118, and part of the active layer 116 will be affected by the electric field formed by the compensation structure 118. A large amount of electrons will accumulate on the side of the active layer 116 close to the compensation structure 118. Therefore, an additional current channel will be formed between the compensation structure 118 and the active layer 116. During the performance test of the transistor, the additional current channel formed above will work normally, thereby promoting the conduction between the first electrode and the second electrode of the transistor, thereby improving the electron mobility, the average on-state current, and the on-state current uniformity of the transistor.

[0067] As shown in Table 1 below, multiple performance parameters of the two display substrates are compared. As can be seen from Table 1, compared with the display substrate without a compensation structure, the display substrate with a compensation structure has an improved saturation threshold voltage from 10.77V to 1.46V, an electron mobility increased by approximately 13 times, and an on-state current uniformity improved from approximately 98% to approximately 69%.

[0068] Table 1

[0069] In some exemplary embodiments, as shown in FIG4A , the display substrate may further include a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked in sequence. A portion of the first insulating layer 11 is located between the first conductive layer 111 and the semiconductor layer 114. A portion of the second insulating layer 12 is located between the semiconductor layer 114 and the second conductive layer 112. A portion of the third insulating layer 13 is located between the second conductive layer 112 and the third conductive layer 113. The materials of the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 may be the same or different. The materials of the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 may include inorganic materials or organic materials. The inorganic material is, for example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ), etc. Organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc. The first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 can be a single layer, a multi-layer structure, or a composite layer structure.

[0070] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0071] The preparation process of the display substrate may include the following steps:

[0072] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include depositing a first conductive film on a substrate and patterning the first conductive film through a patterning process, so that the first conductive film forms a first conductive layer pattern on the substrate, as shown in FIG5 . In an exemplary embodiment, the first conductive layer 111 may be referred to as a first gate metal (GATE1) layer. The first conductive layer pattern may include at least a bottom gate electrode 115.

[0073] As shown in FIG5 , the bottom gate electrode 115 may include a first region 115-1 and a second region 115-2 connected to each other. The first region 115-1 may be in a block shape, for example, a rectangular block shape. The second region 115-2 may be in a strip shape. The second region 115-2 may include a first end and a second end disposed opposite to each other along a second direction Y. The first end of the second region 115-2 is connected to the first region 115-1, and the second end of the second region 115-2 extends in the opposite direction of the second direction Y. The bottom gate electrode 115 may serve as a shielding layer for the transistor, shielding the channel region of the transistor and ensuring the electrical performance of the transistor.

[0074] (12) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process so that the first insulating film forms a first insulating layer, and forming the semiconductor film into a semiconductor layer pattern located on a side of the first insulating layer away from the substrate, as shown in FIG6A and FIG6B , where FIG6B is a plan view schematic diagram of the semiconductor layer in FIG6A .

[0075] In some exemplary embodiments, the semiconductor layer 114 may include at least an active layer 116 of a transistor, and an orthographic projection of the active layer 116 on the plane where the substrate is located at least partially overlaps with an orthographic projection of the bottom gate electrode 115 on the plane where the substrate is located.

[0076] In some exemplary embodiments, the active layer 116 may include a first portion 116-4, a second portion 116-5, and a third portion 116-6 that are connected. The second portion 116-5 and the third portion 116-6 may be located on opposite sides of the first portion 116-4 along the second direction Y. The second portion 116-5 and the third portion 116-6 may be symmetrically arranged along the first portion 116-4. For example, the first portion 116-4 may be block-shaped, for example, a rectangular block. The second portion 116-5 and the third portion 116-6 may be strip-shaped.

[0077] The second portion 116-5 may include a first end and a second end oppositely disposed along the second direction Y, the first end of the second portion 116-5 being connected to the first portion 116-4, and the second end of the second portion 116-5 extending along the second direction Y. The third portion 116-6 may include a first end and a second end oppositely disposed along the second direction Y, the first end of the third portion 116-6 being connected to the first portion 116-4, and the second end of the third portion 116-6 extending in a direction opposite to the second direction Y.

[0078] (13) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process so that the second insulating film forms a second insulating layer covering the semiconductor layer pattern, and forming the second conductive film into a second conductive layer pattern located on a side of the second insulating layer away from the substrate, as shown in FIG7A and FIG7B , FIG7B is a plan view of the second conductive layer in FIG7A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0079] As shown in Figure 7A, the second conductive layer 112 may include at least a top gate electrode 117, the orthographic projection of the top gate electrode 117 on the plane where the substrate is located at least partially overlaps with the orthographic projection of the bottom gate electrode 115 on the plane where the substrate is located, and the top gate electrode 117 and the bottom gate electrode 115 form a transistor with a top-gate and bottom-gate structure.

[0080] The top gate electrode 117 may be in a strip shape extending along the first direction X. The size of the top gate electrode 117 along the second direction Y may be constant. Alternatively, the size of the top gate electrode 117 along the second direction Y may vary along the first direction X.

[0081] In some exemplary embodiments, forming the second conductive layer pattern may further include conducting the active layer 116 so that the active layer 116 forms a first region 116-1, a second region 116-2, and a channel region 116-3 located between the first region 116-1 and the second region 116-2. The first region 116-1 may function as a first electrode or a second electrode of a transistor. The second region 116-2 may function as a second electrode or a first electrode of a transistor. For example, the first region 116-1 may be located in the second portion 116-5, the second region 116-2 may be located in the third portion 116-6, and the channel region 116-3 may be located in the first portion 116-4.

[0082] (14) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern, and patterning the third insulating film through a patterning process so that the third insulating film forms a third insulating layer. The display substrate is provided with a plurality of vias, as shown in FIG8 .

[0083] The plurality of vias may include at least a first via K1, a second via K2, and a third via K3. The orthographic projection of the first via K1 on the substrate plane may partially overlap with the orthographic projection of the first region 116-1 on the substrate plane. For example, the orthographic projection of the first via K1 on the substrate plane may be located within the orthographic projection of the first region 116-1 on the substrate plane. The second insulating layer and the third insulating layer located within the first via K1 are both etched away, and the first via K1 exposes a portion of the first region 116-1. The first via K1 is configured such that a subsequently formed first connection electrode can be connected to the first region 116-1 via the via.

[0084] The orthographic projection of the second via K2 on the plane of the substrate may partially overlap with the orthographic projection of the second region 116-2 on the plane of the substrate. For example, the orthographic projection of the second via K2 on the plane of the substrate may be located within the orthographic projection of the second region 116-2 on the plane of the substrate. The second insulating layer and the third insulating layer located within the second via K2 are both etched away, and the second via K2 exposes a portion of the second region 116-2. The second via K2 is configured such that a subsequently formed second connection electrode can be connected to the second region 116-2 via the via.

[0085] The orthographic projection of the third via K3 on the plane of the substrate may partially overlap with the orthographic projection of the top gate electrode 117 on the plane of the substrate. For example, the orthographic projection of the third via K3 on the plane of the substrate may be located within the orthographic projection of the top gate electrode 117 on the plane of the substrate. The third insulating layer located within the third via K3 is etched away, exposing a portion of the top gate electrode 117. The third via K3 is configured such that a subsequently formed compensation structure can be connected to the top gate electrode 117 via the via.

[0086] (15) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process so that the third conductive film forms a third conductive layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the third conductive layer in FIG9A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0087] The third conductive layer 113 may include a compensation structure 118, a first connection electrode 121, and a second connection electrode 122. The compensation structure 118 may be located between the first connection electrode 121 and the second connection electrode 122. The first connection electrode 121 may be located on one side of the compensation structure 118 along the second direction Y, and the second connection electrode 122 may be located on a side of the compensation structure 118 opposite to the second direction Y.

[0088] The first connection electrode 121 can be a long strip extending along the second direction Y. The orthographic projection of the first connection electrode 121 on the plane where the substrate is located can at least partially overlap with the orthographic projection of the first via K1 on the plane where the substrate is located. For example, the orthographic projection of the first connection electrode 121 on the plane where the substrate is located can include the orthographic projection of the first via K1 on the plane where the substrate is located. The first connection electrode 121 can be connected to the first region 116-1 via the first via K1.

[0089] The second connection electrode 122 may include a first extension segment 122-1 and a second extension segment 122-2 connected to each other. The first extension segment 122-1 may include a first end and a second end oppositely disposed along a first direction X. The second end of the first extension segment 122-1 may extend along the first direction X. The second extension segment 122-2 may include a first end and a second end oppositely disposed. The first end of the second extension segment 122-2 may be connected to the second end of the first extension segment 122-1. The second end of the second extension segment 122-2 may extend along the second direction Y. The orthographic projection of the second extension segment 122-2 on the plane of the substrate at least partially overlaps with the orthographic projection of the second via K2 on the plane of the substrate. For example, the orthographic projection of the second extension segment 122-2 on the plane of the substrate may include the orthographic projection of the second via K2 on the plane of the substrate. The second extension segment 122-2 may be connected to the second region 116-2 via the second via K2.

[0090] The orthographic projection of the compensation structure 118 on the plane of the substrate can be rectangular or quasi-rectangular. The compensation structure 118 can include a main portion 118-3, a first protrusion 118-1, and a second protrusion 118-2 connected to each other. The first protrusion 118-1 and the second protrusion 118-2 can be located on either side of the main portion 118-3. For example, the first protrusion 118-1 can be located on one side of the main portion 118-3 along the second direction Y, and the second protrusion 118-2 can be located on the side of the main portion 118-3 opposite to the second direction Y. For example, the first protrusion 118-1 and the second protrusion 118-2 can be arranged symmetrically along the main portion 118-3.

[0091] The orthographic projection of the main portion 118-3 on the plane of the substrate may include the orthographic projection of the first portion 116-4 on the plane of the substrate, the orthographic projection of the first protrusion 118-1 on the plane of the substrate at least partially overlaps with the orthographic projection of the second portion 116-5 on the plane of the substrate, and the orthographic projection of the second protrusion 118-2 on the plane of the substrate at least partially overlaps with the orthographic projection of the third portion 116-6 on the plane of the substrate.

[0092] Figure 10 is a partial top view of a display substrate according to another embodiment of the present disclosure. Figure 10A is a partial cross-sectional view of a display substrate according to another embodiment of the present disclosure. Figure 10A is a cross-sectional view taken at the position indicated by BB in Figure 10. As shown in Figures 10 and 10A, the display substrate may include a first conductive layer 111, a semiconductor layer 114, a second conductive layer 112, and a third conductive layer 113, sequentially located on one side of a substrate 101. The first conductive layer 111 may include at least a bottom gate electrode 115 of a transistor, the semiconductor layer 114 may include at least an active layer 116 of the transistor, the second conductive layer 112 may include at least a top gate electrode 117 of the transistor, and the third conductive layer 113 may include at least a first connecting electrode 121 and a second connecting electrode 122. The first connecting electrode 121 is configured to be connected to the first electrode of the transistor via a first via K1, and the second connecting electrode 122 is configured to be connected to the second electrode of the transistor via a second via K2.

[0093] As shown in FIG10 , the active layer 116 may further include a compensation region 120 . The orthographic projection of the compensation region 120 on the plane of the substrate 101 does not overlap with the orthographic projection of the top gate electrode 117 on the plane of the substrate 101 . For example, the compensation region 120 is shown within the dashed box in FIG10 . As shown in FIG10 and FIG10A , the active layer 116 may include a first region 116-1, a second region 116-2, and a channel region 116-3 located between the first region 116-1 and the second region 116-2. The first region 116-1 may function as a first electrode or a second electrode of a transistor. The second region 116-2 may function as a second electrode or a first electrode of a transistor.

[0094] As shown in Figures 10 and 10A, the third conductive layer 113 may further include a compensation structure 118, and the compensation structure 118 may include a connecting portion 118a, a first compensation portion 118b, and a second compensation portion 118c. There is a gap between the first compensation portion 118b and the second compensation portion 118c, and the first end of the first compensation portion 118b is connected to the connecting portion 118a, and the second end of the first compensation portion 118b extends along the first direction X. The first end of the second compensation portion 118c is connected to the connecting portion 118a, and the second end of the second compensation portion 118c extends along the first direction X. The connecting portion 118a is connected to the top gate electrode 117 via the third via K3. In the embodiment of the present disclosure, designing the compensation structure 118 to include the connecting portion 118a, the first compensation portion 118b, and the second compensation portion 118c can optimize the overall structure of the compensation structure, reduce the actual size of the compensation structure 118, and avoid redundant structure.

[0095] In some exemplary embodiments, in the direction of a line connecting the center of the orthographic projection of the first region 116-1 and the center of the orthographic projection of the second region 116-2 on the plane of the substrate 101, that is, in the second direction Y, the first compensation portion 118b and the second compensation portion 118c have a first minimum dimension L1, and the portion of the top gate electrode 117 between the first compensation portion 118b and the second compensation portion 118c has a second minimum dimension L2. The first minimum dimension L1 may be greater than or equal to the second minimum dimension L2. For other structures of the display substrate, reference may be made to the description of the preceding embodiments and will not be elaborated upon here.

[0096] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0097] In some exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The active layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene, and the like. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The structure and preparation process shown in the above embodiments of the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, and the present disclosure is not limited thereto.

[0098] The present disclosure also provides a display device comprising the display substrate described in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the present disclosure is not limited thereto.

[0099] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a substrate and at least one transistor located on one side of the substrate, the at least one transistor comprising an active layer and a gate electrode, the active layer comprising a first region, a second region, and a compensation region located between the first region and the second region; the orthographic projection of the compensation region on the plane where the substrate is located does not overlap with the orthographic projection of the gate electrode on the plane where the substrate is located; the display substrate further comprising a compensation structure, the orthographic projection of the compensation structure on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation region on the plane where the substrate is located, and the compensation structure is connected to the gate electrode.

2. The display substrate according to claim 1, wherein: The compensation structure includes at least one of a first compensation portion and a second compensation portion, and the orthographic projection of the first compensation portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation area on the plane where the substrate is located, and the orthographic projection of the second compensation portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the compensation area on the plane where the substrate is located.

3. The display substrate according to claim 2, wherein: The orthographic projection of the first compensation portion on the plane where the substrate is located is located between the first region and the orthographic projection of the gate electrode on the plane where the substrate is located.

4. The display substrate according to claim 3, wherein: The compensation structure further includes a connecting portion, the orthographic projection of the connecting portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the gate electrode on the plane where the substrate is located, the connecting portion is connected to the gate electrode, and the first compensation portion is connected to the connecting portion.

5. The display substrate according to claim 4, wherein: The first compensation portion and the connecting portion are an integral structure connected to each other.

6. The display substrate according to claim 2, wherein: The orthographic projection of the second compensation portion on the plane where the substrate is located is located between the second region and the orthographic projection of the gate electrode on the plane where the substrate is located.

7. The display substrate according to claim 6, wherein: The compensation structure further includes a connecting portion, the orthographic projection of the connecting portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the gate electrode on the plane where the substrate is located, the connecting portion is connected to the gate electrode, and the second compensation portion is connected to the connecting portion.

8. The display substrate according to claim 7, wherein: The second compensation portion and the connecting portion are an integral structure connected to each other.

9. The display substrate according to claim 2, wherein: The first compensation portion and the second compensation portion are an integral structure connected to each other, and an orthographic projection of the compensation structure on the plane where the substrate is located at least partially overlaps with an orthographic projection of the gate electrode on the plane where the substrate is located.

10. The display substrate according to any one of claims 1 to 9, wherein: In a plane perpendicular to the base, the display substrate further includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer sequentially located on one side of the base; the active layer is located in the semiconductor layer, and the gate electrode and the compensation structure are located in different conductive layers.

11. The display substrate according to claim 10, wherein: The gate electrode is located in the second conductive layer, and the compensation structure is located in the third conductive layer.

12. The display substrate according to claim 10, wherein: The at least one transistor further includes a bottom gate electrode, which is located in the first conductive layer. The orthographic projection of the bottom gate electrode on the plane where the substrate is located at least partially overlaps with the orthographic projection of the active layer on the plane where the substrate is located.

13. A display device comprising the display substrate according to any one of claims 1 to 12.

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