Chip and manufacturing method therefor, and electronic device
By introducing a first gate dielectric layer with low defect concentration and a second gate dielectric layer with high dielectric constant into the oxide semiconductor transistor, the threshold voltage drift problem of the oxide semiconductor transistor is solved, and the reliability and stability of the device are improved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-15
AI Technical Summary
The reliability issues faced by oxide semiconductor transistors, especially the bias-temperature reliability (BTI) problem, cause threshold voltage drift and affect device reliability.
Introducing a first gate dielectric layer with a lower defect concentration into the transistor and combining it with a second gate dielectric layer with a high dielectric constant suppresses the positive drift component of the threshold voltage while ensuring the gate's gate control capability.
It effectively suppresses the threshold voltage drift of oxide semiconductor transistors, improves the reliability and stability of the device, and enhances BTI performance.
Smart Images
Figure CN2024131589_15052026_PF_FP_ABST
Abstract
Description
Chips and their fabrication methods, electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202410174392.7, filed on February 7, 2024, entitled "Chip and Method of Fabrication Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, and an electronic device. Background Technology
[0003] With the development of advanced integrated circuit technology, novel transistors that can be fabricated in back-end processes are an effective method to achieve chip miniaturization and improve chip performance. Oxide-semiconductor transistors (OSTs), whose channel layers include oxide semiconductors, have become one of the candidates for next-generation transistor technology due to their advantages such as low leakage current, high mobility, high on / off ratio, low processing temperature, and ease of back-end integration.
[0004] However, reliability issues, such as bias-temperature instability (BTI), are the main problems currently facing oxide semiconductor transistors.
[0005] Summary of the Invention
[0006] To address the aforementioned technical problems, this application provides a chip and its fabrication method, as well as an electronic device, which can improve the BTI of a transistor by suppressing the positive drift component of the threshold voltage using a first gate dielectric layer without affecting the gate control capability.
[0007] In a first aspect, this application provides a chip including a transistor. The transistor includes a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate electrode, which are sequentially stacked. The channel layer is made of an oxide semiconductor and is in contact with the first gate dielectric layer. The defect concentration of the material in the first gate dielectric layer is lower than that of the material in the second gate dielectric layer, and the dielectric constant of the material in the second gate dielectric layer is greater than that of the material in the first gate dielectric layer.
[0008] In this application, on one hand, the channel layer is in contact with the first gate dielectric layer, and the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, that is, the number of defects in the first gate dielectric layer is lower than the number of defects in the second gate dielectric layer, so as to utilize the first gate dielectric layer to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. On the other hand, in addition to including the first gate dielectric layer, the embodiments of this application also include a second gate dielectric layer in contact with the gate, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer, so as to utilize the second gate dielectric layer to ensure the gate control capability of the gate.
[0009] In some possible implementations, the energy difference between the defect levels of the first gate dielectric layer and the conduction band electrons of the channel layer can be greater than the energy difference between the defect levels of the second gate dielectric layer and the conduction band electrons of the channel layer. This allows the first gate dielectric layer to suppress the positive drift component of the threshold voltage, thereby improving the transistor's base-to-timing (BTI). Alternatively, the hydrogen content in the first gate dielectric layer can be lower than that in the second gate dielectric layer. Due to the lower hydrogen content in the first gate dielectric layer, only a small amount of hydrogen from the first gate dielectric layer in contact with the channel layer enters the channel layer as donors and dops with electrons in the channel layer, effectively suppressing the negative drift component of the threshold voltage and improving the transistor's BTI.
[0010] This application does not limit the hydrogen content in the material of the first gate dielectric layer, as long as the hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer. Optionally, the hydrogen content in the material of the first gate dielectric layer is less than 1e 20 atoms / cc.
[0011] Based on the above conditions, the material of the first gate dielectric layer includes hafnium aluminum oxide and aluminum oxide; and / or, the dielectric constant of the material of the second gate dielectric layer is greater than 15, for example, the material of the second gate dielectric layer includes at least one of lanthanum oxide and hafnium dioxide.
[0012] In some possible implementations, considering the high defect concentration, small gap between the second gate dielectric layer and the conduction band electrons of the channel layer, and high hydrogen content—meaning that the second gate dielectric layer still has significant defects that may affect the transistor's band transition temperature (BTI)—the thickness of the first gate dielectric layer can be greater than that of the second gate dielectric layer along the direction from the first gate dielectric layer to the second gate dielectric layer. This ensures that the thickness of the first gate dielectric layer is sufficient to block the second gate dielectric layer, preventing it from trapping electrons in the channel layer and thus improving the transistor's BTI.
[0013] For example, the thickness of the first gate dielectric layer can range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer. For instance, the thickness of the first gate dielectric layer is 3 nm, and the thickness of the second gate dielectric layer is 2 nm.
[0014] In some possible implementations, the chip also includes a substrate on which the transistor is disposed. The transistor also includes a first electrode and a second electrode, both of which are in contact with the channel. The first electrode is the source, and the second electrode is the drain; or, the first electrode is the drain, and the second electrode is the source.
[0015] For transistors with different structures, the stacking positions of the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are different.
[0016] For example, the transistor is a bottom-gate transistor. Along the direction from the substrate to the transistor, the gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are stacked sequentially. The transistor also includes a first protective layer. The first protective layer, the first electrode, and the second electrode are all disposed on the side of the channel layer facing away from the substrate. The first protective layer is disposed between the channel layer and the first and second electrodes. The first protective layer includes a first via and a second via spaced apart. The first electrode contacts the channel layer through the first via, and the second electrode contacts the channel layer through the second via.
[0017] For example, the transistor is a top-gate transistor. Along the direction from the substrate to the transistor, the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are stacked sequentially. The first and second gate dielectric layers are grooved, and the gate is disposed in the groove; the first electrode and the second electrode are disposed on the channel layer and are located on opposite sides of the sidewall of the groove.
[0018] For example, the transistor is a vertical transistor. Along the direction from the substrate to the transistor, the first electrode and the gate are stacked sequentially. The gate includes a cutout portion, and along the sidewall direction away from the cutout portion, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are stacked sequentially; the second electrode is disposed on the side of the channel layer opposite to the first electrode.
[0019] In this case, the chip also includes an insulating layer, and the second gate dielectric layer, the first gate dielectric layer, the channel layer, and the insulating layer are stacked sequentially along the sidewall direction away from the cutout portion. That is, the insulating layer is disposed in the area enclosed by the channel. In this way, without changing the outer dimensions of the channel layer, the embodiments of this application can reduce the thickness of the channel layer by filling the channel layer with an insulating layer, thereby improving the gate control capability of the vertical transistor.
[0020] Furthermore, the first gate dielectric layer and the second gate dielectric layer include sidewalls and a bottom, with the bottom of the second gate dielectric layer in contact with the first electrode. A third through-hole is formed at the bottom of the second gate dielectric layer and the first gate dielectric layer, through which the channel layer contacts the first electrode.
[0021] Secondly, this application provides an electronic device, including a circuit board and the chip described in the first aspect, wherein the chip is disposed on the circuit board.
[0022] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.
[0023] Thirdly, this application provides a method for fabricating a chip, the chip including a transistor, the method for fabricating the transistor including: forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate; the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are sequentially stacked, and the channel layer is in contact with the first gate dielectric layer; wherein, the material of the channel layer includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.
[0024] In some possible implementations, the difference between the defect energy level of the material of the first gate dielectric layer and the conduction band electrons of the channel layer is greater than the difference between the defect energy level of the material of the second gate dielectric layer and the conduction band electrons of the channel layer; and / or, the hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.
[0025] In some possible implementations, forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate electrode on a substrate includes: sequentially forming the gate electrode, the second gate dielectric layer, the first gate dielectric layer, and the channel layer on the substrate. After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate electrode on the substrate, the fabrication method further includes: forming a first protective layer on the channel layer, the first protective layer including a first via and a second via spaced apart; forming a first electrode and a second electrode on the first protective layer, the first electrode contacting the channel layer through the first via, and the second electrode contacting the channel layer through the second via.
[0026] In some possible implementations, forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate includes: sequentially forming a channel layer, a conductive layer, and a second protective layer on the substrate; the second protective layer includes a fourth via; under the protection of the second protective layer, forming a fifth via in the conductive layer to obtain a first electrode and a second electrode, and exposing the surface of the channel layer away from the substrate; and sequentially forming the first gate dielectric layer, the second gate dielectric layer, and the gate in the fourth and fifth vias.
[0027] In some possible implementations, before forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the fabrication method includes: forming a first electrode on the substrate. Forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate includes: forming the gate on the first electrode, the gate including a cutout portion exposing the surface of the first electrode facing away from the substrate; sequentially forming the second gate dielectric layer, the first gate dielectric layer, and the channel layer in the cutout portion along a direction away from the sidewall of the cutout portion; the channel layer contacting the surface of the first electrode facing away from the substrate. After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the fabrication method further includes: forming a second electrode on the side of the channel layer facing away from the first electrode.
[0028] In some possible implementations, after forming the second gate dielectric layer, the first gate dielectric layer, and the channel layer sequentially in the cutout along the sidewall direction away from the cutout, the fabrication method further includes filling the cutout with an insulating layer, the insulating layer being located on the side of the channel layer away from the first gate dielectric layer.
[0029] In some possible implementations, a second gate dielectric layer, a first gate dielectric layer, and a channel layer are sequentially formed in the cutout portion along the direction away from the sidewall of the cutout portion. This includes: sequentially forming a second gate dielectric layer, a first gate dielectric layer, and a sacrificial layer in the cutout portion along the direction away from the sidewall of the cutout portion, so as to protect the sidewall of the first gate dielectric layer with the sacrificial layer; the first gate dielectric layer and the second gate dielectric layer include sidewalls and bottoms, and the bottom of the second gate dielectric layer is in contact with the first electrode; the sacrificial layer covers the sidewalls and bottoms of the first and second gate dielectric layers, and exposes a third through-hole at the bottom of the second and first gate dielectric layers; the sacrificial layer is removed, and a channel layer is filled in the cutout portion, the channel layer being in contact with the first electrode through the third through-hole.
[0030] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description
[0031] Figure 1 is a schematic diagram of the structure of a transistor provided in an embodiment of this application;
[0032] Figure 2 is a schematic diagram of the transistor structure provided in an embodiment of this application;
[0033] Figure 3 is a schematic diagram of the structure of the transistor provided in an embodiment of this application;
[0034] Figure 4a is a schematic diagram of the structure of a transistor provided in an embodiment of this application;
[0035] Figure 4b is a top view of a portion of the structure of a transistor provided in an embodiment of this application;
[0036] Figure 5 is a schematic diagram of the structure of the transistor provided in an embodiment of this application;
[0037] Figure 6 is a flowchart of the transistor fabrication process provided in an embodiment of this application;
[0038] Figure 7a is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0039] Figure 7b is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0040] Figure 7c is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0041] Figure 8 is a flowchart of the transistor fabrication process provided in an embodiment of this application;
[0042] Figure 9a is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0043] Figure 9b is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0044] Figure 9c is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0045] Figure 9d is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0046] Figure 10 is a flowchart of the transistor fabrication process provided in an embodiment of this application;
[0047] Figure 11a is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0048] Figure 11b is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0049] Figure 11c is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0050] Figure 11d is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0051] Figure 12 is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0052] Figure 13a is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application;
[0053] Figure 13b is a diagram illustrating the fabrication process of the transistor provided in an embodiment of this application. Detailed Implementation
[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0055] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0056] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.
[0057] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0058] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.
[0059] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes a memory.
[0060] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory devices, radar, base stations, and other communication equipment containing transistors.
[0061] For ease of explanation, the following description uses a mobile phone as an example. A mobile phone may include a processor, which includes logic circuits and memory. The memory includes a memory array, a memory controller, a decoder, etc. The logic circuits can read and write data to the memory array through the memory controller and decoder. The memory includes a memory array, which includes memory cells, and each memory cell includes a transistor and a capacitor. Of course, other devices may also include transistors, and this application does not limit this.
[0062] As mentioned in the background section, with the development of advanced integrated circuit technology, novel transistors that can be fabricated in back-end processes are an effective method to achieve chip miniaturization and improve chip performance. Oxide-semiconductor transistors (OSTs), whose channel layers include oxide semiconductors, have become one of the candidates for next-generation transistor technology due to their advantages such as low leakage current, high mobility, high on / off ratio, low processing temperature, and ease of back-end integration.
[0063] However, reliability issues, exemplified by BTI, are currently the main problems facing oxide semiconductor transistors.
[0064] For conventional silicon-based transistors, interface defects between the channel layer and the gate dielectric layer cause threshold voltage drift, which is the main cause of BTI degradation in conventional silicon-based transistors.
[0065] For N-type oxide semiconductor transistors (OSTs), defects in the gate dielectric layer and interface will cause a larger positive drift in the threshold voltage (BTI) of the OST. Furthermore, hydrogen (H) diffusion into the OST and electron doping will cause a larger negative drift in the threshold voltage. These positive and negative threshold voltage drifts are the main causes of BTI degradation in OSTs.
[0066] To address these issues, related technologies employ an ultrathin silicon dioxide (SiO2) layer as a barrier layer between the channel layer and the gate dielectric layer to prevent the gate dielectric layer from trapping electrons from the channel layer. However, this technology does not directly reduce the number of defects in the gate dielectric layer; therefore, relying solely on the barrier layer does not significantly improve device reliability.
[0067] Based on this, embodiments of this application provide a chip including a transistor disposed on a substrate. The transistor includes a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate. The channel layer is made of oxide semiconductor, making the transistor an oxide semiconductor transistor (hereinafter collectively referred to as a transistor). This application improves the BTI of the transistor by adding a first gate dielectric layer with a lower defect concentration to suppress the positive drift component of the threshold voltage.
[0068] Specifically, as shown in Figures 1-3, a channel layer 11, a first gate dielectric layer 121, a second gate dielectric layer 122, and a gate 13 are stacked sequentially. On one hand, the channel layer 11 is in contact with the first gate dielectric layer 121, and the defect concentration of the material in the first gate dielectric layer 121 is lower than the defect concentration of the material in the second gate dielectric layer 122. That is, the number of defects in the first gate dielectric layer 121 is lower than the number of defects in the second gate dielectric layer 122, thereby suppressing the positive drift component of the threshold voltage using the first gate dielectric layer 121, thus improving the transistor's threshold voltage transition (BTI). On the other hand, in addition to the first gate dielectric layer 121, this embodiment also includes a second gate dielectric layer 122 in contact with the gate 13, and the dielectric constant of the material in the second gate dielectric layer 122 is greater than the dielectric constant of the material in the first gate dielectric layer 121, thereby ensuring the gate control capability of the gate 13 using the second gate dielectric layer 122.
[0069] In some possible implementations, the materials of the first gate dielectric layer 121 and the second gate dielectric layer 122 are not limited, as long as the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121.
[0070] In addition to satisfying that the defect concentration of the material of the first gate dielectric layer 121 is lower than that of the material of the second gate dielectric layer 122, and that the dielectric constant of the material of the second gate dielectric layer 122 is greater than that of the material of the first gate dielectric layer 121, the following conditions can also be met:
[0071] For example, the energy difference between the defect level of the material of the first gate dielectric layer 121 and the conduction band electrons of the channel layer 11 can be greater than the energy difference between the defect level of the material of the second gate dielectric layer 122 and the conduction band electrons of the channel layer 11. This allows the first gate dielectric layer 121 to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. And / or, the hydrogen content in the material of the first gate dielectric layer 121 is lower than the hydrogen content in the material of the second gate dielectric layer 122. Because the hydrogen content in the first gate dielectric layer 121 is lower, only a small amount of hydrogen from the first gate dielectric layer 121 in contact with the channel layer 11 enters the channel layer 11 as donors and dops with the electrons in the channel layer 11, thereby effectively suppressing the negative drift component of the threshold voltage and improving the BTI of the transistor.
[0072] This application does not limit the hydrogen content in the material of the first gate dielectric layer 121, as long as the hydrogen content in the material of the first gate dielectric layer 121 is lower than the hydrogen content in the material of the second gate dielectric layer 122. Optionally, the hydrogen content in the material of the first gate dielectric layer 121 can be less than 1e 20 atoms / cc (number of atoms per unit volume).
[0073] Optionally, this embodiment does not limit the dielectric constant of the material of the second gate dielectric layer 122, as long as the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121. Optionally, the dielectric constant of the material of the second gate dielectric layer 122 is greater than 15.
[0074] Based on the above conditions, the material of the first gate dielectric layer 121 may include at least one of aluminum oxide (Al2O3) and hafnium aluminum oxide (HfAlO). The material of the second gate dielectric layer 122 may include at least one of lanthanum oxide (La2O3) and hafnium dioxide (HfO2).
[0075] In some possible implementations, as shown in Figure 1, considering the high defect concentration of the second gate dielectric layer 122, the small difference between it and the conduction band electrons of the channel layer 11, and the high hydrogen content—meaning that the second gate dielectric layer 122 still has significant defects that may affect the transistor's band transition temperature (BTI)—the thickness of the first gate dielectric layer 121 can be greater than the thickness of the second gate dielectric layer 122 along the direction from the first gate dielectric layer 121 to the second gate dielectric layer 122. This ensures that the thickness of the first gate dielectric layer 121 is sufficient to block the second gate dielectric layer 122, preventing it from trapping electrons in the channel layer 11 and thus improving the transistor's BTI.
[0076] For example, the thickness of the first gate dielectric layer 121 can range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer 122 is less than the thickness of the first gate dielectric layer 121. For example, the thickness of the first gate dielectric layer 121 is 3 nm, and the thickness of the second gate dielectric layer 122 is 2 nm.
[0077] In some possible implementations, the material of the channel layer 11 is not limited, as long as the material of the channel layer 11 includes oxide semiconductors. For example, the material of the channel layer 11 includes oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium gallium oxide, and indium zinc oxide.
[0078] In some possible implementations, as shown in Figures 1-3, the transistor includes, in addition to the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13, a first electrode 14 and a second electrode 15 that are in contact with the channel layer 11. The first electrode 14 is the source, and the second electrode 15 is the drain; or, the first electrode 14 is the drain, and the second electrode 15 is the source.
[0079] For transistors with different structures, the stacking positions of the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13 are different.
[0080] For example, the transistor shown in Figure 1 is a bottom-gate transistor. The transistor also includes a first protective layer 21. Along the direction from the substrate 10 to the transistor, the gate 13, the second gate dielectric layer 122, the first gate dielectric layer 121, the channel layer 11, and the first protective layer 21 are stacked sequentially. Both the first electrode and the second electrode are disposed on the side of the first protective layer 21 facing away from the substrate 10. The first protective layer 21 includes a first through-hole and a second through-hole spaced apart. The first electrode 14 contacts the channel layer 11 through the first through-hole, and the second electrode 15 contacts the channel layer 11 through the second through-hole.
[0081] For example, the transistor shown in Figure 2 is a top-gate transistor. Along the direction from the substrate 10 to the transistor, a channel layer 11, a first gate dielectric layer 121, a second gate dielectric layer 122, and a gate 13 are stacked sequentially. The first gate dielectric layer 121 and the second gate dielectric layer 122 are recessed, and the gate 13 is disposed within the recess. A first electrode 14 and a second electrode 15 are disposed on the channel layer 11 and in contact with it, located on opposite sides of the recess sidewall, so that the first electrode 14 and the second electrode 15 are electrically isolated from the gate 13 by utilizing the first gate dielectric layer 121 and the second gate dielectric layer 122.
[0082] For example, the transistor shown in Figure 3 is a vertical transistor. Along the direction from the substrate 10 towards the transistor, the first electrode 14 and the gate 13 are stacked sequentially. The gate 13 includes a cutout portion, and along the sidewall direction away from the cutout portion, the second gate dielectric layer 122, the first gate dielectric layer 121, and the channel layer 11 are stacked sequentially. Furthermore, the second electrode 15 is disposed on the side of the channel layer 11 opposite to the first electrode 14; that is, along the direction from the substrate 10 towards the transistor, the first electrode 14 and the second electrode 15 are disposed on opposite sides of the channel layer 11.
[0083] A first dielectric layer 31 is disposed between the first electrode 14 and the gate 13, and a second dielectric layer 32 is disposed between the second electrode 15 and the gate 13. On one hand, the first dielectric layer 31 is used to electrically isolate the first electrode 14 from the gate 13, and the second dielectric layer 32 is used to electrically isolate the second electrode 15 from the gate 13. On the other hand, the first dielectric layer 31 and the second dielectric layer 32 also define the gate length of the gate 13. It should be understood that, in this application, the gate length direction of the gate 13 is the direction from the first electrode 14 to the second electrode 15.
[0084] Based on the vertical transistor shown in Figure 3, as shown in Figures 4a and 4b, the chip may further include an insulating layer 16. Along the sidewall direction away from the cutout portion, the second gate dielectric layer 122, the first gate dielectric layer 121, the channel layer 11, and the insulating layer 16 are sequentially stacked. That is, the insulating layer 16 is disposed within the area enclosed by the channel 11. Thus, without changing the outer dimensions of the channel layer 11, this embodiment of the application can reduce the thickness of the channel layer 11 by filling it with the insulating layer 16, thereby improving the gate control capability of the vertical transistor.
[0085] It should be understood that the thickness direction of the channel layer 11 is the direction from the sidewall of the first gate dielectric layer 121 to the sidewall of the second gate dielectric layer 122.
[0086] [Correction 09.01.2025 according to Rule 91] Furthermore, based on the vertical transistor shown in FIG3 or FIG4a, as shown in FIG5, the first gate dielectric layer 121 and the second gate dielectric layer 122 further include a bottom adjacent to the sidewalls, and the bottom of the second gate dielectric layer 122 is in contact with the first electrode 11. A third via is formed at the bottom of the second gate dielectric layer 122 and the first gate dielectric layer 121, and the channel layer 11 is in contact with the first electrode 14 through the third via.
[0087] Of course, the structure of the transistor can be other than that described in this application. The embodiments of this application do not limit this, as long as the first gate dielectric layer 121 and the second gate dielectric layer 122 are disposed between the channel layer 11 and the gate 13, and the first gate dielectric layer 121 is disposed on the side of the second gate dielectric layer 122 facing the channel layer 11, and the second gate dielectric layer 122 is disposed on the side of the first gate dielectric layer 121 facing the gate 13.
[0088] In another embodiment, this application also provides a method for fabricating a chip, the chip including a transistor, the method for fabricating the transistor including: forming a channel layer 11, a first gate dielectric layer 121, a second gate dielectric layer 122, and a first gate dielectric layer gate 13 on a substrate 10; the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the first gate dielectric layer gate 13 are sequentially stacked; wherein, the material of the channel layer 11 includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 11, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121.
[0089] On the one hand, the defect concentration of the material of the first gate dielectric layer 121 is lower than that of the material of the second gate dielectric layer 122. That is, the number of defects in the first gate dielectric layer 121, which is in contact with the channel layer 11, is lower than the number of defects in the second gate dielectric layer 122. This allows the first gate dielectric layer 121 to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. On the other hand, because the material of the first gate dielectric layer 121 has a lower defect concentration, its dielectric constant is usually also lower. If the dielectric constant of the first gate dielectric layer 121 decreases, it will affect the gate control capability of the gate 13. Therefore, in addition to the first gate dielectric layer 121, this embodiment of the application also includes a second gate dielectric layer 122 in contact with the gate 13, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than that of the material of the first gate dielectric layer 121, so as to ensure the gate control capability of the gate 13 using the second gate dielectric layer 122.
[0090] In some possible implementations, the materials of the first gate dielectric layer 121 and the second gate dielectric layer 122 are not limited, as long as the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121.
[0091] In addition to satisfying that the defect concentration of the material of the first gate dielectric layer 121 is lower than that of the material of the second gate dielectric layer 122, and that the dielectric constant of the material of the second gate dielectric layer 122 is greater than that of the material of the first gate dielectric layer 121, the following conditions can also be met:
[0092] For example, the energy difference between the defect level of the material of the first gate dielectric layer 121 and the conduction band electrons of the channel layer 11 can be greater than the energy difference between the defect level of the material of the second gate dielectric layer 122 and the conduction band electrons of the channel layer 11. This allows the first gate dielectric layer 121 to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. And / or, the hydrogen content in the material of the first gate dielectric layer 121 is lower than the hydrogen content in the material of the second gate dielectric layer 122. Because the hydrogen content in the first gate dielectric layer 121 is lower, only a small amount of hydrogen from the first gate dielectric layer 121 in contact with the channel layer 11 enters the channel layer 11 as donors and dops with the electrons in the channel layer 11, thereby effectively suppressing the negative drift component of the threshold voltage and improving the BTI of the transistor.
[0093] This application does not limit the hydrogen content in the material of the first gate dielectric layer 121, as long as the hydrogen content in the material of the first gate dielectric layer 121 is lower than the hydrogen content in the material of the second gate dielectric layer 122. Optionally, the hydrogen content in the material of the first gate dielectric layer 121 can be less than 1e 20 atoms / cc (number of atoms per unit volume).
[0094] Optionally, this embodiment does not limit the dielectric constant of the material of the second gate dielectric layer 122, as long as the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121. Optionally, the dielectric constant of the second gate dielectric layer 122 is greater than 15.
[0095] Based on the above conditions, the material of the first gate dielectric layer 121 may include at least one of Al2O3 and HfAlO. The material of the second gate dielectric layer 122 may include at least one of La2O3 and HfO2.
[0096] In some possible implementations, as shown in Figure 1, considering the high defect concentration of the second gate dielectric layer 122, the small difference between it and the conduction band electrons of the channel layer 11, and the high hydrogen content—meaning that the second gate dielectric layer 122 still has significant defects that may affect the transistor's band transition temperature (BTI)—the thickness of the first gate dielectric layer 121 can be greater than the thickness of the second gate dielectric layer 122 along the direction from the first gate dielectric layer 121 to the second gate dielectric layer 122. This ensures that the thickness of the first gate dielectric layer 121 is sufficient to block the second gate dielectric layer 122, preventing it from trapping electrons in the channel layer 11 and thus improving the transistor's BTI.
[0097] For example, the thickness of the first gate dielectric layer 121 can range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer 122 is less than the thickness of the first gate dielectric layer 121. For example, the thickness of the first gate dielectric layer 121 is 3 nm, and the thickness of the second gate dielectric layer 122 is 2 nm.
[0098] In some possible implementations, as shown in Figures 1-3, the transistor includes, in addition to the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13, a first electrode 14 and a second electrode 15 that are in contact with the channel layer 11. The first electrode 14 is the source, and the second electrode 15 is the drain; or, the first electrode 14 is the drain, and the second electrode 15 is the source.
[0099] The fabrication process of transistors varies depending on their structure. The fabrication process of the following three types of transistors is described in conjunction with the accompanying drawings.
[0100] The first type uses a bottom-gate transistor, as shown in Figure 6, and can be achieved through the following steps:
[0101] S110, as shown in Figures 7a-7b, a gate 13, a second gate dielectric layer 122, a first gate dielectric layer 121, and a channel layer 11 are sequentially formed on the substrate 10.
[0102] In some possible implementations, the material of the substrate 10 is not limited in the embodiments of this application. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials that can be used for oxide semiconductor deposition, such as glass.
[0103] In some possible implementations, the material of the gate 13 is not limited, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.
[0104] S120, as shown in FIG7c, a first protective layer 21 is formed on the channel layer 11. The first protective layer 21 includes a first through hole and a second through hole arranged at intervals.
[0105] In some possible implementations, the material of the first protective layer 21 may include materials with insulating effects such as silicon dioxide, aluminum oxide, and hafnium oxide.
[0106] S130, as shown in Figure 1, a first electrode 14 and a second electrode 15 are formed on the first protective layer 21. The first electrode 14 is in contact with the channel layer 11 through a first through hole, and the second electrode 15 is in contact with the channel layer 11 through a second through hole.
[0107] In some possible implementations, the first electrode 14 and the second electrode 15 can be made of the same material, including conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.
[0108] The second method uses a top-gate transistor, as shown in Figure 8, and can be achieved through the following steps:
[0109] S210, as shown in Figures 9a-9b, a channel layer 11, a conductive layer 141, and a second protective layer 22 are sequentially formed on the substrate 10. The second protective layer 22 includes a fourth via.
[0110] In some possible implementations, the material of the substrate 10 is not limited in the embodiments of this application. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials that can be used for oxide semiconductor deposition, such as glass.
[0111] In some possible implementations, the material of the conductive layer 141 is not limited in this application embodiment. Optionally, the material of the conductive layer 141 may include conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.
[0112] S220, as shown in Figure 9c, under the protection of the second protective layer 22, a fifth through hole is formed in the conductive layer 141 to obtain the first electrode 14 and the second electrode 15, and expose the surface of the channel layer 11 on the side away from the substrate 10.
[0113] In some possible implementations, the material of the second protective layer 22 may include materials with insulating properties such as silicon dioxide, aluminum oxide, and hafnium oxide.
[0114] S230, as shown in Figure 2, a first gate dielectric layer 121, a second gate dielectric layer 122, and a gate electrode 13 are sequentially formed in the fourth and fifth vias. In this way, the first gate dielectric layer 121 can contact the channel layer 11.
[0115] In some possible implementations, the material of the gate 13 is not limited, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.
[0116] Furthermore, as shown in Figure 9d, after forming the gate 13, the transistor fabrication method may also include: sequentially forming a third protective layer 23 and a conductive lead 40 on the side of the gate 13 away from the substrate 10, and the conductive lead 40 being electrically connected to the first electrode 14 and the second electrode 15 through through holes in the third protective layer 23, the second protective layer 22, etc.
[0117] The third type uses a vertical transistor. As shown in Figure 10, this can be achieved through the following steps:
[0118] S310, as shown in Figure 11a, forms a first electrode 14 on a substrate 10.
[0119] In some possible implementations, the material of the substrate 10 is not limited in the embodiments of this application. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials that can be used for oxide semiconductor deposition, such as glass.
[0120] S320, as shown in FIG11b, a gate 13 is formed on the first electrode 14. The gate 13 includes a cutout portion that exposes the surface of the first electrode 14 on the side away from the substrate 10.
[0121] In some possible implementations, a first dielectric layer 31 is also provided between the first electrode 14 and the gate 13. On the one hand, the first dielectric layer 31 is used to electrically isolate the first electrode 14 from the gate 13; on the other hand, the first dielectric layer 31 is also used to define the gate length of the gate 13.
[0122] In some possible implementations, the material of the gate 13 is not limited, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.
[0123] As shown in Figures 11c-11d, in S330, a second gate dielectric layer 122, a first gate dielectric layer 121, and a channel layer 11 are sequentially formed in the cutout portion along the sidewall direction away from the cutout portion. The channel layer 11 is in contact with the first electrode 14.
[0124] As shown in Figure 3, a second electrode 15 is formed on the side of the channel layer 11 away from the first electrode 14.
[0125] In some possible implementations, a second dielectric layer 32 is also provided between the second electrode 15 and the gate 13. On the one hand, the second dielectric layer 32 is used to electrically isolate the second electrode 15 from the gate 13; on the other hand, the second dielectric layer 32 is also used to define the gate length of the gate 13.
[0126] In some possible implementations, the first electrode 14 and the second electrode 15 can be made of the same material, including conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.
[0127] In some embodiments, there are other structural variations for the third case.
[0128] The first deformable structure is prepared by the following process:
[0129] S310, as shown in Figure 11a, forms a first electrode 14 on a substrate 10.
[0130] S320, as shown in FIG11b, a gate 13 is formed on the first electrode 14. The gate 13 includes a cutout portion that exposes the surface of the first electrode 14 on the side away from the substrate 10.
[0131] S331, as shown in FIG12, a second gate dielectric layer 122, a first gate dielectric layer 121, a channel layer 11, and an insulating layer 16 are sequentially formed in the cutout portion along the direction away from the sidewall of the cutout portion. That is, the insulating layer 16 is disposed in the area enclosed by the channel 11. In this way, without changing the outer dimensions of the channel layer 11, the thickness of the channel layer 11 can be reduced by filling the channel layer 11 with the insulating layer 16, thereby improving the gate control capability of the vertical transistor. The channel layer 11 is in contact with the first electrode 14.
[0132] S340, as shown in Figure 4a, forms a second electrode 15 on the side of the channel layer 11 away from the first electrode 14.
[0133] The second type of deformed structure is prepared by the following process:
[0134] S310, as shown in Figure 11a, forms a first electrode 14 on a substrate 10.
[0135] S320, as shown in FIG11b, a gate 13 is formed on the first electrode 14. The gate 13 includes a cutout portion that exposes the surface of the first electrode 14 on the side away from the substrate 10.
[0136] As shown in Figure 13a, in section S332, a second gate dielectric layer 122, a first gate dielectric layer 121, and a sacrificial layer 50 are sequentially formed in the cutout portion along the direction away from the sidewall of the cutout portion, so as to protect the sidewall of the first gate dielectric layer 121 using the sacrificial layer 50. The first gate dielectric layer 121 and the second gate dielectric layer 122 include sidewalls and bottoms, and the bottom of the second gate dielectric layer 122 is in contact with the first electrode 14. The sacrificial layer 50 covers the sidewalls and bottoms of the first gate dielectric layer 121 and the second gate dielectric layer 122, and exposes the third through-hole at the bottom of the second gate dielectric layer 122 and the first gate dielectric layer 121.
[0137] S333, as shown in Figure 13b, the sacrificial layer 50 is removed, and the channel layer 11 is filled in the hollow part. The channel layer 11 is in contact with the first electrode 14 through the third through hole.
[0138] Based on this, as shown in FIG13b, after the channel layer 11 is formed, an insulating layer 16 can be filled in the cutout portion. That is, the insulating layer 16 is disposed in the area enclosed by the channel 11. In this way, without changing the outer dimensions of the channel layer 11, the present application embodiment can reduce the thickness of the channel layer 11 by filling the channel layer 11 with an insulating layer 16, thereby improving the gate control capability of the vertical transistor.
[0139] As shown in Figure 5, in S340, a second electrode 15 is formed on the side of the channel layer 11 opposite to the first electrode 14.
[0140] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the previous embodiment, and will not be repeated here.
[0141] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A chip, characterized in that, The transistor includes a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate electrode, which are stacked sequentially. The channel layer is made of an oxide semiconductor and is in contact with the first gate dielectric layer; the defect concentration of the material of the first gate dielectric layer is lower than that of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than that of the material of the first gate dielectric layer.
2. The chip according to claim 1, characterized in that, The difference between the defect energy level of the material of the first gate dielectric layer and the conduction band electron of the channel layer is greater than the difference between the defect energy level of the material of the second gate dielectric layer and the conduction band electron of the channel layer; and / or, the hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.
3. The chip according to claim 2, characterized in that, The hydrogen content in the material of the first gate dielectric layer is less than 1e 20 atoms / cc.
4. The chip according to any one of claims 1-3, characterized in that, The material of the first gate dielectric layer includes hafnium aluminum oxide and aluminum oxide; and / or, the dielectric constant of the second gate dielectric layer is greater than 15.
5. The chip according to any one of claims 1-4, characterized in that, Along the direction from the first gate dielectric layer to the second gate dielectric layer, the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.
6. The chip according to any one of claims 1-5, characterized in that, The chip also includes a substrate, and the transistor is disposed on the substrate; The transistor further includes a first electrode and a second electrode, both of which are in contact with the channel.
7. The chip according to claim 6, characterized in that, Along the direction from the substrate to the transistor, the gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are sequentially stacked. The transistor further includes a first protective layer, wherein the first protective layer, the first electrode, and the second electrode are all disposed on the side of the channel layer away from the substrate, and the first protective layer is disposed between the channel layer and the first electrode and the second electrode; The first protective layer includes a first through hole and a second through hole spaced apart. The first electrode contacts the channel layer through the first through hole, and the second electrode contacts the channel layer through the second through hole.
8. The chip according to claim 6, characterized in that, Along the direction from the substrate to the transistor, the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are sequentially stacked. The first gate dielectric layer and the second gate dielectric layer are grooved, and the gate electrode is disposed in the groove; the first electrode and the second electrode are disposed on the channel layer and are located on opposite sides of the sidewall of the groove.
9. The chip according to claim 6, characterized in that, Along the direction from the substrate to the transistor, the first electrode and the gate are stacked sequentially. The gate includes a cutout portion, and along the sidewall direction away from the cutout portion, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are stacked sequentially; the second electrode is disposed on the side of the channel layer opposite to the first electrode.
10. The chip according to claim 6, characterized in that, The chip also includes an insulating layer, and the second gate dielectric layer, the first gate dielectric layer, the channel layer, and the insulating layer are stacked sequentially along the sidewall direction away from the cutout portion.
11. The chip according to claim 9 or 10, characterized in that, The first gate dielectric layer and the second gate dielectric layer include sidewalls and a bottom, wherein the bottom of the second gate dielectric layer is in contact with the first electrode; A third through-hole is formed at the bottom of the second gate dielectric layer and the first gate dielectric layer, and the channel layer contacts the first electrode through the third through-hole.
12. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-11, the chip being disposed on the circuit board.
13. A method for fabricating a chip, characterized in that, The chip includes transistors, and the method for fabricating the transistors includes: A channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate are formed on a substrate; the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are stacked sequentially, and the channel layer is in contact with the first gate dielectric layer; wherein, the material of the channel layer includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.
14. The preparation method according to claim 13, characterized in that, The energy difference between the defect level of the first gate dielectric layer material and the conduction band electrons of the channel layer is greater than the energy difference between the defect level of the second gate dielectric layer material and the conduction band electrons of the channel layer; and / or, The hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.
15. The preparation method according to claim 13 or 14, characterized in that, The process of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on the substrate includes: The gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are sequentially formed on the substrate; After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the fabrication method further includes: A first protective layer is formed on the channel layer, the first protective layer including a first through hole and a second through hole arranged at intervals; A first electrode and a second electrode are formed on the first protective layer. The first electrode is in contact with the channel layer through the first through-hole, and the second electrode is in contact with the channel layer through the second through-hole.
16. The preparation method according to claim 13 or 14, characterized in that, The process of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on the substrate includes: The channel layer, the conductive layer, and the second protective layer are sequentially formed on the substrate; the second protective layer includes a fourth via. Under the protection of the second protective layer, a fifth through hole is formed in the conductive layer to obtain the first electrode and the second electrode, and to expose the surface of the channel layer away from the substrate. The first gate dielectric layer, the second gate dielectric layer, and the gate are sequentially formed in the fourth and fifth vias.
17. The preparation method according to claim 13 or 14, characterized in that, Before forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the fabrication method includes: A first electrode is formed on the substrate; The process of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on the substrate includes: A gate is formed on the first electrode, the gate including a cutout portion that exposes the surface of the first electrode on the side opposite to the substrate; Along the sidewall direction away from the cutout portion, a second gate dielectric layer, a first gate dielectric layer, and a channel layer are sequentially formed in the cutout portion; the channel layer is in contact with the surface of the first electrode on the side away from the substrate; After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the fabrication method further includes: A second electrode is formed on the side of the channel layer opposite to the first electrode.
18. The preparation method according to claim 17, characterized in that, After forming the second gate dielectric layer, the first gate dielectric layer, and the channel layer sequentially in the hollow portion along a direction away from the sidewall of the hollow portion, the fabrication method further includes: An insulating layer is filled in the hollow portion, and the insulating layer is located on the side of the channel layer opposite to the first gate dielectric layer.
19. The preparation method according to claim 17 or 18, characterized in that, The process of sequentially forming a second gate dielectric layer, a first gate dielectric layer, and a channel layer in the hollow portion along a direction away from the sidewall of the hollow portion includes: Along the direction away from the sidewall of the cutout, a second gate dielectric layer, a first gate dielectric layer, and a sacrificial layer are sequentially formed in the cutout; the first gate dielectric layer and the second gate dielectric layer include sidewalls and bottoms, and the bottom of the second gate dielectric layer is in contact with the first electrode; the sacrificial layer covers the sidewalls and bottoms of the first gate dielectric layer and the second gate dielectric layer, and exposes a third through-hole at the bottom of the second gate dielectric layer and the first gate dielectric layer; The sacrificial layer is removed, and a channel layer is filled in the hollow portion, the channel layer being in contact with the first electrode through the third through hole.