Semiconductor integrated circuit device

Abstract

Provided is a layout structure of a capacitive cell in which a forksheet FET and rear-surface wiring are used. The capacitive cell is provided with nanosheet FETs (P1, P2, N1, N2). The surfaces of nanosheets (21a, 21b) on sides facing the nanosheet FETs (N1, N2), or on the sides opposite therefrom, are exposed from gate wiring (31, 32). Power supply wiring (11) for supplying a VDD extends in an X direction on a rear-surface-side wiring layer and overlaps the nanosheet FETs (P1, P2) in plan view. The power supply wiring (11) is connected to the source and the drain of the nanosheet FETs (P1, P2) via vias (61) provided at positions that overlap in plan view. A VSS is supplied to the gate wiring (31, 32).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device having standard cells including a forksheet FET (Field Effect Transistor), which is a nanosheet FET having a fork-shaped gate electrode.

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. One such transistor that has attracted attention is the nanosheet FET.

[0004] Patent Document 1 discloses a standard cell, particularly a capacitor cell structure, that uses a fork sheet FET, which is a nanosheet FET having a fork-shaped gate electrode, in order to reduce the area of ​​a semiconductor integrated circuit device.

[0005] Japanese Patent Application Laid-Open No. 2003-144222 discloses a standard cell in which wiring is provided on the back surface directly below a transistor and the source / drain of the transistor is connected to this wiring in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] International Publication No. 2021 / 171969 U.S. Patent Application Publication No. 2022 / 0375761

[0007] However, the layout structure of a capacitance cell using a fork sheet FET and backside wiring has not been considered.

[0008] The present disclosure aims to provide a layout structure of a capacitance cell using a fork sheet FET and backside wiring.

[0009] A semiconductor integrated circuit device according to an aspect of the present disclosure includes a standard cell that is a capacitive cell, the standard cell including a first nanosheet FET (Field Effect Transistor) of a first conductivity type that includes a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type that includes a second nanosheet extending in the first direction; a first gate wiring that extends in a second direction perpendicular to the first direction, overlaps the first nanosheet in a planar view, and surrounds the periphery of the first nanosheet in the second direction and in a depth direction; a second gate wiring that extends in the second direction, overlaps the second nanosheet in a planar view, and surrounds the periphery of the second nanosheet in the second direction and in the depth direction; and a first power supply voltage that is formed in a first wiring layer on the back side of the first nanosheet FET, extends in the first direction, overlaps the first nanosheet FET in a planar view, and the first nanosheet and the second nanosheet are opposed to each other in the second direction, the first nanosheet has a first side surface in the second direction exposed from the first gate wiring, the second nanosheet has a second side surface opposite to the first side in the second direction exposed from the second gate wiring, the first power supply wiring is connected to the source and drain of the first nanosheet FET via a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a planar view, and a second power supply voltage is supplied to the first gate wiring.

[0010] According to this aspect, the first nanosheet FET includes a first nanosheet. A first power supply wiring that supplies a first power supply voltage is formed on the back side of the first nanosheet FET and overlaps the first nanosheet FET in a planar view. The source and drain of the first nanosheet FET are connected to the first power supply wiring via a first via. A second power supply voltage is supplied to the first gate wiring that serves as the gate of the first nanosheet FET. This allows the first nanosheet FET to function as a capacitor. The first and second nanosheet FETs are fork-sheet FETs, which allows the spacing between them in the second direction or the spacing between them and nanosheet FETs of other standard cells adjacent in the second direction to be narrowed. Furthermore, because the first power supply wiring overlaps the first nanosheet FET in a planar view and the source and drain of the first nanosheet are connected to the first power supply wiring via a via, the area of ​​the layout structure is reduced. Therefore, the area of ​​the capacitor cell can be reduced.

[0011] According to the present disclosure, it is possible to provide a layout structure of a capacitance cell using a fork sheet FET and backside wiring.

[0012] 1A and 1B are cross-sectional views in the vertical direction of the layout structure of FIG. 1A; FIG. 1C is a circuit diagram of the capacitance cell of FIG. 1A; and FIG. 1B are plan views showing an example of a layout structure of an inverter cell. FIG. 1C is a plan view showing an example of a cell row in which capacitance cells and inverter cells according to the first embodiment are arranged. FIG. 1D is a plan view showing an example of a layout structure of a capacitance cell according to a first modification of the first embodiment. FIG. 1E is a plan view showing an example of a layout structure of a capacitance cell according to a second modification of the first embodiment. 12. Plan views showing an example of the layout structure of a capacitance cell according to the third embodiment. (a) and (b) are plan views showing an example of the layout structure of an inverter cell. Plan views showing an example of the configuration of a cell row in which capacitance cells and inverter cells according to the third embodiment are arranged. Plan views showing an example of the layout structure of a capacitance cell according to a first modification of the third embodiment. Plan views showing an example of the layout structure of a capacitance cell according to a second modification of the third embodiment. Plan views showing an example of the layout structure of a capacitance cell according to a fourth embodiment. Plan views showing an example of the layout structure of a capacitance cell according to a fourth modification of the fourth embodiment.

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells), and at least some of the plurality of standard cells include nanosheet FETs. In the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs having fork-shaped gate electrodes.

[0014] In the plan views and cross-sectional views of the following embodiments, the description of each insulating film, etc. may be omitted. Furthermore, in this specification, expressions such as "same size" that mean that the size, etc., is the same are assumed to include the range of manufacturing variations.

[0015] In the following embodiments, "VDD" and "VSS" are used to indicate a power supply voltage or the power supply itself.

[0016] 1 to 3 are diagrams showing an example of a layout structure of a capacitance cell included in a semiconductor integrated circuit device according to a first embodiment, in which Fig. 1 is a plan view, Fig. 2 is a cross-sectional view in the horizontal direction as viewed in a plane, and Figs. 3(a) and 3(b) are cross-sectional views in the vertical direction as viewed in a plane. Fig. 2 is a cross-section along line X1-X1', Fig. 3(a) is a cross-section along line Y1-Y1', and Fig. 3(c) is a cross-section along line Y2-Y2'.

[0017] In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). The dotted lines running vertically and horizontally in plan views such as FIG. 1 and the dotted lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also differ for each layer. Furthermore, components do not necessarily need to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange components on a grid.

[0018] Fig. 4 is a circuit diagram of the capacitance cell shown in Figs. 1 to 3. As shown in Fig. 4, the capacitance cell shown in Figs. 1 to 3 has P-type transistors P1 and P2 and N-type transistors N1 and N2. The P-type transistors P1 and P2 have their sources and drains connected to VDD and their gates connected to VSS. The N-type transistors N1 and N2 have their sources and drains connected to VSS and their gates connected to VDD.

[0019] In the P-type transistors P1 and P2, a capacitance is formed via the gate oxide film between the gate connected to VSS and the source and drain connected to VDD, while in the N-type transistors N1 and N2, a capacitance is formed via the gate oxide film between the gate connected to VDD and the source and drain connected to VSS.

[0020] 1 to 3 are arranged in the X direction together with other standard cells, with their cell frames in contact, to form a cell row. Furthermore, multiple cell rows are arranged in the Y direction with their cell frames in contact. However, every other cell row is flipped upside down.

[0021] As shown in FIG. 1 and other figures, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The BM0 wiring layer is a wiring layer provided on the back side of the transistors in a semiconductor chip. The power supply wiring 11 supplies VDD, and the power supply wiring 12 supplies VSS. The power supply wirings 11 and 12 are shared with capacitance cells and other standard cells in the cell row, and serve as power supply wiring extending in the X direction. The power supply wirings 11 and 12 are also shared between cell rows adjacent to each other in the Y direction.

[0022] Here, in a semiconductor chip, the back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked, and the side on which local wiring, metal wiring, etc. connected to the transistor are stacked is called the front side of the transistor.

[0023] In the capacitance cell shown in FIG. 1 etc., an active region 2P that constitutes the channel, source, and drain of a P-type nanosheet FET that becomes P-type transistors P1 and P2 is formed above the power supply wiring 11. The active region 2P overlaps with the power supply wiring 11 in a planar view. The active region 2P includes nanosheets 21a and 21b that become the channel of the P-type nanosheet FET. In addition, portions 22a, 22b, and 22c of the active region 2P that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 11 via a via 61 formed on the back surface thereof. The via 61 overlaps with the power supply wiring 11 and the active region 2P in a planar view.

[0024] Gate wirings 31 and 32 are formed extending in parallel in the Y direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21a in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 21a facing the transistors N1 and N2 in the Y direction is not covered by the gate wiring 31 and is exposed from the gate wiring 31. The gate wiring 31 serves as the gate of transistor P1. The gate wiring 32 surrounds the outer periphery of the nanosheet 21b in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 21b facing the transistors N1 and N2 in the Y direction is not covered by the gate wiring 32 and is exposed from the gate wiring 32. The gate wiring 32 serves as the gate of transistor P2. In addition, a dummy gate wiring 35 that does not constitute a transistor is formed on the left side of the gate wiring 31 in the drawing.

[0025] An active region 2N that constitutes the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistors N1 and N2 is formed above the power supply wiring 12. The active region 2N overlaps with the power supply wiring 12 in a planar view. The active region 2N includes nanosheets 23a and 23b that become the channel of the N-type nanosheet FET. Furthermore, portions 24a, 24b, and 24c of the active region 2N that become the source or drain of the N-type nanosheet FET are connected to the power supply wiring 12 via a via 62 formed on the back surface thereof. The via 62 overlaps with the power supply wiring 12 and the active region 2N in a planar view.

[0026] Gate wirings 33 and 34 are formed extending in parallel in the Y direction. The gate wiring 33 surrounds the outer periphery of the nanosheet 23a in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 23a facing the transistors P1 and P2 in the Y direction is not covered by the gate wiring 33 and is exposed from the gate wiring 33. The gate wiring 33 serves as the gate of transistor N1. The gate wiring 34 surrounds the outer periphery of the nanosheet 23b in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 23b facing the transistors P1 and P2 in the Y direction is not covered by the gate wiring 34 and is exposed from the gate wiring 34. The gate wiring 34 serves as the gate of transistor N2. In addition, a dummy gate wiring 36 that does not constitute a transistor is formed to the right of the gate wiring 34 in the drawing.

[0027] The dummy gate wiring 35 and the gate wiring 33 are aligned in a line in the Y direction. The gate wiring 31 and the gate wiring 34 are aligned in a line in the Y direction. The gate wiring 32 and the dummy gate wiring 36 are aligned in a line in the Y direction. Dummy gate wirings 37a and 38a extending in the Y direction are formed at the left and right ends of the capacitance cell in the drawing. The dummy gate wirings 37a and 38a include bridge portions.

[0028] The gate wirings 31, 32, 33, and 34 and the dummy gate wirings 35, 36, 37a, and 38a are formed with the same width. The dummy gate wirings 37a and 35, the gate wirings 31 and 32, and the dummy gate wiring 38a are arranged at the same pitch. The dummy gate wiring 37a, the gate wirings 33 and 34, and the dummy gate wirings 36 and 38a are arranged at the same pitch.

[0029] The size of the active regions 2P and 2N in the Y direction is w1. In the capacitance cell, the capacitance value can be increased by increasing the size of the active region in the Y direction.

[0030] Furthermore, the distance d1 between the active region 2P and the active region 2N is smaller than the distance d2 between the power supply wiring 11 and the power supply wiring 12 (d1<d2). That is, in plan view, in the Y direction, the inner edge of the cell of the active region 2P is closer to the cell center than the inner edge of the cell of the power supply wiring 11, and the inner edge of the cell of the active region 2N is closer to the cell center than the inner edge of the cell of the power supply wiring 12.

[0031] Local wirings 41, 42, 43, 44, 45, and 46 are formed extending in the Y direction. The local wirings 42, 44, and 46 contact portions 22a, 22b, and 22c in the active region 2P, respectively. The local wirings 41, 43, and 45 contact portions 24a, 24b, and 24c in the active region 2N, respectively. The local wiring 41 extends to a location where it overlaps with the power supply wiring 11 in a planar view. The local wiring 46 extends to a location where it overlaps with the power supply wiring 12 in a planar view.

[0032] In the M0 wiring layer, metal wirings 51, 52, 53, and 54 extending in the X direction are formed. The M0 wiring layer is a wiring layer provided on the surface side of the transistor. The metal wiring 51 is connected to the local wiring 41 and the gate wirings 31 and 32 through vias. The metal wiring 52 is connected to the local wiring 46 through a via. The metal wiring 53 is connected to the local wiring 41 through a via. The metal wiring 54 is connected to the local wiring 46 and the gate wirings 33 and 34 through vias.

[0033] Gate wirings 31 and 32, which serve as the gates of transistors P1 and P2, receive VSS from power supply wiring 12 via active region 2N, local wiring 41, and metal wiring 51. Gate wirings 33 and 34, which serve as the gates of transistors N1 and N2, receive VDD from power supply wiring 11 via active region 2P, local wiring 46, and metal wiring 54.

[0034] In the capacitor cell shown in FIG. 1, each transistor P1, P2, N1, and N2 is a fork-sheet FET. That is, each transistor is a nanosheet FET, and the nanosheet is exposed from the gate wiring on the side where the P-type transistor and the N-type transistor face each other. Therefore, overlap of the gate wiring is not required on the side where the P-type transistor and the N-type transistor face each other, so the active region 2P and the active region 2N can be arranged closely. This allows the capacitor cell to be reduced in area. Note that the distance between the active region 2P and the active region of another cell (not shown) arranged above the drawing, and the distance between the active region 2N and the active region of another cell (not shown) arranged below the drawing, are greater than the distance d1 between the active region 2P and the active region 2N.

[0035] 1 and other figures, power is supplied to the sources and drains of the transistors P1, P2, N1, and N2 from power supply wiring 11 and 12 formed in the BM0 wiring layer. That is, in the active region 2P, VDD is supplied to portions 22a, 22b, and 22c, which serve as the sources or drains of the P-type transistors P1 and P2, via a via 61 from the power supply wiring 11 formed on their back surfaces. The via 61 is positioned to overlap the power supply wiring 11 and portions 22a, 22b, and 22c in a planar view. VSS is supplied to portions 24a, 24b, and 24c, which serve as the sources or drains of the N-type transistors N1 and N2, via a via 62 from the power supply wiring 12 formed on their back surfaces. The via 62 is positioned to overlap the power supply wiring 12 and portions 24a, 24b, and 24c in a planar view.

[0036] This configuration reduces the area of ​​the layout structure of the capacitance cell. Therefore, the area of ​​the capacitance cell can be reduced. Furthermore, the resistance values ​​in the path from the VDD power supply wiring 11 in the BM0 wiring layer to the nanosheets 21a and 21b of the transistors P1 and P2, and in the path from the VSS power supply wiring 12 in the BM0 wiring layer to the nanosheets 23a and 23b of the transistors N1 and N2, can be reduced. Therefore, the high-speed response of the capacitance formed by the capacitance cell can be improved.

[0037] Furthermore, the via 61 connecting the power supply wiring 11 to the portions 22a, 22b, and 22c is preferably provided in the center of the active region 2P in the Y direction. This allows current to flow evenly in the Y direction through the nanosheets 21a and 21b, allowing the capacitance to function effectively. Furthermore, the via 62 connecting the power supply wiring 12 to the portions 24a, 24b, and 24c is preferably provided in the center of the active region 2N in the Y direction. This allows current to flow evenly in the Y direction through the nanosheets 23a and 23b, allowing the capacitance to function effectively.

[0038] 1 and other figures, gate wirings 31 and 32, which serve as the gates of P-type transistors P1 and P2, are supplied with VSS from M0 wiring 51 via a via. This via is preferably provided in a position that includes a range in the Y direction in plan view where the gate wirings 31 and 32 do not overlap with the nanosheets 21a and 21b. This reduces the resistance in the path from M0 wiring 51 to the portion of the gate wirings 31 and 32 that surrounds nanosheets other than the topmost nanosheet. This improves the high-speed response of the capacitance formed by the capacitance cell.

[0039] Similarly, the gate wirings 33 and 34 that serve as the gates of the N-type transistors N1 and N2 are supplied with VDD from the M0 wiring 54 through a via. This via is preferably provided in a position that includes a range in the Y direction in plan view where the gate wirings 33 and 34 do not overlap with the nanosheets 23a and 23b. This makes it possible to suppress the resistance value in the path from the M0 wiring 54 to the portion of the gate wirings 33 and 34 that surrounds nanosheets other than the uppermost nanosheet.

[0040] In the M0 wiring layer, VDD is applied to the metal wiring 52, and VSS is applied to the metal wiring 53. Therefore, in the M0 wiring layer, VSS wiring and VDD wiring are alternately arranged adjacent to each other, and a capacitance is formed between these wirings. This allows the capacitance value of the capacitance cell to be increased. Note that the metal wirings 52 and 53 may be omitted in the M0 wiring layer.

[0041] 5A and 5B are plan views showing an example of the layout structure of an inverter cell. The inverter cell is an example of another standard cell included in the semiconductor integrated circuit device according to this embodiment. 5A and 5B have basically the same layout structure, but the sizes in the Y direction of the active regions that form the channel, source, and drain of the transistor are different.

[0042] In the inverter cell 1 shown in Figure 5(a), an active region 2P1 that constitutes the channel, source, and drain of a P-type nanosheet FET is formed above the power wiring 11. The active region 2P1 overlaps the power wiring 11 in a planar view. The active region 2P1 includes a nanosheet 25 that serves as the channel of the P-type nanosheet FET. In addition, a portion 26a of the active region 2P1 that serves as the source of the P-type nanosheet FET is connected to the power wiring 11 through a via 63 formed on its back surface.

[0043] An active region 2N1 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 12. The active region 2N1 overlaps the power supply wiring 12 in a planar view. The active region 2N1 includes a nanosheet 27 that serves as the channel of the N-type nanosheet FET. In addition, a portion 28a of the active region 2N1 that serves as the source of the N-type nanosheet FET is connected to the power supply wiring 12 via a via 64 formed on the back surface thereof.

[0044] A gate wiring 38a is formed extending in the Y direction. The gate wiring 38a surrounds the outer periphery of the nanosheet 25 in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 25 on the active region 2N1 side in the Y direction is not covered by the gate wiring 38a and is exposed from the gate wiring 38a.

[0045] A gate wiring 38b is formed extending in the Y direction. The gate wiring 38b surrounds the outer periphery of the nanosheet 27 in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet 27 on the active region 2P1 side in the Y direction is not covered by the gate wiring 38b and is exposed from the gate wiring 38b.

[0046] The gate wiring 38a and the gate wiring 38b are aligned in a line in the Y direction. The gate wiring 38a and the gate wiring 38b are connected via a bridge portion 38c.

[0047] The size w1 in the Y direction of the active regions 2P1 and 2N1 is the same as the size w1 in the Y direction of the active regions 2P and 2N in the capacitance cell shown in FIG.

[0048] A local wiring 47 is formed extending in the Y direction. The local wiring 47 is in contact with the portion 26b in the active region 2P1 and the portion 28b in the active region 2N1.

[0049] In the M0 wiring layer, metal wirings 55 and 56 extending in the X direction are formed. The metal wiring 55 is connected to the gate wiring 38b through a via. The metal wiring 55 serves as the input A of the inverter. The metal wiring 56 is connected to the local wiring 47 through a via. The metal wiring 56 serves as the output Y of the inverter.

[0050] The inverter cell 2 shown in Figure 5(b) has the same layout structure as the inverter cell 1 shown in Figure 5(a). However, the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in Figure 5(a) (w2<w1). That is, the size in the Y direction of the nanosheet 25A is smaller than that of the nanosheet 25. Furthermore, the size in the Y direction of the nanosheet 27A is smaller than that of the nanosheet 27. Therefore, the drive capability of the inverter cell 2 is smaller than that of the inverter cell 1.

[0051] 6 is a plan view showing an example of the configuration of a cell string in this embodiment. In FIG. 6, in a cell string CR, a cell C1 which is the inverter cell 1 shown in FIG. 5(a), a cell C3 which is the capacitance cell shown in FIG. 1, and a cell C2 which is the inverter cell 2 shown in FIG. 5(b) are arranged side by side.

[0052] 6, the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a and 21b constituting the P-type nanosheet FET of cell C3.

[0053] Similarly, the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a and 23b constituting the N-type nanosheet FET of cell C3.

[0054] Furthermore, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same end position on the N-type nanosheet FET side in the Y direction. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same end position on the P-type nanosheet FET side in the Y direction. That is, the positions of the nanosheet surfaces exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0055] In a fork-sheet FET, the nanosheets facing each other and exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row in which cells are aligned in the X direction, as shown in Figure 6, the positions of the nanosheet surfaces exposed from the gate wiring can be aligned in the Y direction to make the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0056] 7 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment. The layout structure according to this modification has a configuration basically similar to that of the layout structure according to the first embodiment. However, the connection relationship between the M0 wiring and the gate wiring, local wiring, etc. is different from that of the first embodiment.

[0057] That is, the M0 wiring 51 is connected to the power supply wiring 11 in the B-M0 wiring layer through a via, and is also connected to the local wiring 46 through a via. The M0 wiring 51 is not connected to the local wiring 41. The M0 wiring 52 is connected to the local wiring 41 through a via, and is also connected to the gate wirings 31 and 32 through vias.

[0058] The M0 wiring 53 is connected to the local wiring 46 through a via hole, and also connected to the gate wirings 33 and 34 through via holes. The M0 wiring 54 is connected to the power supply wiring 12 in the B-M0 wiring layer through a via hole, and also connected to the local wiring 41 through a via hole. The M0 wiring 54 is not connected to the local wiring 46.

[0059] In this modification, VSS is supplied to the gate wirings 31 and 32 from the power supply wiring 12 via a route that goes through the M0 wiring 54, the local wiring 41, and the M0 wiring 52. VDD is supplied to the gate wirings 33 and 34 from the power supply wiring 11 via the route that goes through the M0 wiring 51, the local wiring 46, and the M0 wiring 53. Therefore, the resistance value in the power supply path to the transistor gates is reduced compared to the layout structure of the first embodiment, improving the high-speed response of the capacitance.

[0060] In the layout structure of FIG. 7, the BM0 wiring and the M0 wiring are directly connected through vias, but instead, the BM0 wiring and the M0 wiring may be connected via local wiring.

[0061] 8 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 2 of this embodiment, and FIG. 9 is a circuit diagram of the capacitance cell shown in FIG.

[0062] 9, the capacitance cell shown in FIG. 8 has P-type transistors P1, P2, and P3 and N-type transistors N1, N2, and N3. The P-type transistors P1, P2, and P3 are connected in series between VSS and VDD. The sources and drains of the N-type transistors N1, N2, and N3 are connected to VSS. The gates of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are all connected to VDD.

[0063] In the N-type transistors N1, N2, and N3, a capacitance is formed via the gate oxide film between the gate connected to VDD and the source and drain connected to VSS.

[0064] 8, an active region 2P3 that constitutes the channel, source, and drain of a P-type nanosheet FET that becomes P-type transistors P1, P2, and P3 is formed above the power supply wiring 11. The active region 2P3 overlaps the power supply wiring 11 in a planar view. The active region 2P3 includes nanosheets 121a, 121b, and 121c that become the channel of the P-type nanosheet FET. In addition, a portion 122d of the active region 2P3 that becomes the source of the P-type nanosheet FET that becomes P-type transistor P3 is connected to the power supply wiring 11 via a via formed on its back surface.

[0065] Gate wirings 131a, 132a, and 133a are formed extending in parallel in the Y direction. The gate wirings 131a, 132a, and 133a surround the outer peripheries of the nanosheets 121a, 121b, and 121c in the Y and Z directions via a gate insulating film (not shown). However, the surfaces of the nanosheets 121a, 121b, and 121c facing the transistors N1, N2, and N3 in the Y direction are not covered by the gate wirings 131a, 132a, and 133a and are exposed from the gate wirings 131a, 132a, and 133a. The gate wirings 131a, 132a, and 133a serve as the gates of the transistors P1, P2, and P3.

[0066] An active region 2N3 that constitutes the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistors N1, N2, and N3 is formed above the power supply wiring 12. The active region 2N3 overlaps the power supply wiring 12 in a planar view. The active region 2N3 includes nanosheets 123a, 123b, and 123c that become the channel of the N-type nanosheet FET. In addition, in the active region 2N3, portions 124a, 124b, 124c, and 124d that become the source and drain of the N-type nanosheet FET that becomes the N-type transistors N1, N2, and N3 are connected to the power supply wiring 12 via vias formed on the back surface thereof.

[0067] Gate wirings 131b, 132b, and 133b are formed extending in parallel in the Y direction. The gate wirings 131b, 132b, and 133b surround the outer peripheries of the nanosheets 123a, 123b, and 123c in the Y and Z directions via a gate insulating film (not shown). However, the surfaces of the nanosheets 123a, 123b, and 123c facing the transistors P1, P2, and P3 in the Y direction are not covered by the gate wirings 131b, 132b, and 133b, and are exposed from the gate wirings 131b, 132b, and 133b. The gate wirings 131b, 132b, and 133b serve as the gates of the transistors N1, N2, and N3.

[0068] The gate wiring 131a and the gate wiring 131b are aligned in a line in the Y direction and are connected via a bridge portion 131c. The gate wiring 132a and the gate wiring 132b are aligned in a line in the Y direction and are connected via a bridge portion 132c. The gate wiring 133a and the gate wiring 133b are aligned in a line in the Y direction and are connected via a bridge portion 133c.

[0069] Local interconnects 141, 142, 143, 144, 145, and 146 are formed extending in the Y direction. Local interconnect 141 contacts portion 122a in active region 2P3 and portion 124a in active region 2N3. Local interconnects 142 and 144 contact portions 122b and 122c in active region 2P3, respectively. Local interconnects 143 and 145 contact portions 124b and 124c in active region 2N3, respectively. Local interconnect 146 contacts portion 122d in active region 2P3 and portion 124d in active region 2N3.

[0070] In the M0 wiring layer, metal wirings 151, 152, 153, and 154 extending in the X direction are formed. The metal wiring 151 is connected to the local wiring 141 through a via. The metal wiring 152 is connected to the local wiring 146 and the gate wirings 131a, 132a, and 133a through vias. The metal wiring 153 is connected to the local wiring 146 through a via. The metal wiring 154 is connected to the gate wiring 131b through a via.

[0071] Gate wirings 131a, 132a, and 133a, which serve as the gates of transistors P1, P2, and P3, are supplied with VDD from the power supply wiring 11 via the active region 2P3, local wiring 146, and metal wiring 152. Gate wirings 131b, 132b, and 133b, which serve as the gates of transistors N1, N2, and N3, are connected to gate wirings 131a, 132a, and 133a via bridge sections 131c, 132c, and 133c, respectively, and are therefore supplied with VDD.

[0072] This modification provides the same effects as the first embodiment. That is, each of the transistors P1, P2, P3, N1, N2, and N3 is a fork-sheet FET. Therefore, the active region 2P3 and the active region 2N3 can be arranged close to each other. This allows the area of ​​the capacitance cell to be reduced.

[0073] Furthermore, VSS is supplied to the portions 124a, 124b, 124c, and 124d in the active region 2N3 that serve as the source or drain of the N-type transistors N1, N2, and N3 through vias from the power supply wiring 12 formed on their back surfaces. This configuration reduces the area of ​​the layout structure of the capacitor cell, thereby achieving a smaller area for the capacitor cell. Furthermore, the resistance value in the path from the VSS power supply wiring 12 to the nanosheets 123a, 123b, and 123c of the transistors N1, N2, and N3 can be suppressed. This improves the high-speed response of the capacitor.

[0074] 10 is a plan view showing an example of a layout structure of a capacitance cell included in a semiconductor integrated circuit device according to a second embodiment, and FIG. 11 is a circuit diagram of the capacitance cell shown in FIG.

[0075] 11, the capacitance cell shown in FIG. 10 has P-type transistors P1 and P2 and N-type transistors N1 and N2. Transistors P2 and N1 form a fixed value output section. The fixed value output section outputs a low fixed value (VSS) to node X1 and a high fixed value (VDD) to node X2. The source of transistor P2 is connected to VDD, the drain is connected to the gate of transistor N1, and the gate is connected to the drain of transistor N1. The source of transistor N1 is connected to VSS, and the drain is connected to the gate of transistor P2. The gate of transistor P2 corresponds to node X1, and the gate of transistor N1 corresponds to node X2.

[0076] The source and drain of transistor P1 are connected to VDD, and the gate is connected to node X1. Since VSS is output from the fixed value output unit to node X1, transistor P1 functions as a capacitor. The source and drain of transistor N2 are connected to VSS, and the gate is connected to node X2. Since VDD is output from the fixed value output unit to node X2, transistor N2 functions as a capacitor.

[0077] The transistor P2 functions as a capacitor because its source is connected to VDD, its drain is connected to node X2 (=VDD), and its gate is connected to node X1 (=VSS). The transistor N1 functions as a capacitor because its source is connected to VSS, its drain is connected to node X1 (=VSS), and its gate is connected to node X2 (=VDD).

[0078] The layout structure of the capacitance cell shown in Fig. 10 is substantially the same as the layout structure of the capacitance cell shown in Fig. 1. However, in the layout structure of Fig. 10, in the active region 2P, a portion 22c that serves as the drain of the P-type transistor P2 is not connected to the power supply wiring 11. That is, the via 61 that connects the power supply wiring 11 and the portion 22c in Fig. 1 is omitted in Fig. 10. Also, in the active region 2N, a portion 24a that serves as the drain of the N-type transistor N1 is not connected to the power supply wiring 12. That is, the via 62 that connects the power supply wiring 12 and the portion 24a in Fig. 1 is omitted in Fig. 10.

[0079] According to this embodiment, similarly to the first embodiment, it is possible to realize a reduction in the area of ​​the capacitor cell, and also to improve the high-speed response of the capacitor.

[0080] The layout structure of the capacitance cell according to Modification 1 of the first embodiment shown in Fig. 7 can also be modified in the same manner as in this embodiment. That is, by omitting the via connecting the power supply wiring 11 to the portion 22c of the active region 2P and the via connecting the power supply wiring 12 to the portion 24a of the active region 2N from the layout structure of Fig. 7, the capacitance cell shown in Fig. 11 can be realized.

[0081] 12 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment, and FIG. 13 is a circuit diagram of the capacitance cell shown in FIG.

[0082] As shown in FIG. 13, the capacitance cell shown in FIG. 12 has P-type transistors P1, P2, and P3 and N-type transistors N1, N2, and N3. Transistors P1 and N2 form a fixed value output section. The fixed value output section outputs a low fixed value (VSS) to node X1 and a high fixed value (VDD) to node X2. The source of transistor P1 is connected to VDD, the drain is connected to the gate of transistor N2, and the gate is connected to the drain of transistor N2. The source of transistor N2 is connected to VSS, and the drain is connected to the gate of transistor P1. The gate of transistor P1 corresponds to node X1, and the gate of transistor N2 corresponds to node X2.

[0083] The source of transistor N2 is connected to VSS and the drain is connected to node X1 (=VSS). The source and drain of transistor N3 are connected to VSS. Since the gates of transistors N2 and N3 are connected to node X2 (=VDD), they function as capacitors.

[0084] The transistor P1 has a source connected to VDD, a drain connected to a node X2 (=VDD), and a gate connected to a node X1 (=VSS), so that the transistor P1 functions as a capacitor.

[0085] The layout structure of the capacitance cell shown in Fig. 12 is similar to the layout structure according to the second modification of the first embodiment shown in Fig. 8. Specifically, in the layout structure of Fig. 12, the configurations of the power supply wiring, the active region, and the gate wiring are the same as those in Fig. 8.

[0086] In the active region 2P3, of the portions 122a, 122b, 122c, and 122d, the portions 122a, 122c, and 122d are connected to the power supply wiring 11 through vias. The portion 122b is not connected to the power supply wiring 11. In the active region 2N3, of the portions 124a, 124b, 124c, and 124d, the portions 124a, 124c, and 124d are connected to the power supply wiring 12 through vias. The portion 124b is not connected to the power supply wiring 12.

[0087] Local interconnections 241, 242, 243, 244, 245, 246, 247, and 248 are formed extending in the Y direction. The local interconnections 241, 242, 243, and 244 contact the portions 122a, 122b, 122c, and 122d in the active region 2P3, respectively. The local interconnections 245, 246, 247, and 248 contact the portions 124a, 124b, 124c, and 124d in the active region 2N3, respectively.

[0088] In the M0 wiring layer, metal wirings 251 and 252 extending in the X direction are formed. The metal wiring 251 is connected to the local wiring 242 and the gate wirings 132a and 133a through vias. The metal wiring 252 is connected to the local wiring 246 and the gate wiring 131b through vias.

[0089] According to this modification, similar to the second modification of the first embodiment, it is possible to reduce the area of ​​the capacitor cell, and also to improve the high-speed response of the capacitor.

[0090] (Third embodiment) In the first embodiment described above, in the capacitance cell, the nanosheet of the nanosheet FET is exposed from the gate wiring on the side where the P-type transistor and the N-type transistor face each other. In contrast, in the third embodiment, in the capacitance cell, the nanosheet of the nanosheet FET is exposed from the gate wiring on the side facing the cell frame. This allows the active region to be arranged close to the cell frame, thereby reducing the area of ​​the capacitance cell.

[0091] Fig. 14 is a plan view showing an example of the layout structure of a capacitance cell included in a semiconductor integrated circuit device according to the third embodiment. The circuit diagram of the capacitance cell shown in Fig. 14 is as shown in Fig. 4. The capacitance cell shown in Fig. 14 has the same configuration as the capacitance cells shown in Figs. 1 to 3, and components common to Figs. 1 to 3 are assigned the same reference numerals as in Figs. 1 to 3, and detailed description thereof may be omitted here.

[0092] 1, in the layout structure of Fig. 14, the position of active region 2P is closer to the upper side of the drawing in the Y direction, and the position of active region 2N is closer to the lower side of the drawing in the Y direction. For example, the distance d3 between active region 2P and the cell frame on the upper side of the drawing, and the distance d4 between active region 2N and the cell frame on the lower side of the drawing, are smaller than 1 / 2 of the distance d5 between active region 2P and active region 2N (d3, d4 < d5 / 2).

[0093] In the active region 2P, the surface of nanosheet 21a on the upper side in the Y direction in the drawing is not covered by gate wiring 31 and is exposed from gate wiring 31. Furthermore, the surface of nanosheet 21b on the upper side in the Y direction in the drawing is not covered by gate wiring 32 and is exposed from gate wiring 32. In the active region 2N, the surface of nanosheet 23a on the lower side in the Y direction in the drawing is not covered by gate wiring 33 and is exposed from gate wiring 33. Furthermore, the surface of nanosheet 23b on the lower side in the Y direction in the drawing is not covered by gate wiring 34 and is exposed from gate wiring 34. The size of active regions 2P and 2N in the Y direction is w1.

[0094] In the capacitor cell shown in FIG. 14 , the nanosheet of the P-type transistor is exposed from the gate wiring on the side opposite the side facing the N-type transistor, in other words, on the side facing the transistor of another cell located at the top of the drawing. Therefore, since overlap of the gate wiring is not required on the side facing the transistor of another cell, the active region 2P can be placed close to the active region of the other cell. Similarly, the nanosheet of the N-type transistor is exposed from the gate wiring on the side opposite the side facing the P-type transistor, in other words, on the side facing the transistor of another cell located at the bottom of the drawing. Therefore, since overlap of the gate wiring is not required on the side facing the transistor of another cell, the active region 2N can be placed close to the active region of the other cell. This allows the capacitor cell to be reduced in area.

[0095] Other configurations of the capacitance cell in Fig. 14 are similar to those of the capacitance cells shown in Fig. 1 to Fig. 3. Therefore, the capacitance cell in Fig. 14 can provide the same effects as those of the capacitance cells shown in Fig. 1 to Fig. 3.

[0096] 15(a) and 15(b) are plan views showing an example of the layout structure of an inverter cell. The inverter cell is an example of another standard cell included in the semiconductor integrated circuit device according to this embodiment. The inverter cell shown in FIGS. 15(a) and 15(b) has a configuration similar to that of the inverter cell shown in FIGS. 5(a) and 5(b). Components common to those in FIGS. 5(a) and 5(b) are assigned the same reference numerals as those in FIGS. 5(a) and 5(b), and detailed descriptions thereof may be omitted here.

[0097] 15(a) and 15(b) have basically the same layout structure, but as with FIGS. 5(a) and 5(b), the sizes in the Y direction of the active regions that form the channel, source, and drain of the transistor are different. In the inverter cell 1 shown in FIG. 15(a), the size w1 in the Y direction of the active regions 2P1 and 2N1 is the same as the size w1 in the Y direction of the active regions 2P and 2N in the capacitor cell shown in FIG. 14. In the inverter cell 2 shown in FIG. 15(b), the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in FIG. 15(a) (w2<w1).

[0098] 15(a) and (b), the positions of the active regions 2P1 and 2P2 are shifted toward the upper side of the drawing in the Y direction, and the positions of the active regions 2N1 and 2N2 are shifted toward the lower side of the drawing in the Y direction. In the inverter cell shown in FIG. 15(a) and (b), the nanosheet of the nanosheet FET is exposed from the gate wiring on the side facing the cell frame.

[0099] 15A, in the active region 2P1, the upper surface of the nanosheet 25 in the Y direction is not covered by the gate wiring 38a and is exposed from the gate wiring 38a, and the lower surface of the nanosheet 27 in the Y direction is not covered by the gate wiring 38b and is exposed from the gate wiring 38b.

[0100] 15B, in the active region 2P2, the upper surface of the nanosheet 25A in the Y direction is not covered by the gate wiring 38a and is exposed from the gate wiring 38a, and the lower surface of the nanosheet 27A in the Y direction is not covered by the gate wiring 38b and is exposed from the gate wiring 38b.

[0101] In addition, in Figures 15(a) and (b), normal gate wiring 38 including gate wiring 38a and 38b is formed from the P-type transistor to the N-type transistor, and the gate wiring is not connected via a bridge portion as in Figures 5(a) and (b).

[0102] Fig. 16 is a plan view showing an example of the configuration of a cell row in this embodiment. In Fig. 16, in a cell row CR, a cell C1 which is an inverter cell 1 shown in Fig. 15(a), a cell C3 which is a capacitance cell shown in Fig. 14, and a cell C2 which is an inverter cell 2 shown in Fig. 15(b) are arranged side by side.

[0103] 16, the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a and 21b constituting the P-type nanosheet FET of cell C3.

[0104] Similarly, the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a and 23b constituting the N-type nanosheet FET of cell C3.

[0105] Additionally, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same upper edge position in the Y direction on the drawing. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same lower edge position in the Y direction on the drawing. That is, the positions of the surfaces of the nanosheets exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0106] As described above, in a fork-sheet FET, the nanosheets facing each other and exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row in which cells are aligned in the X direction, as shown in the configuration of Figure 16, the positions of the surfaces of the nanosheets exposed from the gate wiring can be aligned in the Y direction to make the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0107] (Modification 1) FIG. 17 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment. The layout structure according to this modification has a configuration basically similar to that of the layout structure according to the third embodiment. That is, the position of the active region 2P is closer to the upper side of the drawing in the Y direction, and the position of the active region 2N is closer to the lower side of the drawing in the Y direction. However, the connection relationship between the M0 wiring and the gate wiring, local wiring, etc. is different from that of the third embodiment. The relationship between the third embodiment and Modification 1 is the same as the relationship between the first embodiment and Modification 1 thereof.

[0108] That is, in this modification, VSS is supplied to the gate wirings 31 and 32 from the power supply wiring 12 via a path that passes through the M0 wiring 54, the local wiring 41, and the M0 wiring 52. VDD is supplied to the gate wirings 33 and 34 from the power supply wiring 11 via the path that passes through the M0 wiring 51, the local wiring 46, and the M0 wiring 53. Therefore, the resistance value in the power supply path to the transistor gates is reduced compared to the layout structure of the third embodiment, improving the high-speed response of the capacitance.

[0109] In the layout structure of FIG. 17, the BM0 wiring and the M0 wiring are directly connected through vias, but instead, the BM0 wiring and the M0 wiring may be connected via local wiring.

[0110] (Modification 2) Fig. 18 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 2 of this embodiment. The circuit diagram of the capacitance cell shown in Fig. 18 is as shown in Fig. 9. The capacitance cell shown in Fig. 18 has the same configuration as the capacitance cell shown in Fig. 8, and components common to those in Fig. 8 are given the same reference numerals as in Fig. 8, and detailed description thereof may be omitted here. The relationship between the third embodiment and Modification 2 is the same as the relationship between the first embodiment and Modification 2 thereof.

[0111] In the layout structure of FIG. 18, compared with FIG. 8, the position of the active region 2P3 is shifted toward the upper side of the drawing in the Y direction, and the position of the active region 2N3 is shifted toward the lower side of the drawing in the Y direction.

[0112] In the active region 2P3, the upper surface of the nanosheet 121a in the Y direction is not covered by the gate wiring 131a and is exposed from the gate wiring 131a. The upper surface of the nanosheet 121b in the Y direction is not covered by the gate wiring 132a and is exposed from the gate wiring 132a. The upper surface of the nanosheet 121c in the Y direction is not covered by the gate wiring 133a and is exposed from the gate wiring 133a.

[0113] In the active region 2N3, the surface of the nanosheet 123a on the lower side in the Y direction in the drawing is not covered by the gate wiring 131b and is exposed from the gate wiring 131b. The surface of the nanosheet 123b on the lower side in the Y direction in the drawing is not covered by the gate wiring 132b and is exposed from the gate wiring 132b. The surface of the nanosheet 123c on the lower side in the Y direction in the drawing is not covered by the gate wiring 133b and is exposed from the gate wiring 133b.

[0114] In FIG. 18, normal gate wiring 131 including gate wirings 131a and 131b, normal gate wiring 132 including gate wirings 132a and 132b, and normal gate wiring 133 including gate wirings 133a and 133b are formed from the P-type transistor to the N-type transistor, and the gate wirings are not connected via a bridge portion as in FIG. 8.

[0115] This modification provides the same effect as the third embodiment. That is, the active regions 2P3 and 2N3 can be arranged close to the active regions of other cells. This allows the area of ​​the capacitance cell to be reduced.

[0116] Furthermore, VSS is supplied to the portions 124a, 124b, 124c, and 124d in the active region 2N3 that serve as the source or drain of the N-type transistors N1, N2, and N3 through vias from the power supply wiring 12 formed on their back surfaces. This configuration reduces the area of ​​the layout structure of the capacitor cell, thereby achieving a smaller area for the capacitor cell. Furthermore, the resistance value in the path from the VSS power supply wiring 12 to the nanosheets 123a, 123b, and 123c of the transistors N1, N2, and N3 can be suppressed. This improves the high-speed response of the capacitor.

[0117] (Fourth embodiment) In the second embodiment described above, the nanosheet of the nanosheet FET in the capacitance cell is exposed from the gate wiring on the side where the P-type transistor and the N-type transistor face each other. In contrast, in the fourth embodiment, as in the third embodiment, the nanosheet of the nanosheet FET in the capacitance cell is exposed from the gate wiring on the side facing the cell frame. This allows the active region to be arranged close to the cell frame, thereby reducing the area of ​​the capacitance cell.

[0118] Fig. 19 is a plan view showing an example of a layout structure of a capacitance cell included in a semiconductor integrated circuit device according to the fourth embodiment. The circuit diagram of the capacitance cell shown in Fig. 19 is as shown in Fig. 11. The capacitance cell shown in Fig. 19 has a configuration similar to that of the capacitance cell shown in Fig. 10, and components common to those in Fig. 10 are assigned the same reference numerals as in Fig. 10, and detailed description thereof may be omitted here.

[0119] In the layout structure of FIG. 19, compared with FIG. 10, the position of the active region 2P is closer to the upper side of the drawing in the Y direction, and the position of the active region 2N is closer to the lower side of the drawing in the Y direction.

[0120] In the active region 2P, the upper surface of nanosheet 21a in the Y direction is not covered by gate wiring 31 and is exposed from gate wiring 31. Furthermore, the upper surface of nanosheet 21b in the Y direction is not covered by gate wiring 32 and is exposed from gate wiring 32. In the active region 2N, the lower surface of nanosheet 23a in the Y direction is not covered by gate wiring 33 and is exposed from gate wiring 33. Furthermore, the lower surface of nanosheet 23b in the Y direction is not covered by gate wiring 34 and is exposed from gate wiring 34.

[0121] In the capacitor cell shown in FIG. 19 , the nanosheet of the P-type transistor is exposed from the gate wiring on the side opposite the N-type transistor, in other words, on the side opposite the transistor of another cell located at the top of the drawing. Therefore, since overlap of the gate wiring is not required on the side opposite the transistor of another cell, the active region 2P can be placed close to the active region of the other cell. Similarly, the nanosheet of the N-type transistor is exposed from the gate wiring on the side opposite the P-type transistor, in other words, on the side opposite the transistor of another cell located at the bottom of the drawing. Therefore, since overlap of the gate wiring is not required on the side opposite the transistor of another cell, the active region 2N can be placed close to the active region of the other cell. This allows the capacitor cell to be reduced in area.

[0122] Other configurations of the capacitance cell in Fig. 19 are the same as those of the capacitance cell shown in Fig. 10. Therefore, the capacitance cell in Fig. 19 can achieve the same effects as those of the capacitance cell shown in Fig. 10. That is, the capacitance cell can be reduced in area. Furthermore, the high-speed response of the capacitance can be improved.

[0123] (Modification 1) Fig. 20 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment. The circuit diagram of the capacitance cell shown in Fig. 20 is as shown in Fig. 13. The relationship between the fourth embodiment and Modification 1 is the same as the relationship between the second embodiment and Modification 1. The capacitance cell shown in Fig. 20 has a similar configuration to the capacitance cell shown in Fig. 12, and components common to Fig. 12 are assigned the same reference numerals as in Fig. 12, and detailed description thereof may be omitted here.

[0124] In the layout structure of FIG. 20, in comparison with FIG. 12, the position of the active region 2P3 is shifted toward the upper side of the drawing in the Y direction, and the position of the active region 2N3 is shifted toward the lower side of the drawing in the Y direction.

[0125] In the active region 2P3, the upper surface of the nanosheet 121a in the Y direction is not covered by the gate wiring 131a and is exposed from the gate wiring 131a. The upper surface of the nanosheet 121b in the Y direction is not covered by the gate wiring 132a and is exposed from the gate wiring 132a. The upper surface of the nanosheet 121c in the Y direction is not covered by the gate wiring 133a and is exposed from the gate wiring 133a.

[0126] In the active region 2N3, the surface of the nanosheet 123a on the lower side in the Y direction in the drawing is not covered by the gate wiring 131b and is exposed from the gate wiring 131b. The surface of the nanosheet 123b on the lower side in the Y direction in the drawing is not covered by the gate wiring 132b and is exposed from the gate wiring 132b. The surface of the nanosheet 123c on the lower side in the Y direction in the drawing is not covered by the gate wiring 133b and is exposed from the gate wiring 133b.

[0127] In FIG. 20, a normal gate wiring 131 including gate wirings 131a and 131b, a normal gate wiring 132 including gate wirings 132a and 132b, and a normal gate wiring 133 including gate wirings 133a and 133b are formed from the P-type transistor to the N-type transistor, and the gate wirings are not connected via a bridge portion as in FIG. 12.

[0128] According to this modification, similarly to the first modification of the second embodiment, it is possible to reduce the area of ​​the capacitor cell, and also to improve the high-speed response of the capacitor.

[0129] In the above-described embodiment, the nanosheet FET has three sheets that overlap in a planar view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheets of the nanosheet FET are not limited to this.

[0130] The present disclosure can provide a layout structure for a capacitance cell using a fork sheet FET and backside wiring, which is useful for improving the performance of a semiconductor chip, for example.

[0131] 2P, 2N Active area 11, 12 Power supply wiring 21a, 21b, 23a, 23b Nanosheet 25, 25A, 27, 27A Nanosheet 31, 32, 33, 34 Gate wiring 61, 62 Via 121a, 121b, 121c Nanosheet 123a, 123b, 123c Nanosheet 131a, 132a, 133a Gate wiring 131b, 132b, 133b Gate wiring 131c, 132c, 133c Bridge section P1, P2, P3 Nanosheet FET N1, N2, N3 Nanosheet FET C1, C2, C3 Standard cell CR Cell row

Claims

1. A semiconductor integrated circuit device including a standard cell that is a capacitance cell, the standard cell comprising: a first nanosheet FET (Field Effect Transistor) of a first conductivity type including a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type including a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction, overlapping the first nanosheet in a planar view, and surrounding the periphery of the first nanosheet in the second direction and in a depth direction; a second gate wiring extending in the second direction, overlapping the second nanosheet in a planar view, and surrounding the periphery of the second nanosheet in the second direction and in the depth direction; and a first power supply wiring formed in a first wiring layer on the back side of the first nanosheet FET, extending in the first direction, overlapping the first nanosheet FET in a planar view, and supplying a first power supply voltage. a semiconductor integrated circuit device in which the first nanosheet and the second nanosheet face each other in the second direction, a first side surface of the first nanosheet in the second direction being exposed from the first gate wiring, and a second side surface of the second nanosheet opposite the first side in the second direction being exposed from the second gate wiring; the first power supply wiring is connected to the source and drain of the first nanosheet FET via a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a planar view; and a second power supply voltage is supplied to the first gate wiring.

2. A semiconductor integrated circuit device according to claim 1, wherein the first side is the side of the first nanosheet facing the second nanosheet, and the second side is the side of the second nanosheet facing the first nanosheet.

3. A semiconductor integrated circuit device according to claim 1, wherein the first side is the side of the first nanosheet opposite to the side of the second nanosheet, and the second side is the side of the second nanosheet opposite to the side of the first nanosheet.

4. A semiconductor integrated circuit device according to claim 1, wherein the first gate wiring is supplied with the second power supply voltage via an active region that constitutes the second nanosheet FET.

5. A semiconductor integrated circuit device according to claim 1, wherein the standard cell is formed in the first wiring layer, extends in the first direction, overlaps the second nanosheet FET in a planar view, and comprises a second power supply wiring that supplies the second power supply voltage, the second power supply wiring being connected to the source and drain of the second nanosheet FET via a second via provided at a position that overlaps the second power supply wiring and the second nanosheet FET in a planar view, and the second gate wiring is supplied with the first power supply voltage.

6. A semiconductor integrated circuit device according to claim 5, wherein the second gate wiring is supplied with the first power supply voltage via an active region that constitutes the first nanosheet FET.

7. A semiconductor integrated circuit device according to claim 5, wherein the standard cell is connected to the first and second power supply wirings and comprises a fixed value output unit that supplies the second power supply voltage to the first gate wiring and the first power supply voltage to the second gate wiring; the fixed value output unit comprises a third nanosheet FET of the first conductivity type whose source is connected to the first power supply wiring and a fourth nanosheet FET of the second conductivity type whose source is connected to the second power supply wiring; the first gate wiring is electrically connected to the gate of the third nanosheet FET and the drain of the fourth nanosheet FET; and the second gate wiring is electrically connected to the drain of the third nanosheet FET and the gate of the fourth nanosheet FET.

8. A semiconductor integrated circuit device according to claim 2, wherein the first gate wiring and the second gate wiring are connected via a bridge portion.

9. A semiconductor integrated circuit device comprising: a first standard cell which is a capacitance cell; and second and third standard cells which are arranged in the same cell row as the first standard cell and have a logic function, wherein the first standard cell comprises: a first nanosheet FET (Field Effect Transistor) of a first conductivity type including a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type including a second nanosheet extending in the first direction; a first gate wiring which extends in a second direction perpendicular to the first direction, overlaps the first nanosheet in a planar view, and surrounds the periphery of the first nanosheet in the second direction and in a depth direction; a second gate wiring which extends in the second direction, overlaps the second nanosheet in a planar view, and surrounds the periphery of the second nanosheet in the second direction and in the depth direction; and a first power supply wiring which is formed in a first wiring layer on the back side of the first nanosheet FET, extends in the first direction, overlaps the first nanosheet FET in a planar view, and supplies a first power supply voltage. the first nanosheet and the second nanosheet face each other in the second direction, a first side surface of the first nanosheet in the second direction is exposed from the first gate wiring, and a second side surface of the second nanosheet opposite to the first side in the second direction is exposed from the second gate wiring; the first power supply wiring is connected to the source and drain of the first nanosheet FET via a first via provided at a position overlapping the first power supply wiring and the first nanosheet FET in a planar view; a second power supply voltage is supplied to the first gate wiring; the second standard cell comprises: a third nanosheet FET of the first conductivity type including a third nanosheet extending in the first direction; the third standard cell comprises: a fourth nanosheet FET of the first conductivity type including a fourth nanosheet extending in the first direction; the third nanosheet has the same size in the second direction as the first nanosheet and has the same laying range in the second direction; and the fourth nanosheet has a size in the second direction smaller than that of the first nanosheet. Semiconductor integrated circuit device.

10. A semiconductor integrated circuit device according to claim 9, wherein the first side is the side of the first nanosheet facing the second nanosheet, and the second side is the side of the second nanosheet facing the first nanosheet.

11. A semiconductor integrated circuit device according to claim 10, wherein the first nanosheet, the third nanosheet, and the fourth nanosheet have ends on the second nanosheet side positioned at the same position in the second direction.

12. A semiconductor integrated circuit device according to claim 9, wherein the first side is the side of the first nanosheet opposite to the side of the second nanosheet, and the second side is the side of the second nanosheet opposite to the side of the first nanosheet.

13. A semiconductor integrated circuit device according to claim 12, wherein the first nanosheet, the third nanosheet, and the fourth nanosheet have ends at the same position on the opposite side of the second nanosheet in the second direction.

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