Liquid crystal panel and display device

Abstract

A liquid crystal panel according to one embodiment of the present disclosure comprises an effective pixel region and a peripheral region. The peripheral region includes: a peripheral circuit capable of driving a plurality of pixels in the effective pixel region; and a wiring section including a plurality of wires. The peripheral circuit is composed of a plurality of circuit blocks. A plurality of first wires, which constitute a portion of the plurality of wires included in the wiring section, are disposed in a gap between the effective pixel region and at least one circuit block from among the plurality of circuit blocks and extend along the outer edge of the effective pixel region across the entire gap. A plurality of second wires, which are wires other than the plurality of first wires among the plurality of wires included in the wiring section, are disposed at positions opposite the effective pixel region with the plurality of circuit blocks therebetween.

Description

Liquid crystal panel and display device

[0001] The present disclosure relates to a liquid crystal panel and a display device.

[0002] Generally, in a projection display device such as a projector, image light is modulated for each pixel on a transmissive (or reflective) liquid crystal panel based on light emitted from a light source, and the modulated image light is then enlarged and displayed by a projection lens. Such display devices are classified according to their functions or forms into, for example, data projectors for personal computers, front projectors for home theaters, and rear projectors for rear-projector televisions.

[0003] A display device including a liquid crystal panel is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2020-34957

[0005] In projection-type display devices such as projectors, the intensity of light emitted from a light source is very high. Therefore, when light from the light source enters a liquid crystal panel, returned light, scattered light, and other stray light may enter the circuitry surrounding the effective pixel area of ​​the liquid crystal panel (hereinafter referred to as the "peripheral circuit"), potentially causing photodegradation of transistors in the peripheral circuit. It is desirable to provide a liquid crystal panel that can suppress photodegradation of transistors in the peripheral circuit, and a display device including such a liquid crystal panel.

[0006] A liquid crystal panel according to an embodiment of the present disclosure includes an effective pixel region consisting of a plurality of pixels arranged in a matrix, and a peripheral region surrounding the effective pixel region. The peripheral region includes a peripheral circuit capable of driving the plurality of pixels, and a wiring section including a plurality of wires for electrically connecting the peripheral circuit to a controller, a DAC, and a DC-CD converter. Each pixel includes a first TFT and a liquid crystal element. The peripheral circuit is composed of a plurality of circuit blocks, each including a plurality of second TFTs. A plurality of first wires, which are some of the wires included in the wiring section, are arranged in a gap between the effective pixel region and at least one first circuit block among the plurality of circuit blocks, and extend along the outer edge of the effective pixel region across the entire gap. A plurality of second wires, other than the plurality of first wires, are arranged in a position facing the effective pixel region via the plurality of circuit blocks.

[0007] A display device according to an embodiment of the present disclosure includes a liquid crystal panel and a controller for controlling the driving of the liquid crystal panel. The liquid crystal panel has an effective pixel region consisting of a plurality of pixels arranged in a matrix and a peripheral region surrounding the effective pixel region. The peripheral region includes a peripheral circuit capable of driving the plurality of pixels and a wiring section including a plurality of wires for electrically connecting the peripheral circuit to the controller, the DAC, and the DC-CD converter. Each pixel includes a first TFT and a liquid crystal element. The peripheral circuit is composed of a plurality of circuit blocks, each including a plurality of second TFTs. A plurality of first wires, which are some of the wires included in the wiring section, are arranged in a gap between the effective pixel region and at least one first circuit block among the plurality of circuit blocks, and extend along the outer edge of the effective pixel region across the entire gap. A plurality of second wires, other than the plurality of first wires, are arranged in a position facing the effective pixel region via the plurality of circuit blocks.

[0008] In a liquid crystal panel and a display device according to an embodiment of the present disclosure, a wiring section is provided around an effective pixel area consisting of a plurality of pixels arranged in a matrix, the wiring section including a peripheral circuit capable of driving the plurality of pixels and a plurality of wires for electrically connecting the peripheral circuit to a controller, a DAC, and a DC-CD converter. Furthermore, the peripheral circuit is configured with a plurality of circuit blocks, each including a plurality of second TFTs. A plurality of first wires, which are some of the wires included in the wiring section, are disposed in a gap between the effective pixel area and at least one first circuit block and extend along the outer edge of the effective pixel area across the entire gap. As a result, even if light from a light source enters the liquid crystal panel and returning light, scattered light, or the like becomes stray light and enters the peripheral circuit, the intensity of the stray light incident on the transistors of the peripheral circuit is reduced because the transistors of the peripheral circuit are located at a distance from the effective pixel area by the gap.

[0009] FIG. 1 is a diagram illustrating an example of a schematic configuration of a display device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a planar configuration of the liquid crystal panel unit of FIG. 1 (partition plate omitted). FIG. 3 is a diagram illustrating an example of a planar configuration of the liquid crystal panel unit of FIG. 1 (partition plate included). FIG. 4 is a diagram illustrating an example of a cross-sectional configuration of the liquid crystal panel unit of FIG. 3 taken along line A-A. FIG. 5 is a diagram illustrating an example of a circuit configuration of the pixel of FIG. 4. FIG. 6 is a diagram illustrating an example of a circuit configuration of the vertical drive circuit of FIG. 2. FIG. 7 is a diagram illustrating an example of a planar layout of a peripheral circuit section including the vertical drive circuit of FIG. 6. FIG. 8 is a diagram illustrating an example of a planar layout of a peripheral circuit section including the horizontal drive circuit of FIG. 2. FIG. 9 is a diagram illustrating an example of a planar layout of a peripheral circuit section including the precharge control circuit of FIG. 2. FIG. 10 is a diagram illustrating an example of the ON / OFF ratio, Vgs when ON, and Vgs when OFF of each transistor of the vertical drive circuit of FIG. 6. FIG. 11 is a diagram illustrating a modified circuit configuration of the vertical drive circuit of FIG. 2. FIG. 12 is a diagram illustrating an example of a planar layout of a peripheral circuit section including the vertical drive circuit of FIG. 11. FIG. 13 is a diagram illustrating a modified planar layout of a peripheral circuit section including the vertical drive circuit of FIG. 2. FIG. 14 is a diagram illustrating a modified planar layout of the peripheral circuit section of FIG. 12. FIG. 15 is a diagram illustrating a modified planar layout of the peripheral circuit section of FIG. 13. FIG. 16 is a diagram illustrating a modified cross-sectional configuration of the liquid crystal panel unit of FIG. 3 taken along line A-A. FIG. 17 is a diagram illustrating an example planar configuration of a liquid crystal panel unit having the cross-sectional configuration of FIG. 16 (partition panel omitted). FIG. 18 is a diagram illustrating a modified cross-sectional configuration of the liquid crystal panel unit of FIG. 16. FIG. 19 is a diagram illustrating a modified cross-sectional configuration of the liquid crystal panel unit of FIG. 3 taken along line A-A. FIG. 20 is a diagram illustrating an example planar configuration of a liquid crystal panel unit having the cross-sectional configuration of FIG. 19 (partition panel omitted). FIG. 21 is a diagram illustrating a modified cross-sectional configuration of the liquid crystal panel unit of FIG. 19. Fig. 22 is a diagram showing a modified planar configuration (partition plate omitted) of the liquid crystal panel unit of Fig. 1. Fig. 23 is a diagram showing a modified planar configuration (partition plate omitted) of the liquid crystal panel unit of Fig. 1.

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following embodiment. The description will be given in the following order: 1. Embodiment An example in which a wiring section is provided in the gap between an effective pixel region and a peripheral circuit section (FIGS. 1 to 9) 2. Modifications Modification A An example in which the final stage buffer is arranged farthest from the effective pixel area in the vertical drive circuit (FIGS. 10 to 12) Modification B An example in which the n-channel TFT is arranged farthest from the effective pixel area in the vertical drive circuit (FIG. 13) Modification C An example in which the wiring section is arranged farther from the effective pixel area than the vertical drive circuit in Modification A (FIG. 14) Modification D An example in which the wiring section is arranged farther from the effective pixel area than the vertical drive circuit in Modification B (FIG. 15) Modification E An example in which the vertical drive circuit is arranged below the seal layer in the above embodiment and modifications A to C (FIGS. 16 and 17) Modification F An example in which the vertical drive circuit is arranged below the seal layer in Modification D (FIG. 18) Modification G An example in which a light-shielding layer is provided between the wiring section and the peripheral circuit section in the above embodiment and modifications A to C and E (FIGS. 19 and 20) Modification H An example in which a light-shielding layer is provided between the effective pixel area and the peripheral circuit section in Modifications D and F (FIG. 21) Modification I Example in which the horizontal drive circuit is arranged further from the effective pixel area than the wiring layer (FIG. 22). Modification J Example in which the precharge circuit is arranged further from the effective pixel area than the wiring layer (FIG. 23).

[0011] 1. Embodiment [Configuration] A projection-type display device 1 according to an embodiment of the present disclosure will be described. FIG. 1 illustrates a schematic configuration example of the display device 1 according to the present embodiment. The display device 1 is incorporated into, for example, a three-panel transmissive projector. The display device 1 includes, for example, liquid crystal panel units 10R and 10B arranged on an optical axis AX1, and a liquid crystal panel unit 10g arranged on an optical axis AX2 perpendicular to the optical axis AX1. The display device 1 further includes, for example, a cross prism 12 arranged at a location where the optical axes AX1 and AX2 intersect, and a projection lens 13 arranged on the optical axis AX2 and facing the liquid crystal panel unit 10g across the cross prism 12. The liquid crystal panel units 10R and 10B are arranged opposite each other across the cross prism 12.

[0012] The display device 1 further includes, for example, an incident-side polarizer 11a on the light-incident side of each of the liquid crystal panel units 10R, 10G, and 10B, and an exit-side polarizer 11b on the light-exit side of each of the liquid crystal panel units 10R, 10G, and 10B. The display device 1 further includes, for example, one laser light source for each of the liquid crystal panel units 10R, 10G, and 10B. The laser light source for the liquid crystal panel unit 10R is capable of emitting red laser light (red light Lr) toward the liquid crystal panel unit 10R. The laser light source for the liquid crystal panel unit 10G is capable of emitting green laser light (green light Lg) toward the liquid crystal panel unit 10G. The laser light source for the liquid crystal panel unit 10B is capable of emitting blue laser light (blue light Lb) toward the liquid crystal panel unit 10B. These laser light sources are not shown in the figure.

[0013] The incident-side polarizing plate 11a and the exit-side polarizing plate 11b function as a polarizer and an analyzer for the liquid crystal panel (liquid crystal panel 20, described later) included in each of the liquid crystal panel units 10R, 10G, and 10B. The polarization axes of the incident-side polarizing plate 11a and the exit-side polarizing plate 11b are set according to the type of liquid crystal and the display mode used in the liquid crystal panel 20. For example, in the case of a normally black (NB) mode using a VA (Vertical Alignment) liquid crystal, the polarization axes are set to be orthogonal to each other, and the incident-side polarizing plate 11a and the exit-side polarizing plate 11b are arranged in a so-called crossed Nicol configuration.

[0014] (Liquid Crystal Panel Unit) Liquid crystal panel unit 10R modulates incident red light Lr based on a predetermined video signal and emits the resulting red modulated light Lrm. Liquid crystal panel unit 10G modulates incident green light Lg based on a predetermined video signal and emits the resulting green modulated light Lgm. Liquid crystal panel unit 10B modulates incident blue light Lb based on a predetermined video signal and emits the resulting blue modulated light Lbm. Liquid crystal panel units 10r, 10G, and 10B basically have the same device structure. Therefore, in the following description, these liquid crystal panel units 10R, 10G, and 10B will be referred to as liquid crystal panel unit 10 without any particular distinction being made between them.

[0015] The detailed configuration of the liquid crystal panel unit 10 will be described with reference to Figures 2 to 4. Figures 2 and 3 show an example of the planar configuration of the liquid crystal panel unit 10. In Figure 2, a parting plate 31, which will be described later, is omitted. In Figure 3, the state in which the parting plate 31 is attached is shown. Furthermore, in Figure 3, a control board 70, which will be described later, is omitted. Figure 4 shows an example of the cross-sectional configuration of the liquid crystal panel unit 10 taken along line A-A.

[0016] The liquid crystal panel unit 10 includes, for example, a transmissive liquid crystal panel 20, an outer frame 30, a peripheral circuit section 40, a wiring section 50, an FPC 60, and a control board 70. The peripheral circuit section 40 is capable of driving multiple pixels Pix and includes multiple circuit blocks. The peripheral circuit section 40 includes, as the multiple circuit blocks, a horizontal drive circuit 41, two vertical drive circuits 42, and a precharge control circuit 43. The TFTs included in the horizontal drive circuit 41, the two vertical drive circuits 42, and the precharge control circuit 43 correspond to a specific example of a "second TFT" in the present disclosure. An outer frame 30 and a viewfinder 31 are attached to the liquid crystal panel 20. The outer frame 30 is arranged to cover the side surfaces and the outer edges of the light exit surface of the liquid crystal panel 20. The viewfinder 31 is arranged to cover the outer edge of the light entrance surface of the liquid crystal panel 20. The control board 70 has, for example, a controller 71 that controls the peripheral circuit unit 40, a DAC 72 that supplies a signal voltage Vsig to the peripheral circuit unit 40, and a DC-DC converter 73 that supplies multiple power supply voltages and reference voltages to the peripheral circuit unit 40.

[0017] The liquid crystal panel 20 functions as a so-called light valve and is capable of modulating incident light (red light Lr, green light Lg, or blue light Lb) to emit colored light corresponding to an image. The liquid crystal panel 20 has an effective pixel area 20A including a plurality of pixels Pix arranged in a matrix, and a peripheral area 20B surrounding the effective pixel area 20A.

[0018] The liquid crystal panel 20 is a laminate including, for example, a TFT (thin film transistor) substrate 21, a liquid crystal layer 24, and an opposing substrate 27, in this order. The TFT substrate 21 is, for example, a substrate in which multiple thin films made of microfabricated metal or semiconductor (silicon) are formed on a glass substrate. Pixel transistors Tr (described below), a peripheral circuit section 40, and a wiring section 50 are formed on the multiple thin films of the TFT substrate 21. In the TFT substrate 21, the pixel transistors Tr and multiple wirings extending in the row and column directions are formed in the effective pixel region 20A, and the peripheral circuit section 40 and the wiring section 50 are formed in the peripheral region 20B. The multiple wirings formed in the effective pixel region 20A will be described in detail later. The TFT substrate 21 (wiring section 50) is connected to one end of an FPC 60, and a control substrate 70 is connected to the other end of the FPC 60.

[0019] As shown in FIG. 4 , the liquid crystal panel 20 includes a TFT substrate 21, a plurality of pixel electrodes 22, an alignment film 23, a liquid crystal layer 24, an alignment film 25, a common electrode 26, and an opposing substrate 27 stacked in this order. In the liquid crystal panel 20, the portions facing the pixel electrodes 22 in the stacking direction constitute pixels Pix. That is, the liquid crystal panel 20 has a plurality of pixels Pix arranged in a matrix in the effective pixel area 20A. As shown in FIG. 5 , the liquid crystal panel 20 has a plurality of selection lines LG extending in the row direction and a plurality of signal lines LS extending in the column direction in the effective pixel area 20A. The liquid crystal panel 20 further includes pixels Pix adjacent to, for example, points where the selection lines LG and the signal lines LS intersect with each other. Each pixel Pix includes, for example, a pixel transistor Tr and a liquid crystal element LC. The liquid crystal element LC corresponds to, for example, a portion of a laminate formed by laminating a pixel electrode 22, an alignment film 23, a liquid crystal layer 24, an alignment film 25, and a common electrode 26, the portion facing the pixel electrode 22. The pixel transistor Tr corresponds to a specific example of a "first TFT" in the present disclosure.

[0020] The pixel transistor Tr is, for example, a MOS-FET. In the pixel transistor Tr, the gate is connected to a selection line LG, the source is connected to a pixel electrode 22, and the drain is connected to a signal line LS. When a pixel Pix is ​​selected, a selection voltage Vsel is applied to the selection line LG, and a signal voltage Vsig of a signal level corresponding to the gradation level of the selected pixel Pix is ​​applied to the signal line LS. In the liquid crystal element LC, the common electrode 26 is connected to a reference voltage line. A reference voltage Vref is applied to the reference voltage line.

[0021] The pixel electrodes 22 are physically and electrically isolated from one another. The common electrode 26, on the other hand, is a solid film formed across the entire effective pixel area 20A. Each pixel electrode 22 and the common electrode 26 are made of a transparent conductive material, such as indium tin oxide (ITO). The alignment films 23 and 25, for example, align the liquid crystal used in the liquid crystal layer 24. The liquid crystal layer 24 is made of various liquid crystals, such as VA type, TN type, or IPS type, and displays images in, for example, normally black mode or normally white (NW) mode. The alignment films 23 and 25 are made of, for example, vertical alignment films or horizontal alignment films. The counter substrate 27 is made of, for example, a glass substrate. By applying a predetermined voltage between the pixel electrode 22 and the common electrode 26, each liquid crystal element LC modulates light incident from the TFT substrate 21 and emits the modulated light from the counter substrate 27.

[0022] The liquid crystal panel 20 further includes a cover layer 28 on the light-emitting surface facing the TFT substrate 21 and a cover layer 29 on the light-incident surface facing the counter substrate 27, as shown in FIG. 4 . The cover layers 28 and 29 are layers for protecting the liquid crystal panel 20 and are made of, for example, glass substrates. The liquid crystal panel 20 further includes a seal layer 45 disposed between the TFT substrate 21 and the counter substrate 27, as shown in FIG. 4 . The seal layer 45 seals the liquid crystal layer 24 and can fix the TFT substrate 21 and the counter substrate 27 to each other. The seal layer 45 is made of, for example, a resin material having adhesive properties. The seal layer 45 is made of, for example, a resin material containing a material that absorbs stray light within the liquid crystal panel 20 (e.g., carbon black).

[0023] The outer frame 30 has, for example, a frame shape that surrounds the side surface and the outer edge of the light exit surface of the liquid crystal panel 20. An opening 30A is provided in the outer frame 30, and the effective pixel region 20A is exposed within the opening 30A. The outer frame 30 and the side surface of the liquid crystal panel 20 are bonded together by a resin layer 32 made of, for example, a room-temperature curing resin (RTV resin). The outer frame 30 has a mechanism (e.g., protrusions) for attaching a viewer panel 31, for example, at a predetermined position on the side surface. The protrusions are engaged with holes provided in the viewer panel 31, thereby attaching the viewer panel 31 to the outer frame 30. The viewer panel 31 is made of, for example, a light-shielding metal plate or the like, and is a member that shields the peripheral region 20B of the liquid crystal panel 20 from light. An opening 31A is provided in the viewer panel 31, and the effective pixel region 20A is exposed within the opening 31A.

[0024] The vertical drive circuit 42 is capable of performing line-sequential scanning by sequentially selecting a plurality of pixels Pix row by row via a plurality of selection lines LG in accordance with a control signal from the controller 71. The horizontal drive circuit 41 is capable of supplying a signal voltage Vsig based on a video signal to the plurality of pixels Pix via a plurality of signal lines LS in accordance with a control signal from the controller 71. Specifically, the horizontal drive circuit 41 is capable of supplying a pixel signal (signal voltage Vsig) obtained by performing D / A (digital-to-analog) conversion on the video signal in the DAC 72 to each pixel Pix.

[0025] The precharge control circuit 43 is capable of outputting a precharge signal voltage Vp in parallel to a plurality of pixels Pix via a plurality of signal lines LS in accordance with a control signal from the controller 71. The precharge control circuit 43 is capable of applying the precharge signal voltage Vp to the plurality of signal lines LS prior to application of the signal voltage Vsig.

[0026] Next, the circuit configurations of the vertical drive circuit 42, the horizontal drive circuit 41, and the precharge control circuit 43 will be described. Fig. 6 shows an example of the circuit configuration of the vertical drive circuit 42. Fig. 7 shows an example of a planar layout of the peripheral circuit section 40 including the vertical drive circuit 42. Fig. 8 shows an example of a planar layout of the peripheral circuit section 40 including the horizontal drive circuit 41. Fig. 9 shows an example of a planar layout of the peripheral circuit section 40 including the precharge control circuit 43.

[0027] The vertical drive circuit 42 has a drive circuit 42i for each pixel row. As shown in FIG. 6, the drive circuit 42i includes, in order from the rear stage, a buffer circuit 42a, a level shifter circuit 42b, and a 2VCLK circuit 42c.

[0028] The buffer circuit 42a includes, for example, a p-channel TFT (P1) and an n-channel TFT (N1). The connection node between the gate of the p-channel TFT (P1) and the gate of the n-channel TFT (N1) serves as the input terminal of the buffer circuit 42a, and this input terminal is connected to the output terminal of the level shifter circuit 42b. The source of the p-channel TFT (P1) is connected to a power supply voltage line L1, and the drain is connected to the source of the n-channel TFT (N1). The drain of the n-channel TFT (N1) is connected to a power supply voltage line L2. A power supply voltage Vddg is applied to the power supply voltage line L1, and a power supply voltage Vssg is applied to the power supply voltage line L2. The connection node between the drain of the p-channel TFT (P1) and the source of the n-channel TFT (N1) serves as the output terminal OUT_i of the buffer circuit 42a. The output terminal OUT_i is connected to the selection line LG.

[0029] The level shifter circuit 42b includes, for example, p-channel TFTs (P2, P3) and n-channel TFTs (N2, N3). The gate of the p-channel TFT (P2) is connected to the gate of the p-channel TFT (P3) via a NOT circuit. The source of the p-channel TFT (P2) is connected to a power supply voltage line L3, and the drain is connected to the gate of the n-channel TFT (N2). A power supply voltage Vvdd is applied to the power supply voltage line L3. The connection node between the source of the p-channel TFT (P2) and the gate of the n-channel TFT (N2) serves as the output terminal of the level shifter circuit 42b. The source of the p-channel TFT (P3) is connected to the power supply voltage line L3, and the drain is connected to the gate of the n-channel TFT (N3). The connection node between the gate of the p-channel TFT (P3) and the output terminal of the NOT circuit serves as the input terminal of the level shifter circuit 42b. The source of the n-channel TFT (N2) is connected to the source of the n-channel TFT (N3), and the drain is connected to the power supply voltage line Vssg. The source of the n-channel TFT (N3) is connected to the source of the n-channel TFT (N2), and the drain is connected to the power supply voltage line Vssg.

[0030] The 2VCLK circuit 42c includes, for example, p-channel TFTs (P4, P5) and n-channel TFTs (N4, N5). The gate of the p-channel TFT (P4) is connected to the gate of the n-channel TFT (N4), the source is connected to the power supply voltage line L3, and the drain is connected to the source of the n-channel TFT (N4). The gate of the p-channel TFT (P5) is connected to the gate of the n-channel TFT (N5), the source is connected to the power supply voltage line L3, and the drain is connected to the source of the n-channel TFT (N4). The connection node between the drain of the p-channel TFT (P4), the drain of the p-channel TFT (P5), and the source of the n-channel TFT (N4) serves as the output terminal of the 2VCLK circuit 42c. The drain of the n-channel TFT (N4) is connected to the source of the n-channel TFT (N5). The drain of the n-channel TFT (N5) is connected to a power supply voltage line L4. A power supply voltage Vvss is applied to the power supply voltage line L4. The gate of the p-channel TFT (P5) serves as one input terminal IN1_i of the 2VCLK circuit 42c, and the gate of the n-channel TFT (N5) serves as the other input terminal IN2_i of the 2VCLK circuit 42c. The input terminals IN1_i and IN2_i are connected to a bus line LB. A controller 71 is connected to the bus line LB. The bus line LB is a line for transmitting control signals from the controller 71 to the peripheral circuit unit 40.

[0031] In the liquid crystal panel 20, a wiring section 50 is disposed in the gap between the effective pixel area 20A and the vertical drive circuit 42, as shown in FIG. 7 , for example. The wiring section 50 includes a plurality of wires for electrically connecting the peripheral circuit section 40 to the controller 71, the DAC 72, and the DC-CD converter 73. The wiring section 50 includes a plurality of wires (power supply voltage lines L1, L2, L3, and L4, bus wires LB, and precharge wires LP) extending along the outer edge of the effective pixel area 20A across the entire gap between the effective pixel area 20A and the vertical drive circuit 42. Of the wiring section 50, the plurality of wires (power supply voltage lines L1, L2, L3, and L4, bus wires LB, and precharge wires LP) disposed in the gap between the effective pixel area 20A and the vertical drive circuit 42 correspond to a specific example of a “first wire” in the present disclosure. The bus line LB corresponds to a specific example of a "third line" in the present disclosure. Of the lines (power supply voltage lines L1, L2, L3, and L4, bus line LB, and precharge line LP), at least the bus line LB has a width that is 5% or more of the width of the vertical drive circuit 42 when the liquid crystal panel 20 is viewed in a plan view. The DAC 72 and the precharge control circuit 43 are connected to the precharge line LP, and a precharge voltage Vp output from the DAC 72 is applied to the precharge line LP. In the gap between the effective pixel area 20A and the vertical drive circuit 42, a plurality of selection lines LG that connect the vertical drive circuit 42 and a plurality of pixels Pix (effective pixel area 20A) intersect with a plurality of lines that extend along the outer edge of the effective pixel area 20A across the entire gap between the effective pixel area 20A and the vertical drive circuit 42.

[0032] The horizontal drive circuit 41 includes, for example, a plurality of shift registers SR (SR(a1), ..., SR(aj), ..., SR(am)), each assigned to a group of signal lines LS, and a plurality of switch elements SWa, each assigned to a signal line LS in each group of signal lines LS. Each switch in each switch element SWa includes, for example, an n-channel TFT. The output terminal of each shift register SR(a1), ..., SR(aj), ..., SR(am) is connected to the on / off control terminal of each switch element SWa in the corresponding group, and the input terminal is connected to the control board 70 via the FPC 60. In each switch element SWa, the source of each switch is connected to each signal line LS1, ..., LSz, the drain of each switch is connected to each signal line LS, and the gate of each switch is connected to the shift register SR. The horizontal drive circuit 41 is capable of sequentially outputting a signal voltage Vsig from each group to the corresponding signal line LS by sequentially outputting a control signal SR from each shift register SR to the on / off control terminal of each switch element SWa in the corresponding group based on a control signal supplied from the controller 71, for example.

[0033] In the liquid crystal panel 20, a wiring section 50 is disposed in the gap between the effective pixel region 20A and the horizontal drive circuit 41, as shown in FIG. 8 . The wiring section 50 includes a plurality of wirings (signal lines LS1, ..., LSz, bus wiring LB) extending along the outer edge of the effective pixel region 20A across the entire gap between the effective pixel region 20A and the horizontal drive circuit 41. Of the wirings in the wiring section 50, the plurality of wirings (signal lines LS1, ..., LSz, bus wiring LB) disposed in the gap between the effective pixel region 20A and the horizontal drive circuit 41 correspond to a specific example of the "first wiring" of the present disclosure. Of the wirings (signal lines LS1, ..., LSz, bus wiring LB), at least the bus wiring LB has a width that is 5% or more of the width of the horizontal drive circuit 41 when the liquid crystal panel 20 is viewed in a plan view. A plurality of signal lines LS are connected to the signal lines LS1, ..., LSz. In the gap between the effective pixel area 20A and the horizontal drive circuit 41, a plurality of signal lines LS connecting the horizontal drive circuit 41 and a plurality of pixels Pix (effective pixel area 20A) intersect with a plurality of wirings extending along the outer edge of the effective pixel area 20A across the entire gap between the effective pixel area 20A and the vertical drive circuit 42.

[0034] The precharge control circuit 43 includes, for example, a plurality of shift registers SR (SR(b1), ..., SR(bj), ..., SR(bm)), each assigned to a group of signal lines LS, and a plurality of switch elements SWb, each assigned to a signal line LS in each group of signal lines LS. Each switch in each switch element SWb includes, for example, an n-channel TFT. The output terminal of each shift register SR(b1), ..., SR(bj), ..., SR(bm) is connected to the on / off control terminal of each switch element SWb in the corresponding group, and the input terminal is connected to the control board 70 via the FPC 60. The source of each switch in each switch element SWb is connected to the precharge line LP, the drain of each switch is connected to each signal line LS, and the gate of each switch is connected to the shift register SR. The precharge control circuit 43 is capable of sequentially outputting a precharge voltage Vp from each group to the corresponding signal line LS by sequentially outputting a control signal SR from each shift register SR to the on / off control terminal of each switch element SWb in the corresponding group based on a control signal supplied from the controller 71, for example.

[0035] In the liquid crystal panel 20, a wiring section 50 is disposed in the gap between the effective pixel region 20A and the precharge control circuit 43, as shown in FIG. 9 . The wiring section 50 includes a plurality of wirings (precharge lines LP, bus wiring LB) extending along the outer edge of the effective pixel region 20A across the entire gap between the effective pixel region 20A and the precharge control circuit 43. Of the wirings in the wiring section 50, the plurality of wirings (precharge lines LP, bus wiring LB) disposed in the gap between the effective pixel region 20A and the precharge control circuit 43 correspond to a specific example of the “first wiring” of the present disclosure. Of the wirings (precharge lines LP, bus wiring LB), at least the bus wiring LB has a width that is 5% or more of the width of the precharge control circuit 43 when the liquid crystal panel 20 is viewed in a plan view. In the gap between the effective pixel area 20A and the precharge control circuit 43, a plurality of signal lines LS connecting the precharge control circuit 43 and a plurality of pixels Pix (effective pixel area 20A) intersect with a plurality of wires extending along the outer edge of the effective pixel area 20A across the entire gap between the effective pixel area 20A and the precharge control circuit 43. In the wiring section 50, a plurality of "second wires" excluding a plurality of wires corresponding to the above-mentioned "first wires" are arranged in positions facing the effective pixel area 20A via a plurality of circuit blocks included in the peripheral circuit section 40.

[0036] [Effects] Next, effects of the display device 1 according to the present embodiment will be described.

[0037] In the present embodiment, a peripheral circuit unit 40 capable of driving the pixels Pix and a wiring unit 50 including a plurality of wirings for electrically connecting the peripheral circuit unit 40 to the controller 71, the DAC 72, and the DC-CD converter 73 are provided around the effective pixel area 20A, which is made up of a plurality of circuit blocks each including a plurality of TFTs. Among the plurality of wirings included in the wiring unit 50, a plurality of first wirings are disposed in a gap between the effective pixel area 20 and at least one circuit block, and extend along the outer edge of the effective pixel area 20A over the entire gap. Thus, even if light from a light source enters the liquid crystal panel 20 and returning light, scattered light, or the like becomes stray light and enters the peripheral circuit unit 40, the transistors of the peripheral circuit unit 40 are located at a distance from the effective pixel area 20A by the distance of the gap, thereby reducing the intensity of the stray light incident on the transistors of the peripheral circuit unit 40. As a result, photodegradation of the transistors in the peripheral circuit section 40 can be suppressed.

[0038] In this embodiment, at least the bus line LB among the plurality of first lines has a width that is 5% or more of the width of the vertical drive circuit 42, the horizontal drive circuit 41, or the precharge control circuit 43 when the liquid crystal panel 20 is viewed in a plan view. As a result, even if returned light, scattered light, or the like becomes stray light when light from the light source is incident on the liquid crystal panel 20 and enters the peripheral circuit unit 40, the transistors of the peripheral circuit unit 40 are located at a distance from the effective pixel area 20A by at least the wiring width of the bus line LB, so that the intensity of the stray light incident on the transistors of the peripheral circuit unit 40 can be reduced. As a result, photodegradation of the transistors of the peripheral circuit unit 40 can be suppressed.

[0039] In this embodiment, bus wiring LB for transmitting control signals from controller 71 to peripheral circuitry 40 is disposed in the gap between effective pixel region 20A and at least one circuit block, and extends along the outer edge of effective pixel region 20A across the entire gap. As a result, even if returned light, scattered light, etc., becomes stray light when light from the light source enters liquid crystal panel 20 and enters peripheral circuitry 40, the transistors in peripheral circuitry 40 are located at a distance from effective pixel region 20A by at least the wiring width of bus wiring LB, thereby reducing the intensity of stray light incident on the transistors in peripheral circuitry 40. As a result, photodegradation of transistors in peripheral circuitry 40 can be suppressed.

[0040] In this embodiment, a plurality of first wirings are arranged in the gap between the effective pixel area 20A and the vertical drive circuit 42. As a result, even if returned light, scattered light, or the like becomes stray light when light from the light source is incident on the liquid crystal panel 20 and enters the vertical drive circuit 42, the transistors of the vertical drive circuit 42 are located at a distance from the effective pixel area 20A by the above-mentioned gap, so that the intensity of the stray light incident on the transistors of the vertical drive circuit 42 can be reduced. As a result, photodegradation of the transistors of the vertical drive circuit 42 can be suppressed.

[0041] 2. Modifications Next, modifications of the display device 1 according to the above embodiment will be described. The following mainly describes the configurations that are different from the first embodiment.

[0042] [Variation A] Fig. 10 shows an example of the ON / OFF ratio, Vgs when ON, and Vgs when OFF of each TFT included in the vertical drive circuit 42. Fig. 11 shows a variation of the circuit configuration of the vertical drive circuit 42. Fig. 12 is a diagram showing an example of a planar layout of the peripheral circuit section 40 including the vertical drive circuit 42 of Fig. 11 .

[0043] As can be seen from FIG. 10 , the N / OFF ratio of the n-channel TFT (N1), p-channel TFT (P1), and n-channel TFT (N2) in the vertical drive circuit 42 is 99.9%. Here, when the TFTs are ON, photodegradation of the TFTs is more likely to occur, with n-channel TFTs being more susceptible to photodegradation than p-channel TFTs. Therefore, in this modification, the buffer circuit 42a is formed in the vertical drive circuit 42 at a location farthest from the effective pixel area 20A, as shown in FIGS. 11 and 12 . The intensity of stray light incident on the TFTs decreases with increasing distance from the effective pixel area 20A. Therefore, by forming the buffer circuit 42a in the vertical drive circuit 42 at a location farthest from the effective pixel area 20A, the intensity of stray light incident on the buffer circuit 42a can be reduced compared to the above embodiment. As a result, photodegradation of the TFTs included in the buffer circuit 42a can be further suppressed.

[0044] [Variation B] FIG. 13 shows a variation of the planar layout of the peripheral circuit section 40 including the vertical drive circuit 42. For example, as shown in FIG. 13, the vertical drive circuit 42 may include a p-channel region 42p including all p-channel TFTs included in the vertical drive circuit 42 and an n-channel region 42n including all n-channel TFTs included in the vertical drive circuit 42. In this case, the n-channel region 42n is formed farther from the effective pixel region 20A than the p-channel region 42p. The intensity of stray light incident on the TFT decreases with increasing distance from the effective pixel region 20A. Therefore, by forming the n-channel region 42n farther from the effective pixel region 20A than the p-channel region 42p, the average intensity of stray light incident on each n-channel TFT can be reduced compared to the above embodiment. As a result, photodegradation of each n-channel TFT can be further suppressed.

[0045] 14 shows a modified planar layout of the peripheral circuit section 40 including the vertical drive circuit 42 according to Modification A. In this modification, the wiring section 50 is arranged farther from the effective pixel region 20A than the vertical drive circuit 42 in Modification A. Even in this case, the buffer circuit 42a is formed in the vertical drive circuit 42 at a location farthest from the effective pixel region 20A, and therefore the intensity of stray light incident on the buffer circuit 42a can be reduced compared to when the buffer circuit 42a is formed in the vertical drive circuit 42 at a location closest to the effective pixel region 20A. As a result, photodegradation of the TFTs included in the buffer circuit 42a can be suppressed.

[0046] 15 shows a modified planar layout of the peripheral circuit section 40 including the vertical drive circuit 42 according to Modification B. In this modification, the wiring section 50 is arranged farther from the effective pixel region 20A than the vertical drive circuit 42 in Modification B. Even in this modification, the n-channel region 42n is formed farther from the effective pixel region 20A than the p-channel region 42p. This reduces the average intensity of stray light incident on each n-channel TFT, compared to when the n-channel region 42n is formed closer to the effective pixel region 20A than the p-channel region 42p. As a result, photodegradation of each n-channel TFT can be further suppressed.

[0047] [Variation E] Fig. 16 shows a variation of the cross-sectional configuration of the liquid crystal panel unit 10 according to the above embodiment and variations A to C, taken along line A-A in Fig. 3. Fig. 17 shows an example of the planar configuration (parting panel omitted) of the liquid crystal panel unit 10 having the cross-sectional configuration of Fig. 16.

[0048] In this modification, in the above-described embodiment and modifications A to C, the sealing layer 45 covers at least a portion of the multiple circuit blocks (horizontal drive circuit 41, two vertical drive circuits 42, and precharge control circuit 43) included in the peripheral circuit unit 40 when the liquid crystal panel 20 is viewed in plan from the opposing substrate 27 side. Note that FIGS. 16 and 17 illustrate an example in which each circuit block (horizontal drive circuit 41, two vertical drive circuits 42, and precharge control circuit 43) included in the peripheral circuit unit 40 is entirely covered by the sealing layer 45. This allows stray light within the liquid crystal panel 20 to be blocked by the sealing layer 45, thereby reducing the intensity of light incident on at least portions of the multiple circuit blocks (horizontal drive circuit 41, two vertical drive circuits 42, and precharge control circuit 43) included in the peripheral circuit unit 40 that are covered by the sealing layer 45. As a result, photodegradation of the transistors in the peripheral circuit unit 40 can be suppressed compared to when the peripheral circuit unit 40 is not covered by the sealing layer 45.

[0049] [Modification F] FIG. 18 shows a modification of the cross-sectional configuration of the liquid crystal panel unit 10 according to modification D, taken along the line AA in FIG.

[0050] In this modification, in modification D, when the liquid crystal panel 20 is viewed in plan from the opposing substrate 27 side, the sealing layer 45 covers at least two vertical drive circuits 42 out of the plurality of circuit blocks (the horizontal drive circuit 41, the two vertical drive circuits 42, and the precharge control circuit 43) included in the peripheral circuit unit 40. This allows the sealing layer 45 to block stray light within the liquid crystal panel 20, thereby reducing the intensity of light incident on at least portions of the plurality of circuit blocks (the horizontal drive circuit 41, the two vertical drive circuits 42, and the precharge control circuit 43) included in the peripheral circuit unit 40 that are covered by the sealing layer 45. As a result, light-induced degradation of the transistors in the peripheral circuit unit 40 can be suppressed compared to when the peripheral circuit unit 40 is not covered with the sealing layer 45.

[0051] [Variation G] Fig. 19 shows a variation of the cross-sectional configuration of the liquid crystal panel unit 10 according to the above embodiment and variations A to C and E, taken along the line A-A in Fig. 3. Fig. 20 shows an example of the planar configuration (parting panel omitted) of the liquid crystal panel unit 10 having the cross-sectional configuration of Fig. 19.

[0052] In this modification, in the above-described embodiment and modifications A to C and E, the TFT substrate 21 includes a light-shielding layer 46 in a portion corresponding to the gap between the wiring section 50 and each circuit block (the horizontal drive circuit 41, the two vertical drive circuits 42, and the precharge control circuit 43) included in the peripheral circuit section 40, as shown in, for example, FIGS. 19 and 20 . The light-shielding layer 46 is formed, for example, from a metal plate having light-shielding properties. The light-shielding layer 46 is formed, for example, from the same material as the wiring included in the peripheral circuit section 40 and is provided in a layer common to the wiring section 50. The light-shielding layer 46 is provided, for example, in the peripheral region 20B. As a result, even if returned light or scattered light becomes stray light when light from a light source enters the liquid crystal panel 20, the light-shielding layer 46 can prevent the stray light from entering the peripheral circuit section 40. As a result, photodegradation of the transistors in the peripheral circuit section 40 can be suppressed.

[0053] [Modification H] FIG. 21 shows a modification of the cross-sectional configuration of the liquid crystal panel unit 10 according to modifications D and F, taken along the line AA in FIG.

[0054] In the present modified examples D and F, the TFT substrate 21 has a light-shielding layer 46 in a portion corresponding to the gap between the effective pixel region 20A and each circuit block (horizontal drive circuit 41, two vertical drive circuits 42, and precharge control circuit 43) included in the peripheral circuit unit 40, as shown in FIG. 21 . The light-shielding layer 46 is made of, for example, a metal plate having light-shielding properties. The light-shielding layer 46 is made of, for example, the same material as the wiring included in the peripheral circuit unit 40 and is provided in a layer common to the wiring unit 50. The light-shielding layer 46 is provided, for example, in the peripheral region 20B. As a result, even if returned light or scattered light becomes stray light when light from a light source enters the liquid crystal panel 20, the light-shielding layer 46 can prevent the stray light from entering the peripheral circuit unit 40. As a result, photodegradation of the transistors in the peripheral circuit unit 40 can be suppressed.

[0055] [Variation I] Figure 22 shows a variation of the planar configuration of the liquid crystal panel unit 10 according to the above-described embodiment and variations A to H. In this variation, in the above-described embodiment and variations A to H, the horizontal drive circuit 41 is disposed between the effective pixel area 20A and the wiring section 50, for example, as shown in Figure 22. Even in this case, among the circuit blocks (horizontal drive circuit 41, two vertical drive circuits 42, and precharge control circuit 43) included in the peripheral circuit section 40, light degradation of the transistors in the two vertical drive circuits 42 and the precharge control circuit 43 can be suppressed.

[0056] [Variation J] Figure 23 shows a variation of the planar configuration of the liquid crystal panel unit 10 according to the above-described embodiment and variations A to H. In this variation, the horizontal drive circuit 41 and the precharge circuit 43 in the above-described embodiment and variations A to H are arranged, for example, between the effective pixel area 20A and the wiring section 50, as shown in Figure 23. Even in this case, it is possible to suppress light-induced deterioration of the transistors in the two vertical drive circuits 42 among the circuit blocks (the horizontal drive circuit 41, the two vertical drive circuits 42, and the precharge control circuit 43) included in the peripheral circuit section 40.

[0057] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0058] Furthermore, for example, the present disclosure can take the following configuration: (1) A liquid crystal panel comprising: an effective pixel area consisting of a plurality of pixels arranged in a matrix; a peripheral area provided around the effective pixel area and having a peripheral circuit capable of driving the plurality of pixels, and a wiring section including a plurality of wires for electrically connecting the peripheral circuit to a controller, a DAC, and a DC-CD converter, wherein each of the pixels includes a first TFT and a liquid crystal element, the peripheral circuit is constituted by a plurality of circuit blocks each including a plurality of second TFTs, a plurality of first wires which are some of the plurality of wires included in the wiring section are arranged in a gap between the effective pixel area and at least one first circuit block among the plurality of circuit blocks and extend along an outer edge of the effective pixel area across the entire gap, and a plurality of second wires other than the plurality of first wires among the plurality of wires included in the wiring section are arranged in a position facing the effective pixel area with the plurality of circuit blocks interposed therebetween. (2) The liquid crystal panel according to (1), wherein a third wiring included in the plurality of first wirings has a width equal to or greater than 5% of a width of the first circuit block when the liquid crystal panel is viewed in a plane. (3) The liquid crystal panel according to (2), wherein the third wiring is a bus wiring for transmitting a control signal from the controller to the peripheral circuit. (4) The liquid crystal panel according to any one of (1) to (3), wherein one circuit block of the one or more first circuit blocks is a vertical drive circuit for selecting rows of the plurality of pixels, and wherein the plurality of first wirings are disposed in gaps between the effective pixel area and the vertical drive circuit as the gaps. (5) The liquid crystal panel according to any one of (1) to (4), wherein the vertical drive circuit is configured to include a plurality of n-channel TFTs and a plurality of p-channel TFTs, and wherein the plurality of n-channel TFTs are formed farther from the effective pixel area than the plurality of p-channel TFTs.(6) The liquid crystal panel according to any one of (1) to (4), comprising a plurality of selection lines connected to the gates of the first TFTs of the pixels, wherein the vertical drive circuit has, as an output stage, a buffer circuit connected to the plurality of selection lines, the buffer circuit being formed in a position in the vertical drive circuit farthest from the effective pixel area. (7) The liquid crystal panel according to any one of (1) to (6), comprising a laminate including a TFT substrate, a liquid crystal layer, and a counter substrate stacked in this order, and having a seal layer disposed between the TFT substrate and the counter substrate, sealing the liquid crystal layer and fixing the TFT substrate and the counter substrate to each other, wherein the seal layer covers at least a portion of the plurality of circuit blocks when the liquid crystal panel is viewed in plan from the counter substrate side. (8) The liquid crystal panel according to any one of (1) to (7), comprising a laminate including a TFT substrate, a liquid crystal layer, and a counter substrate stacked in this order, wherein the TFT substrate has a light-shielding layer in a portion corresponding to the gap. (9) A display device comprising: a liquid crystal panel; and a controller that controls driving of the liquid crystal panel, wherein the liquid crystal panel has: an effective pixel area consisting of a plurality of pixels arranged in a matrix; and a peripheral area provided around the effective pixel area and having a peripheral circuit capable of driving the plurality of pixels, and a wiring section including a plurality of wires for electrically connecting the peripheral circuit to a controller, a DAC, and a DC-CD converter, wherein each of the pixels includes a first TFT and a liquid crystal element, the peripheral circuit is constituted by a plurality of circuit blocks each including a plurality of second TFTs, a plurality of first wires that are some of the plurality of wires included in the wiring section are arranged in a gap between the effective pixel area and at least one first circuit block among the plurality of circuit blocks, and extend along an outer edge of the effective pixel area across the entire gap, and a plurality of second wires other than the plurality of first wires of the plurality of wires included in the wiring section are arranged in a position facing the effective pixel area via the plurality of circuit blocks.

[0059] In a liquid crystal panel and a display device according to an embodiment of the present disclosure, a wiring section is provided around an effective pixel area consisting of a plurality of pixels arranged in a matrix. The wiring section includes a peripheral circuit capable of driving the plurality of pixels and a plurality of wires for electrically connecting the peripheral circuit to a controller, a DAC, and a DC-CD converter. Furthermore, the peripheral circuit is configured with a plurality of circuit blocks, each including a plurality of second TFTs. A plurality of first wires, which are some of the wires included in the wiring section, are disposed in a gap between the effective pixel area and at least one first circuit block and extend along the outer edge of the effective pixel area across the entire gap. As a result, even if light from a light source enters the liquid crystal panel and returning light or scattered light becomes stray light and enters the peripheral circuit, the transistors of the peripheral circuit are located away from the effective pixel area by the gap, thereby reducing the intensity of the stray light incident on the transistors of the peripheral circuit. As a result, photodegradation of the transistors of the peripheral circuit can be suppressed.

[0060] This application claims priority based on Japanese Patent Application No. 2024-018497, filed on February 9, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0061] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A liquid crystal panel comprising: an effective pixel area consisting of a plurality of pixels arranged in a matrix; a peripheral area provided around the effective pixel area and having a peripheral circuit capable of driving the plurality of pixels; and a wiring section including a plurality of wires for electrically connecting the peripheral circuit with a controller, a DAC, and a DC-CD converter; wherein each of the pixels includes a first TFT and a liquid crystal element; the peripheral circuit is composed of a plurality of circuit blocks each including a plurality of second TFTs; a plurality of first wires which are some of the plurality of wires included in the wiring section are arranged in a gap between the effective pixel area and at least one first circuit block of the plurality of circuit blocks and extend along the outer edge of the effective pixel area across the entire gap; and a plurality of second wires other than the plurality of first wires of the plurality of wires included in the wiring section are arranged in a position facing the effective pixel area via the plurality of circuit blocks.

2. The liquid crystal panel according to claim 1, wherein the third wiring included in the plurality of first wirings has a width that is 5% or more of the width of the first circuit block when the liquid crystal panel is viewed in a plan view.

3. The liquid crystal panel according to claim 2, wherein the third wiring is a bus wiring for transmitting a control signal from the controller to the peripheral circuit.

4. The liquid crystal panel according to claim 1, wherein one of the one or more first circuit blocks is a vertical drive circuit for row selection of the plurality of pixels, and the plurality of first wirings are arranged in the gap between the effective pixel area and the vertical drive circuit as the gap.

5. The liquid crystal panel according to claim 1, wherein the vertical drive circuit is configured to include a plurality of n-channel TFTs and a plurality of p-channel TFTs, and the plurality of n-channel TFTs are formed at locations farther from the effective pixel area than the plurality of p-channel TFTs.

6. The liquid crystal panel according to claim 1, further comprising a plurality of selection lines connected to the gate of the first TFT of each of the pixels, wherein the vertical drive circuit has a buffer circuit connected to the plurality of selection lines as an output stage, and the buffer circuit is formed at a location on the vertical drive circuit farthest from the effective pixel area.

7. The liquid crystal panel according to claim 1, comprising a laminate including a TFT substrate, a liquid crystal layer, and an opposing substrate laminated in this order, and having a sealing layer disposed between the TFT substrate and the opposing substrate, sealing the liquid crystal layer and fixing the TFT substrate and the opposing substrate to each other, wherein the sealing layer covers at least a portion of the plurality of circuit blocks when the liquid crystal panel is viewed in plan from the opposing substrate side.

8. The liquid crystal panel according to claim 1, comprising a laminate including a TFT substrate, a liquid crystal layer and an opposing substrate laminated in this order, the TFT substrate having a light-shielding layer in a portion corresponding to the gap.

9. A display device comprising: a liquid crystal panel; and a controller for controlling the driving of said liquid crystal panel, wherein said liquid crystal panel has: an effective pixel area consisting of a plurality of pixels arranged in a matrix; and a peripheral area provided around said effective pixel area and having a peripheral circuit capable of driving said plurality of pixels; and a wiring section including a plurality of wires for electrically connecting said peripheral circuit with a controller, a DAC, and a DC-CD converter, wherein each of said pixels includes a first TFT and a liquid crystal element, and said peripheral circuit is constituted by a plurality of circuit blocks each including a plurality of second TFTs, and a plurality of first wires which are some of said plurality of wires included in said wiring section are arranged in a gap between said effective pixel area and at least one first circuit block among said plurality of circuit blocks and extend along the outer edge of said effective pixel area across said gap, and a plurality of second wires other than said plurality of first wires are arranged in a position facing said effective pixel area via said plurality of circuit blocks.

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