Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that makes it possible to improve a recovery characteristic by more effectively suppressing hole injection into a diode part in a reverse conducting IGBT (RC-IGBT) in which an IGBT and a diode are incorporated in the same chip.　This semiconductor device has an IGBT and a diode in a same chip, and is characterized in that the IGBT comprises a first conductivity-type first semiconductor layer, a plurality of first trenches formed in the first semiconductor layer; a second conductivity-type body layer sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a first conductivity-type source layer sandwiched between the plurality of first trenches and formed on the body layer, the diode comprises the first semiconductor layer, a plurality of second trenches formed in the first semiconductor layer, an n layer sandwiched between the plurality of second trenches and formed on the first semiconductor layer, and the body layer sandwiched between the plurality of second trenches and formed on the n layer, the n layer and the body layer are partially exposed on the surface in a direction parallel to the second trenches, and the n layer forms a Schottky barrier junction.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device structure and a manufacturing method thereof, and in particular to a technique that is effective when applied to a reverse conducting IGBT (RC-IGBT) in which an IGBT and a diode are built in the same chip.

[0002] IGBTs (Insulated Gate Bipolar Transistors), which are capable of high-power, high-speed switching, are widely used in a wide range of applications, from industrial to consumer, and even automotive applications, including motor control inverters for electric vehicles and trains, and inverter circuits for induction cookware, washing machines, and air conditioners.

[0003] In many applications of IGBTs, there exists a mode in which a freewheeling current flows from the emitter to the collector. Conventionally, to accommodate this freewheeling operation, a freewheeling diode is connected in anti-parallel to the IGBT on a separate chip.

[0004] In recent years, reverse conducting IGBTs (RC-IGBTs), which combine an IGBT and a freewheel diode on a single chip, have become increasingly popular. A reverse conducting IGBT incorporates a freewheel diode into the IGBT chip, and the diode is connected in reverse parallel to the IGBT to perform freewheeling operation.

[0005] As background art in this technical field, for example, there is a technique such as that disclosed in Patent Document 1. Patent Document 1 discloses "Technique for suppressing gate interference in an RC-IGBT employing a diode structure with a Schottky connection."

[0006] In Patent Document 1, n-type pillar layers (24a, 24b) are provided in the diode section, and a Schottky barrier diode is built in, thereby suppressing hole injection into the pn diode.

[0007] Furthermore, Patent Document 2 discloses a "semiconductor device with a short recovery time."

[0008] In Patent Document 2, a connection region 16 is provided in the diode portion, and a lower end 16d and n － The layer 21 has a structure in which a Schottky barrier diode is built in.

[0009] JP 2015-165541 A JP 2017-55079 A

[0010] Reverse conducting IGBTs (RC-IGBTs) have the advantage of being able to reduce chip size by sharing the termination area between the IGBT and diode, and reducing thermal resistance because losses generated in the IGBT area or diode area are dissipated throughout the entire chip.

[0011] On the other hand, since the IGBT and diode are fabricated on the same chip, simultaneous optimization of each chip is difficult, and controlling the lifetime of the diode is particularly difficult, making it difficult to reduce the diode's injection and recovery loss.

[0012] In the above-mentioned Patent Document 1, an n-pillar layer is formed in order to incorporate a Schottky barrier diode in the diode section of the RC-IGBT. However, in order to form this pillar layer, in addition to the normal process of forming the diode section of the RC-IGBT, it is necessary to add a photolithography process and an ion implantation process to form the n-pillar layer. Furthermore, since the n-pillar layer is provided inside the p-body layer, miniaturization is difficult, and there is a problem that there is a limit to the improvement of characteristics.

[0013] In addition, in the above-mentioned Patent Document 2, a connection region is provided in the diode portion, and n － Although a contact layer is provided between the layers, there is no p-body layer in the diode section, so when the breakdown voltage is maintained, the electric field concentrates at the corners of the connection region, which raises concerns about a decrease in the breakdown voltage and an increase in leakage current.

[0014] Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that incorporates an IGBT and a diode on the same chip.

[0015] In order to solve the above-described problems, the present invention provides a semiconductor device having an IGBT and a diode on the same chip, wherein the IGBT comprises a first semiconductor layer of a first conductivity type, a plurality of first trenches formed in the first semiconductor layer, a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a source layer of the first conductivity type sandwiched between the plurality of first trenches and formed on the body layer; the diode comprises the first semiconductor layer, a plurality of second trenches formed in the first semiconductor layer, an n-layer sandwiched between the plurality of second trenches and formed on the first semiconductor layer, and the body layer sandwiched between the plurality of second trenches and formed on the n-layer, wherein the n-layer and the body layer are partially exposed to the surface in a direction parallel to the second trenches, and the n-layer forms a Schottky barrier junction.

[0016] The present invention also provides a method for manufacturing a semiconductor substrate, comprising the steps of: (a) forming a plurality of first trenches in a first region of a main surface of the semiconductor substrate, and forming a plurality of second trenches in a second region; (b) sequentially depositing an insulating film and an electrode film in each of the first trenches and the second trenches, and forming a gate electrode in the first trench and an electrode in the second trench by photolithography and dry etching; (c) forming an n-layer by ion implantation of n-type impurities in the main surface of the semiconductor substrate excluding the first trenches and the second trench; (d) selectively forming a mask between some of the second trenches on the second region; and (e) forming a p-body layer by ion implantation of p-type impurities in the main surface of the semiconductor substrate excluding the first trenches and the second trench. (f) selectively forming a mask between some of the first trenches on the first region and on the second region; (g) forming an n+ layer by ion implantation of n-type impurities on the main surface of the semiconductor substrate excluding the first trenches; (h) selectively forming a mask between some of the first trenches on the first region and between some of the second trenches on the second region; and (i) forming a p+ layer by ion implantation of p-type impurities on the main surface of the semiconductor substrate excluding the first trenches and the second trenches, wherein in the second region, portions of the n layer and the body layer are exposed at the surface of the semiconductor substrate in a direction parallel to the second trenches, and the n layer forms a Schottky barrier junction.

[0017] According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that has an IGBT and a diode built into the same chip.

[0018] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0019] 1A is a perspective view schematically illustrating the structure of a reverse conducting IGBT according to a first embodiment of the present invention; FIG. 1B is a cross-sectional view taken along line AA' of FIG. 1A; FIG. 1C is a diagram illustrating a manufacturing process of the reverse conducting IGBT of FIG. 1A; FIG. 2A is a diagram illustrating a manufacturing process following FIG. 2B; and FIG. 2C is a diagram illustrating a manufacturing process following FIG.

[0020] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0021] A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1A to 2D.

[0022] FIG. 1A is a perspective view schematically illustrating the structure of a reverse conducting IGBT (RC-IGBT) 1 of this embodiment. FIG. 1B is a cross-sectional view taken along the line AA' of FIG. 1A. FIGS. 2A to 2D are diagrams illustrating a manufacturing process for the reverse conducting IGBT 1 of FIGS. 1A and 1B. Note that in each of FIGS. 1A to 2D, the interlayer insulating films, contacts, front electrodes, and back electrodes that the reverse conducting IGBT (RC-IGBT) 1 actually includes are omitted to make the structure easier to understand.

[0023] As shown in FIG. 1A, a reverse conducting IGBT (RC-IGBT) 1 of this embodiment is configured by incorporating an IGBT section 3 and a diode section 4 in the same chip.

[0024] The reverse conducting IGBT 1 is － The semiconductor device has a plurality of trenches 5 formed in the main surface of a semiconductor substrate (silicon substrate) 2. A plurality of trenches 5 are formed in each of the region where the IGBT section 3 is formed and the region where the diode section 4 is formed, and further, a trench 5 is formed in the boundary region between the IGBT section 3 and the diode section 4.

[0025] An insulating film (silicon oxide film) 6 is formed inside each trench 5 so as to cover the bottom and side surfaces of the trench 5 .

[0026] In the region where the IGBT section 3 is formed, an n-layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5, in a manner sandwiched between the trenches 5. Furthermore, on top of the n-layer 9, a p-body layer 10 is formed on the main surface of the semiconductor substrate 2 between the trenches 5, in a manner sandwiched between the trenches 5. Furthermore, on top of the p-body layer 10, an n-layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5, in a manner sandwiched between the trenches 5. ＋ A layer 11 is formed.

[0027] In the IGBT section 3, in the depth direction of FIG. 1A, n ＋ Layer 11 and p ＋ The layers 12 are arranged alternately.

[0028] A gate electrode (polysilicon electrode) 7 is formed inside the trench 5 of the IGBT portion 3 with an insulating film (silicon oxide film) 6 interposed therebetween.

[0029] Meanwhile, in the region where the diode section 4 is formed, an n-layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5, in a manner sandwiched between the trenches 5. Furthermore, a p-body layer 10 is formed on the main surface of the semiconductor substrate 2 between the trenches 5 and in a manner sandwiched between the trenches 5 above the n-layer 9. Furthermore, a p-body layer 10 is formed on the main surface of the semiconductor substrate 2 between the trenches 5 and in a manner sandwiched between the trenches 5 above the p-body layer 10. ＋ A layer 12 is formed.

[0030] In the diode section 4, two p ＋ Between layers 12, p body layer 10, n layer 9 and p body layer 10 are arranged in this order.

[0031] An emitter electrode (polysilicon electrode) 8 is formed inside the trench 5 of the diode portion 4 with an insulating film (silicon oxide film) 6 interposed therebetween.

[0032] 1B , the n layer 9 and p body layer 10 of the diode section 4 are partially exposed on the surface of the semiconductor substrate (silicon substrate) 2, and the n layer 9 forms a Schottky barrier junction (SBD). A pn ​​junction is also formed between the n layer 9 and the p body layer 10.

[0033] An n-buffer layer 14 is formed on the back surface side of the semiconductor substrate 2. A p-layer (collector layer) 15 is further formed outside the n-buffer layer 14 of the IGBT section 3, and a n-layer (collector layer) 16 is further formed outside the n-buffer layer 14 of the diode section 4. ＋ A layer (cathode layer) 16 is formed.

[0034] The reverse conducting IGBT (RC-IGBT) 1 of this embodiment is configured as described above, and in the diode section 4, the n layer 9 provided under the p body layer 10 is exposed to the surface in the depth direction sandwiched between the trenches 5, forming a Schottky barrier junction (SBD). Because it is formed in the depth direction, miniaturization is possible, and there is no need to provide a separate pillar layer or the like.

[0035] Furthermore, when the breakdown voltage is maintained, the surface n layer 9 can maintain the breakdown voltage because a depletion layer extends from the p body layer 10 sandwiching the n layer 9 and the adjacent trench 5 .

[0036] A method for manufacturing the reverse conducting IGBT (RC-IGBT) 1 shown in FIGS. 1A and 1B will be described with reference to FIGS. 2A to 2D.

[0037] First, as shown in FIG. 2A, － A plurality of trenches 5 are formed in the main surface of a mold semiconductor substrate (silicon substrate) 2. At this time, the trenches 5 are formed in a region where the IGBT section 3 is to be formed, a region where the diode section 4 is to be formed, and a boundary region between the IGBT section 3 and the diode section 4.

[0038] Next, an insulating film (silicon oxide film) 6 and a polysilicon film (polysilicon electrodes 7, 8) are formed in this order on the main surface of the semiconductor substrate 2 so as to fill the trench 5 of the IGBT section 3, the trench 5 of the diode section 4, and the trench 5 in the boundary region between the IGBT section 3 and the diode section 4. Photolithography and dry etching are then used to form a gate electrode 7 in the trench 5 of the IGBT section 3, and an emitter electrode 8 in the trench 5 of the diode section 4.

[0039] Next, as shown in FIG. 2B, a deep n-layer 9 is formed on the main surface of the semiconductor substrate 2 excluding the trenches 5, the insulating films 6, and the electrodes 7 and 8 by ion implantation of n-type impurities.

[0040] Next, as shown in FIG. 2C , a mask is selectively formed between some of the trenches 5 above the region where the diode portion 4 is to be formed, and p-type impurity ions are implanted into the main surface of the semiconductor substrate 2 to form a p-body layer 10 .

[0041] In the IGBT section 3, the p-body layer 10 is formed on the entire surface between the trenches 5, and serves as a channel layer.

[0042] On the other hand, in the diode section 4, patterning is performed in a direction parallel to the trench 5, and the p-body layer 10 is formed so that a deep n-layer 9 is partially left on the surface.

[0043] The portion where the p body layer 10 is exposed to the surface becomes a pn diode, and the remaining portion of the n layer 9 becomes a Schottky barrier diode (SBD).

[0044] Next, as shown in FIG. 2D , a mask is selectively formed between some of the trenches 5 in the region where the IGBT section 3 is to be formed and on the region where the diode section 4 is to be formed, and n-type impurity ions are implanted into the main surface of the semiconductor substrate 2 excluding the trenches 5 in the region where the IGBT section 3 is to be formed. ＋ Layer 11 is formed.

[0045] Next, a mask is selectively formed between some of the trenches 5 in the region where the IGBT section 3 is to be formed and between some of the trenches 5 in the region where the diode section 4 is to be formed, and p-type impurity ions are implanted into the main surface of the semiconductor substrate 2 except for the trenches 5 in the region where the IGBT section 3 is to be formed and the trenches 5 in the region where the diode section 4 is to be formed. ＋ Layer 12 is formed.

[0046] The IGBT section 3 has n ＋ Layer 11 and p ＋ The diode section 4 has a p-type body layer 10 and a p-type body layer 12 formed alternately. ＋ A layer 12 is provided. ＋By making layer 12 a part of p-body layer 10, injection from the surface anode layer can also be reduced.

[0047] Although not shown, an interlayer insulating film is then formed on the main surface of the semiconductor substrate 2, and contact holes are formed by photolithography and dry etching to penetrate the interlayer insulating film and expose the semiconductor substrate 2. A metal film is then formed on the main surface of the semiconductor substrate 2 so as to fill the contact holes, and contacts and surface electrodes are formed by photolithography and dry etching.

[0048] Furthermore, the n-type buffer layer 14 on the rear surface, the p-type layer (collector layer) 15, and the n-type ＋ A layer (cathode layer) 16 and a back electrode are formed, and the reverse conducting IGBT (RC-IGBT) 1 is completed.

[0049] As described above, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment is a semiconductor device having an IGBT and a diode on the same chip, and the IGBT section 3 is a first semiconductor layer (n － layer 13) and the first semiconductor layer (n － A plurality of first trenches 5 are formed in the first semiconductor layer (n － a second conductivity type body layer (p body layer 10) formed on the first conductivity type body layer (p layer 13), and a first conductivity type source layer (n ＋ The diode section 4 has a first semiconductor layer (n － layer 13) and the first semiconductor layer (n － A plurality of second trenches 5 are formed in the first semiconductor layer (n － The semiconductor device has an n layer 9 formed on the second trench 5 (layer 13), and a p body layer 10 sandwiched between the plurality of second trenches 5 and formed on the n layer 9, where n layer 9 and p body layer 10 are partially exposed to the surface in a direction parallel to the second trenches 5, and n layer 9 forms a Schottky barrier junction.

[0050] Furthermore, when reverse conducting IGBT (RC-IGBT) 1 is viewed from above, n layer 9 exposed on the surface is sandwiched between two p body layers 10 exposed on the surface.

[0051] In addition, a second conductivity type layer (p ＋ A layer 12) is provided.

[0052] Then, the second conductive type layer (p ＋ The surface of the layer 12) is substantially flush with the exposed surfaces of the n layer 9 and p body layer 10.

[0053] This makes it possible to more effectively suppress hole injection into the diode section and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that incorporates an IGBT and a diode on the same chip.

[0054] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0055] REFERENCE SIGNS LIST 1... reverse conducting IGBT (RC-IGBT) 2... semiconductor substrate (silicon substrate) 3... IGBT section 4... diode section 5... trench 6... insulating film (silicon oxide film) 7... gate electrode (polysilicon electrode) 8... emitter electrode (polysilicon electrode) 9... n layer 10... p body layer 11... n ＋ Layer 12...p ＋ Layer 13...n － Layer 14...n buffer layer 15...p layer (collector layer) 16...n ＋ layer (cathode layer).

Claims

1. A semiconductor device having an IGBT and a diode on the same chip, wherein the IGBT comprises: a first semiconductor layer of a first conductivity type; a plurality of first trenches formed in the first semiconductor layer; a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer; and a source layer of the first conductivity type sandwiched between the plurality of first trenches and formed on the body layer; and the diode comprises: the first semiconductor layer; a plurality of second trenches formed in the first semiconductor layer; an n-layer sandwiched between the plurality of second trenches and formed on the first semiconductor layer; and the body layer sandwiched between the plurality of second trenches and formed on the n-layer, wherein the n-layer and the body layer are partially exposed to the surface in a direction parallel to the second trenches, and the n-layer forms a Schottky barrier junction.

2. A semiconductor device according to claim 1, characterized in that, when the semiconductor device is viewed in plan, the n-layer exposed on the surface is sandwiched between two of the body layers exposed on the surface.

3. A semiconductor device according to claim 1, wherein a second conductivity type layer having a higher concentration than the body layer is provided in a part of the body layer.

4. A semiconductor device according to claim 3, wherein the surface of the second conductivity type layer is substantially flush with the exposed surfaces of the n-layer and the body layer.

5. (a) forming a plurality of first trenches in a first region of a main surface of a semiconductor substrate and forming a plurality of second trenches in a second region; (b) sequentially depositing an insulating film and an electrode film in each of the first trenches and the second trenches, and forming a gate electrode in the first trench and an electrode in the second trench by photolithography and dry etching; (c) forming an n-layer by ion implantation of n-type impurities on the main surface of the semiconductor substrate excluding the first trenches and the second trench; (d) selectively forming a mask between some of the second trenches on the second region; (e) forming a p-body layer by ion implantation of p-type impurities on the main surface of the semiconductor substrate excluding the first trenches and the second trench; (f) selectively forming a mask between some of the first trenches on the first region and on the second region; (g) implanting n-type impurities into the main surface of the semiconductor substrate excluding the first trench; ＋ (h) selectively forming a mask between some of the first trenches on the first region and between some of the second trenches on the second region; and (i) implanting p-type impurities into the main surface of the semiconductor substrate excluding the first trenches and the second trenches. ＋ and forming a layer, wherein in the second region, the n-layer and the body layer are partially exposed at the surface of the semiconductor substrate in a direction parallel to the second trench, and the n-layer forms a Schottky barrier junction.

6. A method for manufacturing a semiconductor device according to claim 5, wherein an IGBT is formed in the first region, and a diode is formed in the second region.

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