Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises a base substrate (SBT), a driving layer (DRL) and a pixel layer (PIXL) which are sequentially stacked; the display panel comprises circuit regions (PA) distributed in an array, and one pixel driving circuit for driving sub-pixels is provided in one circuit region (PA); the driving layer (DRL) is provided with data signal wires (DL), and each pixel driving circuit is provided with a data write transistor (T4) electrically connected to the corresponding data signal wire (DL); the orthographic projection of a channel region (T4A) of the data write transistor on the base substrate (SBT) at least partially overlaps the orthographic projection of the data signal wire (DL) on the base substrate (SBT). The display panel and the display device using the display panel can improve pixel density.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the demand for high PPI (pixel density) LTPO (low temperature polysilicon semiconductor + metal oxide semiconductor) technology is becoming more and more intense; in order to improve the display quality of the display panel, the COE (color film process) scheme can be carried at the same time on the basis of the LTPO technology, and a high sensor opening rate needs to be ensured, so pixel compression is urgently needed to meet the compatibility of the two.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display panel and a display device.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a substrate substrate, a driving layer and a pixel layer which are sequentially stacked; the display panel has an array distribution of circuit regions, and one of the circuit regions has a pixel driving circuit for driving a sub-pixel;

[0007] The driving layer is provided with a data signal trace, and the pixel driving circuit has a data write transistor electrically connected to the data signal trace; the channel region of the data write transistor has a normal projection on the substrate substrate which at least partially overlaps with the normal projection of the data signal trace on the substrate substrate.

[0008] According to an embodiment of the present disclosure, in two circuit regions adjacent in a first direction, the thin film transistors of the two pixel driving circuits are symmetrically arranged;

[0009] The driving layer comprises a transistor layer and a first source-drain metal layer which are sequentially stacked, and the thin film transistor is arranged in the transistor layer;

[0010] The driving layer has a multiplexing via across the boundary line between two adjacent circuit regions, and the first source-drain metal layer is connected to the thin film transistors of the two pixel driving circuits through the multiplexing via.

[0011] According to an embodiment of the present disclosure, the display panel includes an array of first circuit region groups, each of the first circuit region groups including two circuit regions adjacent along a first direction;

[0012] The pixel driving circuit includes a first light-emitting transistor electrically connected to a power voltage terminal; the transistor layer is provided with a first polysilicon conductive structure serving as a first electrode of the two first light-emitting transistors in the first circuit region group;

[0013] The multiplexing via includes a first multiplexing via in the first circuit region group, the first multiplexing via exposing the first polysilicon conductive structure;

[0014] In the first circuit region group, the first source-drain metal layer includes a power voltage metal structure capable of loading a power voltage;

[0015] The power voltage metal structure is electrically connected to the first polysilicon conductive structure through the first multiplexing via.

[0016] According to an embodiment of the present disclosure, the display panel includes an array of first circuit region groups, each of the first circuit region groups including two circuit regions adjacent along a first direction;

[0017] The pixel driving circuit further includes a second reset transistor, a second electrode of the second reset transistor being electrically connected to a second electrode of the first light-emitting transistor; a first electrode of the second reset transistor being electrically connected to a third initialization voltage terminal;

[0018] The transistor layer is provided with a second polysilicon conductive structure serving as a first electrode of the two second reset transistors in the first circuit region group;

[0019] The multiplexing via includes a second multiplexing via in the first circuit region group, the second multiplexing via exposing the second polysilicon conductive structure;

[0020] In the first circuit region group, the first source-drain metal layer includes a third initialization metal structure capable of loading a third initialization voltage;

[0021] The third initialization metal structure is electrically connected to the second polysilicon conductive structure through the second multiplexing via.

[0022] According to an embodiment of the present disclosure, the display panel includes an array of second circuit region groups, each of the second circuit region groups including two circuit regions adjacent along a first direction;

[0023] The pixel driving circuit comprises a driving transistor and a first reset transistor for electrical connection with a first initialization voltage terminal; a first electrode of the driving transistor is electrically connected with a second electrode of the data writing transistor, and a second electrode of the driving transistor is electrically connected with a second electrode of the first reset transistor;

[0024] The transistor layer is provided with a third polycrystalline silicon conductive structure as the first electrode of the two first reset transistors in the second circuit region group;

[0025] The multiplexing via comprises a third multiplexing via in the second circuit region group, and the third multiplexing via exposes the third polycrystalline silicon conductive structure;

[0026] In the second circuit region group, the first source-drain metal layer comprises a first initialization metal structure capable of loading a first initialization voltage;

[0027] The first initialization metal structure is electrically connected with the third polycrystalline silicon conductive structure through the third multiplexing via.

[0028] According to an embodiment of the present disclosure, the driving layer comprises a low-temperature polycrystalline silicon semiconductor layer, a metal oxide semiconductor layer and a first source-drain metal layer which are sequentially stacked;

[0029] The pixel driving circuit further comprises a first reset transistor, a threshold compensation transistor, a driving transistor and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected with a first initialization voltage terminal, a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor and a first electrode of the second light-emitting transistor are electrically connected, and a second electrode of the second light-emitting transistor is electrically connected with a pixel electrode; a second electrode of the threshold compensation transistor is electrically connected with a gate electrode of the driving transistor;

[0030] The channel region of the first reset transistor, the channel region of the driving transistor and the channel region of the second light-emitting transistor are located in the low-temperature polycrystalline silicon semiconductor layer; and the channel region of the threshold compensation transistor is located in the metal oxide semiconductor layer;

[0031] The channel region of the first reset transistor, the channel region of the threshold compensation transistor and the channel region of the second light-emitting transistor are arranged linearly along a second direction.

[0032] According to an embodiment of the present disclosure, the transistor layer comprises a low-temperature polycrystalline silicon semiconductor layer and a metal oxide semiconductor layer which are stacked;

[0033] The pixel driving circuit further comprises a first reset transistor, a threshold compensation transistor, a driving transistor and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected with a first initialization voltage terminal; a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor and a first electrode of the second light-emitting transistor are electrically connected; a second electrode of the second light-emitting transistor is electrically connected with a pixel electrode; a second electrode of the threshold compensation transistor is electrically connected with a gate electrode of the driving transistor;

[0034] The channel region of the first reset transistor, the channel region of the driving transistor and the channel region of the second light-emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is arranged in the metal oxide semiconductor layer;

[0035] Along the first direction, the channel region of the first reset transistor and the channel region of the threshold compensation transistor are arranged alternately.

[0036] According to an embodiment of the present disclosure, in the circuit region, the metal oxide semiconductor layer comprises a first metal oxide structure arranged along a first direction and a second metal oxide structure arranged along a second direction;

[0037] The first metal oxide structure is connected with the second metal oxide structure at one end close to the data writing transistor; the channel region of the threshold compensation transistor is located in the second metal oxide structure.

[0038] According to an embodiment of the present disclosure, the first source-drain metal layer comprises a first metal structure and a second metal structure;

[0039] The second metal structure is electrically connected with the second electrode of the first reset transistor, the second electrode of the driving transistor and the first electrode of the threshold compensation transistor through a via hole;

[0040] The first metal structure is electrically connected with the second electrode of the threshold compensation transistor and the gate electrode of the driving transistor through a via hole;

[0041] The size of the second metal structure along the second direction is smaller than the size of the first metal structure along the second direction.

[0042] According to an embodiment of the present disclosure, the driving layer comprises a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, a first source-drain metal layer and a second source-drain metal layer arranged in sequence;

[0043] The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a second scan signal trace electrically connected with the gate of the data writing transistor.

[0044] In the circuit area, the second scan signal trace includes a first sub scan trace located in the first source-drain metal layer and a second sub scan trace located in the second source-drain metal layer.

[0045] The first sub scan trace is electrically connected with the gate of the data writing transistor through a via, and the second sub scan trace is electrically connected with the first sub scan trace through a via.

[0046] According to an embodiment of the present disclosure, in the circuit area, the metal oxide semiconductor layer includes a second metal oxide structure arranged along the second direction; one end of the second metal oxide structure away from the channel area of the driving transistor is electrically connected with the gate of the driving transistor through the first metal structure located in the first source-drain metal layer.

[0047] In the circuit area, the first metal structure is arranged in overlap with the second sub scan trace.

[0048] According to an embodiment of the present disclosure, the driving layer includes a low temperature poly-silicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer arranged in sequence.

[0049] The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a first sub scan trace electrically connected with the gate of the data writing transistor.

[0050] The first sub scan trace is located in the first source-drain metal layer and is electrically connected with the gate of the data writing transistor through a via.

[0051] According to an embodiment of the present disclosure, in the circuit area, the metal oxide semiconductor layer includes a first metal oxide structure, a second metal oxide structure and a third metal oxide structure connected in sequence, the first metal oxide structure and the third metal oxide structure are arranged in parallel along the second direction; the second metal oxide structure is arranged along the first direction, and the one end of the first metal oxide structure away from the driving transistor and the one end of the third metal oxide structure away from the driving transistor are electrically connected with each other.

[0052] The third metal oxide structure is electrically connected with the gate of the driving transistor through the first metal structure in the first source-drain metal layer at one end close to the driving transistor; and the first metal oxide structure is electrically connected with the second electrode of the driving transistor through the second metal structure in the first source-drain metal layer at one end close to the driving transistor.

[0053] The pixel driving circuit has a threshold compensation transistor, which includes two sub-transistors, and the channel regions of the two sub-transistors are located on the first metal oxide structure and the third metal oxide structure, respectively.

[0054] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked.

[0055] The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure which serves as the second electrode of the first reset transistor.

[0056] The fourth polysilicon conductive structure is electrically connected with the second electrode of the driving transistor through the second metal structure in the first source-drain metal layer at one end close to the channel region of the driving transistor.

[0057] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked.

[0058] The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure and a fifth polysilicon conductive structure, the fourth polysilicon conductive structure serving as the second electrode of the first reset transistor, and the fifth polysilicon conductive structure being connected with the drain electrode of the driving transistor.

[0059] The fourth polysilicon conductive structure is connected with the fifth polysilicon conductive structure at one end close to the channel region of the driving transistor.

[0060] According to an embodiment of the present disclosure, the driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer which are sequentially stacked.

[0061] The pixel driving circuit further includes a second reset transistor and a first light-emitting transistor, the second electrode of the second reset transistor being electrically connected with the second electrode of the first light-emitting transistor, the first electrode of the second reset transistor being electrically connected with a third initialization voltage terminal, and the first light-emitting transistor being electrically connected with a power voltage terminal.

[0062] The driving layer has a third initialization voltage trace for loading a third initialization voltage and an enable signal line for loading an enable signal;

[0063] The third initialization voltage trace is located in the third gate layer and extends along a first direction, and the enable signal line is located in the first gate layer and extends along the first direction; the enable signal line is arranged to overlap the third initialization voltage trace.

[0064] According to a second aspect of the present disclosure, a display device is provided, comprising the display panel described above.

[0065] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0066] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0067] FIG. 1 is a schematic diagram of an array arrangement of circuit regions in an embodiment of the present disclosure.

[0068] FIG. 2 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0069] FIG. 3 is a schematic diagram of a film layer structure of a display panel in an embodiment of the present disclosure.

[0070] FIG. 4 is a schematic diagram of a low-temperature polysilicon semiconductor layer in an embodiment of the present disclosure.

[0071] FIG. 5 is a schematic diagram of a first gate layer in an embodiment of the present disclosure.

[0072] FIG. 6 is a schematic diagram of a second gate layer in an embodiment of the present disclosure.

[0073] FIG. 7 is a schematic diagram of a metal-oxide semiconductor layer in an embodiment of the present disclosure.

[0074] FIG. 8 is a schematic diagram of a third gate layer in an embodiment of the present disclosure.

[0075] FIG. 9 is a schematic diagram of a first source-drain metal layer in an embodiment of the present disclosure.

[0076] FIG. 10 is a schematic diagram of a second source-drain metal layer in an embodiment of the present disclosure.

[0077] FIG. 11 is a schematic diagram of a third source-drain metal layer in one embodiment of the disclosure.

[0078] FIG. 12 is a schematic diagram of a low temperature polysilicon semiconductor layer in one embodiment of the disclosure.

[0079] FIG. 13 is a schematic diagram of a first gate layer in one embodiment of the disclosure.

[0080] FIG. 14 is a schematic diagram of a second gate layer in one embodiment of the disclosure.

[0081] FIG. 15 is a schematic diagram of a metal-oxide-semiconductor layer in one embodiment of the disclosure.

[0082] FIG. 16 is a schematic diagram of a third gate layer in one embodiment of the disclosure.

[0083] FIG. 17 is a schematic diagram of a first source-drain metal layer in one embodiment of the disclosure.

[0084] FIG. 18 is a schematic diagram of a second source-drain metal layer in one embodiment of the disclosure.

[0085] FIG. 19 is a schematic diagram of a low temperature polysilicon semiconductor layer in one embodiment of the disclosure.

[0086] FIG. 20 is a schematic diagram of a first gate layer in one embodiment of the disclosure.

[0087] FIG. 21 is a schematic diagram of a second gate layer in one embodiment of the disclosure.

[0088] FIG. 22 is a schematic diagram of a metal-oxide-semiconductor layer in one embodiment of the disclosure.

[0089] FIG. 23 is a schematic diagram of a third gate layer in one embodiment of the disclosure.

[0090] FIG. 24 is a schematic diagram of a first source-drain metal layer in one embodiment of the disclosure.

[0091] FIG. 25 is a schematic diagram of a low temperature polysilicon semiconductor layer in one embodiment of the disclosure.

[0092] FIG. 26 is a schematic diagram of a first gate layer in one embodiment of the disclosure.

[0093] FIG. 27 is a schematic diagram of a second gate layer in one embodiment of the disclosure.

[0094] FIG. 28 is a schematic diagram of a metal-oxide-semiconductor layer in one embodiment of the disclosure.

[0095] FIG. 29 is a schematic diagram of a third gate layer in one embodiment of the disclosure.

[0096] Figure 30 is a schematic diagram of a first source-drain metal layer in one embodiment of the disclosure.

[0097] Figure 31 is a schematic diagram of a data signal trace and a channel region of a data write transistor that overlap in one embodiment of the disclosure.

[0098] BRIEF DESCRIPTION OF DRAWINGS

[0099] T1, first reset transistor; T2, threshold compensation transistor; T3, driving transistor; T4, data write transistor; T5, first light emitting transistor; T6, second light emitting transistor; T7, electrode reset transistor; T8, second reset transistor; Cst, storage capacitor; CP1, first electrode; CP2, second electrode; Vinit1, first initialization voltage; Vinit2, second initialization voltage; Vinit3, third initialization voltage; N1, first node; N2, second node; N3, third node; N4, fourth node; ResetH, first capacitor reset control signal; ResetP, second capacitor reset control signal; EM, enable signal; GN, first scan signal; Data, data signal; GP, second scan signal; VDD, power voltage; VSS, reference voltage; T1A, channel region of first reset transistor; T2A, channel region of threshold compensation transistor; T3A, channel region of driving transistor; T4A, channel region of data write transistor; T5A, channel region of first light emitting transistor; T6A, channel region of second light emitting transistor; T7A, channel region of electrode reset transistor; T8A, channel region of second reset transistor; HB1, first upper via region; HB2, second upper via region; HB3, third upper via region; HB4, fourth upper via region; HB5, fifth upper via region; HB6, sixth upper via region; HB7, seventh upper via region; HB8, eighth upper via region; HB9, ninth upper via region; HB10, tenth upper via region; HB11, eleventh upper via region; HB12, twelfth upper via region; HB13, thirteenth upper via region; HB14, fourteenth upper via region; HB15, fifteenth upper via region; HB16, sixteenth upper via region; HB17, seventeenth upper via region; HA1, first lower via region; HA2, second lower via region; HA3, third lower via region; HA4, fourth lower via region; HA5, fifth lower via region; HA6, sixth lower via region; HA7, seventh lower via region; HA8, eighth lower via region; HA9, ninth lower via region; HA10, tenth lower via region; HA11, eleventh lower via region; HA12, twelfth lower via region; HA13, thirteenth lower via region; HA14, fourteenth lower via region; HA15, fifteenth lower via region; HA16, sixteenth lower via region; HA17, seventeenth lower via region; HA18, eighteenth lower via region; HB18, eighteenth upper via region; HA19, nineteenth lower via region; HB19, nineteenth upper via region; HA20, twentieth lower via region; HB20, twentieth upper via region; HA21, twentieth first lower via region; HB21, twenty first upper via region; HA22, twenty second lower via region; HB22, twenty second upper via region; HA23, twenty third lower via region; HB23, twenty third upper via region; HA24, twenty fourth lower via region;HB24, twenty-fourth lower via region; HA25, twenty-fifth lower via region; HB25, twenty-fifth upper via region; HA26, twenty-sixth lower via region; HB26, twenty-sixth upper via region; HA27, twenty-seventh lower via region; HB27, twenty-seventh upper via region; HA28, twenty-eighth lower via region; HB28, twenty-eighth upper via region; HA29, twenty-ninth lower via region; HB29, twenty-ninth upper via region; RL1, first capacitor reset control signal line; RL2, second capacitor reset control signal line; EML, enable signal line; GNLA, first scan signal first trace; GNLB, first scan signal second trace; GPL, second scan signal trace; GPL1, first sub-scan trace; GPL2, second sub-scan trace; H1, first direction; H2, second direction; VLT1, first initialization voltage trace; VLT2, second initialization voltage trace; VLT3, third initialization voltage trace; SBT, substrate base plate; DRL, driving layer; TL, transistor layer; LSCL, low temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; SD3, third source-drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; OSCL, metal-oxide semiconductor layer; PLN3, third planarization layer; PDL, pixel definition layer; PEL, pixel electrode layer; COML, common electrode layer; EL, light-emitting functional layer; PIX, sub-pixel; TFE, thin film encapsulation layer; MA1, first bridge portion; MA2, second bridge portion; MA3, third bridge portion; MA4, fourth bridge portion; MA5, fifth bridge portion; MA6, sixth bridge portion; MA7, seventh bridge portion; MA9, ninth bridge portion; MA10, tenth bridge portion; MB1, first conductive portion; MB2, second conductive portion; MB3, third conductive portion; MB4, fourth conductive portion; MC1, first metal portion; MH, multiplexing via; MHA, first multiplexing via; MHB, second multiplexing via; MHC, third multiplexing via; PLA, first polysilicon conductive structure; PLB, second polysilicon conductive structure; PLC, third polysilicon conductive structure; PLD, fourth polysilicon conductive structure; PLE, fifth polysilicon conductive structure; MS1, first metal structure; MS2, second metal structure; OLA, first metal-oxide structure; OLB, second metal-oxide structure; OLC, third metal-oxide structure; SWL, standby signal trace; DL, data signal trace; PA, circuit region; PAS1, first circuit region group; PAS2, second circuit region group. DETAILED DESCRIPTION

[0100] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification. Moreover, the figures can not be to scale and some features can be exaggerated to show details of particular implementations. Measures of thicknesses and lengths and the like are not intended to be exact unless explicitly stated as such.

[0101] Although relative terms such as "on", "under", "lower", "upper" and the like can be used herein to describe one component's relationship to another component, these terms are used for convenience only and are not intended to be limiting. It is to be understood that the use of such relative terms is intended to encompass different positions of an icon's components in which the position can be turned over and the components are positioned "on", "under", "lower", "upper", etc. with respect to one another. A component can be "on", "under", "lower", "upper", etc. another component by directly contacting the other component or by not directly contacting the other component with additional components being interposed therebetween.

[0102] The terms "a", "an", "the" and "at least one" are used to mean one or more of the components / elements / features / constructions; the terms "comprising", "having" and "including" are used to mean that other components / elements / features / constructions can be added; and the terms "first", "second", "third", etc. are used only to distinguish one component / element / feature / construction from another.

[0103] The structure layer A is formed on the side of the structure layer B away from the substrate. It is understood that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure layer A can be at the same physical height as the structure layer B or lower than the structure layer B, wherein the substrate is the height reference.

[0104] In the embodiments of the present disclosure, a thin film transistor includes an active layer, a gate insulating layer, and a gate electrode which are stacked. The active layer is provided on a semiconductor layer, and includes a channel region and a source and a drain which are provided on both sides of the channel region, respectively. The channel region retains a semiconductor property, and the source and the drain are each conductive. In the embodiments of the present disclosure, the functions of the "source" and the "drain" are sometimes exchanged with each other, i.e., the "source" and the "drain" can be exchanged with each other, in the case where transistors of opposite polarities are used or the direction of current is changed in the operation of a circuit, and the like. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor.

[0105] With the rapid development of the display industry, people pursue higher and higher picture quality of display panels, and the demand for high PPI LTPO technology is more and more intense. In order to further improve the picture quality of the display panel, the COE scheme is also used in the LTPO technology, so it is necessary to ensure a high sensor opening rate, and therefore pixel compression is urgently needed to meet the compatibility of both.

[0106] Based on this, the display panel provided by the embodiment of the present disclosure, and Fig. 3 is a schematic diagram of the film layer structure of the display panel in an exemplary embodiment of the present disclosure. Referring to Fig. 3, the display panel includes a substrate SBT, a driving layer DRL and a pixel layer PIXL which are sequentially stacked; the display panel has an array of circuit areas PA, and one pixel driving circuit for driving a sub-pixel is arranged in one circuit area PA; the driving layer DRL is provided with a data signal wire DL, and the pixel driving circuit has a data writing transistor T4 electrically connected with the data signal wire DL; the channel region T4A of the data writing transistor is at least partially overlapped with the normal projection of the data signal wire DL on the substrate SBT (see Fig. 31).

[0107] In the embodiment of the present disclosure, the normal projection of the data signal wire DL on the substrate SBT is overlapped with the normal projection of the channel region T4A of the data writing transistor on the substrate SBT, which realizes the compression of the pixel driving circuit, effectively reduces the size of the single pixel driving circuit, and further helps to improve the pixel density of the display panel.

[0108] Referring to Fig. 2, it is an equivalent circuit diagram of the pixel driving circuit in an exemplary embodiment of the present disclosure. The pixel driving circuit can include a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, a second reset transistor T8 and a storage capacitor Cst. Among them, the first reset transistor T1 and the threshold compensation transistor T2 are N-type thin film transistors, such as metal oxide thin film transistors; the rest of the thin film transistors are P-type thin film transistors, such as low-temperature polysilicon thin film transistors.

[0109] Referring to Fig. 2, the first electrode of the first reset transistor T1 is used to load the first initialization voltage Vinit1, the gate electrode is used to load the first capacitor reset control signal ResetP, and the second electrode of the first reset transistor T1 is connected with the third node N3. The first reset transistor T1 is used to load the first initialization voltage Vinit1 to the third node N3 in response to the first capacitor reset control signal ResetP.

[0110] The first pole of the threshold compensation transistor T2 is electrically connected with the third node N3, the second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, and the gate of the threshold compensation transistor T2 is used for loading the first scanning signal GN; the threshold compensation transistor T2 is used for turning on in response to the first scanning signal GN, so as to write the first initialization voltage Vinit1 of the first reset transistor T1 into the first node N1.

[0111] The first pole of the driving transistor T3 is connected with the second node N2, the second pole of the driving transistor T3 is connected with the third node N3, and the gate of the driving transistor T3 is connected with the first node N1; the driving transistor T3 is configured to turn on or off under the control of the first node N1.

[0112] The first pole of the data writing transistor T4 is used for loading the data signal Data, the second pole of the data writing transistor T4 is electrically connected with the second node N2, and the gate of the data writing transistor T4 is used for loading the second scanning signal GP; the data writing transistor T4 is used for turning on in response to the second scanning signal GP, and loading the data signal Data into the second node N2.

[0113] The first pole of the first light emitting transistor T5 is used for loading the power supply voltage VDD, the second pole of the first light emitting transistor T5 is connected with the second node N2, and the gate is used for loading the enable signal EM.

[0114] The first pole of the second light emitting transistor T6 is connected with the third node N3, the second pole is connected with the fourth node, and the gate is used for loading the enable signal EM; the first light emitting transistor T5 and the second light emitting transistor T6 are used for turning on in response to the enable signal EM.

[0115] The first pole of the electrode reset transistor T7 is used for loading the second initialization voltage Vinit2, the gate of the electrode reset transistor T7 is used for loading the second capacitor reset control signal ResetH, the second pole of the electrode reset transistor T7 is connected with the fourth node N4, and the electrode reset transistor T7 is used for loading the second initialization voltage Vinit2 into the fourth node N4 in response to the second capacitor reset control signal ResetH.

[0116] The first pole of the second reset transistor T8 is used for loading the third initialization voltage Vinit3, the gate of the second reset transistor T8 is used for loading the second capacitor reset control signal ResetH, the second pole of the second reset transistor T8 is connected with the second node N2, and the second reset transistor T8 is used for loading the third initialization voltage Vinit3 into the second node N2 in response to the second capacitor reset control signal ResetH.

[0117] The pixel electrode of the light emitting element is electrically connected with the pixel driving circuit (the connection between the light emitting element and the pixel electrode is not specifically shown in the figure), the common electrode is used to load a reference voltage VSS, one end of the storage capacitor Cst is connected with the first node N1, and the other end is used to load a power voltage VDD.

[0118] Optionally, the substrate SBT can be an inorganic material substrate SBT, an organic material substrate SBT, or a composite substrate formed by laminating an inorganic material substrate SBT and an organic material substrate SBT. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, or sapphire glass. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate SBT, for example, the material of the substrate SBT can include polyimide.

[0119] Optionally, in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor Cst (not specifically shown in the figure). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0120] It can be understood that the types of any two transistors in the pixel driving circuit can be the same or different. For example, in some embodiments, in one pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit, the material of the active layer of some transistors can be low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0121] Optionally, referring to FIG. 3, the driving layer DRL can include a semiconductor layer (see FIG. 3, such as a low-temperature polysilicon semiconductor layer LSCL and a metal-oxide semiconductor layer OSCL), a gate insulating layer (see FIG. 3, such as a first gate insulating layer GI1, a second gate insulating layer GI2 and a third gate insulating layer GI3), a gate layer (see FIG. 3, such as a first gate layer GT1, a second gate layer GT2 and a third gate layer GT3), an interlayer dielectric layer ILD, a source-drain metal layer (see FIG. 3, such as a first source-drain metal layer SD1, a second source-drain metal layer SD2 and a third source-drain metal layer SD3), a planarization layer (see FIG. 3, such as a first planarization layer PLN1, a second planarization layer PLN2 and a third planarization layer PLN3), etc. stacked between the substrate base plate SBT and the pixel layer PIXL. Each thin-film transistor and the storage capacitor Cst (not shown in the drawings) can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer, etc. Of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer can be used to form the channel region (as part of the active layer) of the transistor, and can also be used to form part of the wiring or conductive structure by being made conductive if necessary. The gate layer can be used to form one or more of the gate layer wiring such as the scan wiring, the reset control wiring, the light-emitting control wiring, etc., and can also be used to form the gate electrode of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor Cst. The source-drain metal layer can be used to form the data wiring, the driving power voltage wiring VDDL, etc. of the source-drain metal layer wiring, and can also be used to form part of the electrode plate of the storage capacitor Cst. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as an optical shielding layer between the semiconductor layer and the substrate base plate SBT, etc. Any of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, etc. can also be multi-layered as needed, such as two different semiconductor layers in the driving layer DRL, or two or three source-drain metal layers or two or three gate layers; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0122] As an example, the driving layer DRL can further include a low-temperature polysilicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal-oxide semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1, a second source-drain metal layer SD2 and a third source-drain metal layer SD3 stacked between the substrate base plate SBT and the pixel layer PIXL.

[0123] Optionally, referring to FIG. 3, the pixel layer PI XL can include a pixel electrode layer PEL, an emission functional layer EL, and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE one by one, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area (the area directly connected to the emission functional layer EL) of the pixel electrode, and further define the light-emitting area and light-emitting area of the sub-pixel. The common electrode layer COML covers the emission functional layer EL as a common electrode. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the emission functional layer EL, so that the emission functional layer EL emits light. The part of the emission functional layer EL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element of the sub-pixel. One of the pixel electrode and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0124] In this example, the display panel is an OLED (organic light-emitting diode) display substrate. The emission functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0125] It can be understood that the display panel can also be other types of display panels, such as a QLED (electroluminescence quantum dot) display panel, a QD-OLED (electroluminescence quantum dot and organic light-emitting diode combined) display panel, or other types of display panels.

[0126] In some embodiments of the present disclosure, referring to FIG. 1, in two adjacent circuit areas PA along a first direction, the thin film transistors of the two pixel driving circuits are symmetrically arranged; the driving layer DRL includes a transistor layer TL and a first source-drain metal layer SD1 arranged in sequence, and the thin film transistor is arranged in the transistor layer TL; the driving layer DRL has a multiplexing via MH across the boundary line between the two adjacent circuit areas PA, and the first source-drain metal layer SD1 is connected to the thin film transistors of the two pixel driving circuits through the multiplexing via MH. In this way, the number of vias in the adjacent circuit areas PA is reduced, the lateral compression of the adjacent circuit areas is realized, and the PPI of the display panel is improved.

[0127] In the example of this embodiment, referring to FIG. 1, the display panel includes a first circuit area group PAS1 arranged in an array, and the first circuit area group PAS1 includes two adjacent circuit areas PA along a first direction; the pixel driving circuit includes a first light-emitting transistor T5 for electrical connection with a power voltage terminal; the transistor layer TL is provided with a first polycrystalline silicon conductive structure PLA (see FIG. 4) serving as the first electrode of the two first light-emitting transistors T5 in the first circuit area group PAS1; the multiplexing via MH includes a first multiplexing via MHA in the first circuit area group PAS1, and the first multiplexing via MHA exposes the first polycrystalline silicon conductive structure PLA; in the first circuit area group PAS1, the first source-drain metal layer SD1 includes a power voltage metal structure capable of loading a power voltage VDD; the power voltage metal structure is electrically connected to the first polycrystalline silicon conductive structure PLA through the first multiplexing via MHA. In this way, when the first source-drain metal layer SD1 loads the power voltage VDD, the power voltage VDD is loaded to the first electrode of the first light-emitting transistor T5 in the adjacent circuit area PA through the power voltage metal structure, the power voltage metal structure, and the first multiplexing via MHA, achieving the purpose of simultaneously loading the power voltage VDD to the first electrode of the first light-emitting transistor T5 in the adjacent circuit area, and realizing the lateral compression of the pixel circuit and reducing the size of the pixel driving circuit in the adjacent circuit area PA.

[0128] In the example of the embodiment, referring to FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the display panel includes a first circuit region group PAS1 arranged in an array, the first circuit region group PAS1 includes two adjacent circuit regions PA along a first direction; the pixel driving circuit further includes a second reset transistor T8, a second electrode of the second reset transistor T8 is electrically connected with a second electrode of the data writing transistor T4; a first electrode of the second reset transistor T8 is electrically connected with a third initialization voltage Vinit3 terminal; the transistor layer TL is provided with a second polysilicon conductive structure PLB serving as the first electrode of the two second reset transistors T8 in the first circuit region group PAS1; the multiplexing via MH includes a second multiplexing via MHB in the first circuit region group PAS1, the second multiplexing via MHB exposes the second polysilicon conductive structure PLB; in the first circuit region group PAS1, the first source-drain metal layer SD1 includes a third initialization metal structure capable of loading the third initialization voltage Vinit3; the third initialization metal structure is electrically connected with the second polysilicon conductive structure PLB through the second multiplexing via MHB. In this way, when the first source-drain metal layer SD1 loads the third initialization voltage Vinit3, the third initialization voltage Vinit3 passes through the third initialization metal structure, and the third initialization metal structure is electrically connected with the second polysilicon conductive structure PLB in the adjacent circuit region PA through the second multiplexing via MHB, thereby achieving the purpose of simultaneously loading the third initialization voltage Vinit3 to the first electrode of the second reset transistor T8 in the adjacent circuit region PA, so that the pixel circuit is laterally compressed, and the size of the pixel driving circuit in the adjacent circuit region PA is reduced.

[0129] In the example of the embodiment, the display panel includes an array of second circuit region groups PAS2, each of the second circuit region groups PAS2 including two circuit regions PA adjacent along a first direction; the pixel driving circuit includes a driving transistor T3 and a first reset transistor T1 for electrical connection with a first initialization voltage Vinit1 terminal; the driving transistor T3 has a first electrode electrically connected with a second electrode of a data writing transistor T4, and a second electrode electrically connected with a second electrode of the first reset transistor T1; the transistor layer TL is provided with a third polycrystalline silicon conductive structure PLC as the first electrode of the two first reset transistors T1 in the second circuit region group PAS2 (see FIG. 4); the multiplexing via hole includes a third multiplexing via hole MHC in the second circuit region group PAS2, the third multiplexing via hole MHC exposing the third polycrystalline silicon conductive structure PLC; in the second circuit region group PAS2, the first source-drain metal layer SD1 includes a first initialization metal structure capable of loading the first initialization voltage Vinit1; the first initialization metal structure is electrically connected with the third polycrystalline silicon conductive structure PLC through the third multiplexing via hole MHC. In this way, when the first source-drain metal layer SD1 loads the first initialization voltage Vinit1, the first initialization voltage Vinit1 passes through the first initialization metal structure, and the first initialization metal structure is electrically connected with the third polycrystalline silicon conductive structure PLC of the adjacent circuit region PA through the third multiplexing via hole MHC, achieving the purpose of loading the first initialization voltage Vinit1 to the first electrode of the first reset transistor T1 of the adjacent circuit region PA at the same time, so that the pixel circuit is laterally compressed, and the size of the pixel driving circuit of the adjacent circuit region PA is reduced.

[0130] In some embodiments of the present disclosure, the driving layer DRL includes a low-temperature polycrystalline silicon semiconductor layer LSCL, a metal oxide semiconductor layer OSCL, and a first source-drain metal layer SD1 arranged in sequence; the pixel driving circuit further includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a second light-emitting transistor T6; the first electrode of the first reset transistor T1 is electrically connected with a first initialization voltage Vinit1 terminal, the second electrode of the first reset transistor T1, the first electrode of the threshold compensation transistor T2, the second electrode of the driving transistor T3, and the first electrode of the second light-emitting transistor T6 are electrically connected, and the second electrode of the second light-emitting transistor T6 is electrically connected with a pixel electrode PE; the second electrode of the threshold compensation transistor T2 is electrically connected with the gate electrode of the driving transistor T3; the channel region T1A of the first reset transistor, the channel region T3A of the driving transistor, and the channel region T6A of the second light-emitting transistor are located in the low-temperature polycrystalline silicon semiconductor layer LSCL; the channel region T2A of the threshold compensation transistor is arranged in the metal oxide semiconductor layer OSCL; the channel region T1A of the first reset transistor, the channel region T2A of the threshold compensation transistor, and the channel region T6A of the second light-emitting transistor are arranged in a straight line along a second direction.

[0131] In some embodiments of the present disclosure, the transistor layer TL includes a low-temperature polysilicon semiconductor layer LSCL and a metal oxide semiconductor layer OSCL arranged in a stack; the pixel driving circuit further includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a second light-emitting transistor T6; a first electrode of the first reset transistor T1 is electrically connected to a first initialization voltage Vinit1 terminal, a second electrode of the first reset transistor T1, a first electrode of the threshold compensation transistor T2, a second electrode of the driving transistor T3, and a first electrode of the second light-emitting transistor T6 are electrically connected, and a second electrode of the second light-emitting transistor T6 is electrically connected to a pixel electrode; a second electrode of the threshold compensation transistor T2 is electrically connected to a gate electrode of the driving transistor T3; a channel region of the first reset transistor T1, a channel region of the driving transistor T3, and a channel region of the second light-emitting transistor T6 are located in the low-temperature polysilicon semiconductor layer LSCL; a channel region of the threshold compensation transistor T2 is located in the metal oxide semiconductor layer OSCL; and along a first direction, the channel region of the first reset transistor T1 and the channel region of the threshold compensation transistor T2 are arranged alternately.

[0132] In some embodiments of the present disclosure, referring to FIG. 28, in the circuit area PA, the metal oxide semiconductor layer OSCL includes a first metal oxide structure OLA arranged along a first direction and a second metal oxide structure OLB arranged along a second direction; one end of the first metal oxide structure OLA close to the data writing transistor T4 is connected to one end of the second metal oxide structure OLB close to the driving transistor T3; and the channel region of the threshold compensation transistor T2 is located in the second metal oxide structure OLB.

[0133] In some embodiments of the present disclosure, referring to FIG. 17, the first source-drain metal layer SD1 includes a first metal structure MS1 and a second metal structure MS2; the second metal structure MS2 is electrically connected to the second electrode of the first reset transistor T1, the second electrode of the driving transistor T3, and the first electrode of the threshold compensation transistor T2 through a via; the first metal structure MS1 is electrically connected to the second electrode of the threshold compensation transistor T2 and the gate electrode of the driving transistor T3 through a via; and a size of the second metal structure MS2 along the second direction is smaller than a size of the first metal structure MS1 along the second direction.

[0134] In some embodiments of the present disclosure, referring to FIGS. 3, 17 and 18, the driving layer DRL comprises a low-temperature polysilicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal-oxide semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1 and a second source-drain metal layer SD2 which are sequentially stacked; the first gate layer GT1 is provided with a gate of a data writing transistor T4, and the display panel is provided with a second scan signal trace GPL which is electrically connected with the gate of the data writing transistor T4; in the circuit area PA, the second scan signal trace GPL comprises a first sub-scan trace GPL1 located in the first source-drain metal layer SD1 and a second sub-scan trace GPL2 located in the second source-drain metal layer SD2; the first sub-scan trace GPL1 is electrically connected with the gate of the data writing transistor T4 through a via, and the second sub-scan trace GPL2 is electrically connected with the first sub-scan trace GPL1 through a via.

[0135] In some embodiments of the present disclosure, referring to FIG. 15, in the circuit area PA, the metal-oxide semiconductor layer OSCL comprises a second metal-oxide structure OLB which is arranged along the second direction; one end of the second metal-oxide structure OLB which is away from the channel region of the driving transistor T3 is electrically connected with the gate of the driving transistor T3 through a first metal structure MS1 located in the first source-drain metal layer SD1; in the circuit area PA, the first metal structure MS1 is arranged in overlap with the second sub-scan trace GPL2.

[0136] In some embodiments of the present disclosure, the driving layer DRL comprises a low-temperature polysilicon semiconductor layer LSCL, a first gate layer GT1, a second gate layer GT2, a metal-oxide semiconductor layer OSCL, a third gate layer GT3 and a first source-drain metal layer SD1 which are sequentially stacked; the first gate layer GT1 is provided with a gate of a data writing transistor T4, and the display panel is provided with a first sub-scan trace GPL1 which is electrically connected with the gate of the data writing transistor T4; the first sub-scan trace GPL1 is located in the first source-drain metal layer SD1 and is electrically connected with the gate of the data writing transistor T4 through a via.

[0137] In some embodiments of the present disclosure, referring to FIG. 22, in the circuit region PA, the metal oxide semiconductor layer OSCL includes a first metal oxide structure OLA, a second metal oxide structure OLB, and a third metal oxide structure OLC connected in sequence, the first metal oxide structure OLA and the third metal oxide structure OLC are arranged in parallel along the second direction; the second metal oxide structure OLB is arranged along the first direction, and the first metal oxide structure OLA is electrically connected to the one end of the driving transistor T3 away from the one end of the third metal oxide structure OLC; the one end of the third metal oxide structure OLC close to the driving transistor T3 is electrically connected to the gate of the driving transistor T3 through the first metal structure in the first source-drain metal layer SD1.

[0138] In some embodiments of the present disclosure, referring to FIG. 19, the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD, the fourth polysilicon conductive structure PLD serving as the second pole of the first reset transistor T1; the one end of the fourth polysilicon conductive structure PLD close to the channel region of the driving transistor T3 is electrically connected to the second pole of the driving transistor T3 through the second metal structure in the first source-drain metal layer SD1.

[0139] In some embodiments of the present disclosure, referring to FIG. 19, the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD and a fifth polysilicon conductive structure PLE, the fourth polysilicon conductive structure PLD and the fifth polysilicon conductive structure PLE are electrically connected to each other at the one end close to the channel region of the driving transistor T3, and the fifth polysilicon conductive structure PLE is electrically connected to the second pole of the driving transistor T3.

[0140] In an embodiment of the present disclosure, the driving layer DRL has a third initialization voltage wire VL3 for loading a third initialization voltage Vinit3 and an enable signal line EML for loading an enable signal EM; the third initialization voltage wire VL3 is located in the third gate layer GT3 and extends along the first direction, and the enable signal line EML is located in the first gate layer GT1 and extends along the first direction; the enable signal line EML is arranged overlapping the third initialization voltage wire VL3. In this way, the size of the pixel driving circuit in the second direction can be further compressed.

[0141] As follows, the film layer structure of the first exemplary driving circuit is further introduced.

[0142] FIG. 4 is a schematic diagram of a low-temperature polysilicon semiconductor layer LSCL in an example. Referring to FIGS. 2, 3, and 4, the low-temperature polysilicon semiconductor layer LSCL is provided with the first poles, the second poles, and the channel regions of the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the electrode reset transistor T7, and the second reset transistor T8. Among them, the channel region T4A of the data writing transistor and the channel region T5A of the first light-emitting transistor are arranged along the second direction H2, and the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor are arranged along the first direction H1. Along the first direction H1, the channel region T3A of the driving transistor is located between the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor; along the second direction H2, the channel region T7A of the electrode reset transistor and the channel region T3A of the driving transistor are located on both sides of the channel region T5A of the first light-emitting transistor. Among them, the second pole of the data writing transistor T4, the second pole of the first light-emitting transistor T5, and the first pole of the driving transistor T3 are connected, the second pole of the driving transistor T3 and the first pole of the second light-emitting transistor T6 are electrically connected, and the second pole of the electrode reset transistor T7 and the second pole of the second light-emitting transistor T6 are electrically connected. Among them, in the adjacent two rows of driving circuits, the channel region T7A of the electrode reset transistor of the upper row of driving circuits is arranged adjacent to the channel region T4A of the data writing transistor of the lower row of driving circuits. The second pole of the second reset transistor T8 is electrically connected to the second pole of the first light-emitting transistor T5.

[0143] Referring to FIG. 4, the low-temperature polysilicon semiconductor layer LSCL can be provided with a first lower via region HA1 to a tenth lower via region HA10. The first lower via region HA1 is located at the first pole of the first reset transistor T1, the second lower via region HA2 is located at the second pole of the first reset transistor T1, the third lower via region HA3 is located at the first pole of the data writing transistor T4, the fourth lower via region HA4 is located at the second pole of the data writing transistor T4, the fifth lower via region HA5 is located at the first pole of the second light-emitting transistor T6, the sixth lower via region HA6 is located at the second pole of the second light-emitting transistor T6, the seventh lower via region HA7 is located at the second pole of the electrode reset transistor T7, the eighth lower via region HA8 is located at the second pole of the second reset transistor T8, the ninth lower via region HA9 is located at the first pole of the second reset transistor T8, and the tenth lower via region HA10 is located at the second pole of the first light-emitting transistor T5.

[0144] The low-temperature polysilicon semiconductor layer LSCL can further include a first polysilicon conductive structure PLA, a second polysilicon conductive structure PLB, and a third polysilicon conductive structure PLC.

[0145] Figure 5 is a schematic diagram of the first gate layer GT1 in an example. Referring to Figure 5, the first gate layer GT1 is formed with a first capacitance reset control signal line RL1, a second capacitance reset control signal line RL2, a second scan signal trace GPL, an enable signal line EML, and a first electrode CP1 of a storage capacitor Cst, which extend along a first direction. The first capacitance reset control signal line RL1 extends along the first direction H1 and is used to load a first capacitance reset control signal ResetP to a first reset transistor T1. The second capacitance reset control signal line RL2 extends along the first direction H1 and is used to load a second capacitance reset control signal ResetH to a second reset transistor T8. The enable signal line EML extends along the first direction H1 and overlaps the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor in sequence to multiplex as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to load an enable signal EM. The second scan signal trace GPL extends along the first direction H1 and can overlap the channel region T4A of the data write transistor, and the overlapping part is multiplexed as the gate of the data write transistor T4. The first electrode CP1 of the storage capacitor Cst overlaps the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3. The first electrode CP1 located in the first gate layer GT1 has the eleventh lower via hole region HA11.

[0146] Figure 6 is a schematic diagram of the second gate layer GT2 in an example. Referring to Figure 6, the second gate layer GT2 is provided with a second electrode CP2 of a storage capacitor Cst and a first scan signal second trace GNLB. The second electrode CP2 of the storage capacitor Cst overlaps the first electrode CP1 of the storage capacitor Cst and is provided with a clearance hole to expose part of the first electrode CP1 of the storage capacitor Cst. The first scan signal second trace GNLB extends along the first direction H1. The second electrode CP2 located in the second gate layer GT2 can have the twentieth lower via hole region HA20.

[0147] Fig. 7 is a schematic diagram of the metal-oxide semiconductor layer OSCL in an example. Referring to Fig. 7, the metal-oxide semiconductor layer OSCL is provided with the second electrode, the first electrode and the channel region of the threshold compensation transistor T2, wherein, along the second direction H2, the channel region T1A of the first reset transistor is located on one side of the channel region T2A of the threshold compensation transistor away from the channel region T3A of the driving transistor, and the channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting transistor are located on both sides of the channel region T3A of the driving transistor. Along the first direction H1, the channel region T4A of the data write transistor and the channel region T1A of the first reset transistor of the next row of driving circuits are located on both sides of the channel region T7A of the electrode reset transistor of the previous row of driving circuits. The second electrode of the first reset transistor T1 and the first electrode of the threshold compensation transistor T2 are connected to each other. And along the first direction, the channel region T1A of the first reset transistor and the channel region T2A of the threshold compensation transistor are staggered. The metal-oxide semiconductor layer OSCL has a twelfth lower via region HA12 and a thirteenth lower via region.

[0148] It should be noted that the metal-oxide semiconductor layer OSCL in this example includes a first metal-oxide structure OLA arranged along the first direction and a second metal-oxide structure OLB arranged along the second direction; one end of the first metal-oxide structure OLA close to the data write transistor T4 is connected to one end of the second metal-oxide structure OLB close to the driving transistor T3; the channel region T2A of the threshold compensation transistor T2 is located in the second metal-oxide structure OLB.

[0149] Fig. 8 is a schematic diagram of the third gate layer GT3 in an example. Referring to Fig. 8, the third gate layer GT3 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, a third initialization voltage trace VTL3 and a first scan signal first trace GNLA; wherein the first initialization voltage trace VTL1 extends along the first direction H1, and the first initialization voltage trace VTL1 can be used to load Vinit1; the second initialization voltage trace VTL2 extends along the first direction H1, and the second initialization voltage trace VTL2 can be used to load the second initialization voltage Vinit2; the third initialization voltage trace VTL3 extends along the first direction H1, and the third initialization voltage trace VTL3 can be used to load the third initialization voltage Vinit3; the first scan signal first trace GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping part is multiplexed as the second gate of the threshold compensation transistor T2; the first scan signal first trace GNLA overlaps with the first scan signal second trace GNLB, and the overlapping part is multiplexed as the upper and lower gates of the threshold compensation transistor T2.

[0150] The third gate layer GT3 can also have a fourteenth via hole area HA14 located at the first initialization voltage trace VTL1, a fifteenth via hole area HA15 located at the third initialization voltage trace VTL3, a sixteenth via hole area HA16, a seventeenth via hole area HA17, and an eighteenth via hole area HA18 located at the second initialization voltage trace VTL2.

[0151] FIG. 9 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG. 9, the first source-drain metal layer SD1 is also provided with a first bridge MA1 to a tenth bridge MA10.

[0152] The first bridge MA1 has a first via hole area HB1 and a fourteenth via hole area HB14, wherein the first via hole area HB1 overlaps the first via hole area HA1 and is connected by a via hole, and the fourteenth via hole area HB14 overlaps the fourteenth via hole area HA14 and is connected by a via hole. In this way, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 through the first bridge MA1.

[0153] The second bridge MA2 has a fifteenth via hole area HB15 and a twenty-seventh via hole area HA27, wherein the fifteenth via hole area HB15 overlaps the fifteenth via hole area HA15 and is connected by a via hole, and the twenty-seventh via hole area HA27 overlaps the twenty-seventh via hole area HB27 and is connected by a via hole. In this way, the signal is loaded onto the third initialization voltage trace VTL3 through the second bridge MA2.

[0154] The third bridge MA3 has an eleventh via hole area HB11 and a twelfth via hole area HB12, wherein the eleventh via hole area HB11 overlaps the eleventh via hole area HA11 and is connected by a via hole, and the twelfth via hole area HB12 overlaps the twelfth via hole area HA12 and is connected by a via hole. In this way, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the third bridge MA3.

[0155] The fourth bridge MA4 has a third via hole area HB3 and a twenty-sixth via hole area HA26, wherein the third via hole area HB3 overlaps the third via hole area HA3 and is connected by a via hole, and the twenty-sixth via hole area HA26 overlaps the twenty-sixth via hole area HB26 and is connected by a via hole. In this way, the first electrode of the data write transistor T4 is electrically connected to the second bridge MA2.

[0156] The fifth bridge MA5 has a twenty-first lower via region HA21 and a twentieth upper via region HB20 and a tenth upper via region HB10, wherein the twenty-first lower via region HA21 and the twenty-first upper via region HB21 overlap and are connected by a via, the twentieth upper via region HB20 and the twentieth lower via region HA20 overlap and are connected by a via, and the tenth upper via region HB10 and the tenth lower via region HA10 are connected and connected by a via, so that the power supply voltage VDD is connected to the first electrode of the first light emitting transistor T5 through the fifth bridge MA5.

[0157] The sixth bridge MA6 has a twenty-third lower via region HA23 and a sixth upper via region HB6, wherein the twenty-third lower via region HA23 and the twenty-third upper via region HB23 overlap and are connected by a via, and the sixth upper via region HB6 and the sixth lower via region HA6 overlap and are connected by a via. In this way, the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the first bridge MA6.

[0158] The seventh bridge MA7 has a seventh upper via region HB7 and an eighteenth upper via region HB18, wherein the seventh upper via region HB7 and the seventh lower via region HA7 overlap and are connected by a via, and the eighteenth upper via region HB18 and the eighteenth lower via region HA18 overlap and are connected by a via, so that the second initialization voltage trace VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge MA7.

[0159] The eighth bridge MA8 has a fourth upper via region HB4 and a ninth upper via region HB9, wherein the fourth upper via region HB4 and the fourth lower via region HA4 overlap and are connected by a via, and the ninth upper via region HB9 and the ninth lower via region HA9 overlap and are connected by a via, so that the second electrode of the data write transistor T4 and the second electrode of the second reset transistor T8 are electrically connected through the first bridge MA8.

[0160] The ninth bridge MA9 has a second upper via region HB2, a fifth upper via region HB5 and a thirteenth upper via region HB13, wherein the second upper via region HB2 and the second lower via region HA2 overlap and are connected by a via, the fifth upper via region HB5 and the fifth lower via region HA5 overlap and are connected by a via, and the thirteenth upper via region HB13 and the thirteenth lower via region HA113 overlap and are connected by a via, so that the connection between the second electrode of the first reset transistor T1, the first electrode of the second light emitting transistor T6 and the first electrode of the threshold compensation transistor T2 is realized through the ninth bridge MA9.

[0161] The tenth bridge MA10 has a sixteenth upper via hole region HB16 and an eighth upper via hole region HB8, wherein the sixteenth upper via hole region HB16 and the sixteenth lower via hole region HA16 overlap and are connected by a via hole, and the eighth upper via hole region HB8 and the eighth lower via hole region HA8 overlap and are connected by a via hole. In this way, the third initialization voltage wire VLT3 is electrically connected to the first electrode of the second reset transistor T8 through the tenth bridge MA10.

[0162] Referring to FIG. 10, the second source-drain metal layer SD2 is further provided with a first conductive part MB1 to a fourth conductive part MB4;

[0163] The first conductive part MB1 has a twenty-fifth lower via hole region HA25 and a twenty-sixth upper via hole region HB26, wherein the twenty-fifth lower via hole region HA25 and the twenty-fifth upper via hole region HB25 overlap and are connected by a via hole, and the twenty-sixth upper via hole region HB26 and the twenty-sixth lower via hole region HA26 overlap and are connected by a via hole. In this way, the signal is loaded onto the fourth bridge MA4 through the first conductive part MB1.

[0164] The second conductive part MB2 has a twenty-seventh upper via hole region HB27 and a twenty-second lower via hole region HA22, wherein the twenty-seventh lower via hole region HA27 and the twenty-seventh upper via hole region HB27 overlap and are connected by a via hole, and the twenty-second lower via hole region HA22 and the twenty-second upper via hole region HB22 overlap and are connected by a via hole. In this way, the standby signal on the third source-drain metal layer SD3 is loaded onto the second bridge MA2 through the second conductive part MB2.

[0165] The third conductive part MB3 has a nineteenth lower via hole region HA19 and a twenty-first upper via hole region HB21, wherein the twenty-first upper via hole region HB21 and the twentieth upper via hole region HA21 overlap and are connected by a via hole, and the nineteenth lower via hole region HA19 and the nineteenth upper via hole region HB19 overlap and are connected by a via hole. In this way, the power supply voltage VDD is loaded onto the fifth bridge MA5 through the third conductive part MB3.

[0166] The fourth conductive part MB4 has a twenty-fourth lower via hole region HA24 and a twenty-third upper via hole region HB23, wherein the twenty-fourth lower via hole region HA24 and the twenty-fourth upper via hole region HB24 overlap and are connected by a via hole, and the twenty-third upper via hole region HB23 and the twenty-third lower via hole region HA23 overlap and are connected by a via hole. In this way, the signal of the third source-drain metal layer SD3 is loaded onto the sixth bridge MA6 through the fourth conductive part MB4.

[0167] Referring to FIG. 11, the third source-drain metal layer SD3 is further provided with a power supply voltage wire VDDL, a standby signal wire SWL, a data signal wire DL, and a first metal part MC1;

[0168] The nineteenth upper via region HB19 is arranged on the power voltage wire VDDL; the nineteenth upper via region HB19 overlaps with the nineteenth lower via region HA19 and is connected by a via, so that the power voltage VDD is loaded on the third conductive part MB3 by the power voltage wire VDDL.

[0169] The twenty-second upper via region HB22 is arranged on the standby signal wire SWL; the twenty-second upper via region HB22 overlaps with the twenty-second lower via region HA22 and is connected by a via, so that the standby signal is loaded on the second conductive part MB2.

[0170] The twenty-fifth upper via region HB25 is arranged on the data signal wire DL; the twenty-fifth upper via region HB25 overlaps with the twenty-fifth lower via region HA25 and is connected by a via, so that the data signal Data is loaded on the first conductive part MB1 by the data signal wire DL.

[0171] The twenty-fourth upper via region HB24 is arranged on the first metal part MC1; the twenty-fourth upper via region HB24 overlaps with the twenty-fourth lower via HA24 and is connected by a via, so that the first metal part MC1 is electrically connected with the pixel electrode PE.

[0172] The following further introduces the film layer structure of the second exemplary driving circuit.

[0173] Referring to FIG. 2, FIG. 3 and FIG. 12, the low-temperature polysilicon semiconductor layer LSCL is provided with the first poles, the second poles and the channel regions of the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the electrode reset transistor T7 and the second reset transistor T8. Among them, the channel region T4A of the data writing transistor and the channel region T5A of the first light-emitting transistor are arranged along the second direction H2, and the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor are arranged along the first direction H1. Along the first direction H1, the channel region T3A of the driving transistor is located between the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor; along the second direction H2, the channel region T7A of the electrode reset transistor and the channel region T3A of the driving transistor are located on both sides of the channel region T5A of the first light-emitting transistor. Among them, the second pole of the data writing transistor T4, the second pole of the first light-emitting transistor T5 and the first pole of the driving transistor T3 are connected, the second pole of the driving transistor T3 and the first pole of the second light-emitting transistor T6 are electrically connected, and the second pole of the electrode reset transistor T7 and the second pole of the second light-emitting transistor T6 are electrically connected. Among them, in the adjacent two rows of driving circuits, the channel region T7A of the electrode reset transistor of the last row of driving circuits is arranged adjacent to the channel region T4A of the data writing transistor of the next row of driving circuits. The second pole of the second reset transistor T8 is electrically connected with the second pole of the first light-emitting transistor T5.

[0174] The low-temperature polysilicon semiconductor layer LSCL can be provided with a first lower via region HA1 to a tenth lower via region HA10. The first lower via region HA1 is located at the first electrode of the first reset transistor T1. It should be noted that in the embodiment of the present disclosure, the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD and a fifth polysilicon conductive structure PLE. The channel region T1A of the first reset transistor is located at the fourth polysilicon conductive structure PLD. The fourth polysilicon conductive structure PLD is connected to the fifth polysilicon conductive structure PLE at one end close to the channel region T3A of the driving transistor. The fifth polysilicon conductive structure PLE is connected to the second electrode of the driving transistor T3. Since the fourth polysilicon conductive structure PLD and the fifth polysilicon conductive structure PLE are connected to each other, the first reset transistor T1 and the driving transistor T3 do not need to be connected through a metal structure. Therefore, in the embodiment, the low-temperature polysilicon semiconductor layer LSCL does not need to be provided with a second lower via region HA2. The third lower via region HA3 is located at the first electrode of the data write transistor T4. The fourth lower via region HA4 is located at the second electrode of the data write transistor T4. The fifth lower via region HA5 is located at the first electrode of the second light-emitting transistor T6. The sixth lower via region HA6 is located at the second electrode of the second light-emitting transistor T6. The seventh lower via region HA7 is located at the second electrode of the electrode reset transistor T7. The eighth lower via region HA8 is located at the second electrode of the second reset transistor T8. The ninth lower via region HA9 is located at the first electrode of the second reset transistor T8. The tenth lower via region HA10 is located at the second electrode of the second light-emitting transistor T5.

[0175] FIG. 13 is a schematic diagram of the first gate layer GT1 in an example. Referring to FIG. 13, the first gate layer GT1 is formed with the first capacitance reset control signal line RL1, the second capacitance reset control signal line RL2, the second scan signal trace GPL, the enable signal line EML, and the first electrode CP1 of the storage capacitor Cst extending along the first direction; wherein the first capacitance reset control signal line RL1 extends along the first direction H1 and is used to load the first capacitance reset control signal ResetP for the first reset transistor T1; the second capacitance reset control signal line RL2 extends along the first direction H1 and is used to load the second capacitance reset control signal ResetH for the second reset transistor T8; the enable signal line EML extends along the first direction H1 and overlaps the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor in sequence to multiplex as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to load the enable signal EM. The second scan signal trace GPL extends along the first direction H1, and the second scan signal trace GPL can overlap the channel region T4A of the data write transistor, and the overlapping part is multiplexed as the gate of the data write transistor T4; the first electrode CP1 of the storage capacitor Cst overlaps the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3. The first electrode CP1 located in the first gate layer GT1 can be provided with the eleventh lower via hole region HA11. The second scan signal trace GPL has a twenty-eighth lower via hole region, the twenty-eighth lower via hole region HA28 and the twenty-eighth upper via hole region HB28 overlap and are connected through the via. In this way, the data signal Data is transferred to the second scan signal trace GPL located in the first source / drain metal layer SD1 through the second source / drain metal layer SD2, thereby reducing the length of the second scan signal trace GPL, and the compression of the pixel circuit can be realized.

[0176] FIG. 14 is a schematic diagram of the second gate layer GT2 in an example. Referring to FIG. 14, the second gate layer GT2 is provided with the second electrode CP2 of the storage capacitor Cst and the first scan signal second trace GNLB; wherein the second electrode CP2 of the storage capacitor Cst overlaps the first electrode CP1 of the storage capacitor Cst, and the avoidance hole is arranged to expose part of the first electrode CP1 of the storage capacitor Cst; the first scan signal second trace GNLB extends along the first direction H1 and is used to load the first scan signal GN. The second electrode CP2 located in the second gate layer GT2 can be provided with the twentieth lower via hole region HA20.

[0177] Fig. 15 is a schematic view of an example of a metal-oxide semiconductor layer OSCL. Referring to Fig. 15, the metal-oxide semiconductor layer OSCL is provided with a second electrode, a first electrode and a channel region of a threshold compensation transistor T2, wherein along the second direction H2, the channel region T1A of the first reset transistor is located on one side of the channel region T2A of the threshold compensation transistor away from the channel region T3A of the driving transistor, and the channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting transistor are located on both sides of the channel region T3A of the driving transistor. Along the first direction H1, the channel region T4A of the data writing transistor and the channel region T1A of the first reset transistor of the next row of driving circuit are located on both sides of the channel region T7A of the electrode reset transistor of the previous row of driving circuit. The second electrode of the first reset transistor T1 and the second electrode of the threshold compensation transistor T2 are connected to each other. And along the first direction, the channel region T1A of the first reset transistor and the channel region T2A of the threshold compensation transistor are staggered. The metal-oxide semiconductor layer OSCL is further provided with a twelfth lower via region HA12 and a thirteenth lower via region HA13.

[0178] It should be noted that in the embodiments of the present disclosure, the metal-oxide semiconductor layer OSCL includes a second metal-oxide structure OLB arranged along the second direction; one end of the second metal-oxide structure OLB away from the channel region T3A of the driving transistor is electrically connected to the gate of the driving transistor T3 through the first metal structure MS1 located in the first source-drain metal layer SD1.

[0179] FIG. 16 is a schematic diagram of the third gate layer GT3 in an example. Referring to FIG. 16, the third gate layer GT3 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, a third initialization voltage trace VTL3, and a first scan signal first trace GNLA; wherein the first initialization voltage trace VTL1 extends in a first direction H1, the first initialization voltage trace VTL1 can be used to load Vinit1, the second initialization voltage trace VTL2 extends in the first direction H1, the second initialization voltage trace VTL2 can be used to load a second initialization voltage Vinit2; the third initialization voltage trace VTL3 extends in the first direction H1, the third initialization voltage trace VTL3 can be used to load a third initialization voltage Vinit3; the first scan signal first trace GNLA overlaps with a channel region T2A of the threshold compensation transistor, the overlapping part of the two is multiplexed as a second gate of the threshold compensation transistor T2; the first scan signal first trace GNLA overlaps with a channel region T8A of the second reset transistor, the overlapping part of the two is multiplexed as a second gate of the threshold compensation transistor T2. The third gate layer GT3 further has a fourteenth lower via region HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via region HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via region HA16, a seventeenth lower via region HA17, and an eighteenth lower via region HA18 located at the second initialization voltage trace VTL2.

[0180] FIG. 17 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG. 17, the first source-drain metal layer SD1 is further provided with a first bridge MA1 to a tenth bridge MA10 and a fifteenth bridge MA15;

[0181] The first bridge MA1 has a first upper via region HB1 and a fourteenth upper via region HB14, wherein the first upper via region HB1 overlaps with the first lower via region HA1 and is connected through a via, and the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14. In this way, the first initialization voltage line VTL1 is electrically connected to the first electrode of the first reset transistor T1 through the first bridge MA1.

[0182] The second bridge MA2 has a fifteenth upper via region HB15, wherein the fifteenth upper via region HB15 overlaps with the fifteenth lower via region HA15 and is connected through a via, so as to load the signal of the standby signal trace SWL to the second initialization voltage trace VTL2.

[0183] The third bridge MA3 has an eleventh upper via region HB11 and a twelfth upper via region HB12, wherein the eleventh upper via region HB11 overlaps with the eleventh lower via region HA11 and is connected by a via, and the twelfth upper via region HB12 overlaps with the twelfth lower via region HA12 and is connected by a via, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the transistor T3 through the third bridge MA3.

[0184] The fourth bridge MA4 has a third upper via region HB3 and a twenty-sixth lower via region HA26, wherein the third upper via region HB3 overlaps with the third lower via region HA3 and is connected by a via, and the twenty-sixth lower via region HA26 is connected with the twenty-sixth upper via region HB26 and is connected by a via, so that the data signal Data is electrically connected to the first electrode of the data writing transistor T4 through the third upper via region HB3.

[0185] The fifth bridge MA5 has a twentieth lower via region HA21 and a twentieth upper via region HB20 and a tenth upper via region HB10, wherein the twentieth lower via region HA21 overlaps with the twenty-first upper via region HB21 and is connected by a via, and the twentieth upper via region HB20 overlaps with the twentieth lower via region HA20 and is connected by a via, and the tenth upper via region HB10 is connected with the tenth lower via region HA10 and is connected by a via, so that the power supply voltage VDD is connected to the first electrode of the first light emitting transistor T5 through MA5.

[0186] The sixth bridge MA6 has a sixth upper via region HB6, wherein the sixth upper via region HB6 overlaps with the sixth lower via region HA6 and is connected by a via. So that the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the sixth bridge MA6.

[0187] The seventh bridge MA7 has a seventh upper via region HB7 and an eighteenth upper via region HB18, wherein the seventh upper via region HB7 overlaps with the seventh lower via region HA7 and is connected by a via, and the eighteenth upper via region HB18 overlaps with the eighteenth lower via region HA18 and is connected by a via, so that the second initialization voltage trace VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge MA7.

[0188] The eighth bridge MA8 has a fourth upper via region HB4 and a ninth upper via region HB9, wherein the fourth upper via region HB4 overlaps with the fourth lower via region HA4 and is connected by a via, and the ninth upper via region HB9 overlaps with the ninth lower via region HA9 and is connected by a via, so that the second electrode of the data writing transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge MA8.

[0189] The ninth bridge MA9 has a second upper via region HB2, a fifth upper via region HB5 and a thirteenth upper via region HB13, wherein the second upper via region HB2 and the second lower via region HA2 overlap and are connected by a via, the fifth upper via region HB5 and the fifth lower via region HA5 overlap and are connected by a via, and the thirteenth upper via region HB13 and the thirteenth lower via region HA113 overlap and are connected by a via, so that the second electrode of the first reset transistor T1, the first electrode of the second light emitting transistor T6 and the first electrode of the threshold compensation transistor T2 are connected by the ninth bridge MA9.

[0190] The tenth bridge MA10 has a sixteenth upper via region HB16 and an eighth upper via region HB8, wherein the sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected by a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected by a via. The third initialization voltage wire VLT3 and the first electrode of the second reset transistor T8 are electrically connected by the tenth bridge MA10.

[0191] The fifteenth bridge MA15 has a twenty-eighth upper via region HB28 and a twenty-ninth lower via region HA29, wherein the twenty-eighth upper via region HB28 and the twenty-eighth lower via region HA28 overlap and are connected by a via, and the twenty-ninth lower via region HA29 and the twenty-ninth upper via region HB29 overlap and are connected by a via. The second scan signal GP is loaded to the gate of the data write transistor T4 by the fifteenth bridge MA15.

[0192] FIG. 18 is a schematic view of the second source-drain metal layer SD2 in an example. Referring to FIG. 18, the second source-drain metal layer SD2 is further provided with a first conductive part MB1 to a fourth conductive part MB4;

[0193] The first conductive part MB1 has a twenty-fifth lower via region HA25 and a twenty-sixth upper via region HB26, wherein the twenty-fifth lower via region HA25 and the twenty-fifth upper via region HB25 overlap and are connected by a via, and the twenty-sixth upper via region HB26 and the twenty-sixth lower via region HA26 overlap and are connected by a via, so that the data signal Data is loaded to the fourth bridge MA4 by the first conductive part MB1.

[0194] The second conductive part MB2 has a twenty-seventh lower via region HA27 and a twenty-second lower via region HA22, wherein the twenty-seventh lower via region HA27 and the twenty-seventh upper via region HB27 overlap and are connected by a via, and the twenty-second lower via region HA22 and the twenty-second upper via region HB22 overlap and are connected by a via, so that the standby signal on the third source-drain metal layer SD3 is loaded to the second bridge MA2.

[0195] The third conductive part MB3 has a twenty-first upper via region HB21, wherein the twenty-first upper via region HB21 and the twentieth lower via region HA21 overlap and are connected by a via, so that the power supply voltage VDD is loaded onto the fifth bridge part MA5.

[0196] The fourth conductive part MB4 has a twenty-fourth lower via region HA24 and a twenty-third upper via region HB24; wherein the twenty-fourth lower via region HA24 and the twenty-fourth upper via region HB24 overlap and are connected by a via, and wherein the twenty-third lower via region HA23 and the twenty-third upper via region HB23 overlap and are connected by a via, so that the fourth conductive part MB4 loads a signal onto the sixth bridge part MA6.

[0197] The film layer structure of the third exemplary drive circuit is further described as follows.

[0198] Referring to FIGS. 2, 3 and 19, the low-temperature polysilicon semiconductor layer LSCL can be provided with first to tenth lower via regions HA1 to HA10. The first lower via region HA1 is located at the first electrode of the first reset transistor T1. It should be noted that in the present embodiment, the low-temperature polysilicon semiconductor layer LSCL includes a fourth polysilicon conductive structure PLD and a fifth polysilicon conductive structure PLE, and the channel region T1A of the first reset transistor is located at the fourth polysilicon conductive structure PLD. The fourth polysilicon conductive structure PLD is connected to the fifth polysilicon conductive structure PLE at one end close to the channel region T3A of the drive transistor, and the fifth polysilicon conductive structure PLE is connected to the second electrode of the drive transistor T3. Since the fourth polysilicon conductive structure PLD and the fifth polysilicon conductive structure PLE are connected to each other, the first reset transistor T1 and the drive transistor T3 do not need to be connected by a metal structure, and therefore the low-temperature polysilicon semiconductor layer LSCL does not need to be provided with a second lower via region HA2 in the present embodiment. The third lower via region HA3 is located at the first electrode of the data write transistor T4, the fourth lower via region HA4 is located at the second electrode of the data write transistor T4, the fifth lower via region HA5 is located at the first electrode of the second light-emitting transistor T6, the sixth lower via region HA6 is located at the second electrode of the second light-emitting transistor T6, the seventh lower via region HA7 is located at the second electrode of the electrode reset transistor T7, the eighth lower via region HA8 is located at the second electrode of the second reset transistor T8, the ninth lower via region HA9 is located at the first electrode of the second reset transistor T8, and the tenth lower via region HA10 is located at the second electrode of the second light-emitting transistor T5.

[0199] Figure 20 is a schematic diagram of the first gate layer GT1 in an example. Referring to Figure 20, the first gate layer GT1 is formed with a first capacitance reset control signal line RL1, a second capacitance reset control signal line RL2, a second scan signal trace GPL, an enable signal line EML and a first electrode CP1 of a storage capacitor Cst extending along a first direction; wherein the first capacitance reset control signal line RL1 extends along the first direction H1 and is used to load a first capacitance reset control signal ResetP for a first reset transistor T1; the second capacitance reset control signal line RL2 extends along the first direction H1 and is used to load a second capacitance reset control signal ResetH for a second reset transistor T8; the enable signal line EML extends along the first direction H1 and sequentially overlaps a channel region T5A of the first light-emitting transistor and a channel region T6A of the second light-emitting transistor to multiplex as a gate of the first light-emitting transistor T5 and a gate of the second light-emitting transistor T6. The enable signal line EML can be used to load an enable signal EM. The first electrode CP1 of the storage capacitor Cst overlaps a channel region T3A of the driving transistor to multiplex as a gate of the driving transistor T3; the second scan signal trace GPL extends along the first direction H1 and can overlap a channel region T4A of the data write transistor, and the overlapping part multiplexes as a gate of the data write transistor T4; the first electrode CP1 of the storage capacitor Cst overlaps the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3. The first electrode CP1 located in the first gate layer GT1 can be provided with an eleventh lower via hole region HA11. The second scan signal trace GPL has a twenty-eighth lower via hole region, the twenty-eighth lower via hole region HA28 and a twenty-eighth upper via hole region HB28 overlap and are connected through a via. In this way, the data signal Data is transferred to the first source / drain metal layer SD1 via the second source / drain metal layer SD2 and loaded onto the second scan signal trace GPL, thereby reducing the length of the second scan signal trace GPL, and the compression of the pixel circuit can be realized.

[0200] Figure 21 is a schematic diagram of the second gate layer GT2 in an example. Referring to Figure 21, the second gate layer GT2 is provided with a second electrode CP2 of a storage capacitor Cst and a first scan signal second trace GNLB; wherein the second electrode CP2 of the storage capacitor Cst overlaps the first electrode CP1 of the storage capacitor Cst and is provided with a clearance hole to expose part of the first electrode CP1 of the storage capacitor Cst; the first scan signal second trace GNLB extends along the first direction H1 and is used to load a second scan signal. The second electrode CP2 located in the second gate layer GT2 can be provided with a twentieth lower via hole region HA20.

[0201] Fig. 22 is a schematic view of a metal-oxide semiconductor layer OSCL in an example. Referring to Fig. 22, the metal-oxide semiconductor layer OSCL is provided with a second electrode, a first electrode and a channel region of a threshold compensation transistor T2, wherein along the second direction H2, the channel region T1A of the first reset transistor is located on one side of the channel region T2A of the threshold compensation transistor away from the channel region T3A of the driving transistor, and the channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting transistor are located on both sides of the channel region T3A of the driving transistor. Along the first direction H1, the channel region T4A of the data writing transistor and the channel region T1A of the first reset transistor of the next row of driving circuit are located on both sides of the channel region T7A of the electrode reset transistor of the previous row of driving circuit. The second electrode of the first reset transistor T1 and the second electrode of the threshold compensation transistor T2 are connected to each other. And along the first direction, the channel region T1A of the first reset transistor and the channel region T2A of the threshold compensation transistor are staggered. The metal-oxide semiconductor layer OSCL is further provided with a twelfth lower via region HA12 and a thirteenth lower via region HA13.

[0202] It should be noted that in the embodiments of the present disclosure, the metal-oxide semiconductor layer OSCL includes a first metal-oxide structure OLA, a second metal-oxide structure OLB and a third metal-oxide structure OLC connected in sequence, the first metal-oxide structure OLA and the third metal-oxide structure OLC are arranged side by side along the second direction; the second metal-oxide structure OLB is arranged along the first direction, and the first metal-oxide structure OLA is electrically connected to the third metal-oxide structure OLC away from the driving transistor T3; the third metal-oxide structure OLC is electrically connected to the gate of the driving transistor T3 through the first metal structure MS1 in the first source-drain metal layer SD1.

[0203] FIG. 23 is a schematic view of the third gate layer GT3 in an example. Referring to FIG. 23, the third gate layer GT3 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, a third initialization voltage trace VTL3, and a first scan signal first trace GNLA; the first initialization voltage trace VTL1 extends in a first direction H1, and the first initialization voltage trace VTL1 can be used to load Vinit1; the second initialization voltage trace VTL2 extends in the first direction H1, and the second initialization voltage trace VTL2 can be used to load a second initialization voltage Vinit2; the third initialization voltage trace VTL3 extends in the first direction H1, and the third initialization voltage trace VTL3 can be used to load a third initialization voltage Vinit3; the first scan signal first trace GNLA overlaps with a channel region T2A of the threshold compensation transistor, and the overlapping part is multiplexed as a second gate of the threshold compensation transistor T2; the first scan signal first trace GNLA overlaps with a first scan signal second trace GNLB; and the overlapping part is multiplexed as the upper and lower gates of the threshold compensation transistor T2.

[0204] The third gate layer GT3 can also be provided with a fourteenth lower via region HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via region HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via region HA16, a seventeenth lower via region HA17, and an eighteenth lower via region HA18 located at the second initialization voltage trace VTL2.

[0205] FIG. 24 is a schematic view of the first source-drain metal layer SD1 in an example. Referring to FIG. 24, the first source-drain metal layer SD1 is further provided with a first bridge MA1 to a tenth bridge MA10 and a fifteenth bridge MA15; the first bridge MA1 has a first upper via region HB1 and a fourteenth upper via region HB14, wherein the first upper via region HB1 overlaps with the first lower via region HA1 and is connected through a via, and the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14. In this way, the first initialization voltage line VTL1 is electrically connected to the first pole of the first reset transistor T1 through the first bridge MA1.

[0206] The second bridge MA2 has a fifteenth upper via region HB15, wherein the fifteenth upper via region HB15 overlaps with the fifteenth lower via region HA15 and is connected through a via. In this way, the signal is loaded onto the third initialization voltage trace VTL3 through the second bridge MA2.

[0207] The third bridge MA3 has an eleventh upper via region HB11 and a twelfth upper via region HB12, wherein the eleventh upper via region HB11 overlaps the eleventh lower via region HA11 and is connected to the eleventh lower via region HA11 by a via connection, and the twelfth upper via region HB12 overlaps the twelfth lower via region HA12 and is connected to the twelfth lower via region HA12 by a via connection, so that the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the transistor T2 through the third bridge MA3.

[0208] The fourth bridge MA4 has a third upper via region HB3 and a twenty-sixth lower via region HA26, wherein the third upper via region HB3 overlaps the third lower via region HA3 and is connected to the third lower via region HA3 by a via connection, and the twenty-sixth lower via region HA26 is connected to the twenty-sixth upper via region HB26 by a via connection, so that the data signal Data is electrically connected to the first electrode of the data writing transistor T4 through the third upper via region HB3.

[0209] The fifth bridge MA5 has a twentieth lower via region HA21 and a twentieth upper via region HB20 and a tenth upper via region HB10, wherein the twentieth lower via region HA21 overlaps the twenty-first upper via region HB21 and is connected to the twenty-first upper via region HB21 by a via connection, the twentieth upper via region HB20 overlaps the twentieth lower via region HA20 and is connected to the twentieth lower via region HA20 by a via connection, the tenth upper via region HB10 is connected to the tenth lower via region HA10 and is connected to the tenth lower via region HA10 by a via connection, so that the power supply voltage VDD is connected to the first electrode of the first light emitting transistor T5 through MA5.

[0210] The sixth bridge MA6 has a sixth upper via region HB6, wherein the sixth upper via region HB6 overlaps the sixth lower via region HA6 and is connected to the sixth lower via region HA6 by a via connection, so that the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the sixth bridge MA6.

[0211] The seventh bridge MA7 has a seventh upper via region HB7 and an eighteenth upper via region HB18, wherein the seventh upper via region HB7 overlaps the seventh lower via region HA7 and is connected to the seventh lower via region HA7 by a via connection, and the eighteenth upper via region HB18 overlaps the eighteenth lower via region HA18 and is connected to the eighteenth lower via region HA18 by a via connection, so that the second initialization voltage trace VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge MA7.

[0212] The eighth bridge MA8 has a fourth upper via region HB4 and a ninth upper via region HB9, wherein the fourth upper via region HB4 overlaps the fourth lower via region HA4 and is connected to the fourth lower via region HA4 by a via connection, and the ninth upper via region HB9 overlaps the ninth lower via region HA9 and is connected to the ninth lower via region HA9 by a via connection, so that the second electrode of the data writing transistor T4 is electrically connected to the second electrode of the second reset transistor T8 through the first bridge MA8.

[0213] The ninth bridge MA9 has a second upper via region HB2, a fifth upper via region HB5 and a thirteenth upper via region HB13, wherein the second upper via region HB2 and the second lower via region HA2 overlap and are connected by a via, the fifth upper via region HB5 and the fifth lower via region HA5 overlap and are connected by a via, and the thirteenth upper via region HB13 and the thirteenth lower via region HA113 overlap and are connected by a via. In this way, the ninth bridge MA9 realizes the connection between the second electrode of the first reset transistor T1, the first electrode of the second light-emitting transistor T6 and the first electrode of the threshold compensation transistor T2.

[0214] The tenth bridge MA10 has a sixteenth upper via region HB16 and an eighth upper via region HB8, wherein the sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected by a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected by a via. In this way, the tenth bridge MA10 realizes the electrical connection between the third initialization voltage wire VLT3 and the first electrode of the second reset transistor T8.

[0215] The fifteenth bridge MA15 has a twenty-eighth upper via region, and the twenty-eighth upper via region and the twenty-eighth lower via region overlap and are connected by a via. In this way, the second metal oxide structure OLB is electrically connected to one end of the channel region of the driving transistor T3 through the fifteenth bridge MA15.

[0216] The film layer structure of the fourth exemplary driving circuit is further described as follows.

[0217] Referring to FIGS. 2, 3 and 25, the low-temperature polysilicon semiconductor layer LSCL can be provided with first lower via region HA1 to tenth lower via region HA10, the first lower via region HA1 is located at the first electrode of the first reset transistor T1, the second lower via region HA2 is located at the second electrode of the first reset transistor T1, the third lower via region HA3 is located at the first electrode of the data writing transistor T4, the fourth lower via region HA4 is located at the second electrode of the data writing transistor T4, the fifth lower via region HA5 is located at the first electrode of the second light-emitting transistor T6, the sixth lower via region HA6 is located at the second electrode of the second light-emitting transistor T6, the seventh lower via region HA7 is located at the second electrode of the electrode reset transistor T7, the eighth lower via region HA8 is located at the second electrode of the second reset transistor T8, the ninth lower via region HA9 is located at the first electrode of the second reset transistor T8, and the tenth lower via region HA10 is located at the second electrode of the second light-emitting transistor T5.

[0218] FIG. 26 is a schematic view of the first gate layer GT1 in an example. Referring to FIG. 26, the first gate layer GT1 is formed with the first capacitance reset control signal line RL1, the second capacitance reset control signal line RL2, the second scan signal trace GPL, the enable signal line EML, and the first electrode CP1 of the storage capacitor Cst extending along the first direction; wherein the first capacitance reset control signal line RL1 extends along the first direction H1 and is used to load the first capacitance reset control signal ResetP for the first reset transistor T1; the second capacitance reset control signal line RL2 extends along the first direction H1 and is used to load the second capacitance reset control signal ResetH for the second reset transistor T8; the enable signal line EML extends along the first direction H1 and sequentially overlaps the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor to multiplex as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6. The enable signal line EML can be used to load the enable signal EM. The first electrode CP1 of the storage capacitor Cst overlaps the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3; the second scan signal trace GPL extends along the first direction H1, and the second scan signal trace GPL can overlap the channel region T4A of the data writing transistor, and the overlapping part multiplexes as the gate of the data writing transistor T4; the first electrode CP1 of the storage capacitor Cst overlaps the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3.

[0219] FIG. 27 is a schematic view of the second gate layer GT2 in an example. Referring to FIG. 27, the second gate layer GT2 is provided with the second electrode CP2 of the storage capacitor Cst and the first scan signal second trace GNLB; wherein the second electrode CP2 of the storage capacitor Cst overlaps the first electrode CP1 of the storage capacitor Cst and is provided with a relief hole to expose part of the first electrode CP1 of the storage capacitor Cst; the first scan signal second trace GNLB extends along the first direction H1 and is used to load the second scan signal. The second electrode CP2 of the second gate layer GT2 can be provided with a second via hole region HA20.

[0220] Fig. 28 is a schematic view of the metal-oxide semiconductor layer OSCL in an example. Referring to Fig. 28, the metal-oxide semiconductor layer OSCL is provided with the second electrode, the first electrode and the channel region of the threshold compensation transistor T2, wherein, along the second direction H2, the channel region T1A of the first reset transistor is located on one side of the channel region T2A of the threshold compensation transistor away from the channel region T3A of the driving transistor, and the channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting transistor are located on both sides of the channel region T3A of the driving transistor. Along the first direction H1, the channel region T4A of the data writing transistor and the channel region T1A of the first reset transistor of the next row of driving circuit are located on both sides of the channel region T7A of the electrode reset transistor of the previous row of driving circuit. The second electrode of the first reset transistor T1 and the second electrode of the threshold compensation transistor T2 are connected to each other. And along the first direction, the channel region T1A of the first reset transistor and the channel region T2A of the threshold compensation transistor are staggered. The metal-oxide semiconductor layer OSCL is further provided with a twelfth lower via region HA12 and a thirteenth lower via region HA13.

[0221] It should be noted that, in the embodiments of the present disclosure, the channel region T1A of the first reset transistor, the channel region T3A of the driving transistor and the channel region T6A of the second light-emitting transistor are located in the low-temperature polysilicon semiconductor layer LSCL; the channel region T2A of the threshold compensation transistor is arranged in the metal-oxide semiconductor layer OSCL; and the channel region T1A of the first reset transistor, the channel region T2A of the threshold compensation transistor and the channel region T6A of the second light-emitting transistor are arranged linearly along the second direction.

[0222] Fig. 29 is a schematic view of the third gate layer GT3 in an example. Referring to Fig. 29, the third gate layer GT3 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2, a third initialization voltage trace VTL3 and a first scan signal first trace GNLA; wherein the first initialization voltage trace VTL1 extends along the first direction H1, and the first initialization voltage trace VTL1 can be used to load Vinit1; the second initialization voltage trace VTL2 extends along the first direction H1, and the second initialization voltage trace VTL2 can be used to load the second initialization voltage Vinit2; the third initialization voltage trace VTL3 extends along the first direction H1, and the third initialization voltage trace VTL3 can be used to load the third initialization voltage Vinit3; the first scan signal first trace GNLA overlaps with the channel region T2A of the threshold compensation transistor, and the overlapping part is multiplexed as the second gate of the threshold compensation transistor T2; the first scan signal first trace GNLA overlaps with the first scan signal second trace GNLB; and the overlapping part is multiplexed as the upper and lower gates of the threshold compensation transistor T2.

[0223] The third gate layer GT3 can further be provided with a fourteenth lower via area HA14 located at the first initialization voltage trace VTL1, a fifteenth lower via area HA15 located at the third initialization voltage trace VTL3, a sixteenth lower via area HA16, a seventeenth lower via area HA17, and an eighteenth lower via area HA18 located at the second initialization voltage trace VTL2.

[0224] FIG. 30 is a schematic diagram of the first source-drain metal layer SD1 in an example. Referring to FIG. 30, the first source-drain metal layer SD1 is further provided with a first bridge MA1 to a tenth bridge MA10.

[0225] The first bridge MA1 has a first upper via area HB1 and a fourteenth upper via area HB14, wherein the first upper via area HB1 overlaps the first lower via area HA1 and is connected by a via, and the fourteenth upper via area HB14 overlaps the fourteenth lower via area HA14 and is connected by a via. In this way, the first initialization voltage line VTL1 is electrically connected to the first pole of the first reset transistor T1 through the first bridge MA1.

[0226] The second bridge MA2 has a fifteenth upper via area HB15 and a twenty-seventh lower via area HA27, wherein the fifteenth upper via area HB15 overlaps the fifteenth lower via area HA15 and is connected by a via, and the twenty-seventh lower via area HA27 overlaps the twenty-seventh upper via area HB27 and is connected by a via. In this way, a signal is loaded onto the third initialization voltage trace VTL3 through the second bridge MA2.

[0227] The third bridge MA3 has an eleventh upper via area HB11 and a twelfth upper via area HB12, wherein the eleventh upper via area HB11 overlaps the eleventh lower via area HA11 and is connected by a via, and the twelfth upper via area HB12 overlaps the twelfth lower via area HA12 and is connected by a via. In this way, the second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the third bridge MA3.

[0228] The fourth bridge MA4 has a third upper via area HB3 and a twenty-sixth lower via area HA26, wherein the third upper via area HB3 overlaps the third lower via area HA3 and is connected by a via, and the twenty-sixth lower via area HA26 is connected to the twenty-sixth upper via area HB26 and is connected by a via. In this way, a signal is loaded onto the third initialization voltage trace VTL3 through the second bridge MA2.

[0229] The fifth bridge MA5 has a twentieth lower via region HA21 and a twentieth upper via region HB20 and a tenth upper via region HB10, wherein the twentieth lower via region HA21 and the twenty-first upper via region HB21 overlap and are connected by a via, the twentieth upper via region HB20 and the twentieth lower via region HA20 overlap and are connected by a via, and the tenth upper via region HB10 and the tenth lower via region HA10 are connected and connected by a via, so that the power supply voltage VDD is connected to the first electrode of the first light emitting transistor T5 through MA5.

[0230] The sixth bridge MA6 has a twenty-third lower via region HA23 and a sixth upper via region HB6, wherein the twenty-third lower via region HA23 and the twenty-third upper via region HB23 overlap and are connected by a via, and the sixth upper via region HB6 and the sixth lower via region HA6 overlap and are connected by a via, so that the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the first bridge MA6.

[0231] The seventh bridge MA7 has a seventh upper via region HB7 and an eighteenth upper via region HB18, wherein the seventh upper via region HB7 and the seventh lower via region HA7 overlap and are connected by a via, and the eighteenth upper via region HB18 and the eighteenth lower via region HA18 overlap and are connected by a via, so that the second initialization voltage trace VTL2 is electrically connected to the second electrode of the electrode reset transistor T7 through the seventh bridge MA7.

[0232] The eighth bridge MA8 has a fourth upper via region HB4 and a ninth upper via region HB9, wherein the fourth upper via region HB4 and the fourth lower via region HA4 overlap and are connected by a via, and the ninth upper via region HB9 and the ninth lower via region HA9 overlap and are connected by a via, so that the second electrode of the data write transistor T4 and the second electrode of the second reset transistor T8 are electrically connected through the first bridge MA8.

[0233] The ninth bridge MA9 has a second upper via region HB2, a fifth upper via region HB5 and a thirteenth upper via region HB13, wherein the second upper via region HB2 and the second lower via region HA2 overlap and are connected by a via, the fifth upper via region HB5 and the fifth lower via region HA5 overlap and are connected by a via, and the thirteenth upper via region HB13 and the thirteenth lower via region HA113 overlap and are connected by a via, so that the connection between the second electrode of the first reset transistor T1, the first electrode of the second light emitting transistor T6 and the first electrode of the threshold compensation transistor T2 is realized through the ninth bridge MA9.

[0234] The tenth bridge MA10 has a sixteenth upper via region HB16 and an eighth upper via region HB8, wherein the sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected by a via, and the eighth upper via region HB8 and the eighth lower via region HA8 overlap and are connected by a via. In this way, the third initialization voltage trace VLT3 is electrically connected to the first electrode of the second reset transistor T8 through the tenth bridge MA10.

[0235] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel comprising a base substrate, a driving layer, and a pixel layer stacked in sequence; the display panel having an array of circuit areas, each of the circuit areas having a pixel driving circuit for driving a sub-pixel; The driving layer is provided with a data signal line and the pixel driving circuit has a data writing transistor electrically connected to the data signal line; the orthographic projection of the channel region of the data writing transistor on the base substrate at least partially overlaps with the orthographic projection of the data signal line on the base substrate.

2. The display panel according to claim 1, wherein In two circuit areas adjacent to each other along the first direction, the thin film transistors of the two pixel driving circuits are symmetrically arranged; The driving layer includes a transistor layer and a first source-drain metal layer stacked in sequence, and the thin film transistor is arranged in the transistor layer; The driving layer has a multiplexing via hole that spans a boundary line between two adjacent circuit areas, and the first source-drain metal layer is simultaneously connected to the thin film transistors of the two pixel driving circuits through the multiplexing via hole.

3. The display panel according to claim 2, wherein: The display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit includes a first light emitting transistor for being electrically connected to a power supply voltage terminal; the transistor layer is provided with a first polysilicon conductive structure serving as a first electrode of two first light emitting transistors in the first circuit area group; The multiplexing via includes a first multiplexing via located in the first circuit area group, the first multiplexing via exposing the first polysilicon conductive structure; In the first circuit area group, the first source-drain metal layer includes a power supply voltage metal structure capable of loading a power supply voltage; The power voltage metal structure is electrically connected to the first polysilicon conductive structure through the first multiplexing via.

4. The display panel according to claim 3, wherein: The display panel includes a first circuit area group distributed in an array, and the first circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit further includes a second reset transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; and the first electrode of the second reset transistor is electrically connected to the third initialization voltage terminal; The transistor layer is provided with a second polysilicon conductive structure in the first circuit area group, which serves as the first electrode of the two second reset transistors; The multiplexing via includes a second multiplexing via located in the first circuit area group, the second multiplexing via exposing the second polysilicon conductive structure; In the first circuit area group, the first source-drain metal layer includes a third initialization metal structure capable of applying a third initialization voltage; The third initialization metal structure is electrically connected to the second polysilicon conductive structure through the second multiplexing via.

5. The display panel according to claim 2, wherein: The display panel includes a second circuit area group distributed in an array, and the second circuit area group includes two circuit areas adjacent to each other along a first direction; The pixel driving circuit includes a driving transistor and a first reset transistor electrically connected to a first initialization voltage terminal; a first electrode of the driving transistor is electrically connected to a second electrode of the data writing transistor, and a second electrode of the driving transistor is electrically connected to a second electrode of the first reset transistor; The transistor layer is provided with a third polysilicon conductive structure in the second circuit area group, which serves as the first electrode of the two first reset transistors; The multiplexing via includes a third multiplexing via located in the second circuit area group, wherein the third multiplexing via exposes the third polysilicon conductive structure; In the second circuit area group, the first source-drain metal layer includes a first initialization metal structure capable of applying a first initialization voltage; The first initialization metal structure is electrically connected to the third polysilicon conductive structure through the third multiplexing via. The display panel according to claim 1 , wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a metal oxide semiconductor layer, and a first source-drain metal layer stacked in sequence; The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor and a second light emitting transistor; a first electrode of the first reset transistor and a first initialization transistor The voltage end is electrically connected, the second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, the second electrode of the driving transistor and the first electrode of the second light emitting transistor are electrically connected, and the second electrode of the second light emitting transistor is electrically connected to the pixel electrode; The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor; The channel region of the first reset transistor, the channel region of the driving transistor and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer; The channel region of the first reset transistor, the channel region of the threshold compensation transistor, and the channel region of the second light emitting transistor are arranged in a straight line along a second direction.

7. The display panel according to claim 2, wherein: The transistor layer includes a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer stacked; The pixel driving circuit further includes a first reset transistor, a threshold compensation transistor, a driving transistor, and a second light-emitting transistor; a first electrode of the first reset transistor is electrically connected to the first initialization voltage terminal, a second electrode of the first reset transistor, a first electrode of the threshold compensation transistor, a second electrode of the driving transistor, and a first electrode of the second light-emitting transistor are electrically connected, and a second electrode of the second light-emitting transistor is electrically connected to the pixel electrode; The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor; The channel region of the first reset transistor, the channel region of the drive transistor, and the channel region of the second light emitting transistor are located in the low-temperature polysilicon semiconductor layer; the channel region of the threshold compensation transistor is provided in the metal oxide semiconductor layer; Along the first direction, the channel region of the first reset transistor and the channel region of the threshold compensation transistor are alternately arranged.

8. The display panel according to claim 7, wherein: In the circuit area, the metal oxide semiconductor layer includes a first metal oxide structure arranged along a first direction and a second metal oxide structure arranged along a second direction; One end of the first metal oxide structure close to the data writing transistor and one end of the second metal oxide structure close to the driving transistor are connected to each other; the channel region of the threshold compensation transistor is located in the second metal oxide structure.

9. The display panel according to claim 2, wherein: The first source-drain metal layer includes a first metal structure and a second metal structure; The second metal structure is electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor, and the first electrode of the threshold compensation transistor through a via; The first metal structure is electrically connected to the second electrode of the threshold compensation transistor and the gate of the driving transistor through a via; A dimension of the second metal structure along the second direction is smaller than a dimension of the first metal structure along the second direction.

10. The display panel according to claim 9, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, a first source-drain metal layer, and a second source-drain metal layer, which are stacked in sequence; The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a second scanning signal line electrically connected to the gate of the data writing transistor; In the circuit area, the second scan signal routing line includes a first sub-scan routing line located in the first source / drain metal layer and a second sub-scan routing line located in the second source / drain metal layer; The first sub-scanning line is electrically connected to the gate of the data writing transistor through a via hole, and the second sub-scanning line is electrically connected to the first sub-scanning line through a via hole.

11. The display panel according to claim 10, wherein: In the circuit area, the metal oxide semiconductor layer includes a second metal oxide structure arranged along a second direction; an end of the second metal oxide structure away from the channel region of the driving transistor is electrically connected to the gate of the driving transistor through the first metal structure located in the first source-drain metal layer; In the circuit area, the first metal structure and the second sub-scanning trace are overlapped.

12. The display panel according to claim 1, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence; The first gate layer is provided with a gate of the data writing transistor, and the display panel is provided with a first sub-scanning line electrically connected to the gate of the data writing transistor; The first sub-scanning wiring is located in the first source-drain metal layer and is electrically connected to the gate of the data writing transistor through a via hole.

13. The display panel according to claim 7, wherein: In the circuit region, the metal oxide semiconductor layer includes a first metal oxide structure, a second metal oxide structure, and a third metal oxide structure connected in sequence, wherein the first metal oxide structure and the third metal oxide structure are arranged in parallel along the second direction; the second metal oxide structure is arranged along the first direction, and an end of the first metal oxide structure away from the driving transistor and an end of the third metal oxide structure away from the driving transistor are electrically connected to each other; One end of the third metal oxide structure close to the driving transistor is electrically connected to the gate electrode of the driving transistor through the first metal structure located in the first source-drain metal layer; one end of the first metal oxide structure close to the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer; The pixel driving circuit has a threshold compensation transistor, which includes two sub-transistors. Channel regions of the two sub-transistors are respectively located on the first metal oxide structure and the third metal oxide structure.

14. The display panel according to claim 9, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence; The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure, and the fourth polysilicon conductive structure serves as the second electrode of the first reset transistor; One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is electrically connected to the second electrode of the driving transistor through the second metal structure located in the first source-drain metal layer.

15. The display panel according to claim 5, wherein: The driving layer includes a low-temperature polysilicon semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer stacked in sequence; The low-temperature polysilicon semiconductor layer includes a fourth polysilicon conductive structure and a fifth polysilicon conductive structure, the fourth polysilicon conductive structure serving as the second electrode of the first reset transistor; the fifth polysilicon conductive structure is interconnected with the drain electrode of the driving transistor; One end of the fourth polysilicon conductive structure close to the channel region of the driving transistor is connected to the fifth polysilicon conductive structure.

16. The display panel according to claim 1, wherein The driving layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer stacked in sequence; The pixel driving circuit further includes a second reset transistor and a first light emitting transistor, wherein the second electrode of the second reset transistor is electrically connected to the second electrode of the first light emitting transistor; second The first electrode of the reset transistor is electrically connected to the third initialization voltage terminal; the first light emitting transistor is electrically connected to the power supply voltage terminal; The driving layer has a third initialization voltage wiring for loading a third initialization voltage and an enable signal wiring for loading an enable signal; The third initialization voltage line is located in the third gate layer and extends along the first direction. The enable signal line is located in the first gate layer and extends along the first direction. The enable signal line and the third initialization voltage line are overlapped.

17. A display device comprising the display panel according to any one of claims 1 to 16.

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