Semiconductor device, manufacturing method, integrated circuit, and electronic device

Abstract

A semiconductor device, a manufacturing method, an integrated circuit, and an electronic device, which are used for reducing the dielectric capacitance of semiconductor devices. The semiconductor device comprises a channel layer, a dielectric layer located on the channel layer, a source area and a drain area located on two opposite sides of the channel layer and the dielectric layer, and a first metal gate structure; the dielectric layer comprises an annular first dielectric area and a second dielectric area located on two opposite sides of the first dielectric area; a cavity in contact with the first dielectric area is formed in the second dielectric area; and the first metal gate structure is wrapped in the first dielectric area. By providing, in the second dielectric area, the cavity in contact with the first dielectric area, the low dielectric constant of air in the cavity can be utilized to reduce the overall dielectric constant of the second dielectric area, so as to reduce the dielectric capacitance of the second dielectric area, thereby reducing the RC signal delay from the first metal gate structure to the source area / drain area, and improving the switching performance of the semiconductor device.

Description

Semiconductor device, manufacturing method, integrated circuit and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on February 18, 2024, with application number 202410181713.6 and application name "A semiconductor device, preparation method, integrated circuit and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method, an integrated circuit, and an electronic device. Background Art

[0004] With the continuous development of semiconductor technology, the manufacturing process of semiconductor devices is becoming increasingly advanced. Currently, semiconductor devices have achieved micron and nanometer-level manufacturing, and in the future, they will further develop to the sub-nanometer level. This means that the size of transistors will be even smaller than it is today, and more transistors will be integrated on the same chip (also known as an integrated circuit). The integration density of chips will continue to increase, and the integrated functions will become increasingly powerful.

[0005] However, as transistor sizes shrink, short channel effects (SCE) in transistors become increasingly pronounced. To suppress SCE, the gate's control capability needs to be improved. Traditional transistors use a planar architecture, also known as a planar field-effect transistor (PFET), as shown in Figure 1a. The PFET's channel is flattened on the bottom surface of the gate, and the contact area between the two is small, resulting in less than ideal gate-to-channel electrostatic control. This led to the emergence of the fin field-effect transistor (FinFET), as shown in Figure 1b. Compared to the PFET, the FinFET's gate spans three sides of the channel, significantly increasing the contact area between the gate and the channel and improving gate-to-channel electrostatic control. However, as transistor sizes shrink to below 7nm, the SCE of the FinFET worsens, and the FinFET's electrostatic control is insufficient to suppress the increased SCE. This has prompted the transition from a tri-gate architecture to a gate-all-around architecture, leading to the emergence of the gate-all-around FET (GAAFET), as shown in Figure 1c. The gate of GAAFET surrounds the four sides of the channel, further increasing the contact area between the gate and the channel, thereby providing better electrostatic control characteristics than FinFET. However, the current mainstream GAAFET has the problem of large dielectric capacitance. The larger the dielectric capacitance between the gate and the source / drain, the greater the signal transmission delay between the gate and the source / drain, which is less conducive to improving the switching performance of GAAFET.

[0006] In summary, how to reduce the dielectric capacitance of semiconductor devices is a technical problem that urgently needs to be solved in the GAAFET field. Summary of the Invention

[0007] The present application provides a semiconductor device, a preparation method, an integrated circuit, and an electronic device for reducing the dielectric capacitance of the semiconductor device.

[0008] In a first aspect, the present application provides a semiconductor device comprising: a channel layer, a dielectric layer above the channel layer, a source region and a drain region located on opposite sides of the channel layer and the dielectric layer, and a first metal gate structure, wherein the dielectric layer comprises an annular first dielectric region and a second dielectric region located on opposite sides of the first dielectric region, the second dielectric region having a cavity in contact with the first dielectric region, and the first metal gate structure is wrapped in the first dielectric region.

[0009] By using the above semiconductor device, by providing a cavity in the second dielectric region that contacts the first dielectric region, the low dielectric constant of the air in the cavity can be used to lower the overall dielectric constant of the second dielectric region, thereby reducing the dielectric capacitance of the second dielectric region, reducing the RC signal delay from the first metal gate structure to the source / drain region, and improving the switching performance of the semiconductor device.

[0010] In one possible design, the dielectric constant of the first dielectric region is higher than the dielectric constant of the second dielectric region. For example, the first dielectric region is made of a high dielectric material, and the second dielectric region is made of a low dielectric material.

[0011] The above design surrounds the first metal gate structure with a high-dielectric material, replacing the gate oxide layer and increasing its thickness to suppress tunneling leakage current generated by the first metal gate structure. Furthermore, by placing a low-dielectric material between the high-dielectric material and the source or drain region, the relatively small dielectric constant of the low-dielectric material can be used to reduce dielectric capacitance, minimize RC signal delay, and increase the operating frequency of the semiconductor device.

[0012] In one possible design, the channel layer is shaped like a dumbbell or a concave shape. For example, in the case of multiple channel layers, the channel layers at the edges may be concave, while the channel layers in the middle may be dumbbell-shaped.

[0013] With the above design, according to the negative correlation between resistance and thickness, the greater the thickness of the dumbbell cake or the protrusion of the channel layer, the smaller the resistance of the channel layer, and the smaller the R parameter of the RC signal, thereby reducing the RC signal delay from the first metal gate structure to the source region or the drain region.

[0014] In a further possible design, the thickness of the second dielectric region is less than the thickness of the dumbbell-shaped portion of the dumbbell-shaped channel layer, or less than the thickness of the raised portion of the concave-shaped channel layer. For example, the thickness of the second dielectric region can be 1 / 3, 1 / 4, or even less than the thickness of the dumbbell-shaped portion or the raised portion.

[0015] With the above design, based on the positive correlation between dielectric capacitance and thickness, a smaller thickness of the second dielectric region results in a smaller dielectric capacitance, and thus a smaller C parameter of the RC signal, thereby further reducing the RC signal delay from the first metal gate structure to the source or drain region. Furthermore, a smaller thickness of the second dielectric region also reduces its area, resulting in fewer potential breakdown points within the second dielectric region, thereby further reducing the probability of breakdown from the first metal gate structure to the source or drain region.

[0016] In a further possible design, the first dielectric region is located above the dumbbell rod of the dumbbell-shaped channel layer or above the recessed portion of the concave-shaped channel layer, and the second dielectric region is located above the dumbbell disc of the dumbbell-shaped channel layer or above the raised portion of the concave-shaped channel layer.

[0017] With the above design, the middle position of the channel layer can be etched, and then the first dielectric material can be filled in the circumference of the etched hole to obtain the first dielectric layer. This preparation method is relatively simple and can reduce the difficulty of preparation.

[0018] In a possible design, the cavity is wrapped between the first dielectric region, the second dielectric region and the source region, or between the first dielectric region, the second dielectric region and the drain region.

[0019] With the above design, the cavity penetrates the second dielectric region in a direction perpendicular to the stacking direction. The cavity is longer and contains more air, which can improve the effect of lowering the overall dielectric constant of the second dielectric region.

[0020] In one possible design, the semiconductor device includes a substrate, N+1 aforementioned channel layers, N aforementioned dielectric layers, and N aforementioned first metal gate structures, wherein the N+1 channel layers and the N dielectric layers are alternately stacked above the substrate, and the N first metal gate structures are wrapped one-to-one in the first dielectric regions of the N dielectric layers, where N is a positive integer.

[0021] With the above design, by making the channel layer one more layer than the sacrificial layer, the channel layer can be exposed at the top layer, making it easier to subsequently expand more components on the channel layer.

[0022] In a further possible design, the semiconductor device also includes an insulating layer, a second metal gate structure and a protective layer. The insulating layer and the second metal gate structure are stacked in sequence above the top channel layer, and the protective layer surrounds the three sides of the second metal gate structure except the insulating layer.

[0023] With the above design, the semiconductor device can be packaged on the top to protect the internal structure of the semiconductor device.

[0024] In the second aspect, the present application provides a preparation method, comprising: first alternately stacking a channel layer and a sacrificial layer, then etching the outer portion of the sacrificial layer to form a first groove, then depositing a second dielectric material in the first groove to form a second dielectric region, and then forming a source region and a drain region on both sides of the channel layer and the second dielectric region, respectively, and then etching the remaining sacrificial layer to form a first hole, and opening a second groove connected to the first hole in the second dielectric region, and finally depositing the first dielectric material and the metal gate material in the first hole in sequence to form a first dielectric region and a first metal gate structure wrapped by the first dielectric region. At the same time, the second groove will be sealed by the first dielectric material to form a cavity.

[0025] In one possible design, the thickness of the sacrificial layer is smaller than the thickness of the channel layer.

[0026] With the above design, since the two end portions of the sacrificial layer will be used to prepare the second dielectric region later, the smaller the thickness of the sacrificial layer, the smaller the thickness of the second dielectric region can be, thereby reducing the dielectric capacitance of the second dielectric region and the possibility of breakdown.

[0027] In a possible design, after the second dielectric material is deposited in the first trench, a gap is formed in the formed second dielectric region, and the size of the gap is smaller than the size of the cavity.

[0028] With the above design, the cavity is actually created in two stages. In the first stage, by filling the relatively thin first trench with the second dielectric material, a relatively small gap is created in the center of the second dielectric area due to insufficient filling. Then, in the second stage, the relatively small gap created in the first stage is expanded to form a larger second trench. The second trench is then sealed by depositing the first dielectric material, forming a larger cavity. Due to the larger size of the cavity, more air can be contained within it. The low dielectric constant of this air can be used to effectively reduce the overall dielectric constant of the second dielectric area, thereby reducing the dielectric capacitance of the second dielectric area.

[0029] In one possible design, the dielectric constant of the second dielectric material is smaller than the dielectric constant of the first dielectric material.

[0030] In a possible design, etching the remaining sacrificial layer includes etching the entire remaining sacrificial layer and the surrounding channel layer, so that the etched channel layer has a dumbbell shape or a concave shape.

[0031] In a further possible design, the first dielectric region is located above the dumbbell rod of the dumbbell-shaped channel layer or above the recessed portion of the concave-shaped channel layer, and the second dielectric region is located above the dumbbell disc of the dumbbell-shaped channel layer or above the raised portion of the concave-shaped channel layer.

[0032] In a possible design, the cavity is wrapped between the first dielectric region, the second dielectric region and the source region, or between the first dielectric region, the second dielectric region and the drain region.

[0033] In a possible design, alternately stacking channel layers and sacrificial layers includes alternately stacking N+1 channel layers and N sacrificial layers on a substrate, where N is a positive integer.

[0034] In a further possible design, after alternately stacking the channel layer and the sacrificial layer, it also includes: forming an insulating layer and a second metal gate structure in sequence above the top channel layer, and forming a protective layer on three sides of the second metal gate structure except the insulating layer.

[0035] In a third aspect, the present application provides an integrated circuit, comprising a circuit board and one or more semiconductor devices as designed in the first aspect or any one of the first aspects, wherein the one or more semiconductor devices are arranged on the circuit board.

[0036] In one possible design, one or more semiconductor devices are plugged onto a circuit board.

[0037] In a fourth aspect, the present application provides an electronic device comprising a housing and an integrated circuit as in the third aspect or any one of the designs of the third aspect above, wherein the integrated circuit is disposed in the housing, for example, can be encapsulated in the housing, to achieve protection of the integrated circuit.

[0038] The technical effects that can be achieved in the above-mentioned second to fourth aspects can refer to the description of the beneficial effects in the above-mentioned first aspect, and will not be repeated here one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1a exemplarily shows a schematic structural diagram of a PFET;

[0040] FIG1b exemplarily shows a schematic structural diagram of a FinFET;

[0041] FIG1c exemplarily shows a schematic structural diagram of a GAAFET;

[0042] FIG2 exemplarily shows a schematic diagram of a possible application scenario provided by the present application;

[0043] FIG3 exemplarily shows a partial structural diagram of a gate-all-around semiconductor device provided by the industry;

[0044] FIG4 exemplarily shows a schematic structural diagram of a semiconductor device provided by the present application;

[0045] FIG5 exemplarily shows a schematic structural diagram of another semiconductor device provided by the present application;

[0046] FIG6 a exemplarily shows a structural diagram of another semiconductor device provided by the present application;

[0047] FIG6 b exemplarily shows a structural diagram of another semiconductor device provided by the present application;

[0048] FIG7 exemplarily shows a schematic flow chart of a preparation method provided in the present application;

[0049] FIG8 exemplarily shows a schematic structural diagram of another semiconductor device provided by the present application;

[0050] FIG9 exemplarily shows a schematic structural diagram of yet another semiconductor device provided by the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] The following is an explanation of some of the terms used in this application. It should be noted that these explanations are for the purpose of facilitating understanding by those skilled in the art and do not limit the scope of protection claimed in this application.

[0053] 1. Dielectric Constant and Dielectric Capacitance

[0054] The dielectric constant is the main parameter that reflects the dielectric properties or polarization properties of piezoelectric material dielectrics under the action of an electrostatic field, usually represented by ε. When two conductors are separated by a piezoelectric material dielectric (referred to as a dielectric plate), the dielectric capacitance between the two conductors can be expressed as the following formula (1.1):

[0055] Where C is the dielectric capacitance, A is the area of ​​the dielectric plate, and d is the thickness of the dielectric plate.

[0056] The above formula (1.1) can also be called the capacitance law. According to formula (1.1), when the area and thickness of the dielectric plate are fixed, the dielectric capacitance and the dielectric constant are positively correlated. The smaller the dielectric constant, the smaller the dielectric capacitance, which in turn reduces the switching delay between the two conductors. Therefore, reducing the dielectric constant is an effective means of improving the switching performance of semiconductor devices.

[0057] 2. Sacrificial Layer

[0058] Sacrificial layer technology is one of the manufacturing processes that distinguishes micro-electro-mechanical systems (MEMS) from traditional integrated circuits (ICs). This technology uses a thin film of corrodible or etchable material as an intermediate layer between a structural layer and a substrate, or between two structural layers. After the structural layer is patterned, the intermediate layer is removed using wet or dry etching to create a cavity or movable microstructure. Because the removed intermediate layer only serves as a separation layer, it is called a sacrificial layer.

[0059] 3. Resistance Law

[0060] The resistance law of metal film can be expressed as the following formula (1.2):

[0061] Where r is the resistance of the metal film, ρ is the resistivity of the metal film, l is the length of the metal film, and s is the cross-sectional area of ​​the metal film.

[0062] According to formula (1.2), when the resistivity and length of the metal film are fixed, the thicker the metal film, the larger the cross-sectional area of ​​the metal film, and the smaller the resistance of the metal film. In other words, the resistance of the metal film is negatively correlated with its thickness.

[0063] The previous text introduced some of the terms involved in this application. The following text introduces the possible application scenarios of this application.

[0064] The semiconductor device provided in the present application can be integrated into an integrated circuit, and the integrated circuit can be applied to electronic devices. Please refer to Figure 2, which exemplifies a possible application scenario of the present application, which takes the integration of a semiconductor device inside an electronic device as an example. The electronic device may include a housing, a circuit board arranged in the housing, and a semiconductor device fixed on the circuit board. Optionally, there may be multiple semiconductor devices, and multiple semiconductor devices may be integrated on the same or different circuit boards to form an integrated circuit. In addition, bonding or other connection methods can be used between any semiconductor device and the circuit board, and the connection between the semiconductor device and other devices on the circuit board can be achieved by on-board routing or inter-board routing, thereby achieving signal transmission between the semiconductor device and other devices on the circuit board.

[0065] Exemplarily, the above-mentioned electronic devices can be any type of device with processing capabilities, such as smart terminals (mobile phones, computers, tablets, PDAs, desktops, headphones, speakers, wearable devices, vehicle-mounted devices, virtual reality devices, augmented reality devices, etc.), smart home devices (such as TVs, TV set-top boxes, sweeping robots, smart desk lamps, smart broadband, audio systems, smart lighting systems, electrical control systems, home background music, home theater systems, intercom systems, or video surveillance, etc.), smart manufacturing equipment (such as industrial equipment), smart transportation equipment (such as unmanned vehicles, smart cars, electric cars, digital cars, automated guided vehicles (AGVs), unmanned transport vehicles, trucks, ships, airplanes, drones, trains, subways, or high-speed railways, etc.), robots (navigation robots, autonomous food delivery robots, medical robots or industrial robots, etc.) or surveying and mapping equipment, etc.

[0066] It should be understood that the above application scenarios are only examples, and the semiconductor devices provided in this application can also be applied to other possible scenarios, not limited to the scenarios exemplified above. For example, semiconductor devices can also be used in telecommunications equipment, such as wireless networks, fixed networks, servers, and cloud servers, etc., to increase the speed of providing network services to terminal devices. For another example, semiconductor devices can also be used in electronic devices, such as processors, memories, controllers, input / output modules, and chip modules, etc., to provide switching functions, inverting functions, computing functions, and control functions. For another example, semiconductor devices can also be used in smart life scenarios, such as automatic following trolley cases, smart dining chairs, or smart travel tools, etc. They are not listed here one by one.

[0067] It should be noted that the application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application.

[0068] As described in the background art, current mainstream semiconductor devices are gradually evolving from a tri-gate architecture to a full-gate architecture. For example, please refer to FIG3 , which shows a schematic diagram of a partial structure of a ring-gate semiconductor device provided by the industry. The semiconductor device includes a channel layer 310 disposed on a substrate 500, a dielectric layer 320 disposed on the channel layer 310, a source region 330 (or 340) and a drain region 340 (or 330) disposed on opposite sides of the channel layer 310 and the dielectric layer 320, and a metal gate structure 350. The dielectric layer 320 includes a high-dielectric material region 321 and a low-dielectric material region 322 disposed on opposite sides of the high-dielectric material region 321. The high-dielectric material region 321 is annular, and the metal gate structure 350 is wrapped in the high-dielectric material region 321. The high-dielectric material region 321 is made of a high-dielectric material and is mainly used to replace the gate oxide layer, increase the thickness of the gate oxide, and suppress gate tunneling leakage current. The low-dielectric material region 322 is made of a low-dielectric material having a relatively small dielectric constant, which can reduce dielectric capacitance and the delay of the resistance-capacitance (RC) signal from the metal gate structure 350 to the source region 330 / drain region 340, thereby increasing the operating frequency of the GAAFET.

[0069] However, low-dielectric materials have limited effectiveness in achieving low dielectric constants. For example, the dielectric constants of the most commonly used low-dielectric materials, such as silicon oxycarbide (SiOC) and silicon oxynitride (SiCN), remain around 3.2 to 5. Dielectric constants in this range still produce relatively large dielectric capacitance, resulting in a limited effect of semiconductor devices in reducing RC signal delay.

[0070] In view of this, the present application provides a semiconductor device, which, by opening a cavity in a low-dielectric material region, can utilize the low dielectric constant (approximately 1) of the air in the cavity to effectively reduce the dielectric capacitance of the low-dielectric material region and reduce the delay of the RC signal from the metal gate structure to the source / drain region.

[0071] The semiconductor device proposed in this application is described in detail below with reference to specific drawings.

[0072] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0073] Furthermore, in this application, the terms "greater than," "less than," and "equal to" do not imply absolute correlations; a certain degree of engineering error is permitted. "Thickness" does not imply absolute values; a certain degree of engineering error is permitted. Furthermore, the positional relationship between two components described in the drawings and textual descriptions does not imply an absolute relationship; a certain degree of engineering error is permitted.

[0074] Please refer to FIG4 , which is a schematic structural diagram of a semiconductor device provided in the present application. The semiconductor device may be, for example, a GAAFET. As shown in FIG4 , the semiconductor device includes a channel layer 410, a dielectric layer 420 above the channel layer 410, source and drain regions 430-440 located on opposite sides of the channel layer 410 and the dielectric layer 420, and a first metal gate structure 450. The dielectric layer 420 includes a first dielectric region 421 and a second dielectric region 422 located on opposite sides of the first dielectric region 421. The second dielectric region 422 has a cavity 460 in contact with the first dielectric region 421. The first dielectric region 421 is annular, and the first metal gate structure 450 is wrapped in the first dielectric region 421. The source and drain regions 430-440 can be understood as the source region 430 and the drain region 440, or the drain region 430 and the source region 440. The former is used as an example for the following description.

[0075] In one possible implementation, referring to FIG. 4 , the semiconductor device may include N+1 channel layers 410, N dielectric layers 420, and N first metal gate structures 450. The semiconductor device may also include a substrate 500. The N+1 channel layers 410 and the N dielectric layers 420 are alternately stacked on the substrate 500. The N first metal gate structures 450 are enclosed in the first dielectric regions 421 of the N dielectric layers 420 in a one-to-one correspondence. The source region 430 and the drain region 440 are disposed on opposite sides of the N+1 channel layers 410 and the N dielectric layers 420. For example, the source region 430 is disposed on the left side of the N+1 channel layers 410 and the N dielectric layers 420, and the drain region 440 is disposed on the right side of the N+1 channel layers 410 and the N dielectric layers 420. N may be any positive integer. For example, FIG. 4 uses N=4 as an example. However, in other examples, N may also be other values. For example, in one example, N may be 1. In this case, only two channel layers and one dielectric layer are stacked on the substrate 500, with the dielectric layer sandwiched between the two channel layers. In another example, N may be 2. In this case, three channel layers and two dielectric layers are stacked on the substrate 500, with these five layers stacked in the order of channel layer, dielectric layer, channel layer, dielectric layer, and channel layer. In another example, N may be an integer greater than 3. These examples are not listed here one by one.

[0076] The following describes the various functional components and structures shown in FIG4 , respectively, to provide an exemplary specific implementation solution.

[0077] 1. Dielectric layer

[0078] As previously described, dielectric layer 420 includes a first dielectric region 421 and a second dielectric region 422. First dielectric region 421 and second dielectric region 422 are regions formed of dielectric material. Dielectric material, also known as insulating material, is used to isolate charged conductors or conductors with different potentials, allowing current to flow in a specific direction. The greater the resistivity of a dielectric material, the greater its dielectric constant and the better its insulation performance.

[0079] Optionally, the first dielectric area 421 is annular, which can be understood as the first dielectric area 421 being an annular structure connected end to end. The annular structure can be a rectangular ring as shown in Figure 4, or a circular ring, an elliptical ring, a square ring, a trapezoidal ring, a triangular ring or other regular or irregular ring, etc. This application does not make any specific limitations on this.

[0080] Optionally, the dielectric constant of the first dielectric region 421 may be higher than the dielectric constant of the second dielectric region 422. For example, the first dielectric region 421 is composed of a high dielectric material, and the second dielectric region 422 is composed of a low dielectric material. Among them, the high dielectric material refers to a material with a high dielectric constant, for example, it may include but is not limited to aluminum oxide (AlO), titanium dioxide (TiO2), aluminum oxide-silicon nitride composite materials, ferroelectric materials, polyethylene or polystyrene, etc. The dielectric constant of these materials is very high, usually above 10. Similarly, the low dielectric material refers to a material with a low dielectric constant, for example, it may include but is not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxycarbide (SiOC) or silicon oxynitride (SiCN), etc. The dielectric constant of these materials is relatively low, usually around 3 to 5. By surrounding the first metal gate structure 450 with a high dielectric material, it can be used to replace the gate oxide layer, increase the thickness of the gate oxide layer, and suppress the first metal gate structure 450 from generating tunneling leakage current. By placing the low dielectric material between the high dielectric material and the source region 430 / the drain region 440 , the relatively small dielectric constant of the low dielectric material can be used to reduce the dielectric capacitance, reduce the delay of the RC signal, and increase the operating frequency of the semiconductor device.

[0081] Optionally, the second dielectric region 422 includes a cavity 460. This cavity 460 can be understood as a relatively large cavity structure. This cavity structure is not formed due to a problem in the filling process itself, but rather is a hole or groove intentionally opened in the second dielectric region 422, such as a separate hole or groove, or a hole or groove expanded from a gap caused by a problem in the filling process (such as the gap in FIG. 7 below). The size of the cavity 460 is much larger than the size of the gap. Therefore, the low dielectric constant of the larger volume of air in the large cavity 460 can be used to reduce the overall dielectric capacitance of the second dielectric region 422, thereby reducing the RC signal delay from the first metal gate structure 450 to the source region 430 / drain region 440.

[0082] Further, optionally, the cavity 460 contacts the first dielectric region 421 , which can be understood as one edge of the cavity 460 contacts the first dielectric region 421 , while the other edge of the cavity 460 can be in the second dielectric region 422 or in contact with the source region 430 / drain region 440 . For example, refer to Figure 5, which shows a schematic structural diagram of another semiconductor device provided by the present application. In combination with Figures 4 and 5, the cavity 460 in Figure 4 is enclosed between the second dielectric region 422 and the first dielectric region 421. One edge of the cavity 460 contacts the first dielectric region 421, while the other edge is located in the second dielectric region 422. Therefore, the length of the cavity 460 in the direction connecting the two edges (the X direction in the figure) is less than the length of the second dielectric region 422. In contrast, the cavity 460 in Figure 5 is enclosed between the second dielectric region 422, the first dielectric region 421, and the source region 430 / drain region 440. The two edges of the cavity 460 contact the first dielectric region 421 and the source region 430 / drain region 440, respectively. Therefore, the cavity 460 passes through the second dielectric region 422 in the X direction in the figure, and the length of the cavity 460 in the X direction is equal to the length of the second dielectric region 422. Based on this, if the height of the cavity 460 in the stacking direction (Y direction in the figure) is consistent, the semiconductor device with the structure shown in Figure 5 will have a larger cavity 460. Therefore, its effect on reducing the dielectric constant of the second dielectric region 422 is better than that of the semiconductor device with the structure shown in Figure 4.

[0083] It should be noted that since the cavity 460 in the second dielectric region 422 is in contact with the first dielectric region 421, whether it is the semiconductor device of the structure shown in Figure 4 or the semiconductor device of the structure shown in Figure 5, at least part of the RC signal of the first metal gate structure 450 will be directly transmitted from the first dielectric region 421 to the cavity 460, and then directly or via the second dielectric region 422 to the source region 430 / drain region 440. In the scheme shown in Figure 3, the RC signal will be transmitted from the high dielectric material region 321 to the low dielectric material region 322 and then to the source region 430 / drain region 440. Obviously, the scheme of direct transmission to the cavity 460 can speed up the signal transmission speed at the initial stage of RC signal transmission, which can effectively reduce the switching delay of the semiconductor device.

[0084] It is understood that in other examples, the cavity 460 in the second dielectric region 422 may not contact the first dielectric region 421. For example, the cavity 460 may be entirely buried in the second dielectric region 422, or one edge of the cavity 460 may contact the source region 430 / drain region 440, while the other edge is within the second dielectric region 422. This structural design may complicate the cavity fabrication process, but it can still achieve the effect of reducing dielectric capacitance.

[0085] 2. Channel Layer

[0086] For example, the channel layer 410 may be made of a conductive material. In a gate-all-around semiconductor device, the conductive material may include, but is not limited to, single-crystal silicon nanosheets or nanowires. Nanowires provide the best electrostatic control, while wider nanosheets can provide higher "on" current but also have better electrostatic control than FinFETs.

[0087] For example, referring to Figures 4 or 5 , when a semiconductor device includes at least three channel layers 410, the central channel layer 410 may be dumbbell-shaped. In other words, the central channel layer 410 may be narrow in the middle and wide at both ends. The narrow portion is called the dumbbell shaft, and the wide portions are called the dumbbell pan. All or part of the first dielectric region 421 may be located above the dumbbell shaft, and all or part of the second dielectric region 422 may be located above the dumbbell pan. For example, in the structure shown in Figures 4 or 5 , the first dielectric region 421 is located entirely above the dumbbell shaft, and the second dielectric region 422 is located entirely above the dumbbell pan. This semiconductor device structure is relatively easy to manufacture. For another example, referring to Figure 6a , a portion of the first dielectric region 421 is located above the dumbbell shaft, while the remaining portion is located above the dumbbell pan. While this semiconductor device structure is less convenient to manufacture, it allows for a larger channel region 410 area, thereby further improving current transmission efficiency. For another example, referring to FIG6b , the first medium area 421 is entirely located above the dumbbell bar, while the second medium area 422 is partially located above the dumbbell bar and partially located above the dumbbell pan.

[0088] Furthermore, taking the structure shown in FIG. 5 as an example, when a voltage is applied to the first metal gate structure 450, electrons in the channel layer 410 migrate, causing ions in the source region 430 / drain region 440 in contact with the channel layer 410 to migrate, thereby generating a current between the first metal gate structure 450 and the source region 430 / drain region 440, thereby enabling signal transmission between the first metal gate structure 450 and the source region 430 / drain region 440. However, this signal transmission is affected by RC signal delay, which is positively correlated with the capacitance (C) of the second dielectric region 422 and the resistance (R) of the channel layer 410. The smaller the capacitance C and the resistance R, the smaller the RC signal delay, the faster the signal transmission between the first metal gate structure 450 and the source region 430 / drain region 440, and the easier it is to improve the switching performance of the semiconductor device. Therefore, in order to improve the switching performance of the semiconductor device, the capacitance C of the second dielectric region 422 and the resistance R of the channel layer 410 need to be reduced.

[0089] Optionally, to reduce the capacitance C of the second dielectric region 422, the thickness of the second dielectric region 422 can be configured to be smaller than the thickness of the low dielectric material region of the existing semiconductor device. For example, in the existing semiconductor device shown in FIG3 , the thickness of the low dielectric material region 322 is typically set to 15 nm, while in the semiconductor device shown in the present application, the thickness of the second dielectric region 422 can be configured to a value less than 15 nm, such as 5 nm. Thus, according to the capacitance law formula (1.1) in the terminology explanation section, the capacitance of the dielectric plate is positively correlated with the thickness. Therefore, the smaller the thickness of the second dielectric region 422, the smaller the dielectric capacitance C of the second dielectric region 422, and the more the RC signal delay from the first metal gate structure 450 to the source region 430 / drain region 440 can be reduced. In addition, the smaller the thickness of the second dielectric region 422 , the smaller the area of ​​the second dielectric region 422 , and the fewer breakdown points in the second dielectric region 422 , thereby reducing the breakdown probability from the first metal gate structure 450 to the source region 430 / drain region 440 .

[0090] Optionally, in order to reduce the resistance R of the channel layer 410, the thickness of the dumbbell cake of the channel layer 410 can be configured to be greater than the thickness of the channel layer of the existing semiconductor device. For example, in the existing semiconductor device shown in FIG3 , the thickness of the channel layer 310 is consistent with the thickness of the low dielectric material region 322, both of which are 15 nm, while in the semiconductor device shown in the present application, the thickness of the dumbbell cake of the channel layer 410 can be configured to a value greater than 15 nm, such as 20 nm or 25 nm. In this way, according to the resistance law formula (1.2) in the term explanation part, it can be seen that the resistance of the metal film is negatively correlated with the thickness. Therefore, the greater the thickness of the dumbbell cake of the channel layer 410, the smaller the resistance R of the channel layer 410, and the more it can reduce the RC signal delay from the first metal gate structure 450 to the source region 430 / drain region 440.

[0091] Furthermore, optionally, the thickness of the dumbbell layer of the channel layer 410 can be configured to be greater than the thickness of the second dielectric region 422, for example, three times or four times the thickness of the second dielectric region 422, or even greater. For example, when the thickness of the second dielectric region 422 is 5 nm, the thickness of the dumbbell layer of the channel layer 410 can be configured to be 15 nm, 20 nm, or greater than 20 nm. For example, in one example, the thickness of the second dielectric region 422 can be configured to be 5 nm, while the thickness of the dumbbell layer of the channel layer 410 can be configured to be 25 nm, so that the sum of the thickness of the second dielectric region 422 and the dumbbell layer of the channel layer 410 remains consistent with the sum of the thickness of the channel layer and the low dielectric material region of the existing semiconductor device. In this way, the semiconductor device can be directly compatible with existing chips, for example, it can directly replace one or more semiconductor devices on the existing chip without having to modify the structure of the existing chip, thereby maximizing the reuse of existing chips. For example, in another example, the thickness of the second dielectric region 422 can be configured to be 5 nm, and the thickness of the dumbbell cake of the channel layer 410 can be between 15 and 25 nm. In this way, by making the sum of the thickness of the second dielectric region 422 and the dumbbell cake of the channel layer 410 smaller than the sum of the thickness of the channel layer and the low dielectric material region of the existing semiconductor device, the volume of the semiconductor device can be reduced while reducing the RC signal delay, thereby realizing a miniaturized chip design.

[0092] It will be appreciated that the above description merely illustrates several possible thickness configurations for the second dielectric region 422 and the channel layer 410. In actual semiconductor devices, the second dielectric region 422 and the channel layer 410 may also have other thickness configurations. For example, in another example, the thickness of the second dielectric region 422 may be configured to be the same as the thickness of the dumbbell layer 410, such as 15 nm, 10 nm, or 5 nm. In yet another example, the thickness of the second dielectric region 422 may be configured to be greater than the thickness of the dumbbell layer 410, such as 15 nm for the second dielectric region 422 and 10 nm for the dumbbell layer 410. For example, in another example, the thickness of the second dielectric region 422 can be configured to be smaller than the thickness of the dumbbell layer of the channel layer 410, but different from the thicknesses given above. For example, the thickness of the second dielectric region 422 can be 5 nm, and the thickness of the dumbbell layer of the channel layer 410 can be 15 nm; or the thickness of the second dielectric region 422 can be 15 nm, and the thickness of the dumbbell layer of the channel layer 410 can be 20 nm; or the thickness of the second dielectric region 422 can be 10 nm, and the thickness of the dumbbell layer of the channel layer 410 can be 12 nm. There are many other possible thickness configurations, which are not listed here.

[0093] For example, referring to Figure 4 or Figure 5 , except for the channel layer 410 in the middle, the channel layer 410 at the edges (shown as the upper and lower edges) may have a concave structure. In other words, the channel layer 410 at the edges may have a structure with raised sides and a concave center. The raised portions on the sides are referred to as raised portions, and the concave portion in the center is referred to as a concave portion. The raised portions of the channel layer 410 at the edges are similar to the dumbbell shape of the channel layer 410 in the middle, while the concave portions of the channel layer 410 at the edges are similar to the dumbbell shape of the channel layer 410 in the middle. For example, all or part of the first dielectric region 421 is located above the concave portion, and all or part of the second dielectric region 422 is located above the raised portion. For another example, the thickness of the raised portion is greater than the thickness of the channel layer in conventional semiconductor devices. For another example, the thickness of the raised portion is greater than the thickness of the second dielectric region 422, for example, it may be three times or more the thickness of the second dielectric region 422. And so on. For related content, please refer to the above introduction to dumbbell cakes and dumbbell bars, and I will not repeat them here.

[0094] It should be noted that the present application only limits the thickness of the dumbbell cake of the channel layer 410, but does not limit the thickness of the dumbbell rod of the channel layer 410. For example, the thickness of the dumbbell rod can be greater than the thickness of the second dielectric area 422, or less than the thickness of the second dielectric area 422, or the same as the thickness of the second dielectric area 422. The specific thickness can be determined according to the application scenario requirements or the preparation process.

[0095] 3. Electrode Area

[0096] Here, the electrode region of the semiconductor device refers to a structural region for forming an electrode, and may include, for example, a first metal gate structure 450 , a source region 430 , and a drain region 440 .

[0097] Optionally, the first metal gate structure 450 is used to form a gate of a semiconductor device and can be generally made of a metal material, such as, but not limited to, aluminum, tungsten, molybdenum, silver, aluminum-copper, and titanium-aluminum alloy. There are many methods for preparing the first metal gate structure 450. For example, the gate metal material can be first filled into the corresponding hole through a preparation process such as physical vapor deposition, electron beam evaporation, or magnetron sputtering, and then the surface can be flattened through chemical-mechanical polishing (CMP) to obtain a smooth metal gate structure.

[0098] Optionally, the source region 430 is used to form the source of the semiconductor device, and the drain region 440 is used to form the drain of the semiconductor device. The source region 430 is typically made of a highly doped silicon material, while the drain region 440 is typically made of a low-doped silicon material. This ensures that the source region 430 can provide sufficient electrons and the drain region 440 can absorb electrons.

[0099] In the above-mentioned semiconductor device, the dielectric capacitance of the second dielectric region and the resistance of the channel layer are two important parameters for RC signal delay. The semiconductor device provided in this application uses three means to reduce these two parameters: Means 1, by setting a relatively large cavity in the second dielectric region, the low dielectric constant of the air in the cavity is used to lower the overall dielectric constant of the second dielectric region, thereby reducing the dielectric capacitance of the second dielectric region; Means 2, by setting a relatively small thickness for the second dielectric region, the dielectric capacitance of the second dielectric region is further reduced by taking advantage of the positive correlation between dielectric capacitance and thickness; Means 3, by setting a relatively large thickness for the channel layer, the resistance of the channel layer is reduced by taking advantage of the negative correlation between resistance and thickness. In this way, by combining these three means to reduce resistance and capacitance, the RC signal delay can be effectively reduced, the signal transmission efficiency can be accelerated, and the switching performance of the semiconductor device can be improved.

[0100] Based on the semiconductor device described above, the present application further provides a manufacturing method. Referring to FIG. 7 , a schematic diagram of a possible process of the manufacturing method is shown. Taking the manufacturing of the semiconductor device shown in FIG. 5 as an example, the manufacturing method may include the following steps 1 to 8.

[0101] In step 1, channel layers 410 and sacrificial layers 470 are alternately stacked on the substrate 500 to obtain the structure shown in FIG. 7 (A).

[0102] Here, the sacrificial layer 470 can be understood as a layered structure made of a sacrificial material, which may include but is not limited to polysilicon, photoresist, metal film, or polyimide, etc. For example, in a specific example, the sacrificial layer 470 can be made of silicon germanium (SiGe).

[0103] Optionally, assuming that a layer of channel layer 410 and a layer of sacrificial layer 470 are called a group, the number of alternating stacked groups can be set according to demand. For example, when the demand for integration is relatively high, the number of alternating stacked groups can be set to be larger, such as greater than or equal to 4, and when the demand for low cost is relatively high, the number of alternating stacked groups can be set to be smaller, such as less than 4.

[0104] Furthermore, optionally, the number of channel layers 410 can be one more than the number of sacrificial layers 470. For example, when the number of sacrificial layers 470 is N, the number of channel layers 410 can be N+1, where N is a positive integer. For example, FIG7 takes N as an example, where there are five channel layers and four sacrificial layers. The five channel layers and the four sacrificial layers are alternately stacked on the substrate 500, such that both the bottom and top layers are channel layers 410. Thus, by exposing the channel layer 410 at the top, it is possible to facilitate the subsequent expansion of more components on the channel layer 410.

[0105] However, it should be understood that in another example, the number of channel layers 410 can be the same as the number of sacrificial layers 470, for example, the channel layer 410 is the bottom layer and the sacrificial layer 470 is the top layer, or the channel layer 410 is the top layer and the sacrificial layer 470 is the bottom layer. Alternatively, in another example, the number of sacrificial layers 470 can be greater than the number of channel layers 410, in which case both the bottom layer and the top layer are sacrificial layers 470. This application does not specifically limit the relationship between the number of channel layers 410 and the number of sacrificial layers 470.

[0106] Furthermore, optionally, the thickness of the sacrificial layer 470 may be smaller than the thickness of the channel layer 410. For example, the thickness of the sacrificial layer 470 is 1 / 3, 1 / 4 or less of the thickness of the channel layer 410. For example, the thickness of the sacrificial layer 470 is 5 nm, and the thickness of the channel layer is 15 nm or 20 nm. In this way, since the two end portions of the sacrificial layer 470 will be used to prepare the second dielectric region 422 later, the smaller the thickness of the sacrificial layer 470, the smaller the thickness of the second dielectric region 422 can also be, and thus the dielectric capacitance of the second dielectric region 422 is smaller. The greater the thickness of the channel layer 410, the smaller the resistance of the channel layer 410. By reducing the dielectric capacitance of the second dielectric region 422 and the resistance of the channel layer 410, the effect of reducing the RC signal delay can be achieved.

[0107] It should be understood that the above is only an optional implementation. In other implementations, the thickness of the sacrificial layer 470 may also be equal to or greater than the thickness of the channel layer 410 , and this application does not make any specific limitation on this.

[0108] Step 2: etching the outer portion of the sacrificial layer 470 to form a first groove, thereby obtaining the structure shown in FIG. 7 (B).

[0109] Optionally, a selective etching technique may be used to etch the sacrificial layer 470 inward from the outermost end thereof to a depth of about 3 to 6 nm, so as to form a first groove between the sacrificial layer 470 and the two adjacent channel layers 410 .

[0110] Step three: depositing a second dielectric material in the first trench to form a second dielectric region 422 , thereby obtaining the structure shown in FIG. 7 (C) .

[0111] Optionally, the second dielectric material may be a low-K material, such as SiOC or SiCN, etc. Since the second dielectric region 422 is made of a low-K material, it may also be referred to as a low-K material region, and its dielectric constant is typically 3.2-5.

[0112] Furthermore, optionally, because sacrificial layer 470 is relatively thin, the first trench is also relatively thin. When filling the relatively thin first trench with the second dielectric material, insufficient filling often results in a triangular or quasi-triangular void (also referred to as a hole) in the center of the first trench, as shown in FIG7(C). The dielectric material in the void is air, which has a dielectric constant of approximately 1. Therefore, the presence of the void can lower the overall dielectric constant of the second dielectric region 422. However, since this void is caused by a problem in the filling process, its size is relatively small and it is located approximately in the center of the second dielectric region. Therefore, the effect of this void on reducing the dielectric constant is relatively limited.

[0113] In step 4, a source region 430 and a drain region 440 are formed on both sides of the channel layer 410 and the second dielectric region 422 , respectively, to obtain the structure shown in FIG. 7 (D).

[0114] For example, a single crystal silicon material may be first deposited on the left side of the channel layer 410 and the second dielectric region 422 in the figure, and then a high concentration of ions may be doped into the single crystal silicon material to form the source region 430. Similarly, a single crystal silicon material may be first deposited on the right side of the channel layer 410 and the second dielectric region 422 in the figure, and then a low concentration of ions may be doped into the single crystal silicon material to form the drain region 440.

[0115] Step five: etching the remaining sacrificial layer 470 to form a second hole, thereby obtaining the structure shown in FIG. 7 (E).

[0116] Here, the second hole is obtained by etching the sacrificial layer 470 , and therefore, the height of the second hole is the same as the thickness of the sacrificial layer 470 .

[0117] Step six, etching the channel layer 410 around the second hole, expanding the second hole into the first hole, and opening a second groove in communication with the first hole in the second dielectric region 422 to obtain the structure shown in FIG. 7 (F).

[0118] Here, the first hole is obtained by enlarging the second hole, and therefore, the height of the first hole is greater than the thickness of the sacrificial layer 470 .

[0119] Optionally, since the second hole is located above the center of the channel layer 410, etching the channel layer 410 around the second hole will cause the central region of the channel layer 410 to become thinner, thereby causing the channel layer 410 located in the middle to have a dumbbell shape, while the channel layer 410 located at the edge to have a concave structure. The dumbbell-shaped channel layer's dumbbell-shaped plate and the convex portion of the concave-shaped channel layer are located below the second dielectric region 422, while the dumbbell-shaped channel layer's dumbbell rod and the concave portion of the concave-shaped channel layer are located below the expanded first hole.

[0120] Alternatively, the second trench can be formed by opening a gap in the second dielectric region 422. For example, after the first hole is enlarged, the second dielectric material can be selectively etched at the center of both sides of the first hole until the gap is reached. Then, the second dielectric material surrounding the gap can be selectively etched to open the gap and obtain a larger second trench.

[0121] Furthermore, optionally, if the second dielectric material is etched for a relatively short time and has not yet reached the edge of the second dielectric region 422, one edge of the second trench connects to the first hole, while the other edge lies within the second dielectric region 422. Consequently, the second trench is enclosed by the second dielectric region 422 and the first hole. Conversely, if the second dielectric material is etched for a relatively long time and has already reached the edge of the second dielectric region 422, one edge of the second trench connects to the first hole, while the other edge contacts the source / drain region 430 / 440. Consequently, the second trench is enclosed by the second dielectric region 422, the source / drain region 430 / 440, and the first hole. The latter method results in a larger second trench, more air in the second trench, and a better dielectric constant reduction effect, but requires more etching material, resulting in higher fabrication costs. Therefore, if the demand for a low dielectric constant is high, more etching material can be used to etch a larger cavity, and if the demand for low preparation cost is high, slightly less etching material can be used to etch a slightly smaller cavity, but the cavity will still be much larger than the gap in step three, so it can also have the effect of partially reducing the dielectric constant.

[0122] In step seven, a first dielectric material is deposited around the first hole to form an annular first dielectric region 421 . Meanwhile, the second groove is sealed by the first dielectric material to form a cavity, thereby obtaining the structure shown in FIG. 7 (G).

[0123] Optionally, the first dielectric material may be a high dielectric material (HighK), such as AlO or TiO2, etc. Since the first dielectric region 421 is made of a high dielectric material, the first dielectric region 421 may also be referred to as a high dielectric material region, and its dielectric constant is generally greater than 10.

[0124] Furthermore, optionally, because the first hole is connected to the second groove, when the first dielectric material is deposited circumferentially around the first hole, a portion of the first dielectric material is also deposited where the second groove connects to the first hole, sealing the second groove and forming a cavity. Since the second groove is relatively large, the cavity is also relatively large. This cavity is much larger than the gap formed due to the filling process in step three. In other words, the cavity can contain a larger volume of air. Therefore, the lower dielectric constant of the larger volume of air can be utilized to further reduce the overall dielectric constant of the second dielectric region 422, thereby reducing the dielectric capacitance of the second dielectric region 422.

[0125] Step eight: depositing a metal gate material in the first dielectric region 421 to form a first metal gate structure 450 , thereby obtaining the structure shown in FIG. 7 (H).

[0126] Here, the first metal gate structure 450 is wrapped by the first dielectric region 421. Therefore, the first dielectric region 421 can be used to isolate the first metal gate structure 450 from the channel layer 410, while allowing electrons in the channel layer 410 to approach or move away from the first metal gate structure 450 as the voltage applied to the first metal gate structure 450 changes, thereby achieving conduction or disconnection between the first metal gate structure 450 and the source region 430 / drain region 440.

[0127] Using the above-described fabrication method, the cavity in the second dielectric region is actually created in two stages: the first during the filling phase of the second dielectric region, and the second during the etching phase of the channel layer and the deposition phase of the first dielectric region. In the first stage, by filling the relatively thin sacrificial layer etched trench (i.e., the first trench) with the second dielectric material, a relatively small void is created in the center of the second dielectric region due to insufficient filling. Subsequently, in the second stage, by opening the void in the first stage during the etching of the channel layer, the void is expanded into a larger second trench, which is then sealed by depositing the first dielectric material, forming a relatively large cavity. Due to the larger size of the cavity, more air can be contained within it, and the low dielectric constant of this air can be used to effectively lower the overall dielectric constant of the second dielectric region, thereby reducing the dielectric capacitance of the second dielectric region.

[0128] The above content introduces the specific structure of the semiconductor device provided by this application and the corresponding preparation method, but it should be understood that the structure and preparation method are only examples. The actual semiconductor device may also include more or fewer layers or structures, and the actual preparation method may also include more or fewer steps. This application does not make specific limitations on this.

[0129] For example, please refer to FIG8 , which shows a possible structural schematic diagram of another semiconductor device provided by the present application. The diagram takes the semiconductor device shown in FIG5 as an example, which can be understood as a structure after encapsulating the topmost channel layer of the semiconductor device shown in FIG5 . As shown in FIG8 , in addition to the aforementioned channel layer 410, dielectric layer 420, source region 430, drain region 440 and first metal gate structure 450, the semiconductor device in this example may also include an insulating layer 480, a second metal gate structure 451 and a protective layer 490. The insulating layer 480 is located above the topmost channel layer 410, the second metal gate structure 451 is located above the insulating layer 480, and the protective layer 490 surrounds the three side surfaces of the second metal gate structure 451 except the insulating layer 480, such as the left, top and right side surfaces shown in the diagram.

[0130] Optionally, the second metal gate structure 451 may also be used to form a gate of a semiconductor device, and may generally be made of metal materials, such as but not limited to aluminum, tungsten, molybdenum, silver, aluminum-copper, and titanium-aluminum alloy.

[0131] Optionally, the protective layer 490 may also be referred to as a barrier layer or mask, and may be used to protect the second metal gate structure 451 located therein from being affected by the external environment. The protective layer 490 may be made of a variety of materials, including but not limited to metal materials such as titanium, tantalum, chromium, aluminum, and copper, or non-metal materials such as barium fluoride and calcium fluoride, or a combination of metal and non-metal materials.

[0132] Optionally, an insulating layer 480 may be used to isolate the second metal gate structure 451 from the underlying channel layer 410. The function of the insulating layer 480 is similar to that of the first dielectric region 421. For example, when a voltage is applied to the second metal gate structure 451, the voltage drives electrons in the underlying channel layer 410 to move. Consequently, under the isolation effect of the insulating layer 480, electrons in the source region 430 / drain region 440 are caused to accumulate on the upper surface of the channel layer through the channel layer 410, or electrons in the channel layer 410 are caused to disperse to the source region 430 / drain region 440, thereby achieving conduction between the second metal gate structure 451 and the source region 430 / drain region 440.

[0133] Furthermore, optionally, the insulating layer 480 may be prepared using metal oxides, such as but not limited to aluminum oxide (Al2O3), iron oxide (Fe2O3), sodium oxide (Na2O), magnesium oxide (MgO) and potassium oxide (K2O).

[0134] It can be understood that if the semiconductor device shown in Figure 8 is to be prepared, then in step one shown in Figure 7, after the channel layer 410 and the sacrificial layer 470 are alternately stacked on the substrate 500, an insulating layer 480 can be deposited above the top channel layer 410, and a second metal gate structure 451 can be deposited above the insulating layer 480. Then, a mask is deposited on the periphery of the second metal gate structure 451 to obtain a protective layer 490. After that, subsequent steps two to eight are performed based on this structure to obtain the semiconductor device shown in Figure 8.

[0135] In addition, FIG8 shows that only one row and one column of semiconductor devices are prepared on a substrate. In order to improve the integration of semiconductor devices, multiple rows and columns of semiconductor devices can usually be prepared simultaneously on a substrate. For example, please refer to FIG9, which shows a schematic structural diagram of another semiconductor device provided by the present application. The structure has at least three columns of semiconductor devices prepared on a substrate 500, and each column has at least two rows. The semiconductor devices in adjacent rows can be separated by an isolation layer 510 to reduce mutual interference between the semiconductor devices in adjacent rows. The semiconductor devices in adjacent columns can share the same source region 430 or drain region 440. For example, from left to right, the semiconductor devices in the first column and the semiconductor devices in the second column share the same drain region 440, while the semiconductor devices in the second column and the semiconductor devices in the third column share the same source region 430. The method of sharing the source region or drain region can reduce the difficulty of preparation and further improve the integration.

[0136] It should be noted that, in the semiconductor device shown in FIG8 or FIG9 , the concepts, explanations, detailed descriptions and other steps involved can be found in the descriptions of these contents in the aforementioned structure and method embodiments, and are not repeated here.

[0137] Based on the semiconductor device described above, the present application can also provide an integrated circuit, which may include a circuit board and one or more semiconductor devices arranged on the circuit board, wherein the semiconductor device may be the semiconductor device in any of the aforementioned embodiments, such as the semiconductor device shown in Figures 4, 5, 6a, 6b, 8 or 9.

[0138] Based on the integrated circuit described above, the present application may also provide an electronic device, as shown in FIG2 . This electronic device may include a housing and the integrated circuit, with the integrated circuit disposed within the housing. For example, a circuit board within the integrated circuit may be secured to the inner wall of one housing, with the semiconductor devices on the circuit board facing the inner wall of the other housing, thereby encapsulating the integrated circuit as a whole within the housing and providing protection for the integrated circuit.

[0139] In the above description of the present application, "plurality" means two or more. " / " means or, for example, "A / B" means A or B. The word "optionally" or "exemplarily" is used to indicate an example, illustration or description. Any embodiment or design described in the present application as "example" or "optional" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Alternatively, it can be understood that the use of the word "example" or "optional" is intended to present the concept in a specific way and does not constitute a limitation on the present application.

[0140] In addition, the various numbers involved in this application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. For example, the terms "first", "second", "third" and the like are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. In addition, the terms "comprise" and "have" and any of their variations are intended to cover non-exclusive inclusions, for example, comprising a series of steps or units. Methods, products or equipment are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0141] Furthermore, the above content is only one possible embodiment provided by this application. The structure or method of this embodiment can also be extended to any device or component that requires dielectric capacitors. Moreover, with the evolution of system architecture and the emergence of new scenarios, the structure or method provided by this application is also applicable to similar technical problems, and this application does not specifically limit this.

[0142] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that: The device comprises a channel layer, a dielectric layer above the channel layer, a source region and a drain region located on opposite sides of the channel layer and the dielectric layer, and a first metal gate structure; The dielectric layer includes a first annular dielectric region and second dielectric regions located on two opposite sides of the first dielectric region. The second dielectric region has a cavity in contact with the first dielectric region. The first metal gate structure is wrapped in the first dielectric region.

2. The semiconductor device according to claim 1, wherein The dielectric constant of the first dielectric region is higher than the dielectric constant of the second dielectric region.

3. The semiconductor device according to claim 1 or 2, wherein: The channel layer is in a dumbbell shape or a concave shape.

4. The semiconductor device according to claim 3, wherein The thickness of the second dielectric region is smaller than the thickness of the dumbbell cake of the dumbbell-shaped channel layer, or smaller than the thickness of the convex portion of the concave-shaped channel layer.

5. The semiconductor device according to claim 3 or 4, wherein: The first dielectric region is located above the dumbbell rod of the dumbbell-shaped channel layer or above the concave portion of the concave channel layer, and the second dielectric region is located above the dumbbell disc of the dumbbell-shaped channel layer or above the convex portion of the concave channel layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein The cavity is wrapped between the first dielectric region, the second dielectric region and the source region, or between the first dielectric region, the second dielectric region and the drain region.

7. The semiconductor device according to any one of claims 1 to 6, wherein The semiconductor device includes a substrate, N+1 channel layers, N dielectric layers and N first metal gate structures, wherein the N+1 channel layers and the N dielectric layers are alternately stacked above the substrate, and the N first metal gate structures are wrapped in the first dielectric regions of the N dielectric layers in a one-to-one correspondence, where N is a positive integer.

8. The semiconductor device according to claim 7, wherein Also includes an insulating layer, a second metal gate structure and a protective layer; The insulating layer and the second metal gate structure are sequentially stacked on the uppermost channel layer, and the protection layer surrounds three side surfaces of the second metal gate structure except the insulating layer.

9. A preparation method, characterized in that: The method comprises: Alternatingly stacking channel layers and sacrificial layers; etching a peripheral portion of the sacrificial layer to form a first groove; depositing a second dielectric material in the first trench to form a second dielectric region; forming a source region and a drain region on both sides of the channel layer and the second dielectric region respectively; Etching the remaining sacrificial layer to form a first hole, and opening a second groove in the second dielectric region to communicate with the first hole; A first dielectric material and a metal gate material are sequentially deposited in the first hole to form a first dielectric region and a first metal gate structure wrapped by the first dielectric region. The second groove is sealed by the first dielectric material to form a cavity.

10. The method according to claim 9, wherein The thickness of the sacrificial layer is smaller than the thickness of the channel layer.

11. The method according to claim 9 or 10, wherein: After depositing the second dielectric material in the first trench, a gap is formed in the formed second dielectric region, and the size of the gap is smaller than the size of the cavity.

12. The method according to any one of claims 9 to 11, characterized in that The dielectric constant of the second dielectric material is smaller than the dielectric constant of the first dielectric material.

13. The method according to any one of claims 9 to 12, characterized in that The etching of the remaining sacrificial layer comprises: The entire remaining sacrificial layer and the surrounding channel layer are etched, so that the etched channel layer is in a dumbbell shape or a concave shape.

14. The method according to claim 13, wherein The first dielectric region is located above the dumbbell rod of the dumbbell-shaped channel layer or above the concave portion of the concave channel layer, and the second dielectric region is located above the dumbbell pan of the dumbbell-shaped channel layer or above the convex portion of the concave channel layer.

15. The method according to any one of claims 9 to 14, characterized in that The cavity is wrapped between the first dielectric region, the second dielectric region and the source region, or between the first dielectric region, the second dielectric region and the drain region.

16. The method according to any one of claims 9 to 15, characterized in that The alternately stacked channel layers and sacrificial layers include: N+1 channel layers and N sacrificial layers are alternately stacked on the substrate, where N is a positive integer.

17. The method according to claim 16, wherein After the channel layer and the sacrificial layer are alternately stacked, the method further includes: forming an insulating layer and a second metal gate structure in sequence above the uppermost channel layer; A protection layer is formed on three side surfaces of the second metal gate structure except the insulating layer.

18. An integrated circuit, characterized in that: The invention comprises a circuit board and one or more semiconductor devices according to any one of claims 1 to 8, wherein the one or more semiconductor devices are arranged on the circuit board.

19. An electronic device, characterized in that: The device comprises a housing and the integrated circuit according to claim 18, wherein the integrated circuit is arranged in the housing.

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