Hybrid photonic integrated circuit and manufacturing method

Abstract

The present invention relates to a hybrid photonic integrated circuit comprising: (a) a photonic functional layer having silicon technology comprising: a silicon surface, wherein the silicon surface comprises at least one silicon pillar; a silicon oxide layer, wherein the silicon oxide layer is traversed by the at least one silicon pillar; a waveguide, and (b) a III-V semiconductor layer, wherein the III-V semiconductor layer is in contact with the at least one silicon pillar, the silicon oxide layer, and the waveguide, wherein the III-V semiconductor layer is an intact layer, and wherein the at least one silicon pillar functions as a heat sink. The invention further relates to a method for preparing said hybrid photonic integrated circuit, wherein the method is based on wet or dry etching of silicon, thermal oxidation and chemical mechanical polishing.

Description

[0001] HYBRID PHOTONIC INTEGRATED CIRCUIT AND MANUFACTURING METHOD

[0002] FIELD OF INVENTION

[0003] The present invention falls within the field of photonics. More specifically, the object of the invention relates to a hybrid photonic integrated circuit and its manufacturing method.

[0004] BACKGROUND OF THE INVENTION

[0005] Photonics is a key technology with countless applications, including optical data communications, sensing systems, and quantum technologies. These applications find specific uses in industries such as the automotive industry (e.g., autonomous driving), biomedical applications (lab-on-a-chip devices), or applications in the aerospace and defense industries. In this context, hybrid photonic integrated circuits based on silicon technology combined with III-V semiconductor technology are key to realizing photonic applications on chips. The combination of these technologies generally relies on placing a piece of III-V semiconductor on top of silicon technology. The latter is usually composed of different dielectric materials deposited on a silicon wafer, such that the III-V semiconductor piece sits on top of the dielectric materials.

[0006] In most photonic applications, III-V semiconductors require a bias current to operate. When this bias current is applied, the III-V semiconductor heats up, thereby degrading its performance. Therefore, it is necessary to dissipate the generated heat to prevent performance degradation. Generally, the natural escape route for heat in hybrid photonic integrated circuits is to the silicon technology. However, silicon dielectrics, such as silicon oxide and silicon nitride (which are essential for photonic functionality) have low thermal conductivity.

[0007] As a solution to this problem, the state of the art presents structures that function as heat sinks and are integrated into the architecture of hybrid photonic integrated circuits. Thus, Wang et al. ("Optimization and thermal analysis of hybrid microdisk lasers," 10th International Conference on Group IV Photonics, Seoul, Korea (South), 2013, pp. 49-50) disclose a microdisk laser that incorporates a polysilicon structure as a heat sink in the center such that the laser active layer is thermally connected to the silicon substrate (a good thermal conductor). However, the heat sink structure is formed by an etching step through the III-V semiconductor and silicon oxide layers down to the silicon substrate, followed by the formation of a polysilicon heat sink by chemical mechanical deposition and polishing. This implies the creation of discontinuity spaces in the III-V semiconductor layer.Similarly, US 2022 / 0344233 A1 describes heat dissipating structures that are introduced into the structure after etching procedures through the dielectric material layers.

[0008] Thus, there is a need in this technical field to provide alternative solutions for dissipating the heat generated in the active zone of hybrid photonic integrated circuits.

[0009] DETAILED DESCRIPTION OF THE INVENTION

[0010] In view of the needs in this technical field, the inventors have developed a method for the manufacture of a hybrid photonic integrated circuit (1) wherein a III-V semiconductor is arranged on a silicon technology chip incorporating silicon pillars around dielectric materials (such as silicon oxide and / or silicon nitride), such that the thermal flow for heat dissipation occurs preferentially through said silicon pillars, since silicon has a thermal conductivity an order of magnitude greater than silicon oxide and silicon nitride dielectrics. In this way, more efficient operation of the device is achieved. The method developed by the inventors has the additional advantage that it is not necessary to etch through the III-V semiconductor layer for the integration of the heat dissipating structure, whereby said III-V semiconductor layer remains intact.

[0011] Thus, the invention relates in a first aspect to a hybrid photonic integrated circuit (1) comprising: a) a photonic functional layer of silicon technology comprising:

[0012] - a silicon surface (2), where the silicon surface (2) comprises at least one silicon pillar (3), where the at least one silicon pillar (3) has two bases, a lower base and an upper base, where the lower base is arranged on the silicon surface (2), and where the silicon surface (2) and the at least one silicon pillar (3) form, without interruption, a single piece;

[0013] - a layer of silicon oxide (4), where the layer of silicon oxide (4) comprises two faces, a first face and a second face, where the first face is arranged on the silicon surface (2), and where the layer of silicon oxide (4) is crossed by at least one silicon pillar (3) between the first face and the second face;

[0014] - optionally, a waveguide (5), wherein the waveguide (5) is comprised in the silicon oxide layer (4), and wherein the waveguide (5) is not in direct contact with either the silicon surface (2) or the at least one silicon pillar (3); and b) a layer of a III-V semiconductor (6) or a chip hybridizable with a silicon dielectric technology, wherein the III-V semiconductor layer (6) or the chip hybridizable with a silicon dielectric technology is in contact with the upper base of the at least one silicon pillar (3), with the second face of the silicon oxide layer (4), and optionally with the waveguide (5), and wherein the III-V semiconductor layer (6) or the chip hybridizable with a silicon dielectric technology is not traversed by the at least one silicon pillar (3), where the at least one silicon pillar (3) functions as a heat sink.

[0015] In the context of the invention, the term "photonic integrated circuit" (or PIC, also known as an integrated optical circuit) refers to a microchip that detects, generates, transports, and / or processes light, as it comprises a functional circuit containing more than one photonic component. Thus, in a photonic chip, the photons in the light beam pass through optical components such as waveguides (equivalent to a resistor or electrical cable), lasers (equivalent to transistors), polarizers, and phase shifters. A chip can integrate different technologies with diverse optical properties to create a hybrid circuit. Thus, a hybrid platform can heterogeneously integrate the functionality of an I ll / V semiconductor into a silicon technology platform.In the context of the invention, the term "silicon technology" refers to photonic systems based on silicon and silicon derivatives with which various structural elements with different functional capabilities can be fabricated. For example, silicon and silicon nitride can function as waveguides, while silicon oxide can function as an insulating element. For the microfabrication of silicon technology elements, one must initially start from a silicon surface (2). In the context of the present invention, the term "silicon surface" refers to a surface face of a silicon layer, where the silicon layer typically refers to a sheet consisting of the semiconductor material high-purity crystalline silicon.In the field of microelectronics, sheets of semiconductor materials are usually provided in the form of wafers (or, in English, "wafers") and are generally used to manufacture microcircuits using doping, chemical etching, and vapor deposition techniques. Therefore, in the present invention, the term "silicon layer" can also be understood as "silicon wafer" or "silicon wafer" if the English terminology is used. Another equivalent term to "silicon layer," "silicon wafer," or "silicon wafer" is "silicon substrate," since, for the synthesis of microcircuits, the silicon layer acts as a substrate, on which the remaining layers made of different materials are deposited. Generally, at the microscopic level, the sheet of crystalline silicon semiconductor material can have a thickness in the range of hundreds of micrometers.For example, a 4" silicon wafer may have a thickness of 525 pm, while a 6" wafer may have a thickness of about 675 pm. In embodiments of the invention, the silicon wafer has a (111) orientation, a (100) orientation, or a (110) orientation.

[0016] The object of the present invention is the manufacture of at least one silicon pillar (3) as a structural element within a hybrid photonic integrated circuit (1) with the function of acting as a heat dissipating element from the active zone of the device towards the silicon substrate. In this sense, the at least one silicon pillar (3) of the present invention allows the active zone of the invention (for example, the layer of semiconductor material III-V) to be put in thermal contact with the silicon substrate. In the context of the invention, the term "heat sink" or "heat sink" refers to a structural element integrated into the device that allows and facilitates the transfer of heat flows through it. Said heat transfer capacity is given by the design of the device, specifically by the materials that comprise it and their arrangement.In particular embodiments of the present invention, the photonic integrated circuit comprises at least one, at least two, at least three, at least four, at least five, at least ten, at least twenty, at least thirty, at least forty, at least fifty, at least one hundred, at least two hundred, at least five hundred, at least one thousand, at least two thousand, at least five thousand, at least ten thousand silicon pillars. Thus, in particular embodiments of the present invention, the photonic integrated circuit comprises 1, 2, 3, 4, 5, 6, 10, 12, 15, 20, 30, 40, 50, 60, 70, 80, 90, 100, 120, 150, 200, 250, 500, 750, 1000, 2000, 3000, 4000, 5000, or 10000 silicon pillars. In the context of the invention, the silicon pillar (3) can be manufactured in various geometric shapes that are compatible with the object of the present invention of dissipating heat.Thus, in particular embodiments of the present invention, the silicon pillar (3) may have any of the shapes resulting from the manufacture of said pillars (i.e., the shapes resulting from the wet or dry etching of crystalline silicon), regardless of the crystalline orientation of the silicon wafer. These shapes may include, but are not limited to, a cube shape, a cuboid shape, a triangular prism shape, a rectangular prism shape, a pentagonal prism shape, a cylinder shape, a truncated cone shape, or a truncated pyramid shape. In some embodiments, all of the silicon pillars of the device of the invention have the same geometric shape. In other embodiments, the silicon pillars of the device may combine several different geometric shapes. Advantageously, the at least one silicon pillar (3) of the present invention has two bases, an upper base and a lower base.The upper base is in contact with the active zone (e.g. III-V semiconductor), while the lower base is in contact with the silicon surface (2). In the present invention, the silicon surface (2) and the at least one silicon pillar (3) form, without interruption, a single unique piece. That is, the silicon surface (2) and the at least one silicon pillar (3) are obtained by manufacturing a single common substrate, such that there is no joining interface between the lower base and the silicon surface (2) as such, but rather both structural elements form a single piece. That is, as a result of manufacturing the silicon pillar (3) on the same substrate as the silicon surface (2), the at least one silicon pillar (3) forms a body integral with the silicon surface (2).

[0017] In the context of the invention, the term “waveguide,” in particular an optical waveguide, refers to a physical structure that enables the conduction of electromagnetic waves in the optical spectrum. Generally speaking, optical waveguides can be an optical fiber, transparent dielectric waveguides made of plastic and / or glass, and liquid waveguides. In the context of photonic integrated circuits, optical waveguides are used as components to enable light transmission in optical communication systems on a local or long-distance scale. Optical waveguides can be classified according to their geometry (planar, strip, or fiber waveguides), mode structure (single-mode, multi-mode), refractive index distribution (pass index or gradient), and material (glass, polymer, semiconductor). In relation to the present invention, the waveguide (5) is integrated into the device (i.e., in the hybrid photonic integrated circuit (1)), such that it is embedded in the silicon oxide layer (4), and can optionally be made of silicon and / or silicon nitride. Silicon oxide (SIO2) is used in the context of the present invention due to its properties as a dielectric, where SIO2 is an electrical insulator and a poor thermal conductor. Silicon oxide is also used to optically isolate the waveguides integrated in the optical device of the present invention. In this sense, the silicon oxide encapsulates the waveguide core (silicon nitride or silicon). Since the refractive index of silicon oxide (1.45 at a wavelength of 1.55 pm) is lower than that of the core (2.0 and 3.45 for silicon nitride and silicon respectively), light is guided by the combined structure due to the presence of this higher index material.In the present invention, the silicon oxide layer (4) comprises two faces, a first face and a second face. The silicon oxide layer (4) is traversed by at least one silicon pillar (3) between the first face and the second face. The first face is arranged on the silicon surface (2), while the second face is in contact with the II IV semiconductor. The silicon oxide layer (4) has one or more waveguides of the device of the invention embedded therein. Those skilled in the art can understand that there are methods well known in the state of the art for preparing an opening in the second face of the silicon oxide layer (4), such that a waveguide (5) can be arranged in said opening of the second face of the silicon oxide layer (4). In a particular embodiment of the invention, the waveguide (5) is made of silicon or silicon nitride. On the other hand, silicon nitride (ShN4, SiN. x, or SiN) is a ceramic material that has high hardness and resistance. In the field of microelectronics, silicon nitride is used for various purposes as a dielectric material, passivation layers, hard masks, as a waveguide (5) or as a combination of these. In the context of the present invention, the waveguide (5) (for example, the waveguide (5) made of silicon or silicon nitride) is not in direct contact with either the silicon surface (2) or the at least one silicon pillar (3). In the context of the invention, there must be a minimum effective distance between the waveguide (whether made of silicon nitride or silicon) and the silicon pillar, such that the light beam inside the waveguide does not have a tendency to go towards the silicon pillar. The person skilled in the art can determine at what minimum distance the waveguide (5) must be arranged with respect to the silicon pillar (3), such that the light transmission is not altered.To do this, the person skilled in the art can solve Maxwell's equations in the cross section. Generally, these equations are solved using numerical computational methods, such that the propagation modes in the waveguide (5) are determined. Specifically, the minimum distance of the waveguide (5) will be set taking as a criterion that the imaginary part of the effective propagation index of the modes is sufficiently small for a given application, being of the order of 10'. 18 In the case of ideal materials without losses, this value is considered zero (numerical floor of the calculation).

[0018] In the context of the present invention, a II / IV semiconductor is a material composed of one or more elements from column III (boron, gallium, aluminum, indium, etc.) and column V (arsenic, antimony, phosphorus, etc.) of Mendeleev's periodic table, which correspond to groups 13 and 15, respectively, in the modern periodic table.In particular embodiments, the III-V semiconductor is selected from the group consisting of aluminum antimonide, gallium antimonide, indium antimonide, aluminum arsenide, aluminum gallium arsenide, aluminum indium arsenide, boron arsenide, gallium arsenide, indium gallium arsenide, indium arsenide, phospho-antimonide gallium indium arsenide, phospho-antimonide indium arsenide, gallium phospho-arsenide, indium gallium phospho-arsenide, aluminum phosphide, aluminum gallium phosphide, aluminum gallium indium phosphide, boron phosphide, gallium phosphide, indium gallium phosphide, indium phosphide, aluminum nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum indium nitride, boron nitride, nitride of gallium, gallium indium nitride, indium nitride, and combinations thereof.In the context of the invention, the III-V semiconductor is arranged after the at least one silicon pillar (3) has been manufactured as a heat-dissipating structure, such that the III-V semiconductor is integrated in the hybrid photonic integrated circuit (1) as an intact layer in the sense that it is not penetrated by the at least one silicon pillar (3). In any case, subsequent modifications of the III-V semiconductor layer (6) are possible.In the context of the invention, the III-V semiconductor that is arranged may be comprised either of an III-V semiconductor that has been grown "in-situ" on the upper base of the at least one silicon pillar (3), the second face of the silicon oxide layer (4), and the waveguide (5), or of an III-V semiconductor that has been previously manufactured separately and that is subsequently arranged on the upper base of the at least one silicon pillar (3), the second face of the silicon oxide layer (4), and the waveguide (5)).

[0019] The present invention also contemplates hybrid systems comprising, instead of a III-V semiconductor, a chip that can be hybridized with a silicon dielectric technology, such that any chip that can be placed on top of a silicon dielectric technology (and that generates heat) could take advantage of this invention of silicon pillars as heat dissipation and thermal barrier reduction structures between the device to be heated and the silicon wafer. In a second aspect, the invention relates to a method for manufacturing a hybrid photonic integrated circuit (1) according to claim 1, wherein the method comprises: i. providing a silicon surface (2) and optionally cleaning the silicon surface (2);

[0020] i. creating at least one silicon pillar (3) by wet or dry etching of the silicon surface (2); iii. creating a silicon oxide layer (4) by thermal oxidation, and polishing the silicon oxide layer (4) until obtaining a first confluence surface, where said first confluence surface comprises the upper base of the at least one silicon pillar (3) and the second upper face of the silicon oxide layer (4); iv. etching the silicon oxide layer (4) of the first confluence surface, such that an opening is generated on the second face of the silicon oxide layer (4); v. depositing a waveguide on the first confluence surface and polishing the waveguide until obtaining a second confluence surface, where said second confluence surface comprises the upper base of the at least one silicon pillar (3), the second face of the silicon oxide layer (4), and a surface of the waveguide (5); vi.arranging the III-V semiconductor layer (6) on the second confluence surface, such that the III-V semiconductor layer (6) is in contact with the upper base of the at least one silicon pillar (3), with the second face of the silicon oxide layer (4), and with the waveguide (5).

[0021] Step (i) of the method of the invention begins with the provision of a silicon surface (2), where the silicon surface (2) must be perfectly clean in order to carry out the microfabrication processes of the invention. For this reason, it may be necessary to carry out the method of the present invention in a clean room (also called a clean room). Optionally, the method provides a step for cleaning the silicon surface (2) through methods well known in the state of the art. In one embodiment of the invention, the optional step of cleaning the silicon surface (2) is carried out by wet etching or dry etching, isotropically or anisotropically. In one embodiment of the invention, the optional step of cleaning the silicon surface (2) is carried out by RCA cleaning.As used in the context of the present invention, etching, also known by its English terminology, can be performed in various ways, varying the direction of application and the nature of the etching agents used. Depending on the direction of application, etching can be isotropic or anisotropic, and depending on the nature of the agents used, it can be dry or wet etching. Depending on the etching carried out, the procedure to be followed is one or the other, and the morphology of the surface where the etching is applied will depend on it. Isotropic etching removes material uniformly in all directions; therefore, this etching generally produces smooth surfaces. However, anisotropic etching removes material along specific crystallographic planes, thus producing specific profiles such as sharp corners or edges and surfaces that exhibit roughness due to crystallographic exposure.Wet etching, also known as chemical or liquid etching, involves the removal of material through the use of chemical substances. Materials not protected by the masks deposited after a prior lithography step will be removed by the chemical substances. In particular embodiments of the invention, the chemical substances used to remove the material consist of solutions of potassium hydroxide and / or tetramethylammonium hydroxide. This type of etching involves chemical reactions where the chemical substance diffuses into the material to be removed, causing the two to react with each other, resulting in the diffusion of the reaction byproducts from the reacted surface. In contrast, in dry etching, the material is removed using plasma or gaseous agents.In all of them, a reaction occurs, which takes place through the use of kinetic energy from particle beams, chemical reactions, or a combination of both. Physical etching requires high-energy beams (ions, electrons, or photons) to remove atoms from the surface. Chemical etching, also known as vapor etching, does not use chemicals; in this case, gases are used to attack the surface. Among the etching methods that combine physical and chemical phenomena, reactive ion etching (RIE) stands out. By combining both phenomena, higher resolution is achieved and the time required is shorter compared to other types of etching. The reactive ion etching (RIE) technique can be implemented in conjunction with the inductively coupled plasma (ICP) technique. In the field of the invention, ICP-RIE refers to the etching process that uses an inductively coupled plasma source.With this process, materials are etched using a chemically reactive plasma under low-pressure conditions, combined with ion-induced etching. In one embodiment, the etching in step (ii.b) of the method of the invention is isotropic etching or anisotropic etching. In one embodiment, the etching in step (ii.c) is isotropic etching. In the latter case, those skilled in the art know that, in certain experimental situations, isotropic etching by wet etching can be essentially anisotropic on substrates such as silicon, since some chemicals (e.g., KOH) attack in a different way depending on the crystal direction. In one embodiment, the etching in step (ii.c) is anisotropic etching. In one embodiment, the etching in step (iv) of the method of the invention is dry plasma etching using the ICP-RIE technique.

[0022] In the context of the invention, "lithography" or "photolithography" refers to a process commonly used in the manufacture of semiconductor devices or integrated circuits, in which a design pattern is transferred directly or via a mask (or photomask) to a surface. The mask can be prepared in a variety of materials, such as rigid metal masks, printed transparent acetate films, etc. Photomasks can also be printed directly onto the surface to be treated, if the coating material needs to have special properties. In these cases, the pattern of a primary photomask can be transferred to a layer of photoresist material (positive or negative) to produce a secondary mask.This secondary mask of photoresist material can be used to etch the pattern into the underlying material, which can then be used as a protective mask in a final etching step of the layer of material of interest. This would be the case, for example, of transferring the pattern from the initial mask to a silicon nitride mask to etch a silicon surface (2). In the context of the invention, “etching” refers to the process used to remove certain layers of material from a surface during device manufacturing. Lithography techniques are well known to those skilled in the art for putting this aspect of the invention into practice (Sharma E, et al., Evolution in Lithography Techniques: Microlithography to Nanolithography, Nanomaterials (Basel), 2022 Aug 11;12(16):2754).

[0023] In the context of the invention, the term “thermal oxidation” refers to a process commonly used in microfabrication to obtain an oxide layer in the device design. Thus, in the context of the invention, “thermal oxidation” refers to the treatment by which silicon oxide is grown at the expense of the silicon surface (2). Thermal oxidation can be wet or dry, where wet oxidation is carried out in the presence of water vapor at a temperature of 800-1200°C, while dry oxidation is carried out with pure oxygen at a temperature of about 1200°C. In the case of silicon, wet oxidation and dry oxidation are carried out respectively according to equations (1) and (2):

[0024] (1) Si + 2H2O S¡02+ 2H2

[0025] (2) If + O2— > S¡02

[0026] In one embodiment, the thermal oxidation of step (iii) of the method of the invention is wet oxidation or dry oxidation. In embodiments of the invention, the oxidation of step (iii) of the method of the invention is wet oxidation (i.e., in the presence of water vapor), wherein the wet oxidation is carried out at a temperature of between 800-1200°C. In particular embodiments, the wet oxidation is carried out at 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, or 1200°C. In embodiments of the invention, the wet oxidation is carried out for at least 1, 2, 3, 4, 5, 8, 10, 12, or 15 hours. In a particular embodiment, the wet oxidation is carried out at 1100°C for at least 12 hours.

[0027] In the context of the invention, the term “depositing” or “deposition” refers to a step of coating a substrate with some type of material. Deposition may refer to spin coating capable of depositing a photoresist layer onto a substrate, such as a silicon wafer. In embodiments of the invention, the deposition step may be chemical vapor deposition (CVD). In particular embodiments, the deposition may be selected from the group consisting of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDP-CVD), subatmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), and combinations thereof.In particular embodiments of the invention, the deposition step may be a physical vapor deposition (PVD) step, such as sputtering. The choice of deposition method will be determined by the material to be deposited.

[0028] In the field of the invention, “chemical mechanical polishing” or “chemical mechanical planarization” refers to a surface smoothing process by the action of mechanical and chemical forces where chemical etching and abrasive polishing are carried out simultaneously. In one embodiment, the polishing of step (iii) and / or the polishing of step (v) of the method of the invention is chemical mechanical polishing. In one embodiment, step (ii) of the method of the invention comprises: (i) a) depositing a layer of silicon nitride on the silicon surface (2); (ii) b) etching the silicon nitride layer until a silicon nitride mask is created on the silicon surface (2); (ii) c) etching the silicon surface (2) that is not protected by the silicon nitride mask such that at least one silicon pillar (3) is formed on the silicon surface (2).

[0029] Thus, in one embodiment of the invention, the etching on the silicon surface (2) to form the silicon pillars is carried out through a hard mask of silicon nitride. In this step of the process, once the silicon surface (2) has been etched, the silicon nitride mask remains deposited on the upper base of the silicon pillars. For this reason, it is necessary that during the subsequent chemical mechanical polishing stage (part of stage (iii) in the method of the invention) said hard mask of silicon nitride deposited on the upper base of the silicon pillars be completely removed.

[0030] All of the terms and embodiments described above are applicable to any aspect and embodiment of the invention. In accordance with the present invention, the singular term "the," "a," "one," "an," equally refers to its plural counterpart, "the," "the," "some," "somes," unless it is clear from the context that the term clearly refers to a species in the singular. The term "comprises" or "comprising," as used herein, also describes "consists of" or "consisting of" in accordance with generally accepted patent practice.

[0031] EXAMPLES

[0032] The following invention is described by means of the following examples, which should be interpreted as merely illustrative and not limiting the scope of the invention.

[0033] Example 1: Process for preparing a hybrid photonic integrated circuit with heat sink

[0034] The inventors have designed a process for preparing a hybrid photonic integrated circuit, where the circuit features silicon pillars that act as a heat sink structure. In this process, the pillars are essentially created by a combination of wet silicon etching, followed by thermal oxidation and chemical mechanical polishing. The process has the steps shown in Figure 1, which are compared with the typical steps for preparing a hybrid photonic integrated circuit that does not include a heat sink.

[0035] Thus, panel (a) of Figure 1 shows a preparation procedure of a hybrid photonic integrated circuit that does not include a heat sink, where the steps are:

[0036] #1 . Cleaning the silicon surface.

[0037] #2. Wet oxidation of the silicon surface to obtain a surface layer of silicon oxide.

[0038] #3. Deposition of a silicon nitride layer by low-pressure chemical vapor deposition (LPCVD).

[0039] #4. Lithography of a mask with the circuit of interest for a waveguide, followed by dry etching of the silicon nitride surface using inductively coupled plasma, reactive-ion etching (ICP-RIE).

[0040] #5. Deposition of a silicon oxide layer by plasma-enhanced chemical vapor deposition (PECVD), followed by chemical mechanical polishing.

[0041] #6. Arrangement of a III-V semiconductor layer.

[0042] On the other hand, panel (b) of Figure 1 shows a preparation procedure of a hybrid photonic integrated circuit with heat sink, where the steps are:

[0043] #1 . Cleaning the silicon surface.

[0044] #2. Lithography of a mask with the two-dimensional surface design of the structure that will function as a heat sink (i.e., silicon pillars), followed by wet etching of the silicon surface in the parts not protected by the mask to produce said three-dimensional structure.

[0045] #3. Wet oxidation of the silicon surface to obtain a surface layer of silicon oxide, followed by chemical mechanical polishing until a silicon surface (corresponding to the silicon pillars) and a silicon oxide surface are exposed.

[0046] #4. Lithography of a mask with the circuit of interest for a waveguide, followed by dry etching of the silicon oxide surface using inductively coupled plasma, reactive-ion etching (ICP-RIE).

[0047] #5. Deposition of a silicon nitride layer by low-pressure chemical vapor deposition (LPCVD), followed by chemical mechanical polishing to reveal a silicon surface (corresponding to the silicon pillars), a silicon oxide surface, and a silicon nitride surface (corresponding to a silicon nitride waveguide).

[0048] #6. Arrangement of a III-V semiconductor layer.

[0049] Heat conduction in a cross-section of the hybrid photonic integrated circuit resulting from each of the procedures is shown in panel (c) of Figure 1, where in both cases a heat source is placed on the top surface (of the III-V semiconductor layer). It can be seen that the heat in the circuit cross-section resulting from the procedure (Figure 1 (c), left) is directly transmitted to the dielectric materials of silicon technology (i.e., silicon oxide and silicon nitride) which have relatively low thermal conductivity, while the heat in the circuit cross-section resulting from the procedure (Figure 1 (c), right) follows a heat flow through a path through the silicon pillars, which have comparatively higher thermal conductivity.

[0050] 1.1 Process simulation

[0051] The feasibility of the manufacturing process was simulated using one of the best semiconductor process simulation tools on the market (Sentaurus Process, by Synopsys). The flow simulation results are shown in Figures 2(ac).

[0052] #1 . Cleaning the silicon surface.

[0053] #2a. Deposition of a layer of silicon nitride.

[0054] #2b. Lithography on the silicon nitride layer of a mask with the two-dimensional surface design of the structure that will function as a heat sink (i.e., silicon pillars), followed by etching (isotropic or anisotropic) of the silicon nitride layer in the parts not protected by the mask, thus producing a silicon nitride mask. #2c. Wet (anisotropic) etching of the silicon surface in the parts not protected by the silicon nitride mask to produce the three-dimensional silicon pillar structure.

[0055] #3a. Wet thermal oxidation of the silicon surface to obtain a surface layer of silicon oxide, at a temperature of 1100°C for 20 minutes in the presence of water vapor.

[0056] #3b. Chemical mechanical polishing until a silicon surface (corresponding to the silicon pillars) and a silicon oxide surface are exposed.

[0057] #4. Lithography of a mask with the circuit of interest for a waveguide, followed by dry etching of the silicon oxide surface using inductively coupled plasma, reactive-ion etching (ICP-RIE).

[0058] #5. Deposition of a silicon nitride layer by low-pressure chemical vapor deposition (LPCVD), followed by chemical mechanical polishing to reveal a silicon surface (corresponding to the silicon pillars), a silicon oxide surface, and a silicon nitride surface (corresponding to a silicon nitride waveguide).

[0059] #6. Arrangement of a III-V semiconductor layer.

[0060] As seen in the step descriptions in Figures 2(ac), the creation of the silicon pillars occurs through a combination of steps 2 and 3. It should be noted that silicon dioxide grows on both sides of the initial silicon interface as silicon oxidizes. Thus, the oxide grows to a certain thickness depending on the oxidation time, where the newly created oxide is 46% below the position of the original silicon surface and 54% above it. The silicon nitride masking in step 2c prevents the created silicon pillar from oxidizing from the top. This can be observed in step 3a, where the silicon dioxide grows at the expense of the silicon both vertically and within the pillar; and the reduced lateral dimension of the pillar can be appreciated compared to steps 2c and 3a.

[0061] 1.2 Experimental verification

[0062] Likewise, to evaluate the manufacturing process, silicon pillars are formed in the laboratory according to the designed procedure. This allows the feasibility of the process to be verified by obtaining a result comparable to the simulations performed with the Sentaurus Process software.

[0063] Figure 3 shows micrographs obtained using a scanning electron microscope (SEM) during the preparation process of a hybrid photonic integrated circuit with a heat sink according to the invention. Specifically, these micrographs show the microscopic results obtained after combining steps 2c and 3a of the process flow shown in Figure 1(b).

[0064] Similarly, Figure 4 shows the micrographs obtained by scanning electron microscopy (SEM) during the process of forming the silicon pillars in a hybrid photonic integrated circuit with a heat sink according to the invention. Specifically, these micrographs show the result obtained at the microscopic level after carrying out the combination of steps #2b, #2c and #3a of the process flow in Figure 2(a)-2(b):

[0065] (a) Formation of the silicon nitride (SiN) oxidation mask: A silicon nitride oxidation mask is created to prevent the underlying silicon from oxidizing. The mask is created by lithography, followed by dry etching using ICP-RIE. The mask-protected regions correspond to the intended positions of the silicon pillars.

[0066] (b) Anisotropic etching in potassium hydroxide (KOH): Anisotropic etching in potassium hydroxide initiates the formation of silicon pillars. The etching depth is controlled to achieve 54% of the desired final pillar thickness. This step produces trapezoidal profiles, which are characteristic of silicon substrates. <100> .

[0067] (c) Wet oxidation for silicon oxide layer growth (S¡O2): The silicon oxide layer grows by wet oxidation. During this process, the silicon nitride mask effectively protects the underlying silicon from oxidizing agents, allowing precise control of the oxidation process.

[0068] (d)-(f) . Oxidation progression: As oxidation progresses, the silicon oxide layer extends to the top of the silicon pillars, defining their final dimensions and shape. This stage ensures the complete formation of the pillars fully embedded in silicon oxide.

[0069] Figure 5 shows a scanning electron microscope (SEM) micrograph that provides greater detail of a single silicon pillar (area under the dashed curve) resulting from step 3a of the process flow in Figure 2(b). This micrograph demonstrates the feasibility of the process by providing results comparable to those obtained from simulations performed with Synopsys' Sentaurus Process software.

[0070] DESCRIPTION OF THE FIGURES

[0071] Figure 1: (a) Process flow for preparing a commonly used waveguide platform without heat sink structures, (b) Process flow for preparing a silicon pillar waveguide platform, (c) Final cross-section of both technologies, with a heat source at the top, indicating preferred heat flow paths.

[0072] Figure 2: (a) Detailed explanation from stage #1 to stage #2b in the process flow of Figure 1(b). (b) Detailed explanation from stage #2c to stage #3b in the process flow of Figure 1(b). (c) Detailed explanation from stage #4 to stage #5b in the process flow of Figure 1(b).

[0073] Figure 3: Cross sections illustrating the circuit preparation procedure, from stage #2 to #3 in the process flow of Figure 1 (b).

[0074] Figure 4: Cross sections illustrating the circuit preparation procedure, from step #2b to #3a of the process flow in Figure 2(a)-2(b).

[0075] Figure 5: Cross section illustrating a silicon pillar obtained after carrying out step #3a of the process flow in Figure 2(b).

[0076] NUMERICAL REFERENCES USED IN THE FIGURES

[0077] In order to assist in a better understanding of the technical characteristics of the invention, the aforementioned figures are accompanied by a series of numerical references where, for illustrative and non-limiting purposes, the following is represented:

Claims

CLAIMS 1. A hybrid photonic integrated circuit (1) comprising: a) a silicon technology photonic functional layer comprising: - a silicon surface (2), where the silicon surface (2) comprises at least one silicon pillar (3), where the at least one silicon pillar (3) has two bases, a lower base and an upper base, where the lower base is arranged on the silicon surface (2), and where the silicon surface (2) and the at least one silicon pillar (3) form, without interruption, a single piece; - a layer of silicon oxide (4), where the layer of silicon oxide (4) comprises two faces, a first face and a second face, where the first face is arranged on the silicon surface (2), and where the layer of silicon oxide (4) is crossed by at least one silicon pillar (3) between the first face and the second face; - optionally, a waveguide (5), wherein the waveguide (5) is comprised in the silicon oxide layer (4), and wherein the waveguide (5) is not in direct contact with either the silicon surface (2) or the at least one silicon pillar (3); and b) a layer of a III-V semiconductor (6) or a chip hybridizable with a silicon dielectric technology, wherein the III-V semiconductor layer (6) or the chip hybridizable with a silicon dielectric technology is in contact with the upper base of the at least one silicon pillar (3), with the second face of the silicon oxide layer (4), and optionally with the waveguide (5), and wherein the III-V semiconductor layer (6) or the chip hybridizable with a silicon dielectric technology is not traversed by the at least one silicon pillar (3), where the at least one silicon pillar (3) functions as a heat sink.

2. A hybrid photonic integrated circuit (1) according to claim 1, wherein the hybrid photonic integrated circuit (1) comprises a waveguide (5), and wherein the waveguide (5) is a silicon or silicon nitride waveguide (5).

3. A method for manufacturing a hybrid photonic integrated circuit (1) according to any one of claims 1 or 2, wherein the method comprises: i. providing a silicon surface (2) and, optionally, cleaning the silicon surface (2); i. creating at least one silicon pillar (3) by wet or dry etching of the silicon surface (2); iii. creating a silicon oxide layer (4) by thermal oxidation, and polishing the silicon oxide layer (4) until obtaining a first confluence surface, where said first confluence surface comprises the upper base of the at least one silicon pillar (3) and the second upper face of the silicon oxide layer (4); iv. etching the silicon oxide layer (4) of the first confluence surface, such that an opening is generated on the second face of the silicon oxide layer (4); v. depositing a waveguide on the first confluence surface and polishing the waveguide until obtaining a second confluence surface, where said second confluence surface comprises the upper base of the at least one silicon pillar (3), the second face of the silicon oxide layer (4), and a surface of the waveguide (5); vi.arranging the III-V semiconductor layer (6) on the second confluence surface, such that the III-V semiconductor layer (6) is in contact with the upper base of the at least one silicon pillar (3), with the second face of the silicon oxide layer (4), and with the waveguide (5).

4. The method according to claim 3, wherein step (i) comprises: i. a) depositing a layer of silicon nitride on the silicon surface (2); ii. b) etching the silicon nitride layer to create a silicon nitride mask on the silicon surface (2); ii. c) etching the silicon surface (2) that is not protected by the silicon nitride mask such that the at least one silicon pillar (3) is formed on the silicon surface (2).

5. The method according to claim 4, wherein the etching of step (ii.b) is isotropic etching or anisotropic etching and / or wherein the etching of step (ii.c) is isotropic etching or anisotropic etching.

6. The method according to any one of claims 3 to 5 wherein the etching of step (iv) is dry plasma etching using the ICP-RIE technique.

7. The method according to any one of claims 3 to 6, wherein the thermal oxidation of step (iii) is wet oxidation or dry oxidation.

8. The method according to claim 6, wherein the oxidation of step (iii) is wet oxidation and wherein the wet oxidation is carried out in the presence of steam at 1100°C for at least 12 hours.

9. The method according to any one of claims 3 to 8, wherein the polishing of step (iii) and / or step (v) is chemical mechanical polishing.

Images