Semiconductor device and storage device

Abstract

Provided is a semiconductor device that can be miniaturized and highly integrated. The semiconductor device has an insulating layer having an opening, a first transistor, and a second transistor. The first transistor has a first oxide semiconductor layer including a channel formation region, and the second transistor has a second oxide semiconductor layer including a channel formation region. The first oxide semiconductor layer and the second oxide semiconductor layer are provided apart from each other in a first opening. In plan view, the opening is circular. In plan view, each portion of the first and second oxide semiconductor layers that is located in the opening are arc-shaped.

Description

Semiconductor device, memory device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, or memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including first and second oxide semiconductor layers, first to fourth insulating layers, and first to fifth conductive layers. The first conductive layer and the second conductive layer are provided over the first insulating layer to be spaced apart from each other. The second insulating layer is located over the first conductive layer and the second conductive layer. The third conductive layer is located over the second insulating layer. The third insulating layer is located over the second insulating layer and the third conductive layer. The fourth conductive layer and the fifth conductive layer are provided over the third insulating layer to be spaced apart from each other. The third insulating layer, the third conductive layer, and the second insulating layer have a first opening. The first opening has a portion overlapping with the first conductive layer, a portion overlapping with the second conductive layer, and a portion overlapping with the first insulating layer located between the first conductive layer and the second conductive layer. The fourth insulating layer covers a side surface of the first opening. The first oxide semiconductor layer has a region facing the third conductive layer with the fourth insulating layer sandwiched therebetween in the first opening, a region in contact with the first conductive layer in the first opening, and a region in contact with the fourth conductive layer outside the first opening. The second oxide semiconductor layer has a region facing the third conductive layer with the fourth insulating layer sandwiched therebetween in the first opening, a region in contact with the second conductive layer in the first opening, and a region in contact with the fifth conductive layer outside the first opening.

[0014] In the above semiconductor device, it is preferable that the fourth insulating layer in the first opening has a circular shape in a planar view, and that the first oxide semiconductor layer and the second oxide semiconductor layer in the first opening each have an arc shape in a planar view.

[0015] In the above semiconductor device, it is preferable that the first conductive layer has a recess overlapping the first opening, the fourth insulating layer be in contact with a side surface of the recess, and the first oxide semiconductor layer be in contact with at least a portion of a bottom surface of the recess.

[0016] In the above semiconductor device, it is preferable that the first conductive layer has a first layer and a second layer on the first layer, and the second layer has a recess.

[0017] In the above semiconductor device, it is preferable that the fourth insulating layer contacts a part of the side surface of the fourth conductive layer facing the first opening, and the first oxide semiconductor layer contacts another part of the side surface of the fourth conductive layer facing the first opening.

[0018] In the above semiconductor device, it is preferable that the fourth insulating layer contacts a part of the side surface of the first conductive layer facing the first opening, and the first oxide semiconductor layer contacts another part of the side surface of the first conductive layer facing the first opening.

[0019] In the above semiconductor device, the first oxide semiconductor layer is preferably in contact with the first insulating layer in the first opening.

[0020] In the semiconductor device, an outer edge of the first opening of the first oxide semiconductor layer is preferably located closer to the first opening than an outer edge of the first opening of the fourth conductive layer.

[0021] The semiconductor device preferably includes a fifth insulating layer and a sixth conductive layer, wherein the fifth insulating layer is located on the first oxide semiconductor layer and the second semiconductor layer, and the sixth conductive layer has, in the first opening, a region facing the third conductive layer with the fourth insulating layer, the first oxide semiconductor layer, and the fifth insulating layer sandwiched therebetween, and a region facing the third conductive layer with the fourth insulating layer, the second oxide semiconductor layer, and the fifth insulating layer sandwiched therebetween.

[0022] In the above semiconductor device, it is preferable that the bottom surface of the portion of the sixth conductive layer located between the first conductive layer and the second conductive layer is located closer to the first insulating layer than the top surface of the portion of the first conductive layer that does not overlap with the first opening.

[0023] The semiconductor device preferably includes a sixth insulating layer and a seventh conductive layer, wherein the sixth insulating layer is located on the fifth insulating layer and has a second opening at a position overlapping the first opening, the sixth conductive layer has a region located within the second opening, and the seventh conductive layer is located on the sixth insulating layer and has a region in contact with the sixth conductive layer.

[0024] One embodiment of the present invention is a memory device including the semiconductor device and a capacitor, wherein one of a pair of electrodes of the capacitor is electrically connected to the first conductive layer.

[0025] One embodiment of the present invention is a memory device including the semiconductor device and a capacitor, wherein the other of the pair of electrodes of the capacitor is electrically connected to a fourth conductive layer.

[0026] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or memory device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views showing an example of a semiconductor device. FIG. 1E is a schematic perspective view showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing an example of a semiconductor device. FIG. 6 is a cross-sectional view showing an example of a semiconductor device. FIG. 7 is a cross-sectional view showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B and 16C are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 17B and 17C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 20B and 20C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 21A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 21B and 21C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 22A is a plan view showing an example of a manufacturing method of a semiconductor device. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device, and Fig. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device.23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a semiconductor device. FIGS. 28B to 28D are cross-sectional views illustrating an example of a semiconductor device. FIG. 29A is a plan view illustrating an example of a semiconductor device. FIGS. 29B to 29D are cross-sectional views illustrating an example of a semiconductor device. FIG. 30 is a band diagram of an oxide semiconductor layer. FIGS. 31A and 31B are plan views illustrating an example of a memory device. FIG. 31C is a cross-sectional view showing an example of a memory device. FIG. 31D is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 32 is a schematic perspective view showing an example of a memory device. FIGS. 33A and 33B are cross-sectional views showing an example of a memory device. FIGS. 34A to 34C are plan views showing an example of a memory device. FIGS. 35A and 35B are plan layouts showing an example of a memory device. FIGS. 36A and 36B are plan layouts showing an example of a memory device. FIG. 37A is a cross-sectional view showing an example of a memory device. FIG. 37B is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 38 is a cross-sectional view showing an example of a memory device. FIG. 39 is a cross-sectional view showing an example of a memory device. FIG. 40 is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 41A to 41F are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 42A and 42B are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 43 is a block diagram illustrating a CPU. FIGS. 44A and 44B are perspective views of a semiconductor device. FIGS. 45A and 45B are perspective views of a semiconductor device. FIG. 46 is a conceptual diagram illustrating the hierarchy of a storage device.47A and 47B are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 47C is a diagram illustrating an example of an electronic component using a semiconductor device according to one embodiment of the present invention. FIG. 48 is a diagram illustrating an example of an electronic component. FIGS. 49A to 49C are diagrams illustrating an example of a mainframe computer. FIG. 49D is a diagram illustrating an example of space equipment. FIG. 49E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 50A to 50F are diagrams illustrating an example of electronic equipment. FIGS. 51A to 51G are diagrams illustrating an example of electronic equipment. FIGS. 52A to 52F are diagrams illustrating an example of electronic equipment.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0036] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0037] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0038] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0039] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0040] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as AＸ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0041] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0042] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0043] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0044] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0045] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0046] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0047] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0048] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0049] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0050] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0051] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0052] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0053] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1A to 29D.

[0054] A semiconductor device according to one embodiment of the present invention includes a first insulating layer having a first opening, a first transistor, and a second transistor. The first transistor includes a first oxide semiconductor layer including a channel formation region, and the second transistor includes a second oxide semiconductor layer including a channel formation region. The first oxide semiconductor layer and the second oxide semiconductor layer are spaced apart from each other through the first opening. Such a structure enables miniaturization or high integration of the semiconductor device.

[0055] The first transistor and the second transistor each include a first conductive layer and a second insulating layer. The first conductive layer is located over the first insulating layer and has a second opening that overlaps with the first opening. In the second opening, the first oxide semiconductor layer faces the first conductive layer with the second insulating layer interposed therebetween, and the second oxide semiconductor layer has a region that faces the first conductive layer with the second insulating layer interposed therebetween. In this case, the first conductive layer functions as a gate electrode, and the second insulating layer functions as a gate insulating layer.

[0056] Note that the first opening is preferably circular in plan view. Furthermore, the portions of the first oxide semiconductor layer and the second oxide semiconductor layer located at the openings are preferably arc-shaped in plan view. With this structure, the distance between the first conductive layer and the first oxide semiconductor layer and the distance between the first conductive layer and the second oxide semiconductor layer are approximately uniform, so that a gate electric field can be applied to the first oxide semiconductor layer and the second oxide semiconductor layer approximately uniformly. Therefore, the electrical characteristics of the first transistor and the second transistor can be improved.

[0057] The first transistor and the second transistor each include a second conductive layer and a third conductive layer, the second conductive layer and the third conductive layer being located at different heights, one of the second conductive layer and the third conductive layer functioning as a source electrode and the other of the second conductive layer and the third conductive layer functioning as a drain electrode.

[0058] In the transistor of one embodiment of the present invention, the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0059] In the transistor of one embodiment of the present invention, a source electrode, an oxide semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0060] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of the first insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0061] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, the memory device can be highly integrated and has low power consumption.

[0062] <Structural Example 1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 16C.

[0063] FIG. 1A is a plan view of a semiconductor device having two transistors. FIG. 1B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 1A. FIG. 1D is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 1B. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.

[0064] 1A to 1D includes an insulating layer 210 over a substrate (not shown), transistors 200a and 200b over the insulating layer 210, an insulating layer 280 over the insulating layer 210, and an insulating layer 281 over the insulating layer 280. The insulating layer 210, the insulating layer 280, and the insulating layer 281 function as interlayer films. Note that hereinafter, the transistors 200a and 200b may be collectively referred to as transistors 200.

[0065] [Transistor 200] The transistor 200a includes a conductive layer 220a over the insulating layer 210, a conductive layer 255 over the insulating layer 280, a conductive layer 240a over the insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230a over the conductive layer 220a and the conductive layer 240a, an insulating layer 250 over the oxide semiconductor layer 230a, and a conductive layer 260 over the insulating layer 250.

[0066] Similarly, the transistor 200b includes a conductive layer 220b over the insulating layer 210, a conductive layer 255 over the insulating layer 280, a conductive layer 240b over the insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230b over the conductive layer 220b and the conductive layer 240b, an insulating layer 250 over the oxide semiconductor layer 230b, and a conductive layer 260 over the insulating layer 250.

[0067] The transistors 200a and 200b have a linear symmetry with respect to the dashed-dotted line A3-A4. Therefore, the structure of the transistor 200b can be described by referring to the description of the structure of the transistor 200a, by replacing the transistor 200a, the conductive layer 220a, the conductive layer 240a, and the oxide semiconductor layer 230a with the transistor 200b, the conductive layer 220b, the conductive layer 240b, and the oxide semiconductor layer 230b, respectively, and by making appropriate necessary modifications. Hereinafter, the transistor 200a will be mainly described.

[0068] 1A to 1D. Specifically, FIG. 1E is a perspective schematic view of the semiconductor device shown in FIG. 1A, taken along dashed-dotted line B1-B2, and also includes a transistor 200a. The dashed-dotted line B1-B2 in FIG. 1A includes the side surface of the oxide semiconductor layer 230a located on the conductive layer 240a, on the dashed-dotted line A3-A4 side. Some components (such as an interlayer insulating layer) are omitted in FIG. 1E.

[0069] 1A to 1E, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in FIGS. 1A to 1D and 1E, the directions do not necessarily have to match.

[0070] In the transistor 200a, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 255 functions as a first gate electrode, the insulating layer 225 functions as a first gate insulating layer, the conductive layer 260 functions as a second gate electrode, the insulating layer 250 functions as a second gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and the drain electrode.

[0071] The conductive layer 255 is provided to extend in the X direction, and the conductive layer 260 is provided to extend in the Y direction. The region where the conductive layer 255 extends functions as a first gate wiring, and the region where the conductive layer 260 extends functions as a second gate wiring. The direction in which the conductive layer 260 extends may be parallel to the direction in which the conductive layer 255 extends. For example, the conductive layer 260 may be provided to extend in the X direction.

[0072] The conductive layer 220a and the conductive layer 220b are provided on the insulating layer 210 and spaced apart from each other. The conductive layer 220a and the conductive layer 220b are provided extending in the Y direction. The conductive layer 220a and the conductive layer 220b may be provided extending in the X direction or may be provided in an island shape.

[0073] The insulating layer 280 is located on the conductive layer 220a and the conductive layer 220b, and the insulating layer 281 is located on the conductive layer 255.

[0074] 1A to 1D, the insulating layer 280, the conductive layer 255, and the insulating layer 281 have openings 290 that reach the conductive layers 220a, 220b, and the insulating layer 210. The openings 290 have a portion that overlaps with the conductive layer 220a, a portion that overlaps with the conductive layer 220b, and a portion that overlaps with the insulating layer 210 located between the conductive layers 220a and 220b.

[0075] The opening 290 includes an opening in the insulating layer 280, an opening in the conductive layer 255, and an opening in the insulating layer 281. The shape and size of the opening 290 in a plan view may differ depending on the layer. When the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric. In this specification and the like, a circle is not limited to a perfect circle.

[0076] At least some of the components of the transistor 200a are disposed in the opening 290. Specifically, the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located in the opening 290. Furthermore, the portions of the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the conductive layer 260 that are disposed in the opening 290 are provided so as to reflect the shape of the opening 290.

[0077] The conductive layer 240a and the conductive layer 240b are provided spaced apart from each other on the insulating layer 281. The conductive layer 240a and the conductive layer 240b are provided extending in the Y direction. The conductive layer 240a and the conductive layer 240b may be provided extending in the X direction or may be provided in an island shape.

[0078] The conductive layer 240a has a cutout portion at a position overlapping the opening 290. In a plan view, the outline of the cutout portion matches or approximately matches a part of the outline of the opening 290. For example, in a plan view, if the opening 290 is circular, the cutout portion will be arc-shaped. The side surface of the opening 290 can be considered to include the side surface of the insulating layer 280, the side surface of the conductive layer 255, the side surface of the insulating layer 281, and the side surface of the conductive layer 240a.

[0079] When the conductive layers 240a and 240b do not have a cutout portion, for example, when the side surfaces of the conductive layers 240a and 240b facing each other are straight in a plan view and the conductive layers 240a and 240b do not overlap with the opening 290, the distance between the conductive layers 240a and 240b is at least the same as or longer than the width of the opening 290. On the other hand, when the conductive layers 240a and 240b each have a cutout portion, the distance between the conductive layers 240a and 240b, specifically, the shortest distance between the conductive layers 240a and 240b at a position where they do not overlap with the opening 290, can be made shorter than the width of the opening 290. Therefore, the distance between the conductive layers 240a and 240b can be shortened, and the integration degree of the semiconductor device can be increased.

[0080] The insulating layer 225 is provided along at least a portion of the side surface of the opening 290. In FIGS. 1B to 1D , the insulating layer 225 is provided so as to cover the side surface of the opening 290. Specifically, the insulating layer 225 has a region in contact with the side surface of the insulating layer 281, a region in contact with the side surface of the conductive layer 255, and a region in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 225 also has a region in contact with the side surface of the conductive layer 240a on the opening 290 side, and a region in contact with the side surface of the conductive layer 240b on the opening 290 side. The insulating layer 225 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0081] The insulating layer 225 has a region in contact with the side surface of the conductive layer 220a facing the opening 290 and a region in contact with the side surface of the conductive layer 220b facing the opening 290. The insulating layer 225 also has a region in contact with the insulating layer 210.

[0082] The oxide semiconductor layer 230a and the oxide semiconductor layer 230b are spaced apart from each other. As shown in FIG. 1D , the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290 are each formed in an arc shape in plan view.

[0083] The oxide semiconductor layer 230a is provided in the opening 290 so as to cover part of the insulating layer 225. The oxide semiconductor layer 230a has a region facing the conductive layer 255 in the opening 290 with the insulating layer 225 sandwiched therebetween. The oxide semiconductor layer 230a has a region in contact with the top surface of the conductive layer 220a in the opening 290 and a region in contact with the top surface of the conductive layer 240a outside the opening 290. The oxide semiconductor layer 230a also has a region in contact with part of a portion of the insulating layer 210 that overlaps with the opening 290.

[0084] Furthermore, outside the opening 290, the edge of the oxide semiconductor layer 230a is located more inward than the edge of the conductive layer 240a. Furthermore, the edge of the oxide semiconductor layer 230a on the outer side of the opening 290 is located closer to the opening 290 than the edge of the conductive layer 240a on the outer side of the opening 290. Furthermore, in a plan view, the outline of the oxide semiconductor layer 230a on the outer side of the opening 290 is located more inward than the outline of the conductive layer 240a on the outer side of the opening 290. In this case, the upper surface of the conductive layer 240a has a region in contact with the insulating layer 250 and a region in contact with the oxide semiconductor layer 230a.

[0085] The insulating layer 250 is provided to cover the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290. The insulating layer 250 is provided on the insulating layer 281 to cover the top surfaces and side surfaces of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the conductive layer 240a, and the conductive layer 240b. The insulating layer 250 has a region that is in contact with a part of the portion of the insulating layer 210 that overlaps with the opening 290. The insulating layer 250 has a recessed portion at a position that overlaps with the opening 290.

[0086] The conductive layer 260 is provided so as to fill at least a part of the recess of the insulating layer 250. The conductive layer 260 has, in the opening 290, a region facing the oxide semiconductor layer 230a with the insulating layer 250 sandwiched therebetween and a region facing the oxide semiconductor layer 230b with the insulating layer 250 sandwiched therebetween. The conductive layer 260 also has, in the opening 290, a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween and a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230b, and the insulating layer 250 sandwiched therebetween. The bottom surface of the portion of the conductive layer 260 located between the conductive layer 220a and the conductive layer 220b is located closer to the insulating layer 210 than the top surface of the portion of the conductive layer 220a that does not overlap with the opening 290.

[0087] As described above, the oxide semiconductor layer 230a is provided inside the opening 290. The transistor 200a has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220a) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240a) is located above, and thus current flows vertically. That is, a channel is formed along the side surface of the opening 290. That is, the transistor 200a is a vertical transistor.

[0088] The conductive layer 255 has a region facing the conductive layer 260 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween. A region of the oxide semiconductor layer 230a sandwiched between the conductive layer 255 and the conductive layer 260 and its vicinity functions as a channel formation region of the transistor 200a. One of a region of the oxide semiconductor layer 230a near the conductive layer 220a and a region of the oxide semiconductor layer 230a near the conductive layer 240a functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0089] With the above structure, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200a to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0090] Furthermore, the semiconductor device of this embodiment has a structure in which the channel formation regions of the transistor 200a and the transistor 200b are provided in one opening 290. With this structure, miniaturization or high integration of the semiconductor device can be achieved.

[0091] 1A to 1D includes a conductive layer 255 that functions as a first gate electrode and a conductive layer 260 that functions as a second gate electrode. The potential applied to the conductive layer 260 is changed independently of the potential applied to the conductive layer 255, and the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 260, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 260, the drain current when the potential applied to the conductive layer 255 is 0 V can be made smaller than when a negative potential is not applied. Note that the conductive layer 255 may function as a second gate electrode, and the conductive layer 260 may function as a first gate electrode.

[0092] Alternatively, the conductive layer 260 may be connected to the conductive layer 255. By connecting the conductive layer 255 and the conductive layer 260 and applying the same potential thereto, it is possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0093] As described above, the semiconductor device illustrated in FIGS. 1A to 1D has two gate electrodes (the first gate electrode and the second gate electrode), and therefore the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0094] The conductive layer 240a is preferably not located inside the opening 290. That is, the conductive layer 240a preferably does not have a region in contact with the side surface of the insulating layer 281 in the opening 290. With such a structure, the notch of the conductive layer 240a and the opening of the insulating layer 281 can be formed at the same time. Furthermore, when the side surface of the conductive layer 240a and the side surface of the insulating layer 281 are aligned or substantially aligned in the opening 290, the film thickness distribution of the insulating layer 225, the oxide semiconductor layer 230a, and the like provided inside the opening 290 can be made uniform. Furthermore, the insulating layer 225, the oxide semiconductor layer 230a, and the like can be prevented from being separated by a step or the like between the conductive layer 240a and the insulating layer 281.

[0095] Here, enlarged views of FIGS. 1B and 1D are shown in FIGS. 2A and 2B, respectively.

[0096] As shown in FIG. 2B , the side surface of the conductive layer 255 on the opening 290 side faces the side surface of the oxide semiconductor layer 230a with the insulating layer 225 interposed therebetween, and the side surface of the conductive layer 260 faces the side surface of the oxide semiconductor layer 230a with the insulating layer 250 interposed therebetween. That is, in a plan view, at least a part of the portion of the oxide semiconductor layer 230a located at the opening 290 becomes a channel formation region. In this case, for example, the channel width of the transistor 200a is determined by the periphery of the portion of the oxide semiconductor layer 230a located at the opening 290. That is, the channel width of the transistor 200a is determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view) and the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. In FIGS. 2A and 2B , the width D of the opening 290 is shown, and in FIG. 2B , the channel width W of the transistor 200a and the distance Hab between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are shown. The distance Hab can be measured on the XY plane including the conductive layer 255 .

[0097] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200a, for example, the area of ​​the transistor 200a in a plan view, is roughly determined by the width D of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200a, thereby enabling a semiconductor device to be highly integrated.

[0098] The width D of the opening 290 may vary in the depth direction (or in the Z direction when the side surfaces of the opening 290 are perpendicular to the substrate surface). Here, the shortest distance between the two side surfaces of the insulating layer 281 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the insulating layer 281 is used as the width D of the opening 290. The cross-sectional view here refers to a cross section passing through the center (or center of gravity) of the opening 290 as viewed from the Z direction, viewed from the X direction or the Y direction. Alternatively, the width D may be the width of the opening 290 at the highest position in the insulating layer 281, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average of these three widths. Here, an example is shown in which the width D is determined using the width of the opening 290 in the insulating layer 281, but the method for determining the width D is not particularly limited. For example, the width D may be the shortest distance between two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view, or the shortest distance between two side surfaces of the insulating layer 281 on the opening 290 side. Furthermore, for example, the width D may be the shortest distance between the side surface of the conductive layer 240a on the opening 290 side and the side surface of the conductive layer 240b on the opening 290 side in a cross-sectional view.

[0099] When the opening 290 is formed by photolithography, the width D of the opening 290 is set by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0100] The width D of the opening 290 is greater than the distance Hab. More specifically, the width D of the opening 290 is preferably greater than the sum of twice the film thickness of the insulating layer 225 and the distance Hab. This allows the oxide semiconductor layer 230a and the oxide semiconductor layer 230b to be provided within the opening 290. Here, the film thickness of the insulating layer 225 refers to the width of at least a portion of the insulating layer 225 in the A1-A2 direction. Furthermore, the width D of the opening 290 is more preferably greater than the sum of twice the film thickness of the insulating layer 225, twice the film thickness of the oxide semiconductor layer 230a, and the distance Hab. This prevents the film thickness of the oxide semiconductor layer 230a from becoming thin (reduced), thereby ensuring the area of ​​the channel formation region in a plan view. Here, the film thickness of the oxide semiconductor layer 230a refers to the width of at least a portion of the oxide semiconductor layer 230a located in the opening 290 in the A1-A2 direction.

[0101] Furthermore, it is preferable that the distance Hab is small. By reducing the distance Hab, the channel width W can be increased. Furthermore, miniaturization or high integration of the semiconductor device can be achieved. The distance Hab is, for example, preferably 10 nm or more and 60 nm or less, more preferably 10 nm or more and 50 nm or less, even more preferably 10 nm or more and 40 nm or less, and even more preferably 10 nm or more and 30 nm or less. Furthermore, the distance Hab is, for example, preferably 5 nm or more and 50 nm or less, more preferably 5 nm or more and 40 nm or less, and even more preferably 5 nm or more and 30 nm or less.

[0102] The channel length of the transistor 200a is the distance between the source region and the drain region. For example, when the conductive layer 255 functions as a first gate electrode, the channel length of the transistor 200a is the length of a region of the oxide semiconductor layer 230a facing the conductive layer 255 with the insulating layer 225 sandwiched therebetween, in a cross-sectional view. In other words, it can be said that the channel length of the transistor 200a is determined by the thickness of the conductive layer 255. When the conductive layer 260 and the conductive layer 255 are connected to each other, the channel length of the transistor 200a is the length of a region of the oxide semiconductor layer 230a sandwiched between the conductive layer 260 and the conductive layer 255, in a cross-sectional view. In other words, it can be said that the channel length of the transistor 200a is determined by the thickness of the conductive layer 255. In FIG. 2A , the channel length L of the transistor 200a is indicated by a dashed line with a double-headed arrow.

[0103] Furthermore, when the conductive layer 260 functions as a first gate electrode, it can be said that the channel length of the transistor 200a is determined by the thickness of the insulating layer 280, the thickness of the conductive layer 255, the thickness of the insulating layer 281, the thickness of the conductive layer 240a, and the like on the conductive layer 220a in a cross-sectional view.

[0104] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200a can be set by the thickness of the conductive layer 255 or the like. Therefore, the channel length of the transistor 200a can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200a, thereby improving its frequency characteristics.

[0105] Note that the channel length of the transistor 200a is determined by the film thickness of the conductive layer 255 and the like, and therefore does not affect the area occupied by the transistor 200a, for example, the area of ​​the transistor 200a in a plan view. By setting the channel length of the transistor 200a to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the opening 290 and the like.

[0106] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and 1 μm or less, 500 nm or less, or 300 nm or less.

[0107] The channel length L of the transistor 200a is preferably at least shorter than the channel width W of the transistor 200a. The channel length L of the transistor 200a is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200a. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0108] Note that the channel width W of the transistor 200a may be equal to or less than the channel length L of the transistor 200a. With such a structure, miniaturization or high integration of a semiconductor device can be achieved.

[0109] As described above, by forming the opening 290 to have a circular shape in a plan view, the insulating layer 225 at the opening 290 has a circular, annular, or annular shape in a plan view. Specifically, the insulating layer 225 has a cylindrical portion having an opening concentric with the opening 290. The oxide semiconductor layer 230a is provided in an arc shape. The insulating layer 250 and the conductive layer 260 are provided along the shapes of the insulating layer 225 and the oxide semiconductor layer 230a. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230a and the distance between the conductive layer 260 and the oxide semiconductor layer 230a become approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230a approximately uniformly.

[0110] In this embodiment, the opening 290 is circular in plan view, but the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0111] As shown in Figure 2B, the opening 290 is preferably circular in plan view. By making it circular, the processing accuracy when forming the opening can be improved, and an opening of a fine size can be formed. For example, as shown in Figures 3A and 3B, the opening 290 may be substantially rectangular with rounded corners in plan view. With this configuration, the channel width per unit area can be increased, and the on-current can be increased.

[0112] 1B shows an example in which the conductive layer 240a has a single-layer structure. Note that the conductive layer 240a can have a stacked structure of two or more layers. The conductive layer 240a shown in FIG. 2A has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 over the conductive layer 240a1.

[0113] 1B shows an example in which the conductive layer 220a has a single-layer structure. Note that the conductive layer 220a can have a stacked structure of two or more layers. The conductive layer 220a shown in FIG. 2A has a two-layer structure including a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1.

[0114] 1B illustrates a configuration in which the upper surface of the conductive layer 220a is flat. However, the present invention is not limited to this. For example, the conductive layer 220a may have a recess.

[0115] 4A has a recess at a position overlapping with the opening 290. When the conductive layer 220a has a two-layer structure of a conductive layer 220a1 and a conductive layer 220a2, the recess is provided in the conductive layer 220a2. In this case, the bottom surface of the recess corresponds to the bottom surface of the recess in the conductive layer 220a2, and the side surface of the recess corresponds to the side surface of the recess in the conductive layer 220a2. The bottom of the opening 290 can be considered to include the bottom surface of the recess in the conductive layer 220a2, and the side surface of the opening 290 can be considered to include the side surface of the recess in the conductive layer 220a2, the side surface of the insulating layer 280, the side surface of the conductive layer 255, and the side surface of the insulating layer 281.

[0116] By providing a recess in the position where the conductive layer 220a overlaps with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220a in contact with the insulating layer 280, with the top surface of the insulating layer 210 in the region overlapping with the conductive layer 220a as the reference, compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface where the transistor is to be formed. Here, the top surface of the insulating layer 210 in the region overlapping with the conductive layer 220a is used as the reference. The surface used as the reference is not limited to the surface where the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0117] When a recess is provided in the conductive layer 220a, a recess may be provided in the insulating layer 210 at a position overlapping the opening 290. In this case, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 within the opening 290 can each be made lower.

[0118] As shown in FIG. 4B , the conductive layer 220a2 preferably has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220a2, and then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220a2. Therefore, in FIG. 4B , the side surface of the second recess is aligned with the side surface of the insulating layer 280 at the opening 290, and the side surface of the first recess is aligned with the surface of the insulating layer 225 facing the oxide semiconductor layer 230a. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0119] 4B , the insulating layer 225 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220a, and also contacts the side surfaces of the insulating layer 280, the conductive layer 255, the insulating layer 281, and the conductive layer 240a within the opening 290. The oxide semiconductor layer 230a contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 220a and the side surfaces of the insulating layer 225 within the opening 290. The insulating layer 250 is located inside the oxide semiconductor layer 230a within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0120] The conductive layer 220a2 has the first recess and the second recess, so that the side surface of the conductive layer 220a2 contacts the oxide semiconductor layer 230a. This increases the contact area between the conductive layer 220a2 and the oxide semiconductor layer 230a, thereby reducing the contact resistance between the conductive layer 220a2 and the oxide semiconductor layer 230a. This prevents a decrease in the on-state current of the transistor 200a due to the contact resistance between the conductive layer 220a2 and the oxide semiconductor layer 230a.

[0121] Furthermore, since the conductive layer 260 is provided in the recess of the insulating layer 210, the height of the bottom surface of the conductive layer 260 can be reduced. Therefore, a gate electric field can be easily applied to the channel formation region of the oxide semiconductor layer 230a, and the electrical characteristics of the transistor 200a can be improved. Furthermore, a gate electric field can be easily applied to a region of the oxide semiconductor layer 230a in contact with the conductive layer 220a2, and the on-state current of the transistor 200a can be increased. Furthermore, whether the conductive layer 220a or the conductive layer 240a is used as the drain electrode, the electrical characteristics of the transistor 200a can be improved.

[0122] 4B illustrates an example in which the conductive layer 220a2 has a first recess and a second recess, but the present invention is not limited to this. For example, as shown in FIG. 5A, the conductive layer 220a2 may have only the second recess. In other words, the conductive layer 220a2 may not have a recess in the region overlapping with the insulating layer 225.

[0123] A recess may be formed in the conductive layer 220a2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The semiconductor device shown in Fig. 4B illustrates an example in which a recess is formed in the conductive layer 220a2 in both steps, whereas the semiconductor device shown in Fig. 5A illustrates an example in which a recess is not formed in the conductive layer 220a2 in the step of forming the opening 290, but is formed in the step of forming the insulating layer 225.

[0124] 5A , the insulating layer 225 is in contact with the side surfaces of the insulating layer 280, the conductive layer 255, the insulating layer 281, the conductive layer 240a, and the top surface of the conductive layer 220a2 within the opening 290. The oxide semiconductor layer 230a is in contact with the bottom and side surfaces of the recesses of the conductive layer 220a2 and the side surface of the insulating layer 225 within the opening 290.

[0125] When a recess is formed in the conductive layer 220a2 in the step of forming the insulating layer 225, the oxide semiconductor layer 230a can be in contact with the bottom and side surfaces of the recess in the conductive layer 220a2. This is preferable because it increases the contact area between the oxide semiconductor layer 230a and the conductive layer 220a2 and reduces the contact resistance between the oxide semiconductor layer 230a and the conductive layer 220a2.

[0126] Furthermore, for example, as shown in FIG. 5B, the transistor 200a may have a configuration in which the insulating layer 225 does not cover the side surfaces of the conductive layer 240a2.

[0127] 5B contacts the bottom and side surfaces of the recess of conductive layer 220a, and also contacts the side surfaces of insulating layer 280, conductive layer 255, insulating layer 281, and part of the side surfaces of conductive layer 240a1 within opening 290. Furthermore, insulating layer 225 does not contact the side surfaces of conductive layer 240a2 within opening 290. Note that insulating layer 225 may contact one or more of the side surfaces of conductive layer 240a1 and conductive layer 240a2 within opening 290, or may cover part or all of each side surface.

[0128] 5B, the channel length of the transistor 200a can be shortened, and thus a transistor with large on-state current can be realized.

[0129] When the side surface of the conductive layer 240a2 facing the opening 290 has a portion that is not covered with the insulating layer 225, that portion is in contact with the oxide semiconductor layer 230a. That is, the oxide semiconductor layer 230a is in contact with the side surface of the conductive layer 240a2 facing the opening 290. In other words, the oxide semiconductor layer 230a is in contact with another part of the side surface of the conductive layer 240a facing the opening 290. This increases the contact area between the oxide semiconductor layer 230a and the conductive layer 240a2, thereby reducing the contact resistance between the oxide semiconductor layer 230a and the conductive layer 240a. Similarly, when the insulating layer 225 does not cover the side surface of the conductive layer 240a2 and does not cover at least a portion of the side surface of the conductive layer 240a1, the portion that is not covered with the insulating layer 225 is in contact with the oxide semiconductor layer 230a. This makes it possible to increase the contact area between the oxide semiconductor layer 230a and the conductive layer 240a, and to reduce the contact resistance between the oxide semiconductor layer 230a and the conductive layer 240a.

[0130] 6, the recess of the conductive layer 220a2 preferably has a curved portion. When the recess has a curved portion, the portions of the oxide semiconductor layer 230a, the insulating layer 250, and the like provided on the recess near the recess may also have a curved portion. In other words, the portion may have a curved or concave surface in cross-sectional view. Furthermore, the portion may not have a corner (right angle or acute angle) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the breakdown voltage of the transistor 200a, and suppresses electrostatic breakdown of the transistor 200a. Therefore, the reliability of the semiconductor device can be improved.

[0131] <Constituent Materials of Semiconductor Device> Materials that can be used for the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. Note that hereinafter, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b may be collectively referred to as the oxide semiconductor layer 230. The conductive layer 220a and the conductive layer 220b may be collectively referred to as the conductive layer 220. The conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240.

[0132] [Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0133] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0134] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the oxide semiconductor layer 230, the transistor 200 can be referred to as an OS transistor.

[0135] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0136] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0137] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0138] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0139] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0140] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0141] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0142] In addition, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 5.

[0143] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 280, insulating layer 281, insulating layer 250, insulating layer 225, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0144] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0145] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0146] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0147] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0148] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0149] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0150] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0151] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0152] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Examples of metal oxides containing one or both of hafnium and zirconium include hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0153] As described later, a metal oxide containing one or both of hafnium and zirconium is also a material for an insulating layer that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0154] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0155] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0156] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0157] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0158] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide.

[0159] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0160] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0161] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0162] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0163] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0164] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0165] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0166] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0167] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0168] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0169] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0170] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0171] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 and can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0172] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0173] 2A shows an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0174] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0175] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0176] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0177] Note that the thickness of the insulating layer 280 on the conductive layer 220 a or 220 b affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately according to the design value of the channel length of the transistor 200 .

[0178] FIG. 2A shows an example in which the insulating layer 280 has a single-layer structure. Note that the insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 7, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220 and the conductive layer 255 and prevent high resistance.

[0179] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0180] The insulating layer 281 can be made of an insulating material that can be used for the insulating layer 280 .

[0181] FIG. 2A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 7, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can suppress oxidation of the conductive layer 255 and the conductive layer 240 and prevent high resistance.

[0182] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 281_1 and the insulating layer 281_3, and a silicon oxide film for the insulating layer 281_2. Note that each of the insulating layer 281_1 and the insulating layer 281_3 may have a stacked structure of two or more layers.

[0183] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0184] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0185] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0186] FIG. 2A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0187] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0188] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0189] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0190] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0191] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0192] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0193] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0194] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0195] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0196] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0197] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0198] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0199] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0200] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0201] Therefore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferably used.

[0202] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, which can prevent oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240a in the opening 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240a in the opening 290 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0203] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the side surface of the opening 290 and form an insulating layer 225 with a uniform thickness.

[0204] The insulating layer 225 may be made of the above-mentioned material that can have ferroelectricity.

[0205] 4A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, as shown in FIG. 8, the insulating layer 225 can have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.

[0206] 8 illustrates an example in which the insulating layer 225 has a two-layer structure including an insulating layer 225_1 in contact with the conductive layer 220, the insulating layer 280, the conductive layer 255, the insulating layer 281, and the conductive layer 240, and an insulating layer 225_2 located between the insulating layer 225_1 and the oxide semiconductor layer 230. The insulating layer 225 illustrated in FIG. 8 can be said to have a two-layer structure including the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0207] It is preferable that the insulating layer 225_1 provided in contact with the side surface of the insulating layer 280 in the opening 290 be a barrier insulating layer against hydrogen, and the insulating layer 225_2 provided in contact with the oxide semiconductor layer 230 be an insulating layer having a function of capturing or fixing hydrogen. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable that a silicon nitride film be used for the insulating layer 225_1, and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film be used for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of hafnium and aluminum, and oxygen.

[0208] Furthermore, the insulating layer 225_1 can be a barrier insulating layer against hydrogen, and the insulating layer 225_2 can be an insulating layer having a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable to use a silicon nitride film for the insulating layer 225_1 and a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of silicon and aluminum, and oxygen. In particular, when a silicon oxide film is used for the insulating layer 225_2, the insulating layer 225_2 contains silicon and oxygen.

[0209] Typically, a silicon nitride film and a silicon oxide film can be used as the insulating layer 225_1 and the insulating layer 225_2, respectively. The thicknesses of the insulating layer 225_1 and the insulating layer 225_2 are set to 2 nm and 2 nm, respectively.

[0210] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0211] Another example of the structure of the insulating layer 225 shown in FIG. 8 is shown in FIGS. 9A and 9B.

[0212] In the transistor 200a shown in Figure 9A, an example is shown in which the insulating layer 225_1 is provided in contact with a portion of the bottom surface and the side surface of the recess formed by the conductive layer 220a2, and the insulating layer 225_2 is located inside the insulating layer 225_1 in the opening 290 and is provided in contact with another portion of the bottom of the recess formed by the conductive layer 220a2.

[0213] In the transistor 200a shown in FIG. 9B , the conductive layer 220a2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220a2, and then when processing the insulating layer 225_1, the first recess is provided in the conductive layer 220a2. Therefore, in FIG. 9B , the side surface of the second recess and the side surface of the insulating layer 280 in the opening 290 coincide or nearly coincide with each other, and the side surface of the first recess and the surface of the insulating layer 225_1 facing the insulating layer 225_2 coincide or nearly coincide with each other.

[0214] In the transistor 200a shown in Figure 9B, the insulating layer 225_1 is provided in contact with the bottom and side surfaces of the second recess of the conductive layer 220a2, and the insulating layer 225_2 is provided in contact with the bottom and side surfaces of the first recess of the conductive layer 220a2.

[0215] 9A or 9B can be formed by providing the insulating layer 225_1 on the side surface of the opening 290 and then forming and processing an insulating film to be the insulating layer 225_2. Compared to the transistor 200a shown in FIG. 8, the region where the insulating layer 225_1 is in contact with the oxide semiconductor layer 230 is reduced, and a structure in which the insulating layer 225_2 is in contact with the oxide semiconductor layer 230 can be realized.

[0216] The insulating layer 225 can have a three-layer structure including a first insulating layer, a second insulating layer, and a third insulating layer. For example, it is preferable that one of the first to third insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, and the others are insulating layers having a region containing excess oxygen. With such a structure, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced.

[0217] The insulating layer 225 can have a four-layer structure including a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. For example, it is preferable that one of the first to fourth insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, another is an insulating layer having a region containing excess oxygen, and the others are insulating layers having a barrier property against oxygen. With such a structure, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

[0218] Note that the stacked structure of the first to fourth insulating layers in the insulating layer 225 can be referred to the stacked structure of the first to fourth insulating layers in the insulating layer 250. Note that the stacked order in the insulating layer 225 is preferably the reverse of that in the insulating layer 250. For example, when the insulating layer 225 has a three-layer structure, the insulating layer 225 can have a three-layer structure including a second insulating layer in contact with the conductive layer 255, a first insulating layer on the second insulating layer, and a third insulating layer on the first insulating layer. In this case, the third insulating layer is in contact with the oxide semiconductor layer 230.

[0219] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 255, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0220] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0221] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0222] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0223] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0224] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0225] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0226] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0227] The conductive layer 220a shown in FIG. 2A has a two-layer structure including a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 220a2 and a material having higher conductivity than the conductive layer 220a2 for the conductive layer 220a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220a2 and tungsten for the conductive layer 220a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 220a1. Using an oxide conductor for the conductive layer 220a2, which is mainly in contact with the oxide semiconductor layer 230a, can reduce contact resistance with the oxide semiconductor layer 230a. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 220a can increase the conductivity of the conductive layer 220a.

[0228] Note that the conductive layer 220a1 may be formed using a conductive material containing oxygen, and the conductive layer 220a2 may be formed using a material having higher conductivity than the conductive layer 220a1. In this case, the conductive layer 220a is formed using a material having higher conductivity in a layer closest to the channel formation region of the oxide semiconductor layer 230a. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200a can be increased.

[0229] 4A illustrates an example in which the conductive layer 220a1 and the conductive layer 220a2 each have a single-layer structure. Note that one or both of the conductive layer 220a1 and the conductive layer 220a2 may have a stacked structure of two or more layers. For example, as illustrated in FIG. 10A , the conductive layer 220a1 has a two-layer structure including a conductive layer 220a11 and a conductive layer 220a12 on the conductive layer 220a11. In this case, the conductive layer 220a has a three-layer structure including the conductive layer 220a11, the conductive layer 220a12 on the conductive layer 220a11, and the conductive layer 220a2 on the conductive layer 220a12. For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220a11, a highly conductive material as the conductive layer 220a12, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220a2. Specifically, it is preferable to use titanium nitride for the conductive layer 220a11, tungsten for the conductive layer 220a12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220a2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230a. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230a. Compared to tungsten, the oxide conductor has lower contact resistance with the oxide semiconductor layer 230a, which can shorten the current path between the source and drain, thereby increasing the on-state current of the transistor 200a. With this structure, the conductive layer 220a can maintain conductivity even when in contact with the oxide semiconductor layer 230a. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220a by the insulating layer 210 can be suppressed. In addition, the conductivity of the conductive layer 220a can be increased by using a metal material (tungsten in this example) that has higher conductivity than an oxide conductor and titanium nitride as the conductive layer 220a12. Note that the conductive layer 220b11 and the conductive layer 220b12 shown in FIG. 10A can be formed using a conductive material that can be used for the conductive layer 220a11 and the conductive layer 220a12, respectively.

[0230] The conductive layer 240a shown in FIG. 2A has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. By using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the oxide semiconductor layer 230a, the contact resistance with the oxide semiconductor layer 230a can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240a, the conductivity of the conductive layer 240a can be increased.

[0231] Note that the conductive layer 240a1 may be formed using a conductive material containing oxygen, and the conductive layer 240a2 may be formed using a material having higher conductivity than the conductive layer 240a1. In this case, an oxide conductor is used for the conductive layer 240a that is closest to the channel formation region of the oxide semiconductor layer 230a. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200a can be increased.

[0232] The conductive layer 255 has a region that functions as a first gate wiring. The conductive layer 255 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 255 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255.

[0233] The conductive layer 255 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0234] 2A shows an example in which the conductive layer 255 has a single-layer structure. Note that the conductive layer 255 can also have a stacked structure of two or more layers.

[0235] The thickness of the conductive layer 255 is preferably 2 nm to 50 nm, more preferably 3 nm to 30 nm, even more preferably 4 nm to 20 nm, and still more preferably 5 nm to 15 nm.

[0236] The conductive layer 260 can be made of any conductive material that can be used for the conductive layer 255 .

[0237] 4A shows an example in which the conductive layer 260 has a single-layer structure. Note that the conductive layer 260 can have a stacked structure of two or more layers. For example, as shown in FIG. 10B, the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0238] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0239] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0240] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0241] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 260 and the insulating layer 250.

[0242] The insulating layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230.

[0243] 4A shows a configuration in which the side surface of the conductive layer 240a in the opening 290 and the side surface of the insulating layer 281 in the opening 290 are flush (which can also be described as coinciding, approximately coinciding, aligned, or roughly aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 240a in the opening 290 and the side surface of the insulating layer 281 in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240a in the opening 290 and the inclination of the side surface of the insulating layer 281 in the opening 290 may differ from each other. In this case, part of the side surface of the opening 290 has a tapered shape.

[0244] 11A and 11B show examples in which at least a portion of the side surface of the opening 290 is tapered. Fig. 11A shows an example in which the side surface of the conductive layer 240a in the opening 290 is tapered, and Fig. 11B shows an example in which the side surface of the conductive layer 240a, the side surface of the insulating layer 281, the side surface of the conductive layer 255, and the side surface of the insulating layer 280 in the opening 290 are each tapered.

[0245] By tapering the side surface of the opening 290, the coverage of the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the side surface of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240a in the opening 290 and the taper angle (angle θ281) of the side surface of the insulating layer 281 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the opening 290.

[0246] Furthermore, for example, it is preferable that angle θ240 is smaller than angle θ281. With such a configuration, coverage of the side surface of conductive layer 240a in opening 290 by insulating layer 225, oxide semiconductor layer 230a, etc. is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 281 has a stacked structure, the inclination of the side surface of each layer in opening 290 may be different. Similarly, when conductive layer 240a has a stacked structure, the inclination of the side surface of each layer in opening 290 may be different.

[0247] As described above, the oxide semiconductor layer 230 can have a stacked structure of two or more layers.

[0248] Fig. 12A shows an example in which the oxide semiconductor layer 230 of the semiconductor device shown in Fig. 8 has a two-layer structure. The oxide semiconductor layer 230a shown in Fig. 12A can have a two-layer structure including an oxide semiconductor layer 230a1 and an oxide semiconductor layer 230a2 on the oxide semiconductor layer 230a1.

[0249] 12B shows an example in which the oxide semiconductor layer 230 of the semiconductor device shown in Fig. 8 has a three-layer structure. The oxide semiconductor layer 230a shown in Fig. 12B can have a three-layer structure including an oxide semiconductor layer 230a1, an oxide semiconductor layer 230a2 on the oxide semiconductor layer 230a1, and an oxide semiconductor layer 230a3 on the oxide semiconductor layer 230a2.

[0250] For an oxide semiconductor layer that can be used for the oxide semiconductor layers 230a1 to 230a3, the description in Embodiment 2 can be referred to.

[0251] 4A illustrates a configuration in which the end of the oxide semiconductor layer 230a in the opening 290 is located more inward than the end of the conductive layer 220a on the opening 290 side (on the side surface of the conductive layer 220b in the opening 290). Also illustrated is a configuration in which the oxide semiconductor layer 230a contacts the top surface of the insulating layer 210 in the opening 290. By configuring the end of the oxide semiconductor layer 230a in the opening 290 to be located on the insulating layer 210, it becomes relatively easy to process the oxide semiconductor film that becomes the oxide semiconductor layer 230a.

[0252] Note that the present invention is not limited to this as long as there is a region inside the opening 290 where the oxide semiconductor layer 230a and the conductive layer 220a are in contact with each other. FIG. 13A shows a configuration example in which the oxide semiconductor layer 230a is not in contact with the top surface of the insulating layer 210 in the opening 290. The configuration shown in FIG. 13A can increase the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b without reducing the contact area between the conductive layer 220a and the oxide semiconductor layer 230a. This makes it possible to shorten the distance between the conductive layer 220a and the conductive layer 220b, thereby enabling miniaturization or high integration of the semiconductor device.

[0253] 13B , the oxide semiconductor layer 230a may have a different ratio between the film thickness (hereinafter referred to as the first film thickness) of a portion where the upper surface of the conductive layer 240a or the conductive layer 220a is to be formed and the film thickness (hereinafter referred to as the second film thickness) of a portion where the side surface of the opening 290 is to be formed. For example, when a portion of the oxide semiconductor layer 230a is formed by sputtering, the oxide semiconductor layer 230a may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 13B , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle θ281 shown in FIG. 11B is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230a tends to be.

[0254] 1A and 1B illustrate a configuration in which the edge of the oxide semiconductor layer 230a is located more inward than the edge of the conductive layer 240a outside the opening 290. However, the present invention is not limited to this. For example, the edge of the oxide semiconductor layer 230a may coincide or substantially coincide with the edge of the conductive layer 240 outside the opening 290.

[0255] 14A to 14C show a semiconductor device having a structure in which the edge of the oxide semiconductor layer 230a coincides with or substantially coincides with the edge of the conductive layer 240 outside the opening 290. In FIG.

[0256] Fig. 14A is a plan view of a semiconductor device having two transistors. Fig. 14B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 14A. Fig. 14C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 14A. Note that Fig. 1D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 14B.

[0257] 14A to 14C, the conductive layer 240a and the oxide semiconductor layer 230a can be formed at the same time, which eliminates the need to separately form the conductive layer 240a and the oxide semiconductor layer 230a, thereby reducing the number of steps.

[0258] In the configurations shown in FIGS. 14A to 14C, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided to extend in the Y direction.

[0259] 15A to 16C , examples of the configuration of a transistor that is partially different from the configuration of the transistor 200 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0260] Fig. 15A is a plan view of a semiconductor device having two transistors. Fig. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 15A. Fig. 15C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 15A. Note that Fig. 1D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 15B.

[0261] 15A to 15C includes an insulating layer 210 over a substrate (not shown), transistors 200Aa and 200Ab over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 281 over the insulating layer 280, an insulating layer 284, an insulating layer 285 over the insulating layer 284, and conductive layers 265 over the transistors 200Aa, 200Ab, 284, and 285. The insulating layer 210, the insulating layer 280, the insulating layer 281, the insulating layer 284, and the insulating layer 285 function as interlayer films. Note that hereinafter, the transistors 200Aa and 200Ab may be collectively referred to as the transistor 200A.

[0262] The transistors 200Aa and 200Ab have a linearly symmetrical configuration with respect to the dashed-dotted line A3-A4. Therefore, the configuration of the transistor 200Ab can be understood by referring to the description of the configuration of the transistor 200Aa by replacing the transistor 200Aa, the conductive layer 220a, the conductive layer 240a, and the oxide semiconductor layer 230a with the transistor 200Ab, the conductive layer 220b, the conductive layer 240b, and the oxide semiconductor layer 230b, respectively, and making appropriate necessary modifications. Hereinafter, the transistor 200Aa will be mainly described.

[0263] [Transistor 200A] The semiconductor device illustrated in FIGS. 15A to 15C differs from the semiconductor device illustrated in FIGS. 1A to 1D in that a conductive layer 265, an insulating layer 284, and an insulating layer 285 are included.

[0264] The conductive layer 265 functions as a second gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0265] The transistor 200Aa includes a conductive layer 220a, a conductive layer 255, a conductive layer 240a, an insulating layer 225, an oxide semiconductor layer 230a, an insulating layer 250, and a conductive layer 260. The conductive layer 265 has a region in contact with the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200Aa.

[0266] In the transistor 200Aa, the stacked structure from the conductive layer 220a to the insulating layer 250 is the same as that of the transistor 200a described above, and therefore detailed description thereof will be omitted.

[0267] 15B and 15C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions overlapping openings 290. Conductive layer 260 is disposed so that at least a portion thereof is located within opening 270. Conductive layer 260 contacts insulating layer 250 within opening 270.

[0268] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0269] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240a via the insulating layers 284 and 285. This increases the physical distance between the conductive layer 265 and the conductive layer 240a, thereby reducing the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240a. Note that the conductive layer 240a and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0270] 15B shows an example in which the width of opening 270 is smaller than the width D of opening 290. The smaller the width of opening 270, the greater the physical distance between conductive layer 240a and conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between conductive layer 240a and conductive layer 260 can be, which is preferable. For example, the width of opening 270 is preferably the same as or smaller than the width of opening 290.

[0271] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0272] That is, the transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0273] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0274] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0275] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 284. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 284, an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0276] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0277] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0278] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0279] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0280] Note that a structure similar to that of the transistor 200 can also be applied to the transistor 200A.

[0281] The above is a description of the semiconductor device including the transistor 200Aa and the transistor 200Ab.

[0282] Fig. 16A is a plan view of a semiconductor device having two transistors. Fig. 16B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 16A. Fig. 16C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 16A. Note that Fig. 1D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 16B.

[0283] 16A to 16C includes an insulating layer 210 over a substrate (not shown), transistors 200Ba and 200Bb over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 281 over the insulating layer 280, an insulating layer 284, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the insulating layer 284. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films. Note that hereinafter, the transistors 200Ba and 200Bb may be collectively referred to as the transistor 200B.

[0284] The transistors 200Ba and 200Bb have a linear symmetry with respect to the dashed-dotted line A3-A4. Therefore, the structure of the transistor 200Bb can be understood by referring to the description of the structure of the transistor 200Ba, by replacing the transistor 200Ba, the conductive layer 220a, the conductive layer 240a, and the oxide semiconductor layer 230a with the transistor 200Bb, the conductive layer 220b, the conductive layer 240b, and the oxide semiconductor layer 230b, respectively, and by making appropriate necessary modifications. Hereinafter, the transistor 200Ba will be mainly described.

[0285] [Transistor 200B] The semiconductor device shown in FIGS. 16A to 16C differs from the semiconductor device shown in FIGS. 15A to 15C in that the insulating layer 250 has a portion in contact with the side surface of the insulating layer 284 in the opening 270.

[0286] In the transistor 200Ba, the stacked structure from the conductive layer 220a to the oxide semiconductor layer 230a is similar to that of the above-described transistor 200a, and therefore detailed description thereof will be omitted.

[0287] The insulating layer 250 is in contact with the oxide semiconductor layer 230 and the insulating layer 284 within the opening 270. The portion of the insulating layer 250 that is disposed within the opening 270 is provided to reflect the shape of the opening 270. Specifically, the insulating layer 250 is provided so as to cover the side surface of the opening 270 (the side surface of the insulating layer 284). Then, the conductive layer 260 is provided so as to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 270.

[0288] In the transistor 200Ba, the conductive layer 260 does not overlap with the top surface of the conductive layer 240a, which reduces the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260. As shown in FIG. 16B , in a cross-sectional view, the maximum width of the conductive layer 260 is smaller than the width D of the opening 290. When the maximum width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a can be reduced, which is preferable. Note that, for example, as shown in FIG. 16B , the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0289] 16B shows an example in which the width of opening 270 is smaller than width D of opening 290. It is more preferable that the width of opening 270 is the same as or smaller than the width of opening 290. This is preferable because conductive layer 260 does not overlap the upper surface of conductive layer 240a and the parasitic capacitance generated between conductive layer 260 and conductive layer 240a can be reduced.

[0290] Although the present embodiment mainly illustrates an example in which the conductive layer 260 does not overlap with the upper surface of the conductive layer 240a, the conductive layer 260 may have a portion that overlaps with the upper surface of the conductive layer 240a. The smaller the overlapping portion, the smaller the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a, which is preferable. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265 in FIG. 16B ).

[0291] That is, the transistor 200B has a structure in which the parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode and the parasitic capacitance between the gate wiring and the other of the source electrode and the drain electrode are reduced, thereby improving the frequency characteristics of a circuit using the transistor.

[0292] Note that the same structure as at least one of the transistor 200 and the transistor 200A can also be applied to the transistor 200B.

[0293] 17A to 27C , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts that are similar to those described above may be omitted.

[0294] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0295] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0296] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0297] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0298] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0299] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0300] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0301] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0302] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0303] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0304] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0305] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0306] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0307] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0308] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0309] An example of a method for manufacturing the semiconductor device shown in FIG. 4A will be described with reference to FIGS. 17A to 27C.

[0310] 17A to 17C, an insulating layer 210 is formed on a substrate (not shown), and then a conductive layer 220a and a conductive layer 220b are formed on the insulating layer 210. For example, a first conductive film that will become the conductive layer 220a1 and the conductive layer 220b1 is formed, a second conductive film that will become the conductive layer 220a2 and the conductive layer 220b2 is formed on the first conductive film, and the first conductive film and the second conductive film are processed to form the conductive layer 220a that has the conductive layer 220a1 and the conductive layer 220a2 and the conductive layer 220b that has the conductive layer 220b1 and the conductive layer 220b2.

[0311] 18A to 18C , an insulating layer 280 is formed over the conductive layer 220a, the conductive layer 220b, and the insulating layer 210. Note that after the insulating layer 280 is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 280. As the planarization treatment, planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 255, which functions as a wiring, is formed can be flattened, and discontinuity of the conductive layer 255 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0312] 18A to 18C , a conductive layer 255 is formed over the insulating layer 280. The conductive layer 255 is preferably formed by, for example, a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in a deposition gas, the hydrogen concentration in the conductive layer 255 can be reduced, and entry of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0313] 19A to 19C, an insulating layer 281 is formed over the conductive layer 255 and the insulating layer 280. Note that after the insulating layer 281 is formed, CMP treatment is preferably performed to planarize the top surface of the insulating layer 281. By performing the planarization treatment on the insulating layer 281, the surfaces on which the conductive layers 240a and 240b are to be formed can be planarized, and discontinuities in the conductive layers 240a and 240b can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0314] 19A to 19C, a conductive film 240f1 is formed on the insulating layer 281, and a conductive film 240f2 is formed on the conductive film 240f1. The conductive film 240f1 is a conductive film that will later become the conductive layers 240a1 and 240b1, and the conductive film 240f2 is a conductive film that will later become the conductive layers 240a2 and 240b2. Note that hereinafter, the conductive films 240f1 and 240f2 may be collectively referred to as the conductive film 240f.

[0315] 20A to 20C, openings 290 are formed in the conductive film 240f, the insulating layer 281, the conductive layer 255, and the insulating layer 280. The openings 290 are formed so that at least a portion of the upper surfaces of the conductive layer 220a2, the conductive layer 220b2, and the insulating layer 210 are exposed. At this time, recesses are preferably provided in the conductive layer 220a2 and the conductive layer 220b2 at positions overlapping with the openings 290. By forming the openings 290, it is preferable that the bottom and side surfaces of the recesses of the conductive layer 220a2 and the conductive layer 220b2 are exposed. Furthermore, a recess may be provided in the insulating layer 210 between the conductive layer 220a and the conductive layer 220b at a position overlapping with the openings 290.

[0316] To achieve microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process parts of the conductive layer 220a2 and the conductive layer 220b2, parts of the insulating layer 280, parts of the conductive layer 255, and parts of the conductive film 240f when forming the opening 290. Dry etching is particularly preferable because it is suitable for microfabrication. The opening 290 may be formed under different processing conditions depending on the layer. Depending on the materials and processing conditions of conductive layer 220a2, conductive layer 220b2, insulating layer 280, conductive layer 255, insulating layer 281, conductive film 240f1, and conductive film 240f2, the slope of the side surfaces of conductive layer 220a2 and conductive layer 220b2, the slope of the side surfaces of insulating layer 280, the slope of the side surfaces of conductive layer 255, the slope of the side surfaces of insulating layer 281, the slope of the side surfaces of conductive film 240f1, and the slope of the side surfaces of conductive film 240f2 within opening 290 may differ from one another.

[0317] Furthermore, by the process of forming the opening 290 or the like, a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recesses of the conductive layer 220a2 and the conductive layer 220b2, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 281, the side surfaces of the conductive film 240f1, and the top and side surfaces of the conductive film 240f2. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in such a region.

[0318] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0319] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the formation of the oxide semiconductor layer 230.

[0320] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 280 and the like as much as possible.

[0321] 21A to 21C , an insulating layer 225 is formed so as to cover the opening 290. The insulating layer 225 is provided in contact with the exposed upper surface of the insulating layer 210 (if the insulating layer 210 has a recess at a position overlapping the opening 290, the bottom and side surfaces of the recess), the bottom and side surfaces of the recesses of the conductive layers 220a2 and 220b2, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 281, the side surfaces of the conductive film 240f1, and the upper surface and side surfaces of the conductive film 240f2.

[0322] The insulating layer 225 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided in the opening 290. This allows the insulating layer 225 to be provided with good coverage.

[0323] In this embodiment, the insulating layer 225 is formed by depositing a first insulating film and a second insulating film in this order using the ALD method. For example, a silicon nitride film is deposited as the first insulating film using the PEALD method, and a silicon oxide film is deposited as the second insulating film using the PEALD method. At this time, it is preferable to deposit the first insulating film and the second insulating film consecutively without exposing them to the atmosphere. By depositing the first insulating film and the second insulating film consecutively without exposing them to the atmosphere, it is possible to increase productivity. In addition, it is possible to reduce impurities (typically moisture, etc.) that are introduced into the interface between the first insulating film and the second insulating film and the vicinity thereof.

[0324] 22A to 22C, the insulating layer 225 is processed to expose the top surface of the conductive film 240f2, and to expose the conductive layer 220a2, the conductive layer 220b2, and the insulating layer 210 in the opening 290. In the opening 290, it is preferable that the bottom surfaces of the recesses of the conductive layer 220a2 and the conductive layer 220b2 are exposed.

[0325] By processing the insulating layer 225 by anisotropic etching, it is possible to remove the region of the insulating layer 225 located on the top surface of the conductive film 240f2 and the region located on the bottom surface of the opening 290, and leave the insulating layer 225 only on the side surface within the opening 290. It is preferable to process the insulating layer 225 by performing highly anisotropic etching using a dry etching method.

[0326] As described using FIG. 4B, when processing the insulating layer 225, a portion of the conductive layer 220a2 and the conductive layer 220b2 may be removed, and a recess (the first recess described above) may be formed in the conductive layer 220a2 and the conductive layer 220b2.

[0327] It is preferable to perform a treatment for supplying oxygen after the insulating layer 225 is formed and before the insulating layer 225 is processed (see FIGS. 21A to 21C ). This allows oxygen to be supplied to the second insulating film, and oxygen can be supplied from the second insulating film to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, by providing the first insulating film having a barrier property against oxygen, diffusion of oxygen into the conductive layer 220, the conductive layer 255, and the conductive layer 240 can be suppressed, and a decrease in the conductivity of the conductive layer 220, the conductive layer 255, and the conductive layer 240 can be suppressed. Therefore, the range of materials that can be selected for the conductive layer 220, the conductive layer 255, and the conductive layer 240 can be broadened.

[0328] Alternatively, a process for supplying oxygen may be performed after the insulating layer 225 is processed (see FIGS. 22A to 22C ). As a result, oxygen is supplied to the second insulating film, and oxygen can be supplied from the second insulating film to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, by using an oxide conductor for the conductive layer 220a2, the conductive layer 220b2, and the conductive film 240f2, a decrease in the conductivity of the conductive layer 220a2, the conductive layer 220b2, and the conductive film 240f2 can be suppressed even when a process for supplying oxygen is performed after the second insulating film is processed.

[0329] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the second insulating film by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition or may be left as it is. In the case where the deposited oxide film is left as it is, the oxide film can be used as part of the oxide semiconductor layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound gas containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0330] 23A to 23C , an oxide semiconductor film 230f, which will later become the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, is formed so as to cover the opening 290. The oxide semiconductor film 230f is provided in contact with the bottom surfaces and side surfaces of the recesses of the conductive layer 220a2 and the conductive layer 220b2, the exposed upper surface of the insulating layer 210, the side surfaces of the insulating layer 225, the side surfaces of the conductive film 240f1, and the upper surface and side surfaces of the conductive film 240f2.

[0331] The description in Embodiment 2 can be referred to for a method for forming the oxide semiconductor film 230f.

[0332] In this embodiment, a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film are deposited in this order as the oxide semiconductor film 230f. The first oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a1 and the oxide semiconductor layer 230b1 shown in FIG. 12B . The second oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a2 and the oxide semiconductor layer 230b2 shown in FIG. 12B . The third oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a3 and the oxide semiconductor layer 230b3 shown in FIG. 12B .

[0333] For example, an In—Ga—Zn oxide film is formed as a first oxide semiconductor film by a thermal ALD method, an indium oxide film is formed as a second oxide semiconductor film by a thermal ALD method, and an In—Ga—Zn oxide film is formed as a third oxide semiconductor film by a sputtering method.

[0334] Note that the first oxide semiconductor film and the second oxide semiconductor film are preferably formed successively without exposure to the air. By forming the first oxide semiconductor film and the second oxide semiconductor film successively without exposure to the air, productivity can be improved. Furthermore, impurities (typically moisture) introduced into the interface between the first oxide semiconductor film and the second oxide semiconductor film and the vicinity thereof can be reduced.

[0335] After the second oxide semiconductor film is formed, a process of supplying oxygen to the second oxide semiconductor film may be performed. By this process, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after the process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0336] Next, it is preferable to perform heat treatment. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and even more preferably from 350° C. to 550° C. For details of the heat treatment, see the above description.

[0337] The gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0338] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 230. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor layer 230, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor layer 230, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 230. Therefore, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0339] In the case where the second insulating film of the insulating layer 225 contains oxygen, oxygen is preferably supplied from the insulating film containing oxygen to the channel formation region of the oxide semiconductor layer 230 by the heat treatment. Ｏ H can be reduced.

[0340] In this manner, excess oxygen may be supplied to the oxide semiconductor layer 230 from an insulating layer in contact with the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be generated. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0341] Note that microwave plasma treatment may be performed after the second oxide semiconductor film or the third oxide semiconductor film is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow. Note that the details of the microwave plasma treatment will be described in Embodiment 2.

[0342] 24A to 24C , the oxide semiconductor film 230f is processed to expose part of the top surface of the conductive film 240f2 and part of the top surface of the insulating layer 210 at a position overlapping with the opening 290. By this processing, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are formed.

[0343] 24A to 24C , the above processing is preferably performed so that only the top surface of the insulating layer 210 is exposed in the opening 290. In other words, the above processing is preferably performed so that the conductive layer 220a, the conductive layer 220b, and the insulating layer 225 are not exposed in the opening 290. In this way, the base film during the above processing is only the insulating layer 210, which makes it relatively easy to process the oxide semiconductor film 230f.

[0344] Cleaning treatment is preferably performed to remove impurities or the like attached to the surface of the oxide semiconductor layer 230 during the above processing. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0345] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0346] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water or carbonated water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration or temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0347] The ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor layer 230 and the like can be reduced by using such a frequency.

[0348] The cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0349] 25A to 25C, the conductive film 240f is processed to form the conductive layer 240a (conductive layer 240a1 and conductive layer 240a2) and the conductive layer 240b (conductive layer 240b1 and conductive layer 240b2). Specifically, the conductive layer 240a2 and the conductive layer 240b2 are formed from the conductive film 240f2, and the conductive layer 240a1 and the conductive layer 240b1 are formed from the conductive film 240f1.

[0350] Note that the oxide semiconductor film 230f and the conductive film 240f can be processed at the same time, whereby the semiconductor device illustrated in FIGS. 14A to 14C can be manufactured.

[0351] 26A to 26C , an insulating layer 250 is formed to cover the opening 290. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The insulating layer 250 is formed in the opening 290, which has a large aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0352] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow. Note that the details of the microwave plasma treatment will be described in Embodiment 2.

[0353] In addition, when the insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the formation of the third insulating layer. Furthermore, microwave plasma treatment may be performed again after the formation of the first insulating layer. In this way, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least two times or more).

[0354] After the third insulating layer is formed, treatment for supplying oxygen to the third insulating layer may be performed, thereby making it possible to supply oxygen to the oxide semiconductor layer 230. Note that the above description can be referred to for details of the treatment for supplying oxygen.

[0355] In this embodiment, the insulating layer 250 is formed by depositing an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film in this order using an ALD method.

[0356] 27A to 27C, a conductive layer 260 is formed on the insulating layer 250. The conductive layer 260 is preferably provided so as to fill the opening 290.

[0357] The conductive layer 260 is formed in the opening 290 having a large aspect ratio. Therefore, the conductive layer 260 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0358] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0359] In the semiconductor device exemplified in the above-described <Configuration Example 1 of Semiconductor Device>, two transistors are provided in one opening, and each transistor has two gate electrodes. Note that the present invention is not limited to this. For example, the transistor included in the semiconductor device may be a single-gate transistor having one gate electrode.

[0360] 28A to 29D, a description will be given of a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device>. Note that a description of the same parts as those described above will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if the functions are the same, the same reference numerals will be used and the description may be omitted.

[0361] <Structural Example 2 of Semiconductor Device> Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 28A to 28D.

[0362] Fig. 28A is a plan view of a semiconductor device having two transistors. Fig. 28B is a cross-sectional view taken along dashed dotted lines A1-A2 shown in Fig. 28A. Fig. 28C is a cross-sectional view taken along dashed dotted lines A3-A4 shown in Fig. 28A. Fig. 28D is a cross-sectional view taken along dashed dotted lines A5-A6 shown in Fig. 28B.

[0363] 28A to 28D includes an insulating layer 210 on a substrate (not shown), a transistor 200Ca and a transistor 200Cb on the insulating layer 210, an insulating layer 280 on the insulating layer 210, an insulating layer 281, and an insulating layer 283 on the transistor 200Ca and the transistor 200Cb. Note that hereinafter, the transistors 200Ca and 200Cb may be collectively referred to as the transistor 200C.

[0364] 28A to 28D differ from the semiconductor device shown in Figures 1A to 1D in that the semiconductor device shown in Figures 28A to 28D does not have the conductive layer 260 and the insulating layer 250 and has the insulating layer 283. The semiconductor device shown in Figures 28A to 28D also differs from the semiconductor device shown in Figures 1A to 1D in that the semiconductor device shown in Figures 28A to 28D does not have the conductive layer 260 and has the insulating layer 283 instead of the insulating layer 250.

[0365] The transistors 200Ca and 200Cb have a linearly symmetrical configuration with respect to the dashed-dotted line A3-A4. Therefore, the configuration of the transistor 200Cb can be understood by referring to the description of the configuration of the transistor 200Ca, by replacing the transistor 200Ca, the conductive layer 220a, the conductive layer 240a, and the oxide semiconductor layer 230a with the transistor 200Cb, the conductive layer 220b, the conductive layer 240b, and the oxide semiconductor layer 230b, respectively, and making appropriate necessary modifications. Hereinafter, the transistor 200Ca will be mainly described.

[0366] The transistor 200Ca includes a conductive layer 220a, a conductive layer 255, a conductive layer 240a, an insulating layer 225, and an oxide semiconductor layer 230a over the conductive layer 220a and the conductive layer 240a.

[0367] In the transistor 200Ca, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 255 functions as a gate electrode, the insulating layer 225 functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and the drain electrode. The conductive layer 255 has a region that functions as a gate wiring. That is, the transistor 200Ca is a single-gate transistor.

[0368] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0369] The insulating layer 283 may be made of an insulating material that can be used for the insulating layer 250 .

[0370] Note that an insulating layer can be provided between the oxide semiconductor layer 230a and the insulating layer 283 or over the insulating layer 283 so as to fill the opening 290. For the insulating layer, the insulators described in [Insulating Layer] above can be used as a single layer or a stacked layer.

[0371] The manufacturing cost can be reduced by not providing the conductive layer 260. In addition, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration of the semiconductor device can be achieved.

[0372] Note that the same structure as at least one of the transistor 200, the transistor 200A, and the transistor 200B can also be applied to the transistor 200C.

[0373] <Structural Example 3 of Semiconductor Device> Another structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 29A to 29D.

[0374] Fig. 29A is a plan view of a semiconductor device having two transistors. Fig. 29B is a cross-sectional view taken along dashed dotted lines A1-A2 shown in Fig. 29A. Fig. 29C is a cross-sectional view taken along dashed dotted lines A3-A4 shown in Fig. 29A. Fig. 29D is a cross-sectional view taken along dashed dotted lines A5-A6 shown in Fig. 29B.

[0375] 29A to 29D includes an insulating layer 210 on a substrate (not shown), transistors 200Da and 200Db on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. Note that hereinafter, the transistors 200Da and 200Db may be collectively referred to as the transistor 200D.

[0376] The semiconductor device shown in FIGS. 29A to 29D differs from the semiconductor device shown in FIGS. 1A to 1D in that the semiconductor device does not have the conductive layer 255 and the insulating layer 281.

[0377] The transistors 200Da and 200Db have a linearly symmetrical configuration with respect to the dashed-dotted line A3-A4. Therefore, the configuration of the transistor 200Db can be understood by referring to the description of the configuration of the transistor 200Da by replacing the transistor 200Da, the conductive layer 220a, the conductive layer 240a, and the oxide semiconductor layer 230a with the transistor 200Db, the conductive layer 220b, the conductive layer 240b, and the oxide semiconductor layer 230b, respectively, and making appropriate necessary modifications. The following description will mainly focus on the transistor 200Da.

[0378] The transistor 200Da includes a conductive layer 220a, a conductive layer 240a, an insulating layer 225, an oxide semiconductor layer 230a over the conductive layer 220a and the conductive layer 240a, an insulating layer 250, and a conductive layer 260.

[0379] In the transistor 200Da, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and the drain electrode. The conductive layer 260 has a region that functions as a gate wiring. That is, the transistor 200Da is a single-gate transistor.

[0380] 29A to 29C, the conductive layer 260 is provided extending in the X direction.

[0381] The manufacturing cost can be reduced by not providing the conductive layer 255 and the insulating layer 281. In addition, the area occupied by the semiconductor device can be reduced, and miniaturization or high integration of the semiconductor device can be achieved.

[0382] 29A to 29C may be configured without the insulating layer 225. The configuration without the insulating layer 225 can reduce manufacturing costs. Furthermore, the area occupied by the semiconductor device can be reduced, enabling miniaturization or high integration of the semiconductor device. Furthermore, the contact area between the oxide semiconductor layer 230a and the conductive layer 220a can be increased, thereby reducing the contact resistance between the oxide semiconductor layer 230a and the conductive layer 220a. Similarly, the contact area between the oxide semiconductor layer 230a and the conductive layer 240a can be increased, thereby reducing the contact resistance between the oxide semiconductor layer 230a and the conductive layer 240a.

[0383] Note that the same structure as at least one of the transistor 200, the transistor 200A, and the transistor 200B can also be applied to the transistor 200D.

[0384] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0385] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor layer of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor layer with a stacked structure, it may be difficult to identify boundaries between stacked films, as described later.

[0386] [Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0387] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, IAZO). Examples of usable metal oxides include indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide) can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0388] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0389] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0390] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0391] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0392] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0393] A structural example of an oxide semiconductor layer capable of increasing the field-effect mobility of a transistor will be described. For example, it is preferable to use indium oxide or a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the oxide semiconductor layer has indium oxide and IGZO on the indium oxide. In addition, it is preferable to use IGZO containing nitrogen as the oxide semiconductor layer. For example, it is preferable to use IGZO containing nitrogen during or after film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. For the oxide semiconductor layer, at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO is preferably used.

[0394] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0395] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (poly-crystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0396] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0397] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0398] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0399] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is to be formed.

[0400] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0401] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0402] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0403] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0404] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface on which the oxide semiconductor layer is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor layer has crystallinity.

[0405] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the oxide semiconductor layer, the on-state current of a transistor can be increased and frequency characteristics can be improved. For example, indium oxide is preferably used for the oxide semiconductor layer.

[0406] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, the metal oxide becomes a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, an In—Zn oxide can be used for the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout can be used. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0407] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Thus, the reliability of a transistor including an oxide semiconductor layer can be improved.

[0408] For example, the oxide semiconductor layer can be made of an In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof can be used. Alternatively, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used.

[0409] The oxide semiconductor layer can be made of an In—Zn oxide containing an element M. Specifically, a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a composition thereof, an atomic ratio of In:M:Zn=1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn=1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn=1:1:2 or a composition thereof, an atomic ratio of In:M:Zn=4:2:3 or a composition thereof, an atomic ratio of In:M:Zn=1:3:2 or a composition thereof, or an atomic ratio of In:M:Zn=1:3:4 or a composition thereof can be used.

[0410] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0411] Furthermore, when forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not match.

[0412] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0413] The oxide semiconductor layer of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0414] The first to third layers may each be made of the metal oxides described above.

[0415] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout can be used. For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereabout can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0416] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0417] By sandwiching the second layer between the first layer and the third layer, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0418] For example, a band diagram of the oxide semiconductor layer 230a including the oxide semiconductor layers 230a1 to 230a3 and their vicinity shown in FIG. 12B is as shown in FIG. 30. In FIG. 30, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 30 also shows the valence band maximum (VBM) and the conduction band minimum (CBM) of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250 when no voltage is applied between the gate and the source. In FIG. 30, the vacuum level Vac is indicated by a dashed line.

[0419] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250. Therefore, the relationship in height between the upper ends of the valence bands and the relationship in height between the lower ends of the conduction bands will be mainly described using the band diagram in FIG. 30 .

[0420] Depending on the constituent elements and compositions of the oxide semiconductor layers 230a1 to 230a3, the oxide semiconductor layer 230a2 may be sandwiched between the oxide semiconductor layers 230a1 and 230a3, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor layer 230a2, as shown in FIG. 30 . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 30 ) flows in the oxide semiconductor layer 230a2. Therefore, an increase in on-state current or improvement in reliability can be achieved.

[0421] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0422] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen or water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. Note that the same effect may be achieved by using a metal oxide having a lower In content than the second layer for the first layer and the third layer.

[0423] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, in which the third layer contains indium and gallium.

[0424] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0425] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0426] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0427] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0428] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described compositions stacked together. For example, the first layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0429] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by a sputtering method, a CVD method, a vacuum evaporation method, an MBE method, a PLD method, an ALD method, or the like.

[0430] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0431] The oxide semiconductor layer of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0432] The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is formed than the second deposition method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which can further increase the crystallinity of the oxide semiconductor layer.

[0433] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0434] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0435] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0436] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the second film formation method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the crystallization of the metal oxide may be inhibited by the inclusion of impurities such as silicon into the metal oxide. Furthermore, there is a concern that the use of an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when a heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0437] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, impurities can be prevented from being mixed into the oxide semiconductor layer. Furthermore, alloying with a layer on which the metal oxide is to be formed can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0438] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0439] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, and the like with a high aspect ratio.

[0440] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which the oxide semiconductor layer is formed.

[0441] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to have crystallinity. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0442] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0443] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0444] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0445] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0446] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0447] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) or the like is used as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0448] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0449] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0450] The second layer is preferably formed by sputtering.

[0451] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0452] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0453] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0454] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0455] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer to be formed and the metal oxide can be reduced to an extent that it cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0456] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or EDX.

[0457] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0458] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0459] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0460] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0461] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0462] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0463] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0464] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by forming a first layer on a surface to be formed by a first film formation method, forming a second layer by a second film formation method, and then forming a third layer by the first film formation method.

[0465] Even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, the oxide semiconductor layer can have a structure in which the entire oxide semiconductor layer including the first layer and the third layer has the CAAC structure by crystal growth using the second layer as a nucleus. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0466] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0467] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0468] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0469] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0470] When the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0471] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0472] As described above, in the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers here) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown by solid-phase growth using the second layer as a nucleus or seed, thereby forming an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a deposition method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0473] In the oxide semiconductor layer, a region having a CAAC structure is preferably present widely throughout the layer. The region having the CAAC structure in the first layer is crystallinely connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystallinely connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer may be expressed as a single layer.

[0474] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0475] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0476] In addition, when the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured in such a manner that a first layer is formed on a surface to be formed by a first film formation method, a second layer is formed by the first film formation method, and a third layer is formed by the second film formation method.

[0477] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content in the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0478] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to have crystals that reflect the orientation of the crystals of the third layer. In this case, for example, in cross-sectional observation of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the second layer.

[0479] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0480] In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0481] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) that are introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0482] One or more of the first to third layers may have a stack of layers with different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide with a high Ga content by the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer by the first film formation method.

[0483] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0484] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0485] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0486] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0487] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0488] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0489] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 220 or the conductive layer 240, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0490] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0491] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor layer. Nuclei or seeds are formed. Lateral growth of the nuclei or seeds is also induced. It is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0492] On the other hand, a reaction occurs between part of oxygen present in the oxide semiconductor layer before the microwave plasma treatment and hydrogen in the oxide semiconductor layer, in other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove hydrogen from the oxide semiconductor layer. ２ The hydrogen concentration in the oxide semiconductor layer can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor layer can be further reduced by increasing the temperature during the microwave plasma treatment.

[0493] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0494] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0495] The crystallinity of the layer formed by the first film formation method can be increased, which can further increase the crystallinity of a layer formed over the layer, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0496] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0497] After the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0498] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

[0499] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0500] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after the ALD film formation, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0501] Furthermore, it is preferable that at least a portion of the first layer or the second layer formed using the first film formation method is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method serves as a nucleus or seed. It is preferable that the region in the first layer or the second layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0502] Furthermore, because the CAAC is formed from the top to the bottom of the first layer or the second layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first layer or the second layer can be increased. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0503] As described above, by performing microwave plasma treatment and / or heat treatment, the crystallinity of the entire oxide semiconductor layer can be improved. Furthermore, impurities in the oxide semiconductor layer can be reduced. Crystal growth can be performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, thereby further improving the crystallinity.

[0504] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0505] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor layer, or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0506] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the oxide semiconductor layer by heat or the like applied after the treatment.

[0507] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the first layer or the second layer formed by the first film formation method by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately after the formation, or may be left as it is. When the formed oxide film is left as it is, the oxide film can be used as a layer (second layer or third layer) provided on the first layer or the second layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0508] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0509] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0510] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0511] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without using the second film formation method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming a first layer by the first film formation method, the crystallinity of the first layer can be increased. Therefore, the crystallinity of a second layer formed on the first layer by the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0512] As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed by the first film formation method can be used as a nucleus or seed to cause solid-phase growth of the oxide semiconductor thereover, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can also be referred to as an AG CAAC.

[0513] When the oxide semiconductor layer has a stacked structure of two or more layers, it can also be formed by forming a metal oxide using one type of film formation method. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be formed by, for example, forming the first layer and the second layer in this order by a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. For example, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the first layer to the third layer can also be formed by a sputtering method. Furthermore, some of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer may be formed by ALD.

[0514] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0515] The oxide semiconductor layer in this embodiment can be used as the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer that is a surface to be formed corresponds to the insulating layer 280 or the like described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor layer 230a1, the second layer can be used as the oxide semiconductor layer 230a2, and the third layer can be used as the oxide semiconductor layer 230a3.

[0516] The oxide semiconductor layer of this embodiment preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed.

[0517] It is estimated that an oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor layer having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0518] In the semiconductor device described in the above embodiment, metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0519] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer is preferably 1 nm to 20 nm, further preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. Furthermore, the average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0520] The first layer preferably has a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0521] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0522] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0523] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0524] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0525] [Impurities in Oxide Semiconductor Layer] Here, the influence of each impurity in the oxide semiconductor layer will be described.

[0526] As described in the above embodiment, in a transistor including an oxide semiconductor in a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities such as hydrogen, carbon, and nitrogen can cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor layer is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor layer refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0527] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0528] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３The following applies.

[0529] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0530] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0531] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0532] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0533] 31A to 39. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0534] 31A to 31C , the configuration of a memory device having a transistor and a capacitor will be described. Figures 31A and 31B are plan views of a memory device having two memory cells. Figure 31C is a cross-sectional view taken along dashed line A1-A2 shown in Figures 31A and 31B .

[0535] Fig. 32 is a schematic perspective view of the memory device shown in Fig. 31A to Fig. 31C. Specifically, Fig. 32 is a schematic perspective view of a memory device including two memory cells. In Fig. 32, only the outlines of some components (such as an interlayer insulating layer) are indicated by dotted lines.

[0536] 31A to 31C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, memory cells 150a and 150b on the conductive layer 110, and an insulating layer 180, an insulating layer 280, and an insulating layer 281 on the conductive layer 110. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 281 function as interlayer films. The conductive layer 110 functions as wiring. Note that hereinafter, the memory cells 150a and 150b may be collectively referred to as memory cells 150.

[0537] The memory cell 150a includes a capacitor 100a over the conductive layer 110 and a transistor 200a over the capacitor 100a. Similarly, the memory cell 150b includes a capacitor 100b over the conductive layer 110 and a transistor 200b over the capacitor 100b.

[0538] The capacitor 100a and the capacitor 100b have the same configuration. Hereinafter, the capacitors 100a and 100b may be collectively referred to as the capacitor 100. For the configuration of the capacitor 100b, the description of the configuration of the capacitor 100a can be referred to by substituting the capacitor 100b for the capacitor 100a and making appropriate necessary modifications. Hereinafter, the capacitor 100a will be mainly described.

[0539] The capacitor element 100 a includes a conductive layer 115 on a conductive layer 110 , an insulating layer 130 on the conductive layer 115 , and a conductive layer 120 on the insulating layer 130 .

[0540] In the capacitor 100a, the conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0541] 31B illustrates some of the components of the capacitors 100a and 100b, as well as conductive layers 215a, 215b, 220a, and 220b, which will be described later. Also, FIG. 31B illustrates an opening 290 where parts of the structures of the transistors 200a and 200b are provided.

[0542] 31B and 31C , the insulating layer 180 has openings 190a and 190b that reach the conductive layer 110. At least a portion of the conductive layer 115 of the capacitor 100a is disposed in the opening 190a, and at least a portion of the conductive layer 115 of the capacitor 100b is disposed in the opening 190b. The conductive layer 115 of the capacitor 100a has a region in contact with the top surface of the conductive layer 110 in the opening 190a and a region in contact with the side surface of the insulating layer 180 in the opening 190a. The insulating layer 130 of the capacitor 100a is disposed so that at least a portion of it is located in the opening 190a. The conductive layer 120 of the capacitor 100a is disposed so that at least a portion of it is located in the opening 190a.

[0543] 31C , the conductive layer 120 of the capacitor 100a is preferably provided so as to fill the opening 190a. The films provided inside the opening 190a are preferably formed by ALD, which improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed by ALD.

[0544] The capacitor 100a has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface within the opening 190a, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190a, the larger the capacitance of the capacitor 100a. Increasing the capacitance per unit area of ​​the capacitor 100a in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization and high integration of memory devices.

[0545] 31C shows an example in which the side surface of opening 190a is perpendicular to the top surface of conductive layer 110. In this case, opening 190a has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0546] A conductive layer 115 is provided along the side surface of the opening 190a and the upper surface of the conductive layer 110. An insulating layer 130 and a conductive layer 120 are stacked on the conductive layer 115 so as to fill the opening 190a. A capacitor 100a having such a configuration may be referred to as a trench capacitor. Note that the configuration of the capacitor 100a is not limited to this, and for example, a pillar-type capacitor element, a parallel-plate capacitor element, or the like may also be used.

[0547] An insulating layer 181 is disposed on the capacitor element 100a and the capacitor element 100b. An insulating layer 185 is disposed on the insulating layer 181 and the conductive layer 120, and an insulating layer 210 is disposed on the insulating layer 185.

[0548] The insulating layer 210 and the insulating layer 185 have openings that reach the conductive layer 120 of the capacitor 100a and the conductive layer 120 of the capacitor 100b. A conductive layer 215a is provided in the opening that reaches the conductive layer 120 of the capacitor 100a, and a conductive layer 215b is provided in the opening that reaches the conductive layer 120 of the capacitor 100b.

[0549] The conductive layer 120 of the capacitor 100a is connected to the conductive layer 220a through the conductive layer 215a. This connects the upper electrode of the capacitor 100a to one of the source electrode and the drain electrode of the transistor 200a. Similarly, the conductive layer 120 of the capacitor 100b is connected to the conductive layer 220b through the conductive layer 215b. This connects the upper electrode of the capacitor 100b to one of the source electrode and the drain electrode of the transistor 200b.

[0550] Note that the conductive layer 220a can be provided without providing the conductive layer 215a in an opening that reaches the conductive layer 120 of the capacitor 100a. Similarly, the conductive layer 220b can be provided without providing the conductive layer 215b in an opening that reaches the conductive layer 120 of the capacitor 100b. This eliminates the need to provide the conductive layer 215a and the conductive layer 215b, thereby reducing the number of steps.

[0551] The insulating layer 140 can be made of an insulating material that can be used for the insulating layer 210 .

[0552] Since the insulating layer 180 functions as an interlayer film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low dielectric constant can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. Note that the insulating layer 180 can use an insulating material that can be used for the insulating layer 280, or the like.

[0553] The insulating layer 181 can be made of an insulating material that can be used for the insulating layer 180 .

[0554] The insulating layer 185 can be formed as a single layer or a stacked layer using any of the insulating materials described in the section [Insulating Layer] of Embodiment 1. For example, a barrier insulating layer against hydrogen is preferably used for the insulating layer 185. With such a structure, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0555] The conductive layer 215a and the conductive layer 215b can be formed as a single layer or a stacked layer using any of the conductive materials described in the section [Conductive Layer] in Embodiment 1.

[0556] 31A illustrates components of the transistor 200a and the transistor 200b. The description of the transistor 200a and the transistor 200b in Embodiment 1 ( FIG. 4A ) can be referred to, and detailed description thereof will be omitted. The transistor included in the memory cell 150 is not limited to the transistor 200, and any of the transistors exemplified in Embodiment 1 can be applied.

[0557] As shown in FIGS. 31A and 31B, the conductive layers 220a and 220b are provided in an island shape.

[0558] As shown in FIG. 31C , the transistor 200a is provided so as to overlap with the capacitor 100a. Furthermore, an opening 290 in which part of the structure of the transistor 200a is provided has a region overlapping with an opening 190a in which part of the structure of the capacitor 100a is provided. With this configuration, the transistor 200a and the capacitor 100a can be provided without significantly increasing the occupied area in a plan view. The same applies to the arrangement of the transistor 200b and the capacitor 100b. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0559] 31B and 31C show an example in which the width of opening 190a is smaller than the width of opening 290. There are no particular limitations on the size relationship between the width of opening 190a and the width of opening 290. From the viewpoint of miniaturization, it is preferable that the width of opening 190a is smaller than the width of opening 290. The same applies to the size relationship between the width of opening 190b and the width of opening 290.

[0560] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0561] Fig. 31D shows a circuit diagram of the memory device shown in Fig. 31A to Fig. 31C. As shown in Fig. 31D, the configuration shown in Fig. 31A to Fig. 31C functions as two memory cells.

[0562] One of the source and drain of the transistor 200a is connected to one of the pair of electrodes of the capacitor 100a, the other of the source and drain of the transistor 200a is connected to the wiring BILa, a first gate of the transistor 200a is connected to the wiring WOL, and a second gate of the transistor 200a is connected to the wiring BGL. The other of the pair of electrodes of the capacitor 100a is connected to the wiring CAL.

[0563] One of the source and drain of the transistor 200b is connected to one of a pair of electrodes of the capacitor 100b, the other of the source and drain of the transistor 200b is connected to a wiring BILb, a first gate of the transistor 200b is connected to a wiring WOL, and a second gate of the transistor 200b is connected to a wiring BGL. The other of the pair of electrodes of the capacitor 100b is connected to a wiring CAL.

[0564] Here, the wiring BILa corresponds to the conductive layer 240a, the wiring BILb corresponds to the conductive layer 240b, the wiring WOL corresponds to the conductive layer 255, the wiring BGL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. Note that the wiring WOL and the wiring BGL can be interchanged. The conductive layer 260 may function as the wiring BGL, and the conductive layer 255 may function as the wiring WOL.

[0565] As shown in Figures 31A and 31C, it is preferable that the conductive layer 255 is provided extending in the X direction, and the conductive layers 240a and 240b are provided extending in the Y direction. With this configuration, the wiring BILa and wiring BILb and the wiring WOL are provided to intersect with each other. Also, in Figures 31B and 31C, the wiring CAL is provided parallel to the wiring WOL. Note that the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring BILa and wiring BILb, for example. Also, in Figures 31A and 31C, the wiring BGL is provided extending in the Y direction. Note that the present invention is not limited to this. The wiring BGL may be provided extending in the X direction.

[0566] The memory cells will be described in detail in a later embodiment.

[0567] [Capacitor 100] The capacitor 100a includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0568] The conductive layer 110 functions as wiring CAL and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0569] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0570] The conductive layer 115 has a region 101 with rounded corners within the recess of the conductive layer 110. This allows for more suppression of electric field concentration in the insulating layer 130 near the region 101 than, for example, when the region 101 has a corner (right angle or acute angle) in a cross-sectional view. Furthermore, the end 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface of the insulating layer 180. This allows for more suppression of electric field concentration in the insulating layer 130 near the end 103 than when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 prevents dielectric breakdown of the insulating layer 130, thereby providing a highly reliable memory device. The reference plane can be the top surface of the substrate, the top surface of the insulating layer 140, or the like.

[0571] The conductive layer 115 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. The conductive layer 115 is preferably formed as a single layer or a stacked layer using a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layer 115 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layer 115 from being oxidized.

[0572] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to contact the upper surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 is preferably structured to cover the side edges of the conductive layer 115. This can prevent the conductive layer 115 and the conductive layer 120 from shorting out.

[0573] Alternatively, a structure may be used in which the side edges of the insulating layer 130 coincide with the side edges of the conductive layer 115. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0574] It is preferable to use a material with a high relative dielectric constant for the insulating layer 130. By using a material with a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current and also ensure sufficient capacitance of the capacitive element 100a.

[0575] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternati...

Claims

first and second oxide semiconductor layers, first to fourth insulating layers, and first to fifth conductive layers; the first conductive layer and the second conductive layer are provided on the first insulating layer and spaced apart from each other; the second insulating layer is located on the first conductive layer and on the second conductive layer; the third conductive layer is located on the second insulating layer; the third insulating layer is located on the second insulating layer and on the third conductive layer; the fourth conductive layer and the fifth conductive layer are provided on the third insulating layer and spaced apart from each other; the third insulating layer, the third conductive layer, and the second insulating layer have a first opening; the first opening has a portion overlapping the first conductive layer, a portion overlapping the second conductive layer, and a portion overlapping the first insulating layer located between the first conductive layer and the second conductive layer; the fourth insulating layer covers a side surface of the first opening; the first oxide semiconductor layer has a region facing the third conductive layer with the fourth insulating layer sandwiched therebetween in the first opening, a region in contact with the first conductive layer in the first opening, and a region in contact with the fourth conductive layer outside the first opening; the second oxide semiconductor layer has a region facing the third conductive layer with the fourth insulating layer sandwiched therebetween in the first opening, a region in contact with the second conductive layer in the first opening, and a region in contact with the fifth conductive layer outside the first opening. 　 In claim 1, the fourth insulating layer in the first opening has a circular shape in a plan view, the first oxide semiconductor layer and the second oxide semiconductor layer in the first opening each have an arc shape in a plan view. 　 In claim 1, the first conductive layer has a recess overlapping the first opening; the fourth insulating layer is in contact with a side surface of the recessed portion, the first oxide semiconductor layer is in contact with at least a portion of a bottom surface of the recess. 　 In claim 3, the first conductive layer includes a first layer and a second layer on the first layer; The second layer has the recess. 　 In claim 1, the fourth insulating layer is in contact with a part of a side surface of the fourth conductive layer on the first opening side, the first oxide semiconductor layer is in contact with another part of the side surface of the fourth conductive layer on the first opening side. 　 In claim 5, the fourth insulating layer is in contact with a part of a side surface of the first conductive layer on the side of the first opening, the first oxide semiconductor layer is in contact with another part of the side surface of the first conductive layer on the first opening side. 　 In claim 1, the first oxide semiconductor layer is in contact with the first insulating layer in the first opening. 　 In claim 1, an outer end of the first oxide semiconductor layer on the first opening side is located closer to the first opening side than an outer end of the fourth conductive layer on the first opening side. 　 In claim 1, a fifth insulating layer and a sixth conductive layer; the fifth insulating layer is located on the first oxide semiconductor layer and the second semiconductor layer; the sixth conductive layer has, in the first opening, a region facing the third conductive layer with the fourth insulating layer, the first oxide semiconductor layer, and the fifth insulating layer sandwiched therebetween, and a region facing the third conductive layer with the fourth insulating layer, the second oxide semiconductor layer, and the fifth insulating layer sandwiched therebetween. 　 In claim 9, a bottom surface of a portion of the sixth conductive layer located between the first conductive layer and the second conductive layer is located closer to the first insulating layer than an upper surface of a portion of the first conductive layer that does not overlap with the first opening. 　 In claim 9, a sixth insulating layer and a seventh conductive layer; the sixth insulating layer is located on the fifth insulating layer and has a second opening at a position overlapping the first opening; the sixth conductive layer has a region located within the second opening; The seventh conductive layer is disposed on the sixth insulating layer and has a region in contact with the sixth conductive layer. 　 A semiconductor device comprising: a semiconductor device according to any one of claims 1 to 11; and a capacitive element; one of a pair of electrodes of the capacitor is electrically connected to the first conductive layer. 　 A semiconductor device comprising: a semiconductor device according to any one of claims 1 to 11; and a capacitive element; the other of the pair of electrodes of the capacitor is electrically connected to the fourth conductive layer.

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