Semiconductor device

Abstract

A semiconductor device (100) comprises a cooler (10), a base plate (20), a circuit board (30), a semiconductor element (40), a case (60), an adhesive layer (64), and a bolt (70). The cooler has an upper surface (10a) in which a screw hole (10b) is formed. The base plate has a first main surface (20a) and a second main surface (20b). The base plate is disposed on the cooler such that the first main surface faces the upper surface. The circuit board has a base material (31), a first conductor pattern (32), and a second conductor pattern (33). The base material has a third main surface (31a) and a fourth main surface (31b). The first conductor pattern and the second conductor pattern are disposed on the third main surface and the fourth main surface, respectively. The circuit board is disposed on the base plate such that the first conductor pattern faces the second main surface. The semiconductor element is disposed on the second conductor pattern.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] For example, Japanese Patent Laid-Open No. 2021-072326 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a cooler, a heat dissipation member, a circuit board, and a semiconductor element. The heat dissipation member is disposed on the cooler. The circuit board is disposed on the heat dissipation member. The semiconductor element is disposed on the circuit board.

[0003] Japanese Patent Application Laid-Open No. 2021-072326

[0004] In the semiconductor device described in Patent Document 1, when a heat dissipation member made of graphite is fixed to a cooler, stress may be applied to the heat dissipation member due to, for example, a difference in the linear expansion coefficient between the heat dissipation member and the cooler, which may result in a deterioration in the function of the heat dissipation member. The present disclosure has been made in view of such problems in the prior art. More specifically, the present disclosure provides a semiconductor device that can suppress a deterioration in the function of the base plate.

[0005] The semiconductor device according to the present disclosure comprises a cooler, a base plate, a circuit board, a semiconductor element, a case, an adhesive layer, and bolts. The cooler has an upper surface on which a screw hole is formed. The base plate has a first main surface and a second main surface opposite the first main surface. The base plate is disposed on the cooler so that the first main surface faces the upper surface. The circuit board has a substrate and a first conductor pattern and a second conductor pattern. The substrate has a third main surface and a fourth main surface opposite the third main surface. The first conductor pattern and the second conductor pattern are disposed on the third and fourth main surfaces, respectively. The circuit board is disposed on the base plate so that the first conductor pattern faces the second main surface. The semiconductor element is disposed on the second conductor pattern. The case has side walls, an upper wall, and a protruding portion. The side walls have a lower end and an upper end, and are bonded to the base plate at the lower end by an adhesive layer. The upper wall is continuous with the upper end so as to define the internal space of the case. The protrusion protrudes from the outer wall surface of the side wall at the lower end. A through hole is formed in the protrusion so as to overlap with the screw hole in a plan view. A bolt is passed through the through hole and threaded into the screw hole.

[0006] According to the semiconductor device according to the present disclosure, it is possible to suppress the degradation of the functionality of the base plate.

[0007] 1 is a schematic cross-sectional view of the semiconductor device 100. FIG. 2 is a schematic cross-sectional view of the semiconductor device 200. FIG. 3 is a simulation result showing the relationship between the value obtained by dividing the second thermal conductivity by the first thermal conductivity and the heat dissipation performance of the semiconductor device 100.

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] First Embodiment A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0010] (Configuration of Semiconductor Device 100) The configuration of the semiconductor device 100 will be described below.

[0011] Fig. 1 is a schematic cross-sectional view of a semiconductor device 100. As shown in Fig. 1, the semiconductor device 100 includes a cooler 10, a base plate 20, a circuit board 30, a semiconductor element 40, electrodes 50 and 51, bonding wires 52, a case 60, bolts 70, and a sealing material 80.

[0012] The cooler 10 has an upper surface 10a. A screw hole 10b is formed in the upper surface 10a. The cooler 10 is made of a metal material with high thermal conductivity. An example of the material of the cooler 10 is an aluminum alloy.

[0013] The base plate 20 has a main surface 20a, a main surface 20b, and a side surface 20c. The main surface 20b is the surface opposite to the main surface 20a. The normal direction of the main surface 20a is defined as a first direction DR1, and the direction perpendicular to the first direction DR1 is defined as a second direction DR2. The main surface 20a and the main surface 20b form both end surfaces of the base plate 20 in the first direction DR1 (i.e., in the thickness direction of the base plate 20). The side surface 20c is a surface of the base plate 20 that is continuous with the main surface 20a and the main surface 20b.

[0014] The base plate 20 is disposed on the cooler 10. More specifically, the base plate 20 is disposed on the cooler 10 so that the main surface 20b faces the top surface 10a. A heat transfer layer 11 is interposed between the top surface 10a and the main surface 20b. The heat transfer layer 11 is preferably made of a resin material with high thermal conductivity. The heat transfer layer 11 may contain a filler to improve thermal conductivity. A specific example of the heat transfer layer 11 is silicone grease. When the base plate 20 is disposed on the cooler 10, the screw hole 10b is located outside the base plate 20 in a plan view (i.e., when viewed along the first direction DR1).

[0015] The base plate 20 is, for example, an anisotropic base plate. However, the base plate 20 does not have to be an anisotropic base plate. The thermal conductivity of the base plate 20 in the first direction DR1 (i.e., the thermal conductivity of the base plate 20 in the thickness direction) is defined as the first thermal conductivity. The thermal conductivity of the base plate 20 in the second direction DR2 (i.e., the thermal conductivity of the base plate 20 in the in-plane direction) is defined as the second thermal conductivity. The second thermal conductivity is, for example, higher than the first thermal conductivity. It is preferable that the second thermal conductivity be no more than twice the first thermal conductivity.

[0016] The linear expansion coefficient of the base plate 20 in the first direction DR1 (i.e., the linear expansion coefficient of the base plate 20 in the thickness direction) is defined as the first linear expansion coefficient. The linear expansion coefficient of the base plate 20 in the second direction DR2 (i.e., the linear expansion coefficient of the base plate 20 in the in-plane direction) is defined as the second linear expansion coefficient. The second linear expansion coefficient is, for example, smaller than the first linear expansion coefficient. The second linear expansion coefficient is preferably smaller than the first linear expansion coefficient and 10 ppm / °C or less. The bending strength of the base plate 20 is preferably 100 MPa or more.

[0017] The base plate 20 is made of a composite material such as a metal matrix composite (MMC). The MMC constituting the base plate 20 is, for example, an aluminum alloy MMC. The base plate 20 is manufactured by a method described in Japanese Patent No. 7382105. If the base plate 20 is not an anisotropic base plate, the base plate 20 is made of, for example, copper.

[0018] The circuit board 30 has a base material 31. The base material 31 has a main surface 31a and a main surface 31b. The main surface 31b is the surface opposite to the main surface 31a. The main surface 31a and the main surface 31b form both end surfaces of the base material 31 in the thickness direction (i.e., in the first direction DR1). The base material 31 is made of an electrically insulating material. The base material 31 is made of, for example, ceramics.

[0019] The circuit board 30 further includes a conductor pattern 32 and a conductor pattern 33. The conductor pattern 32 is disposed on the main surface 31a. The conductor pattern 33 is disposed on the main surface 31b. The conductor pattern 33 includes, for example, a first portion 33a and a second portion 33b. The first portion 33a and the second portion 33b are electrically isolated from each other. The conductor patterns 32 and 33 are made of a conductive material such as a metal material. The conductor patterns 32 and 33 are made of, for example, copper or a copper alloy.

[0020] The circuit board 30 is disposed on the base plate 20. More specifically, the circuit board 30 is disposed on the base plate 20 so that the conductor pattern 32 faces the main surface 20b. A bonding material 34 is interposed between the conductor pattern 32 and the main surface 20b, and the conductor pattern 32 is bonded to the main surface 20b by the bonding material 34. The constituent material of the bonding material 34 is, for example, a brazing material, a solder alloy, or a sintered body containing silver particles or copper particles.

[0021] The semiconductor element 40 is, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a Schottky barrier diode (SBD), a diode, etc. The semiconductor element 40 has a semiconductor substrate. The semiconductor substrate is made of, for example, silicon. The semiconductor substrate may also be made of silicon carbide. The semiconductor element 40 has a main surface 40a and a main surface 40b. The main surface 40b is the surface opposite to the main surface 40a. The main surface 40a and the main surface 40b form both end surfaces of the semiconductor element 40 in the thickness direction (i.e., in the first direction DR1).

[0022] The semiconductor element 40 has an electrode 41 on its principal surface 40a and an electrode 42 on its principal surface 40b. The semiconductor element 40 is disposed on the first portion 33a so that the principal surface 40a (i.e., the electrode 41) faces the first portion 33a. A bonding material 43 is interposed between the first portion 33a and the electrode 41, and the first portion 33a is bonded to the electrode 41 by the bonding material 43. This electrically connects the semiconductor element 40 to the first portion 33a. The constituent material of the bonding material 43 is, for example, a solder alloy or a sintered body containing silver particles or copper particles.

[0023] The electrode 50 and the electrode 51 are bonded to the first portion 33a and the second portion 33b, respectively, by, for example, a bonding material 53. As a result, the electrode 50 is electrically connected to the first portion 33a, and the electrode 51 is electrically connected to the second portion 33b. The constituent materials of the electrodes 50 and 51 are, for example, copper or a copper alloy. The constituent material of the bonding material 53 is, for example, a solder alloy or a sintered body containing silver particles or copper particles. The bonding wire 52 is bonded to the electrode 42 at one end and to the second portion 33b at the other end. As a result, the semiconductor element 40 is also electrically connected to the second portion 33b. The constituent material of the bonding wire 52 is, for example, aluminum.

[0024] The case 60 has a side wall 61, an upper wall 62, and a protrusion 63. The side wall 61 extends along a first direction DR1. The side wall 61 has a lower end 61a and an upper end 61b in the first direction DR1. The upper end 61b is the end opposite the lower end 61a. The main surface 20b is adhered to the inner wall surface of the side wall 61 at the lower end 61a by an adhesive layer 64. The inner wall surface at the lower end 61a faces the side surface 20c. The adhesive layer 64 is made of, for example, an adhesive.

[0025] The upper wall 62 is continuous with the upper end portion 61b so as to close the internal space of the case 60. The upper wall 62 is formed with a through hole 62a and a through hole 62b. The electrode 50 is led out to the outside of the case 60 through the through hole 62a, and the electrode 51 is led out to the outside of the case 60 through the through hole 62b.

[0026] The protrusions 63 protrude from the outer wall surface of the side wall 61 at the lower end 61a. The protrusions 63 are located, for example, at the four corners of the case 60 in a plan view. A through hole 63a is formed in the protrusion 63. The through hole 63a penetrates the protrusion 63 along the first direction DR1. The through hole 63a is located at a position overlapping the screw hole 10b in a plan view. A bushing 65 may be inserted into the through hole 63a. The bushing 65 is made of, for example, a metal material. The bolt 70 is passed through the through hole 63a (and the bushing 65) and then threaded into the screw hole 10b. This attaches the case 60 to the cooler 10.

[0027] From another perspective, the base plate 20 is not bolted to the cooler 10 and is not fixed to the cooler 10. When the semiconductor device 100 is assembled (i.e., when the case 60 is fixed to the cooler 10 with the bolts 70), the stress applied to the main surface 20a is preferably 0.5 MPa or more, and the bending stress applied to the base plate 20 is preferably 100 MPa or less.

[0028] The sealing material 80 fills the space defined by the inner wall surface and main surface 20b of the case 60. The sealing material 80 does not need to completely fill the space defined by the inner wall surface and main surface 20b of the case 60. The sealing material 80 seals the circuit board 30, the semiconductor element 40, the electrodes 50, 51, and the bonding wires 52. However, the electrodes 50 and 51 may be partially exposed from the sealing material 80. The constituent material of the sealing material 80 is an electrically insulating gel material or resin material.

[0029] In the above example, the semiconductor device 100 has one base plate 20 and one circuit board 30. Even when the semiconductor device 100 has multiple base plates 20 and multiple circuit boards 30, it is preferable that one circuit board 30 is disposed on one base plate 20. This makes it possible to mount multiple circuit boards 30 (semiconductor elements 40) on one semiconductor device 100.

[0030] (Method of Manufacturing the Semiconductor Device 100) A method of manufacturing the semiconductor device 100 will be described below.

[0031] In the manufacturing process of the semiconductor device 100, first, the circuit board 30 is placed on the base plate 20 so that the main surface 20b and the conductor pattern 32 face each other with the bonding material 34 interposed therebetween. Second, the semiconductor element 40 is placed so that the electrode 41 and the first portion 33a face each other with the bonding material 43 interposed therebetween. At this time, the electrodes 50 and 51 are also placed so that the electrodes 50 and 51 face the first portion 33a and the second portion 33b, respectively, with the bonding material 53 interposed therebetween. Third, heating is performed to bond the main surface 20b and the conductor pattern 32 with the bonding material 34, the electrode 41 and the first portion 33a with the bonding material 43, the electrode 50 and the first portion 33a with the bonding material 53, and the electrode 51 and the second portion 33b with the bonding material 53. Note that pressure may be applied during the heating process, if necessary.

[0032] Fourth, wire bonding is performed to bond electrode 42 to one end of bonding wire 52 and second portion 33b to the other end of bonding wire 52. Fifth, adhesive layer 64 is used to attach case 60 to base plate 20. Sixth, uncured sealant 80 is poured into the space defined by the inner wall surface and main surface 20b of case 60, and the poured sealant 80 is heated and cured. Seventh, a heat transfer layer 11 is interposed between main surface 20a and top surface 10a, and bolts 70 are passed through through holes 63a and screwed into threaded holes 10b, thereby fixing case 60 to cooler 10. As described above, the structure of semiconductor device 100 shown in FIG. 1 is formed.

[0033] (Effects of the Semiconductor Device 100) The effects of the semiconductor device 100 will be described below in comparison with a semiconductor device according to a comparative example.

[0034] 2 is a schematic cross-sectional view of a semiconductor device 200. As shown in FIG. 2, the semiconductor device 200 includes a cooler 10, a circuit board 30, a semiconductor element 40, electrodes 50 and 51, bonding wires 52, a case 60, bolts 70, and a sealing material 80. In this respect, the configuration of the semiconductor device 200 is common to the configuration of the semiconductor device 100.

[0035] The semiconductor device 200 has a base plate 21 instead of the base plate 20. The base plate 21 has a main surface 21a and a main surface 21b. The main surface 21a faces the upper surface 10a with the heat transfer layer 11 therebetween, and the main surface 21b faces the conductive pattern 32 with the bonding material 34 therebetween. A through hole 21c is formed in the main surface 21b. The base plate 21 may or may not be an anisotropic base plate.

[0036] In the semiconductor device 200, the case 60 does not have a protrusion 63. Furthermore, in the semiconductor device 200, the lower end 61a is in contact with the main surface 21b, and the inner wall surface of the side wall 61 at the lower end 61a is adhered to the main surface 21b by an adhesive layer 64. In the semiconductor device 200, the bolt 70 is passed through the through hole 21c and then screwed into the screw hole 10b. In these respects, the configuration of the semiconductor device 200 differs from the configuration of the semiconductor device 100.

[0037] In the semiconductor device 200, the base plate 21 is fixed to the cooler 10. Therefore, stress caused by temperature differences and differences in thermal expansion coefficients between the base plate 21 and the cooler 10 is easily applied to the base plate 21. Therefore, there is a risk of the base plate 21 being damaged, particularly if the material constituting the base plate 21 has weak mechanical strength. On the other hand, in the semiconductor device 100, the base plate 20 is not fixed to the cooler 10 (it is only in contact with the cooler 10 via the heat transfer layer 11), so stress is less likely to be applied to the base plate 20. Therefore, even if the base plate 20 is an anisotropic base plate with weak mechanical strength, damage to the base plate 20 (deterioration of the function of the base plate 20) is suppressed.

[0038] 3 shows the results of a simulation showing the relationship between the value obtained by dividing the second thermal conductivity by the first thermal conductivity and the heat dissipation performance of the semiconductor device 100. The horizontal axis in FIG. 3 represents the value obtained by dividing the second thermal conductivity by the first thermal conductivity. The vertical axis in FIG. 3 represents the maximum temperature T on the surface of the semiconductor element 40. ｊ , the maximum temperature on the main surface 20b is T ｃ When the heat generation amount of the semiconductor element 40 is W, (T ｊ -T ｃ ) / W (unit: °C / watt). As shown in FIG. 3, when the value obtained by dividing the second thermal conductivity by the first thermal conductivity exceeds 2, (T ｊ -T ｃ ) / W increases, which deteriorates the heat dissipation performance of the semiconductor device 100. Therefore, by setting the value obtained by dividing the second thermal conductivity by the first thermal conductivity to 2 or less, the thermal resistance of the semiconductor device 100 is optimized, and the heat dissipation performance can be further improved.

[0039] When the second linear expansion coefficient is smaller than the first linear expansion coefficient and is 10 ppm / ° C. or less, the linear expansion coefficient of the base plate 20 becomes close to the linear expansion coefficient of the circuit board 30. Therefore, in this case, it is possible to reduce the thermal stress applied to the bonding material 34 due to the difference in the linear expansion coefficients between the base plate 20 and the circuit board 30, and it is possible to improve the heat cycle life of the semiconductor device 100.

[0040] When a semiconductor device 100 has multiple base plates 20 and circuit boards 30, and one circuit board 30 is arranged on one base plate 20 (one base plate 20 and one circuit board 30 form a pair), it is possible to mount multiple semiconductor elements 40 on one semiconductor device 100, and it is possible to increase the capacity of the semiconductor device 100.

[0041] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0042] 100 semiconductor device, 10 cooler, 10a upper surface, 10b screw hole, 11 heat transfer layer, 20 base plate, 20a, 20b main surface, 20c side surface, 21 base plate, 21a, 21b main surface, 21c through hole, 30 circuit board, 31 substrate, 31a, 31b main surface, 32 conductor pattern, 33 conductor pattern, 33a first portion, 33b second portion, 34 bonding material, 40 semiconductor element, 40a, 40b main surface, 41 electrode, 42 electrode, 43 bonding material, 50, 51 electrode, 52 bonding wire, 53 bonding material, 60 case, 61 side wall, 61a lower end, 61b upper end, 62 upper wall, 62a, 62b through hole, 63 protrusion, 63a through hole, 64 Adhesion layer, 65 bushing, 70 bolt, 80 encapsulant, 200 semiconductor device, DR1 first direction, DR2 second direction.

Claims

1. A semiconductor device comprising: a cooler; a base plate; a circuit board; a semiconductor element; a case; an adhesive layer; and bolts; wherein the cooler has an upper surface on which a screw hole is formed; the base plate has a first main surface and a second main surface opposite to the first main surface; the base plate is placed on the cooler so that the first main surface faces the upper surface; the circuit board has a substrate, a first conductor pattern, and a second conductor pattern; the substrate has a third main surface and a fourth main surface opposite to the third main surface; the first conductor pattern and the second conductor pattern are placed on the third main surface and the fourth main surface, respectively; the circuit board is placed on the base plate so that the first conductor pattern faces the second main surface; the semiconductor element is placed on the second conductor pattern; and the case has side walls, an upper wall, and a protrusion. a semiconductor device, wherein the side wall has a lower end and an upper end, and is adhered to the base plate at the lower end with the adhesive layer; the upper wall is connected to the upper end so as to define an internal space of the case; the protrusion protrudes from an outer wall surface of the side wall at the lower end; a through hole is formed in the protrusion so as to overlap the screw hole in a planar view; and the bolt is passed through the through hole and screwed into the screw hole.

2. The semiconductor device according to claim 1, wherein the stress applied to said first main surface is 0.5 MPa or more.

3. The semiconductor device according to claim 1 or 2, wherein the base plate is an anisotropic base plate.

4. The semiconductor device described in claim 3, wherein the thermal conductivity of the anisotropic base plate in a direction perpendicular to the normal direction of the first main surface is not more than twice the thermal conductivity of the anisotropic base plate in the normal direction of the first main surface.

5. A semiconductor device as described in claim 3 or claim 4, wherein the linear expansion coefficient of the anisotropic base plate in a direction perpendicular to the normal direction of the first main surface is smaller than the linear expansion coefficient of the anisotropic base plate in the normal direction of the first main surface and is 10 ppm / °C or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein one of the circuit boards is disposed on one of the base plates.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor element has a semiconductor substrate, and the semiconductor substrate is made of silicon carbide.

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