Light detection device and electronic apparatus

Abstract

A light detection device includes a plurality of pixels, a plurality of floating diffusions, and a first amplification transistor. Each pixel includes a photoelectric conversion unit and a transfer transistor. The plurality of pixels include a first small pixel group, a second small pixel group, and a third small pixel group. The plurality of floating diffusions hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group. The first amplification transistor amplifies a signal voltage corresponding to a charge held in one or more of the floating diffusions. A first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group. The second small pixel group is positioned between the first region and a third small pixel group.

Description

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

[0001] The present technology relates to a light detection device and an electronic apparatus, and for example, relates to a light detection device and an electronic apparatus that can be further downsized.

[0002] <CROSS REFERENCE TO RELATED APPLICATIONS> This application claims the benefit of Japanese Priority Patent Application JP 2024-021778 filed on February 16, 2024, the entire contents of which are incorporated herein by reference.

[0003] It has been proposed that an image pickup element such as a complementary metal oxide semiconductor (CMOS) image sensor is further downsized by sharing a floating diffusion (FD) (see, for example, PTL 1).

[0004] WO 2016 / 158439 A

[0005] In a case where the size of the image pickup element is further reduced, it is necessary to reduce the size of the transistor, and there is a possibility that characteristics of the transistor are deteriorated. It is desired that the image pickup element is further miniaturized and characteristics are not degraded even in a case where the image pickup element is miniaturized.

[0006] The present disclosure has been made in view of such a situation, and an object thereof is to further downsize a light detection device such as an imaging device.

[0007] According to an embodiment of the present disclosure, there is provided a light detection device including a plurality of pixels. Each pixel includes a photoelectric conversion unit and a transfer transistor. The plurality of pixels includes a first small pixel group, a second small pixel group, and a third small pixel group. The light detection device also includes a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group. The light detection device also includes a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions. A first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group. The second small pixel group is positioned between the first region and a third small pixel group. Aspects include wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes the first small pixel group and the second small pixel group, and the first region is arranged in a central region of the large pixel group. Aspects include wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a one-by-four grid, and the first region is arranged between the first large pixel group and a second large pixel group. Aspects include wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a four-by-one grid, and the first region is arranged between the first large pixel group and a second large pixel group. Aspects include wherein each small pixel group includes four floating diffusions connected to a floating diffusion provided in the first region, and the floating diffusion provided in the first region is shared by 16 pixels included in a large pixel group. Aspects include wherein the first small pixel group, the first region, and the second small pixel group are included in a first large pixel group, and the third small pixel group is included in a second large pixel group adjacent to the first large pixel group. Aspects include wherein the transfer transistor includes an electrode in the photoelectric conversion unit. Aspects include wherein a region in which P-type or N-type impurities are diffused is provided between transfer transistors of two or more pixels. Aspects include wherein an oxide film is provided between transfer transistors of two or more pixels. Aspects include wherein the transfer transistor includes an electrode in contact with the oxide film. Aspects include wherein the first region includes an element separation portion including an oxide film. Aspects include wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided across a first large pixel group and across a second large pixel group, and each small pixel group includes four floating diffusions connected by a respective linear wire to a floating diffusion provided in the first region. Aspects include wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided in a large pixel group, and each small pixel group includes four floating diffusions connected by a respective wire to a floating diffusion provided in the first region, wherein one of the respective wires has a bent portion. Aspects include wherein a first distance between a center of the first small pixel group and a center of the second small pixel group differs from a second distance between the center of the second small pixel group and a center of the third small pixel group. Aspects include wherein the second small pixel group is adjacent to the third small pixel group. Aspects include the light detection device further including a second region including a second amplification transistor positioned between the third small pixel group and a fourth small pixel group, and wherein the second amplification transistor is configured to amplify a signal voltage corresponding to a charge held in a floating diffusion associated with the third small pixel group. Aspects include wherein a first large pixel group includes the first small pixel group and a fourth small pixel group; a second large pixel group includes the second small pixel group and a fifth small pixel group; each of the first, second, fourth, and fifth small pixel groups include four pixels; each pixel of the first large pixel group shares one or more floating diffusions; each pixel of the second large pixel group shares one or more floating diffusions; and the first large pixel group is separated from the second large pixel group by the first region. According to an embodiment of the present disclosure, there is provided an electronic apparatus including a light detection device. The light detection device including a plurality of pixels. Each pixel including a photoelectric conversion unit and a transfer transistor. The plurality of pixels including a first small pixel group, a second small pixel group, and a third small pixel group. The light detection device further including a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group. The light detection device further including a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions. A first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group, and the second small pixel group is positioned between the first region and a third small pixel group. A light detection device according to an aspect of the present technology includes a pixel including a photoelectric conversion unit, a charge holding unit that holds a charge generated by the photoelectric conversion unit, a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit, in which the charge holding unit is shared by four of the pixels and is arranged at a center of four of the transfer units, a first small pixel group including a first of the charge holding units, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including a second of the charge holding units, and a third small pixel group including a third of the charge holding units are arranged in this order, and a first distance between the first charge holding unit and the second charge holding unit is different from a second distance between the second charge holding unit and the third charge holding unit.

[0008] An electronic apparatus according to an aspect of the present technology includes a light detection device including a pixel including a photoelectric conversion unit, a charge holding unit that holds a charge generated by the photoelectric conversion unit, a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit, in which the charge holding unit is shared by four of the pixels and is arranged at a center of four of the transfer units, a first small pixel group including a first of the charge holding units, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including a second of the charge holding units, and a third small pixel group including a third of the charge holding units are arranged in this order, and a first distance between the first charge holding unit and the second charge holding unit is different from a second distance between the second charge holding unit and the third charge holding unit, and a processing unit that processes a signal from the light detection device.

[0009] A light detection device according to an aspect of the present technology includes a pixel including a photoelectric conversion unit, a charge holding unit that holds a charge generated by the photoelectric conversion unit, a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit. The charge holding unit is shared by the four pixels and is arranged at the center of the four transfer units, a first small pixel group including a first charge holding unit, a first region in which a transistor including an amplification transistor is arranged, a second small pixel group including a second charge holding unit, and a third small pixel group including a third charge holding unit are arranged in this order, and a first distance between the first charge holding unit and the second charge holding unit is different from a second distance between the second charge holding unit and the third charge holding unit.

[0010] The electronic apparatus according to an aspect of the present technology includes the light detection device.

[0011] Note that the light detection device and the electronic apparatus may be independent devices, or may be internal blocks that constitute one device.

[0012] Fig. 1 is a view depicting a configuration example of an embodiment of a light detection device to which the present technology is applied.Fig. 2 is a view for describing a configuration example of a pixel group in the first embodiment.Fig. 3 is a view for describing a configuration example of a pixel group in the first embodiment.Fig. 4 is a view for describing arrangement of transistors.Fig. 5 is a view for describing a distance between FDs.Fig. 6 is a view for describing a distance between FDs.Fig. 7 is a view for describing a configuration example of a pixel group in the second embodiment.Fig. 8 is a view for describing a configuration example of a pixel group in the second embodiment.Fig. 9 is a view for describing a configuration example of a pixel group in the third embodiment.Fig. 10 is a view for describing a configuration example of a pixel group in the third embodiment.Fig. 11 is a view for describing a configuration example of a pixel group in the fourth embodiment.Fig. 12 is a view for describing a configuration example of a pixel group in the fourth embodiment.Fig. 13 is a view for describing a configuration example of a pixel group in the fifth embodiment.Fig. 14 is a view for describing a configuration example of a pixel group in the fifth embodiment.Fig. 15 is a view for describing a configuration example of a pixel group in the sixth embodiment.Fig. 16 is a view for describing a configuration example of a pixel group in the sixth embodiment.Fig. 17 is a view for describing a configuration example of a pixel group in the seventh embodiment.Fig. 18 is a view for describing a configuration example of a pixel group in the seventh embodiment.Fig. 19 is a view for describing arrangement of transistors.Fig. 20 is a view for describing a distance between FDs.Fig. 21 is a view for describing a configuration example of a pixel group in the eighth embodiment.Fig. 22 is a view for describing a configuration example of a pixel group in the eighth embodiment.Fig. 23 is a view for describing a configuration example of a pixel group in the ninth embodiment.Fig. 24 is a view for describing a configuration example of a pixel group in the ninth embodiment.Fig. 25 is a view for describing a configuration example of a pixel group in the tenth embodiment.Fig. 26 is a view for describing a configuration example of a pixel group in the tenth embodiment.Fig. 27 is a view for describing a configuration example of a pixel group in the eleventh embodiment.Fig. 28 is a view for describing a configuration example of a pixel group in the eleventh embodiment.Fig. 29 is a view for describing a configuration example of a pixel group in the twelfth embodiment.Fig. 30 is a view for describing a configuration example of a pixel group in the twelfth embodiment.Fig. 31 is a view for describing a configuration example of a pixel group in the thirteenth embodiment.Fig. 32 is a view for describing a configuration example of a pixel group in the thirteenth embodiment.Fig. 33 is a view for describing a configuration example of a pixel group in the fourteenth embodiment.Fig. 34 is a view for describing a configuration example of a pixel group in the fourteenth embodiment.Fig. 35 is a view for describing a configuration example of a pixel group in the fifteenth embodiment.Fig. 36 is a view for describing a configuration example of a pixel group in the fifteenth embodiment.Fig. 37 is a view for describing a configuration example of a pixel group in the sixteenth embodiment.Fig. 38 is a view for describing a configuration example of a pixel group in the sixteenth embodiment.Fig. 39 is a view for describing a configuration example of a pixel group in the seventeenth embodiment.Fig. 40 is a view for describing a configuration example of a pixel group in the seventeenth embodiment.Fig. 41 is a view for describing a configuration example of a pixel group in the eighteenth embodiment.Fig. 42 is a view for describing a configuration example of a pixel group in the eighteenth embodiment.Fig. 43 is a view for describing a configuration example of a pixel group in the nineteenth embodiment.Fig. 44 is a view for describing a configuration example of a pixel group in the nineteenth embodiment.Fig. 45 is a view for describing a configuration example of a pixel group in the twentieth embodiment.Fig. 46 is a view for describing a configuration example of a pixel group in the twentieth embodiment.Fig. 47 is a view for describing a configuration example of a pixel group in the twenty-first embodiment.Fig. 48 is a view for describing a configuration example of a pixel group in the twenty-first embodiment.Fig. 49 is a view for describing a configuration example of a pixel group in the twenty-second embodiment.Fig. 50 is a view for describing a configuration example of a pixel group in the twenty-second embodiment.Fig. 51 is a view for describing a configuration example of a pixel group in the twenty-third embodiment.Fig. 52 is a view for describing a configuration example of a pixel group in the twenty-third embodiment.Fig. 53 is a view for describing a configuration example of a pixel group in the twenty-fourth embodiment.Fig. 54 is a view for describing a configuration example of a pixel group in the twenty-fourth embodiment.Fig. 55 is a view for describing a configuration example of a pixel group in the twenty-fifth embodiment.Fig. 56 is a view for describing a configuration example of a pixel group in the twenty-fifth embodiment.Fig. 57 is a view for describing a configuration example of a pixel group in a twenty-sixth embodiment.Fig. 58 is a view for describing a configuration example of a pixel group in a twenty-sixth embodiment.Fig. 59 is a view for describing a configuration example of a pixel group in a twenty-seventh embodiment.Fig. 60 is a view for describing a configuration example of a pixel group in a twenty-seventh embodiment.Fig. 61 is a view for describing a configuration example of a pixel group in a twenty-eighth embodiment.Fig. 62 is a view for describing a configuration example of a pixel group in a twenty-eighth embodiment.Fig. 63 is a view for describing a configuration example of a pixel group in a twenty-ninth embodiment.Fig. 64 is a view for describing a configuration example of a pixel group in a twenty-ninth embodiment.Fig. 65 is a view for describing a configuration example of a pixel group in a thirtieth embodiment.Fig. 66 is a view for describing a configuration example of a pixel group in a thirtieth embodiment.Fig. 67 is a view for describing a configuration example of a pixel group in a thirty-first embodiment.Fig. 68 is a view for describing a configuration example of a pixel group in a thirty-first embodiment.Fig. 69 is a view for describing a configuration example of a pixel group in a thirty-second embodiment.Fig. 70 is a view for describing a configuration example of a pixel group in a thirty-second embodiment.Fig. 71 is a view for describing a configuration example of a pixel group in a thirty-third embodiment.Fig. 72 is a view for describing a configuration example of a pixel group in a thirty-third embodiment.Fig. 73 is a view for describing a configuration example of a pixel group in a thirty-fourth embodiment.Fig. 74 is a view for describing a configuration example of a pixel group in a thirty-fourth embodiment.Fig. 75 is a view for describing a configuration example of a pixel group in a thirty-fifth embodiment.Fig. 76 is a view for describing a configuration example of a pixel group in a thirty-fifth embodiment.Fig. 77 is a view for describing a configuration example of a pixel group in a thirty-sixth embodiment.Fig. 78 is a view for describing a configuration example of a pixel group in a thirty-sixth embodiment.Fig. 79 is a block diagram depicting a configuration example of an electronic apparatus.Fig. 80 is a view depicting an example of a schematic configuration of an endoscopic surgery system.Fig. 81 is a block diagram depicting an example of a functional configuration of a camera head and a camera control unit (CCU).Fig. 82 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 83 is a diagram of assistance in depicting an example of installation positions of an outside-vehicle information detecting section and an image pickup unit.

[0013] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0014] <Configuration example of imaging device> Fig. 1 depicts a configuration example in an embodiment of a light detection device to which the present technology is applied.

[0015] A light detection device 1 of Fig. 1 includes a pixel array unit 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit unit around the pixel array unit 3. The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0016] The pixel 2 includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors. The plurality of pixel transistors includes MOS transistors such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, for example.

[0017] The control circuit 8 receives data instructing an input clock, an operation mode and the like, and outputs data such as internal information about the light detection device 1. That is, the control circuit 8 generates a clock signal and a control signal which serve as a reference for operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like on the basis of a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

[0018] The vertical drive circuit 4 includes, for example, a shift register, selects a predetermined pixel drive line 10, supplies a pulse for driving the pixels 2 to the selected pixel drive line 10, and drives the pixels 2 in units of rows. That is, the vertical drive circuit 4 sequentially selects and scans the pixels 2 of the pixel array unit 3 in units of rows in a longitudinal direction and supplies a pixel signal based on a signal charge generated according to a received light amount by a photoelectric conversion unit of each of the pixels 2 to the column signal processing circuit 5 through a vertical signal line 9.

[0019] The column signal processing circuit 5 is arranged for each column of the pixels 2 performs the signal process such as noise removal on the signals output from the pixels 2 of one row for each pixel column. For example, the column signal processing circuit 5 performs the signal process such as correlated double sampling (CDS) or double data sampling (DDS) for removing pixel-specific fixed pattern noise, and AD conversion.

[0020] The horizontal drive circuit 6 including a shift register, for example, sequentially selects each of the column signal processing circuits 5 by sequentially outputting horizontal scanning pulses to output the pixel signal from each of the column signal processing circuits 5 to a horizontal signal line 11.

[0021] The output circuit 7 performs the signal process on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 to output the processed signals. For example, there is a case where the output circuit 7 performs only buffering, or a case where the output circuit 7 performs black level adjustment, column variation correction, various types of digital signal processes, and the like. An input / output terminal 13 communicates signals with the outside.

[0022] The light detection device 1 configured as described above is a CMOS image sensor called a column AD system in which the column signal processing circuit 5 that perform CDS processing, DDS processing, and AD conversion processing is arranged for each pixel column.

[0023] <First embodiment> Fig. 2 is a view depicting a planar configuration example of the pixel array unit 3 of the light detection device 1 according to the first embodiment, and Fig. 3 is a view depicting a cross-sectional configuration example taken along line A-A' in Fig. 2.

[0024] The pixel array unit 3 depicted in Fig. 2 depicts a portion including 16 pixels 2 of 4×4. In the first embodiment, the description will be continued by exemplifying a case where 16 pixels share a floating diffusion (FD).

[0025] A small pixel group 20 includes 4 pixels 2 of 2×2, and a large pixel group 50a includes 4 sets (4 units) of small pixel groups 20. The small pixel group 20-1 illustrated in the upper left part of the drawing includes a pixel 2-1, a pixel 2-2, a pixel 2-3, and a pixel 2-4. The small pixel group 20-2 illustrated in the upper right part of the drawing includes a pixel 2-5, a pixel 2-6, a pixel 2-7, and a pixel 2-8. The small pixel group 20-3 illustrated at the lower left in the drawing includes a pixel 2-9, a pixel 2-10, a pixel 2-11, and a pixel 2-12. The small pixel group 20-4 illustrated in the lower right of the drawing includes a pixel 2-13, a pixel 2-14, a pixel 2-15, and a pixel 2-16.

[0026] As illustrated in Fig. 3, each pixel 2 includes a photodiode (PD) 31, and has a configuration in which the charge accumulated in the PD 31 is transferred to the FD 23 by a transfer gate 22 of the transfer transistor.

[0027] The pixels 2-1 to 2-4 of the small pixel group 20-1 includes a PD 31-1 to a PD 31-4 (not illustrated), and include transfer gates 22-1 to 22-4, respectively. An FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0028] The pixels 2-5 to 2-8 of the small pixel group 20-2 includes a PD 31-5 to a PD 31-8 (not illustrated), and include transfer gates 22-5 to 22-8, respectively. An FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0029] The pixels 2-9 to 2-12 of the small pixel group 20-3 includes a PD 31-9 to a PD 31-12 (not illustrated), and include transfer gates 22-9 to 22-12, respectively. An FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0030] The pixels 2-13 to 2-16 of the small pixel group 20-4 includes a PD 31-13 to a PD 31-16 (not illustrated), and include transfer gates 22-13 to 22-16, respectively. An FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0031] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. The wire 40 is also connected to the FD 23-5 provided above the center of the large pixel group 50 in the drawing via a contact 24-5. Therefore, the FDs 23-1 to 23-5 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50. Hereinafter, in a case where it is not necessary to distinguish the FDs 23-1 to 23-5 individually or in a case where it is indicated that the FDs function as one FD, the FDs are simply referred to as the FDs 23.

[0032] A reset transistor 25 is provided above the FD 23-5 in the drawing, and the FD 23 is reset by the reset transistor 25.

[0033] An amplification transistor 26 is provided on the lower side in Fig. 2, and a contact 24-6 is provided at the gate of the amplification transistor 26. The contact 24-6 is connected to the wire 40. The FDs 23-1 to 23-5 are connected to the amplification transistor 26 via the wire 40.

[0034] The amplification transistor 26 has a transfer gate connected to the FD 23 and a drain connected to a power supply VDD 28, and serves as an input unit of a readout circuit that reads a signal corresponding to the charge held in the FD 23, a so-called source follower circuit. That is, the amplification transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via a selection transistor 27, so that it is possible to constitute a source follower circuit together with a constant current source (not illustrated) connected to one end of the vertical signal line 9.

[0035] As illustrated in Fig. 2, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 are arranged in a line in the longitudinal direction at the central portion of the large pixel group 50. A contact connected to the power supply VDD 28 and a contact connected to the vertical signal line 9 (VSL region 29) are also arranged in a line in the longitudinal direction together with the transistor at the central portion of the large pixel group 50.

[0036] The description of the cross-sectional configuration example taken along line A-A' in Fig. 2 will be continued with reference to Fig. 3. The pixel 2-11, the pixel 2-12, the amplification transistor 26, the pixel 2-15, and the pixel 2-16 taken along line A-A' are arranged in this order. In Fig. 3, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side. An inter-pixel separation portion 32-11 for separating from the pixel 2 (not illustrated) is provided left of the PD 31-11, and an inter-pixel separation portion 32-12 for separating from the PD 31-12 is provided right of the PD 31-11.

[0037] An inter-pixel separation portion 32-13 is provided between the PD 31-12 and the PD 31-15, an inter-pixel separation portion 32-14 is provided between the PD 31-15 and the PD 31-16, and an inter-pixel separation portion 32-15 is provided between the PD 31-16 and the PD 31 (not illustrated) of the adjacent pixel 2. The inter-pixel separation portion 32 can include an oxide film.

[0038] Above the inter-pixel separation portion 32-11 in the drawing, a cell well 35-11 and a FLAT separation portion 33-11 are provided. Above the inter-pixel separation portion 32-12 in the drawing, a cell well 35-12 and a FLAT separation portion 33-12 are provided. Above the inter-pixel separation portion 32-13 in the drawing, the cell well 35-13 is provided and above the cell well 35-13 in the drawing, a FLAT separation portion 33-13, a channel region 37 of the amplification transistor 26, and a FLAT separation portion 33-14 are provided.

[0039] Above the inter-pixel separation portion 32-14 in the drawing, a cell well 35-14 and a FLAT separation portion 33-15 are provided. Above the inter-pixel separation portion 32-15 in the drawing, a cell well 35-15 and a FLAT separation portion 33-16 are provided.

[0040] The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other. An element separation portion provided at the front face (located on the upper side in Fig. 3, a face where the transfer gate 22 is formed) of the silicon substrate where the PD 31 is formed is referred to as a FLAT separation portion 33, and the element separation portion of the silicon substrate deeper from the front face is referred to as a cell well 35. The FLAT separation portion 33 and the cell well 35 may be regions having different concentrations of P-type impurities, or may have substantially the same concentration and may be integrally formed.

[0041] Note that in the case that the PD 31 includes the region in which the N-type impurity is diffused, the cell well 35 and the FLAT separation portion 33 include the region in which the P-type impurity is diffused. In the case that the PD 31 includes the region in which the P-type impurity is diffused, the cell well 35 and the FLAT separation portion 33 include the region in which the N-type impurity is diffused.

[0042] The transfer gate 22-11 is provided on the PD 31-11 located between the FLAT separation portion 33-11 and the FLAT separation portion 33-12. The transfer gate 22-12 is provided on the PD 31-12 located between the FLAT separation portion 33-12 and the FLAT separation portion 33-13. The transfer gate 22-15 is provided on the PD 31-15 located between the FLAT separation portion 33-14 and the FLAT separation portion 33-15. The transfer gate 22-16 is provided on the PD 31-16 located between the FLAT separation portion 33-15 and the FLAT separation portion 33-16.

[0043] The arrangement of the active region and the transistor will be described with reference to Fig. 4. Fig. 4 is a view depicting a large pixel group 50a-1 and a large pixel group 50a-2 arranged vertically. The pixels 2 are separated by the inter-pixel separation portion 32 (Fig. 3), and the element separation portion is provided in an active region in the pixel 2. The element separation portion is, for example, the cell well 35 and the FLAT separation portion 33.

[0044] In an active region 70-1, a reset transistor 25-1 is provided. In an active region 70-2, a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided. In an active region 70-3, a selection transistor 27-2 and an amplification transistor 26-2 are provided.

[0045] The active region 70-1 is formed across the large pixel group 50a-1 and a large pixel group 50a (not illustrated) arranged above the large pixel group 50a-1. The active region 70-2 is formed across the large pixel group 50a-1 and the large pixel group 50a-1 arranged below the large pixel group 50a-2. The active region 70-3 is formed across the large pixel group 50a-2 and the large pixel group 50a (not illustrated) arranged below the large pixel group 50a-2.

[0046] Attention is paid to the large pixel group 50a-1. The pixels 2-1 to 2-16 arranged in the large pixel group 50a-1 use the reset transistor 25-1 arranged in the active region 70-1, and the selection transistor 27-1 and the amplification transistor 26-1 arranged in the active region 70-2. The pixel 2 in the large pixel group 50a-1 is configured to perform processing using a transistor arranged in the active region 70-2 formed in the large pixel group 50a-1 and a transistor arranged in the active region 70-1 formed across another large pixel group 50a.

[0047] With such a configuration, the transistor can be arranged such that the distance of the wire 40 is minimized (or alternatively, decreased).

[0048] The power supply VDD 28 is shared by the large pixel group 50a. A power supply VDD 28-2 is provided in the active region 70-2 formed across the large pixel group 50a-1 and the large pixel group 50a-2, is provided at the boundary between the large pixel group 50a-1 and the large pixel group 50a-2, and is shared by the pixels 2 arranged in the large pixel group 50a-1 and the large pixel group 50a-2.

[0049] The distance between the adjacent FDs 23 will be described with reference to Figs. 5 and 6. Fig. 5 depicts a planar configuration example of the large pixel group 50a-1 and the large pixel group 50a-2 adjacent to each other side by side. Fig. 6 is a view depicting a cross-sectional configuration example taken along line A-A' in Fig. 2 as in Fig. 3.

[0050] Referring to Fig. 5, one pixel 2 has a length A in each of the longitudinal direction and the lateral direction. The length of one side of the pixel 2 is a distance from the center of the inter-pixel separation portion 32 to the center of the inter-pixel separation portion 32 each of which is between the pixels 2. Referring to Fig. 6, for example, the distance from the center of the inter-pixel separation portion 32-11, left of the pixel 2-11, illustrated at the left end in the drawing to the inter-pixel separation portion 32-12 right of the pixel 2-11 is the length A.

[0051] The length A is also a distance from the center of the inter-pixel separation portion 32 to the contact 24 connected to the FD 23. For example, referring to Fig. 5, the distance from the contact 24-3 in the small pixel group 20-3 at the lower left of the large pixel group 50a-1 to the center of the inter-pixel separation portion 32 provided between the adjacent large pixel groups 50a (not illustrated) on the left side in the drawing is the length A.

[0052] At the center of the large pixel group 50a-1, a contact 24-5 provided in the FD 23-5, a contact 24-6 connected to the amplification transistor 26, a contact 24-7 connected to the vertical signal line 9, and a contact 24-8 connected to the power supply VDD are arranged in a line.

[0053] A distance from the center of the inter-pixel separation portion 32 between the pixels 2 in the small pixel group 20 to the contact 24 arranged at the center of the large pixel group 50a-1 is a length B. Since the center of the inter-pixel separation portion 32 between the pixels 2 in the small pixel group 20 is also a position where the contact 24 connected to the FD 23 is located, the distance between the contact 24 connected to the FD 23 and the contact 24 connected to the transistor is the length B.

[0054] For example, the distance from the contact 24-3 at the center in the small pixel group 20-3 to the contact 24-6 connected to the amplification transistor 26 in the large pixel group 50a-1 is the length B. In cross-sectional view, as illustrated in Fig. 6, for example, the distance from the center of the inter-pixel separation portion 32-12 between the pixel 2-11 and the pixel 2-12 to the center of the gate of the amplification transistor 26 is the length B.

[0055] As illustrated in Fig. 6, the length of the PD 31 in the lateral direction is a length C. The length of the PD 31 arranged in the small pixel group 20 is configured by the length C.

[0056] A relationship between length A, length B, and length C is a relationship of length C < length A < length B. Focusing on the length A and the length B, the interval at which the FDs 23 are arranged will be described. The distance between the FD 23-3 and the FD 23-4 in the large pixel group 50a-1 is a length obtained by adding the distance between the contact 24-3 of the FD 23-3 and the contact 24-6 of the amplification transistor 26 = length B to the distance between the contact 24-6 of the amplification transistor 26 and the contact 24-4 of the FD 23-4 = length B, and thus, is (2× length B).

[0057] The distance between the FD 23-4 in the large pixel group 50a-1 and the FD 23-7 in the large pixel group 50a-2 is a length obtained by adding the distance between the contact 24-4 of the FD 23-4 and the center of the inter-pixel separation portion 32 = length A to the distance between the center of the inter-pixel separation portion 32 and the contact 24-11 of the FD 23-7 = length A, and is thus (2× length A).

[0058] The contact 24-3, the contact 24-4, and the contact 24-11 are linearly arranged in a line and are arranged adjacent to each other. The distance between the contact 24-3 and the contact 24-4 is (2× length B), whereas the distance between the contact 24-4 and the contact 24-11 is (2× length A), so that they are different. That is, in this case, the distance between the FD 23-3 and the FD 23-4 in the adjacent positional relationship is different from the distance between the FD 23-4 and the FD 23-7 in the adjacent positional relationship. That is, the distances between the FDs 23 are not equal intervals but different intervals.

[0059] As described above, the FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor (region where the transistor is arranged) interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor (region where the transistor is arranged) interposed therebetween are different from each other.

[0060] The FDs 23 are arranged so as to have different distances therebetween, but as illustrated in Fig. 6, the size of each PD 31 is configured to be equal. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 6, the cell well 35-13 below the amplification transistor 26 is formed to be larger than the other cell wells 35, and the PD 31-12 and the PD 31-15 are adjusted so as not to be larger than the other PDs 31.

[0061] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0062] <Second embodiment> Fig. 7 depicts a planar configuration example of a large pixel group 50b according to the second embodiment, and Fig. 8 is a view depicting a cross-sectional configuration example of the large pixel group 50b taken along line A-A' in Fig. 7. In the large pixel group 50b in the second embodiment illustrated in Figs. 7 and 8, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0063] The large pixel group 50b in the second embodiment illustrated in Figs. 7 and 8 is different from the large pixel group 50a in the first embodiment in that a transfer gate 22b is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 8, the transfer gate 22b of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate (in the PD 31) are combined.

[0064] As illustrated in Fig. 7, the vertical electrode of the transfer gate 22 is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0065] The transfer efficiency can be improved by configuring the transfer gate 22 to include the vertical electrode.

[0066] Also in the second embodiment, as in the first embodiment, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0067] <Third embodiment> Fig. 9 depicts a planar configuration example of a large pixel group 50c in the third embodiment, A of Fig. 10 depicts a cross-sectional configuration example of the large pixel group 50c taken along line A-A' in Fig. 9, and B of Fig. 10 is a view depicting a cross-sectional configuration example of the large pixel group 50c taken along line B-B' in Fig. 9. In the large pixel group 50c in the third embodiment illustrated in Figs. 9 and 10, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0068] The large pixel group 50c in the third embodiment illustrated in Figs. 9 and 10 is different from the large pixel group 50a in the first embodiment in that a transfer gate 22c is a transfer gate having a vertical structure, and the other points are similar.

[0069] As illustrated in Fig. 10, the transfer gate 22c of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Further, the transfer gate 22c is formed in a shape so as to sandwich a portion corresponding to the inter-pixel separation portion.

[0070] Referring to A of Fig. 10, an STI 61-12 is formed on a cell well 35-12 (substrate front face side) formed at an inter-pixel separation portion 32-12 provided between the PD 31-11 and the PD 31-12. A transfer gate 22c-11 of the PD 31-11 and a transfer gate 22c-12 of the PD 31-12 are formed so as to sandwich the STI 61-12. The transfer gate 22c has a vertical electrode in contact with the STI 61.

[0071] Similarly, referring to A of Fig. 10, an STI 61-16 is formed on a cell well 35-14 (substrate front face side) formed at an inter-pixel separation portion 32-14 provided between the PD 31-15 and the PD 31-15. A transfer gate 22c-15 of the PD 31-15 and a transfer gate 22c-16 of the PD 31-16 are formed so as to sandwich the STI 61-16.

[0072] B of Fig. 10 is a view depicting a cross-sectional configuration example of a large pixel group 50c taken along line B-B' of Fig. 9. The pixel 2-1, the pixel 2-3, and the pixel 2-4 taken along line B-B' are arranged. As illustrated in B of Fig. 10, the STI 61-3 is formed on the substrate front face between the PD 31-1 included in the pixel 2-1 and the PD 31-3 included in the pixel 2-3. A transfer gate 22c-1 of the transfer transistor of the pixel 2-1 and a transfer gate 22c-3 of the transfer transistor of the pixel 2-3 are configured in a shape having a vertical electrode so as to sandwich the STI 61-3.

[0073] As illustrated in B of Fig. 10, in the transfer gate 22c-3 arranged on the pixel 2-3, vertical electrodes are formed at both ends so as to sandwich the PD 31-3, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22c-3 is formed in a shape that looks like a Π shape in cross-sectional view.

[0074] The STI 61-4 is formed on the substrate front face between the PD 31-3 included in the pixel 2-3 and the PD 31-4 included in the pixel 2-4. A transfer gate 22c-3 of the transfer transistor of the pixel 2-3 and a transfer gate 22c-4 of the transfer transistor of the pixel 2-4 are configured in a shape having a vertical electrode so as to sandwich the STI 61-4.

[0075] In the third embodiment, since the transfer gates 22 of the transfer transistors are configured to be close to each other, the STI 61 is provided between the transfer gates 22c in order to reduce the influence thereof, and the STI 61 can include an oxide film.

[0076] As illustrated in Fig. 9, the vertical electrode of the transfer gate 22c is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22c is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0077] The transfer efficiency can be improved by configuring the transfer gate 22c to include the vertical electrode.

[0078] Also in the third embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0079] <Fourth embodiment> Fig. 11 depicts a planar configuration example of a large pixel group 50d in the fourth embodiment, and Fig. 12 is a view depicting a cross-sectional configuration example of the large pixel group 50d taken along line A-A' in Fig. 11. In the large pixel group 50d in the fourth embodiment illustrated in Figs. 11 and 12, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0080] The large pixel group 50d in the fourth embodiment illustrated in Figs. 11 and 12 is different from the large pixel group 50a in the first embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0081] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0082] In cross-sectional view, as illustrated in Fig. 12, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements.

[0083] Also in the fourth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0084] <Fifth embodiment> Fig. 13 depicts a planar configuration example of a large pixel group 50e in the fifth embodiment, and Fig. 14 is a view depicting a cross-sectional configuration example of the large pixel group 50e taken along line A-A' in Fig. 13. In the large pixel group 50e in the fifth embodiment illustrated in Figs. 13 and 14, portions similar to those of the large pixel group 50b in the second embodiment illustrated in Figs. 7 and 8 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0085] The large pixel group 50e in the fifth embodiment illustrated in Figs. 13 and 14 is different from the large pixel group 50b in the second embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0086] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0087] In cross-sectional view, as illustrated in Fig. 14, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, the transfer gate 22 includes a vertical electrode.

[0088] Also in the fifth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PE 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0089] <Sixth embodiment> Fig. 15 depicts a planar configuration example of the large pixel group 50f in the sixth embodiment, A of Fig. 16 depicts a cross-sectional configuration example of the large pixel group 50f taken along line A-A' in Fig. 15, and B of Fig. 16 is a view depicting a cross-sectional configuration example of the large pixel group 50f taken along line B-B' in Fig. 15. In the large pixel group 50f in the sixth embodiment illustrated in Figs. 15 and 16, portions similar to those of the large pixel group 50c in the third embodiment illustrated in Figs. 9 and 10 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0090] The large pixel group 50f in the sixth embodiment illustrated in Figs. 15 and 16 is different from the large pixel group 50c in the third embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0091] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0092] In cross-sectional view, as illustrated in A of Fig. 16, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, the transfer gate 22 has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0093] Also in the sixth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0094] <Seventh embodiment> Fig. 17 depicts a planar configuration example of a large pixel group 50g in the seventh embodiment, and A in Fig. 18 is a view depicting a cross-sectional configuration example of the large pixel group 50g taken along line A-A' in Fig. 17. In the large pixel group 50g in the seventh embodiment illustrated in Figs. 17 and 18, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0095] Also in the seventh embodiment illustrated in Fig. 17, the FD 23 is shared by 16 pixels 2. The small pixel group 20-1 illustrated in the upper left part of the drawing includes a pixel 2-1, a pixel 2-2, a pixel 2-3, and a pixel 2-4. The small pixel group 20-2 illustrated in the upper right part of the drawing includes a pixel 2-5, a pixel 2-6, a pixel 2-7, and a pixel 2-8. The small pixel group 20-3 illustrated at the lower left in the drawing includes a pixel 2-9, a pixel 2-10, a pixel 2-11, and a pixel 2-12. The small pixel group 20-4 illustrated in the lower right of the drawing includes a pixel 2-13, a pixel 2-14, a pixel 2-15, and a pixel 2-16.

[0096] As illustrated in Fig. 18, each pixel 2 includes the PD 31, and has a configuration in which the charge accumulated in the PD 31 is transferred to the FD 23 by the transfer gate 22 of the transfer transistor. The pixels 2-1 to 2-4 of the small pixel group 20-1 includes a PD 31-1 to a PD 31-4 (not illustrated), and include transfer gates 22-1 to 22-4, respectively. An FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0097] The pixels 2-5 to 2-8 of the small pixel group 20-2 includes a PD 31-5 to a PD 31-8 (not illustrated), and include transfer gates 22-5 to 22-8, respectively. An FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0098] The pixels 2-9 to 2-12 of the small pixel group 20-3 includes a PD 31-9 to a PD 31-12 (not illustrated), and include transfer gates 22-9 to 22-12, respectively. An FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0099] The pixels 2-13 to 2-16 of the small pixel group 20-4 includes a PD 31-13 to a PD 31-16 (not illustrated), and include transfer gates 22-13 to 22-16, respectively. An FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0100] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. The wire 40 is also connected to the FD 23-5 provided right of the center of the large pixel group 50 in the drawing via a contact 24-5. Therefore, the FDs 23-1 to 23-5 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50.

[0101] The reset transistor 25 is provided right of the FD 23-5 in the drawing. The amplification transistor 26 is provided on the left side in Fig. 17, and the contact 24-6 is provided at the gate of the amplification transistor 26. The contact 24-6 is connected to the wire 40. The FDs 23-1 to 23-5 are connected to the amplification transistor 26 via the wire 40.

[0102] As illustrated in Fig. 17, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 are arranged in a line in the lateral direction of the central portion of the large pixel group 50. A contact connected to the power supply VDD 28 and a contact connected to the vertical signal line 9 (VSL region 29) are also arranged in a line in the lateral direction together with the transistor at the central portion of the large pixel group 50. As described above, the large pixel group 50g in the seventh embodiment is different from the large pixel group 50a in the first embodiment in that the transistors are arranged in the lateral direction, and the other points are basically the similar.

[0103] The description of cross-sectional configuration example taken along line A-A' in Fig. 17 will be continued with reference to Fig. 18. The pixel 2-1, the pixel 2-3, the amplification transistor 26, the pixel 2-9, and the pixel 2-11 taken along line A-A' are arranged in this order. In Fig. 17, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side. An inter-pixel separation portion 32-1 for separating from the pixel 2 (not illustrated) is provided left of the PD 31-1, and an inter-pixel separation portion 32-2 for separating from the PD 31-3 is provided right of the PD 31-1.

[0104] An inter-pixel separation portion 32-3 is provided between the PD 31-3 and the PD 31-9, an inter-pixel separation portion 32-4 is provided between the PD 31-9 and the PD 31-11, and an inter-pixel separation portion 32-5 is provided between the PD 31-11 and the PD 31 (not illustrated) of the adjacent pixel 2. The inter-pixel separation portion 32 can include an oxide film.

[0105] Above the inter-pixel separation portion 32-1 in the drawing, a cell well 35-1 and a FLAT separation portion 33-1 are provided. Above the inter-pixel separation portion 32-2 in the drawing, a cell well 35-2 and a FLAT separation portion 33-2 are provided. Above the inter-pixel separation portion 32-3 in the drawing, a cell well 35-3 is provided and above the cell well 35-3 in the drawing, a FLAT separation portion 33-3, a channel region 37 of the amplification transistor 26, and a FLAT separation portion 33-4 are provided.

[0106] Above the inter-pixel separation portion 32-4 in the drawing, a cell well 35-4 and a FLAT separation portion 33-5 are provided. Above the inter-pixel separation portion 32-5 in the drawing, a cell well 35-5 and a FLAT separation portion 33-6 are provided. The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other.

[0107] The transfer gate 22-1 is provided on the PD 31-1 located between the FLAT separation portion 33-1 and the FLAT separation portion 33-2. The transfer gate 22-3 is provided on the PD 31-3 located between the FLAT separation portion 33-2 and the FLAT separation portion 33-3. The transfer gate 22-9 is provided on the PD 31-9 located between the FLAT separation portion 33-4 and the FLAT separation portion 33-5. The transfer gate 22-11 is provided on the PD 31-11 located between the FLAT separation portion 33-5 and the FLAT separation portion 33-6.

[0108] The arrangement of the active region and the transistor will be described with reference to Fig. 19. Fig. 19 is a view depicting a large pixel group 50g-1 (right side in the drawing) and a large pixel group 50g-2 (left side in the drawing) adjacent in the lateral direction. The pixels 2 are separated by the inter-pixel separation portion 32 (Fig. 18), and the element separation portion is provided in an active region in the pixel 2. The element separation portion is, for example, the cell well 35 and the FLAT separation portion 33.

[0109] In an active region 70-1, a reset transistor 25-1 is provided. In an active region 70-2, a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided. In an active region 70-3, a selection transistor 27-2 and an amplification transistor 26-2 are provided.

[0110] The active region 70-1 is formed across the large pixel group 50g-1 and the large pixel group 50g (not illustrated) arranged right of the large pixel group 50g-1. The active region 70-2 is formed across the large pixel group 50g-1 and the large pixel group 50g-1 arranged left of the large pixel group 50g-2. The active region 70-3 is formed across the large pixel group 50g-2 and the large pixel group 50g (not illustrated) arranged left of the large pixel group 50g-2.

[0111] Attention is paid to the large pixel group 50g-1. The pixels 2-1 to 2-16 arranged in the large pixel group 50g-1 use the reset transistor 25-1 arranged in the active region 70-1, and the selection transistor 27-1 and the amplification transistor 26-1 arranged in the active region 70-2. The pixel 2 in the large pixel group 50g-1 is configured to perform processing using a transistor arranged in the active region 70-2 formed in the large pixel group 50g-1 and a transistor arranged in the active region 70-1 formed across another large pixel group 50g.

[0112] With such a configuration, the transistor can be arranged such that the distance of the wire 40 is minimized (or alternatively, decreased).

[0113] The power supply VDD 28 is shared by the large pixel group 50g. The power supply VDD 28-2 is provided in the active region 70-2 formed across the large pixel group 50g-1 and the large pixel group 50g-2, is provided at the boundary between the large pixel group 50g-1 and the large pixel group 50g-2, and is shared by the pixels 2 arranged in each of the large pixel group 50g-1 and the large pixel group 50g-2.

[0114] The distance between the adjacent FDs 23 will be described with reference to Fig. 20. Fig. 20 depicts a planar configuration example of the large pixel group 50g-1 and the large pixel group 50g-2 that are vertically adjacent to each other.

[0115] Referring to Fig. 20, one pixel 2 is formed to have a length A in each of the longitudinal direction and the lateral direction. The length of one side of the pixel 2 is a distance from the center of the inter-pixel separation portion 32 to the center of the inter-pixel separation portion 32 each of which is between the pixels 2. For example, a distance from the center of the inter-pixel separation portion 32 above the pixel 2-11 illustrated in the upper left part of the drawing to the inter-pixel separation portion 32 below is the length A.

[0116] The length A is also a distance from the center of the inter-pixel separation portion 32 to the contact 24 connected to the FD 23. For example, referring to Fig. 20, the distance to the center of the inter-pixel separation portion 32 provided between the contact 24-1 in the small pixel group 20-1 upper left of the large pixel group 50g-1 and the adjacent large pixel group 50g (not illustrated) on the upper side in the drawing is the length A.

[0117] In the lateral direction of the center of the large pixel group 50g-1, the contact 24-5 provided in the FD 23-5, the contact 24-6 connected to the amplification transistor 26, the contact 24-7 connected to the vertical signal line 9, and the contact 24-8 connected to the power supply VDD are arranged in a line.

[0118] A distance from the center of the inter-pixel separation portion 32 between the pixels 2 in the small pixel group 20 to the contact 24 arranged at the center of the large pixel group 50g-1 is the length B. Since the center of the inter-pixel separation portion 32 between the pixels 2 in the small pixel group 20 is also a position where the contact 24 connected to the FD 23 is located, the distance between the contact 24 connected to the FD 23 and the contact 24 connected to the transistor is the length B.

[0119] For example, the distance between the contact 24-1 at the center in the small pixel group 20-1 and the contact 24-6 connected to the amplification transistor 26 in the large pixel group 50g-1 is the length B.

[0120] Also in the large pixel group 50g illustrated in Fig. 20, as described with reference to Fig. 6, the length of each PD 31 in the lateral direction is configured by the length C. The length of the PD 31 arranged in the small pixel group 20 is configured to be the length C, and the size of the PD 31 of each pixel 2 is configured to be uniform.

[0121] There is a relationship of length A < length B, and the interval at which the FD 23 is arranged will be described focusing on length A and length B. The distance between the FD 23-1 and the FD 23-3 in the large pixel group 50g-1 is a length obtained by adding the distance between the contact 24-1 of the FD 23-1 and the contact 24-6 of the amplification transistor 26 = length B and the distance between the contact 24-6 of the amplification transistor 26 and the contact 24-3 of the FD 23-3 = length B, and thus, is (2× length B).

[0122] The distance between the FD 23-3 in the large pixel group 50g-1 and the FD 23-11 in the large pixel group 50g-2 is a length obtained by adding the distance between the contact 24-3 of the FD 23-3 and the center of the inter-pixel separation portion 32 = length A and the distance between the center of the inter-pixel separation portion 32 and the contact 24-11 of the FD 23-11 = length A, and is thus (2× length A).

[0123] The contact 24-1, the contact 24-3, and the contact 24-11 are linearly arranged in a line and are arranged adjacent to each other. The distance between the contact 24-1 and the contact 24-3 is (2× length B), whereas the distance between the contact 24-3 and the contact 24-11 is (2× length A), so that they are different. That is, in this case, the distance between the FD 23-1 and the FD 23-3 in the adjacent positional relationship is different from the distance between the FD 23-3 and the FD 23-11 in the adjacent positional relationship. That is, the distances between the FDs 23 are not equal intervals but different intervals.

[0124] As described above, the FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor (region where the transistor is arranged) interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor (region where the transistor is arranged) interposed therebetween are different from each other.

[0125] Although the FDs 23 are arranged so as to have different distances therebetween, the size of the PD 31 is configured to be equal as in the case described with reference to Fig. 6. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 18, the cell well 35-3 below the amplification transistor 26 is formed to be larger than the other cell wells 35, and the PD 31-3 and the PD 31-9 are adjusted so as not to be larger than the other PDs 31.

[0126] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0127] Also in the seventh embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0128] <Eighth embodiment> Fig. 21 depicts a planar configuration example of a large pixel group 50h according to the eighth embodiment, and Fig. 22 is a view depicting a cross-sectional configuration example of the large pixel group 50h taken along line A-A' in Fig. 21. In the large pixel group 50h in the eighth embodiment illustrated in Figs. 21 and 22, portions similar to those of the large pixel group 50g in the seventh embodiment illustrated in Figs. 17 and 18 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0129] The large pixel group 50h in the second embodiment illustrated in Figs. 21 and 22 is different from the large pixel group 50g in the seventh embodiment in that a transfer gate 22h is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 22, the transfer gate 22h of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined.

[0130] As illustrated in Fig. 21, the vertical electrode of the transfer gate 22h is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0131] The transfer efficiency can be improved by configuring the transfer gate 22h to include the vertical electrode.

[0132] Also in the eighth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0133] <Ninth embodiment> Fig. 23 depicts a planar configuration example of a large pixel group 50i according to the ninth embodiment, A of Fig. 24 depicts a cross-sectional configuration example of the large pixel group 50i taken along line A-A' in Fig. 23, and B of Fig. 24 is a view depicting a cross-sectional configuration example of the large pixel group 50i taken along line B-B' in Fig. 23. In the large pixel group 50i in the ninth embodiment illustrated in Figs. 23 and 24, portions similar to those of the large pixel group 50g in the seventh embodiment illustrated in Figs. 17 and 18 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0134] The large pixel group 50i in the ninth embodiment illustrated in Figs. 23 and 24 is different from the large pixel group 50g in the seventh embodiment in that a transfer gate 22i is a transfer gate having a vertical structure, and the other points are similar.

[0135] As illustrated in Fig. 24, the transfer gate 22i of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Further, the transfer gate 22i is formed in a shape so as to sandwich a portion corresponding to the inter-pixel separation portion. The transfer gate 22i is formed in a Π shape as in the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0136] Referring to A of Fig. 24, for example, an STI 61-3 is formed on a cell well 35-2 (substrate front face side) formed at an inter-pixel separation portion 32-2 provided between the PD 31-1 and the PD 31-3. A transfer gate 22i-1 of the PD 31-1 and a transfer gate 22i-3 of the PD 31-3 are formed so as to sandwich the STI 61-3. Another transfer gate 22i is also formed in a shape having a vertical electrode in contact with the STI 61.

[0137] B of Fig. 24 is a view depicting a cross-sectional configuration example of the large pixel group 50i taken along line B-B' of Fig. 23. The pixel 2-5, the pixel 2-7, and the pixel 2-8 taken along line B-B' are arranged. As illustrated in B of Fig. 24, the STI 61-7 is formed on the substrate front face between the PD 31-5 included in the pixel 2-5 and the PD 31-7 included in the pixel 2-7, and a transfer gate 22i-5 of the transfer transistor of the pixel 2-5 and a transfer gate 22i-7 of the transfer transistor of the pixel 2-7 are configured in a shape having a vertical electrode so as to sandwich (contact) the STI 61-3.

[0138] As illustrated in B of Fig. 24, in the transfer gate 22i-7 arranged on the pixel 2-7, vertical electrodes are formed at both ends so as to sandwich the PD 31-7, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22i-7 is formed in a shape that looks like a Π shape in cross-sectional view.

[0139] In the ninth embodiment, since the transfer gates 22i of the transfer transistors are configured to be close to each other, the STI 61 is provided between the transfer gates 22i in order to reduce the influence thereof, and the STI 61 can include an oxide film.

[0140] As illustrated in Fig. 23, the vertical electrode of the transfer gate 22i is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22i is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0141] The transfer efficiency can be improved by configuring the transfer gate 22i to include the vertical electrode.

[0142] Also in the ninth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0143] <Tenth embodiment> Fig. 25 depicts a planar configuration example of a large pixel group 50j in the tenth embodiment, and Fig. 26 is a view depicting a cross-sectional configuration example of the large pixel group 50j taken along line A-A' in Fig. 25. In the large pixel group 50j in the tenth embodiment illustrated in Figs. 25 and 26, portions similar to those of the large pixel group 50g in the seventh embodiment illustrated in Figs. 17 and 18 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0144] The large pixel group 50j in the tenth embodiment illustrated in Figs. 25 and 26 is different from the large pixel group 50g in the seventh embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0145] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50j around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0146] In cross-sectional view, as illustrated in Fig. 26, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements.

[0147] Also in the tenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0148] <Eleventh embodiment> Fig. 27 depicts a planar configuration example of a large pixel group 50k according to the eleventh embodiment, and Fig. 28 is a view depicting a cross-sectional configuration example of the large pixel group 50k taken along line A-A' in Fig. 27. In the large pixel group 50k in the eleventh embodiment illustrated in Figs. 27 and 28, portions similar to those of the large pixel group 50h in the eighth embodiment illustrated in Figs. 21 and 22 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0149] The large pixel group 50k in the eleventh embodiment illustrated in Figs. 27 and 28 is different from the large pixel group 50h in the eighth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0150] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50k around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0151] In cross-sectional view, as illustrated in Fig. 28, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, a transfer gate 22k has a vertical electrode.

[0152] Also in the eleventh embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the seventh embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0153] <Twelfth embodiment> Fig. 29 depicts a planar configuration example of a large pixel group 50m according to the twelfth embodiment, A of Fig. 30 depicts a cross-sectional configuration example of the large pixel group 50m taken along line A-A' in Fig. 29, and B of Fig. 30 is a view depicting a cross-sectional configuration example of the large pixel group 50m taken along line B-B' in Fig. 29. In the large pixel group 50m in the twelfth embodiment illustrated in Figs. 29 and 30, portions similar to those of the large pixel group 50i in the ninth embodiment illustrated in Figs. 23 and 24 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0154] The large pixel group 50m in the twelfth embodiment illustrated in Figs. 29 and 30 is different from the large pixel group 50i in the ninth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0155] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0156] In cross-sectional view, as illustrated in A of Fig. 30, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, the transfer gate 22m has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0157] Also in the twelfth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0158] <Thirteenth embodiment> Fig. 31 depicts a planar configuration example of a large pixel group 50n according to the thirteenth embodiment, and Fig. 32 is a view depicting a cross-sectional configuration example of the large pixel group 50n taken along line A-A' in Fig. 31. In the large pixel group 50n in the thirteenth embodiment illustrated in Figs. 31 and 32, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0159] The large pixel group 50n in the thirteenth embodiment is different from the large pixel group 50a in the first embodiment in the region where the active region is formed and the arrangement of the transistors arranged in the active region, and the other points are similar. The large pixel group 50n in the thirteenth embodiment is different from the large pixel group 50a in the first embodiment in that transistors used in the large pixel group 50n are arranged in an active region provided in one large pixel group 50n.

[0160] Referring to Fig. 31, the active region 70 is provided in the large pixel group 50n. In the active region 70, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 are provided. A signal from each pixel 2 from the pixel 2-1 to the pixel 2-16 arranged in the large pixel group 50n is processed by the reset transistor 25, the amplification transistor 26, and the selection transistor 27 arranged in the active region 70. The pixels 2 in the large pixel group 50n are configured to perform processing using a transistor arranged in the active region 70 formed in the large pixel group 50n.

[0161] In a case where each pixel 2 in the large pixel group 50n is configured to perform processing using the transistors arranged in one active region 70 in the large pixel group 50n, as illustrated in Fig. 31, the wire 40 including a bent portion is arranged.

[0162] The pixels 2-1 to 2-4 of the small pixel group 20-1 include the transfer gates 22-1 to 22-4, respectively, and the FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0163] The pixels 2-5 to 2-8 of the small pixel group 20-2 include the transfer gates 22-5 to 22-8, respectively, and the FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0164] The pixels 2-9 to 2-12 of the small pixel group 20-3 include the transfer gates 22-9 to 22-12, respectively, and the FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0165] The pixels 2-13 to 2-16 of the small pixel group 20-4 include the transfer gates 22-13 to 22-16, respectively, and an FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0166] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. The wire 40 is also connected to the contact 24-6 of the amplification transistor 26 provided at the center of the large pixel group 50n. The wire 40 connecting the FDs 23-1 to 23-4 (the contacts 24-1 to 24-4) and the contact 24-6 is arranged in an H shape. This shape is a shape that minimizes (or alternatively, decreases) the routing of the wire 40.

[0167] The wire 40 is also connected to the FD 23-5 provided above the center of the large pixel group 50 in the drawing via a contact 24-5. In the example illustrated in Fig. 31, since the contact 24-2 and the contact 24-5 are connected, the wire 40 provided between the contact 24-2 and the contact 24-5 has a bent portion.

[0168] Also in the large pixel group 50n in the thirteenth embodiment, the FDs 23-1 to 23-5 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50.

[0169] The description of cross-sectional configuration example taken along line A-A' in Fig. 31 will be continued with reference to Fig. 32. The pixel 2-1, the pixel 2-2, the reset transistor 25, the pixel 2-5, and the pixel 2-6 taken along line A-A' are arranged in this order. In Fig. 31, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side. An inter-pixel separation portion 32-1 for separating from the pixel 2 (not illustrated) is provided left of the PD 31-1, and an inter-pixel separation portion 32-2 for separating from the PD 31-2 is provided right of the PD 31-1.

[0170] An inter-pixel separation portion 32-3 is provided between the PD 31-2 and the PD 31-5, an inter-pixel separation portion 32-4 is provided between the PD 31-5 and the PD 31-6, and an inter-pixel separation portion 32-5 is provided between the PD 31-6 and the PD 31 (not illustrated) of the adjacent pixel 2. The inter-pixel separation portion 32 can include an oxide film.

[0171] Above the inter-pixel separation portion 32-1 in the drawing, a cell well 35-1 and a FLAT separation portion 33-1 are provided. Above the inter-pixel separation portion 32-2 in the drawing, a cell well 35-2 and a FLAT separation portion 33-2 are provided. Above the inter-pixel separation portion 32-3 in the drawing, a cell well 35-3 is provided and above the cell well 35-3 in the drawing, a FLAT separation portion 33-3, a channel region 37 of the reset transistor 25, and a FLAT separation portion 33-4 are provided.

[0172] Above the inter-pixel separation portion 32-4 in the drawing, a cell well 35-4 and a FLAT separation portion 33-5 are provided. Above the inter-pixel separation portion 32-5 in the drawing, a cell well 35-5 and a FLAT separation portion 33-6 are provided. The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other.

[0173] The transfer gate 22-1 is provided on the PD 31-1 located between the FLAT separation portion 33-1 and the FLAT separation portion 33-2. The transfer gate 22-2 is provided on the PD 31-2 located between the FLAT separation portion 33-2 and the FLAT separation portion 33-3. The transfer gate 22-5 is provided on the PD 31-5 located between the FLAT separation portion 33-4 and the FLAT separation portion 33-5. The transfer gate 22-6 is provided on the PD 31-6 located between the FLAT separation portion 33-5 and the FLAT separation portion 33-6.

[0174] Also in the large pixel group 50n illustrated in Figs. 31 and 32, the relationship of the distance between the adjacent FDs 23 described with reference to Figs. 5 and 6 is established. For example, the distance between the adjacent FDs 23 in the adjacent large pixel group 50n is (2× length A), and the distance between the adjacent FDs 23 with the transistor in the large pixel group 50n interposed therebetween is (2× length B).

[0175] The FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor interposed therebetween are different from each other.

[0176] Although the FDs 23 are arranged so as to have different distances therebetween, the size of the PD 31 is configured to be equal as in the case described with reference to Fig. 6. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 32, the cell well 35-3 below the amplification transistor 26 is formed to be larger than the other cell wells 35, and the PD 31-2 and the PD 31-5 are adjusted so as not to be larger than the other PDs 31.

[0177] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0178] Also in the thirteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0179] <Fourteenth embodiment> Fig. 33 depicts a planar configuration example of a large pixel group 50p according to the fourteenth embodiment, and Fig. 34 is a view depicting a cross-sectional configuration example of the large pixel group 50p taken along line A-A' in Fig. 33. In the large pixel group 50p in the fourteenth embodiment illustrated in Figs. 33 and 34, portions similar to those of the large pixel group 50n in the thirteenth embodiment illustrated in Figs. 31 and 32 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0180] The large pixel group 50p in the fourteenth embodiment illustrated in Figs. 33 and 34 is different from the large pixel group 50n in the thirteenth embodiment in that a transfer gate 22p is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 34, the transfer gate 22p of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined.

[0181] As illustrated in Fig. 33, the vertical electrode of the transfer gate 22 is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0182] The transfer efficiency can be improved by configuring the transfer gate 22p to include the vertical electrode.

[0183] Also in the fourteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the thirteenth embodiment, even in a case where the light detection device 1 is downsized, the charge transfer region can be secured while maintaining the region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0184] <Fifteenth embodiment> Fig. 35 depicts a planar configuration example of a large pixel group 50q in the fifteenth embodiment, A of Fig. 36 depicts a cross-sectional configuration example of the large pixel group 50q taken along line A-A' in Fig. 35, and B of Fig. 36 is a view depicting a cross-sectional configuration example of the large pixel group 50q taken along line B-B' in Fig. 35. In the large pixel group 50q in the fifteenth embodiment illustrated in Figs. 35 and 36, portions similar to those of the large pixel group 50n in the thirteenth embodiment illustrated in Figs. 31 and 32 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0185] The large pixel group 50q in the fifteenth embodiment illustrated in Figs. 35 and 36 is different from the large pixel group 50n in the thirteenth embodiment in that a transfer gate 22q is a transfer gate having a vertical structure, and the other points are similar.

[0186] As illustrated in Fig. 36, the transfer gate 22q of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Furthermore, the transfer gate 22q is formed in a shape so as to sandwich a portion corresponding to the inter-pixel separation portion 32.

[0187] Referring to A of Fig. 36, an STI 61-9 is formed on a cell well 35-12 (substrate front face side) provided between the PD 31-9 and the PD 31-10. A transfer gate 22q-9 of the PD 31-9 and a transfer gate 22q-10 of the PD 31-10 are formed so as to sandwich (contact) the STI 61-9. The STI 61 is also formed between the other pixels 2, and the transfer gate 22q of the PD 31 is formed so as to sandwich the STI 61 (so as to be in contact with the STI 61).

[0188] B of Fig. 36 is a view depicting a cross-sectional configuration example of the large pixel group 50q taken along line B-B' of Fig. 35. The pixel 2-1, the pixel 2-3, and the pixel 2-4 taken along line B-B' are arranged. As illustrated in B of Fig. 36, the STI 61-3 is formed on the substrate front face between the PD 31-1 included in the pixel 2-1 and the PD 31-3 included in the pixel 2-3. A transfer gate 22q-1 of the transfer transistor of the pixel 2-1 and a transfer gate 22q-3 of the transfer transistor of the pixel 2-3 are configured in a shape having a vertical electrode so as to sandwich the STI 61-3.

[0189] As illustrated in B of Fig. 36, in the transfer gate 22q-3 arranged on the pixel 2-3, vertical electrodes are formed at both ends so as to sandwich the PD 31-3, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22q-3 is formed in a shape that looks like a Π shape in cross-sectional view.

[0190] In the fifteenth embodiment, since the transfer gates 22q of the transfer transistors are configured to be close to each other, the STI 61 is provided between the transfer gates 22q in order to reduce the influence, and the STI 61 can include an oxide film.

[0191] As illustrated in Fig. 35, the vertical electrode of the transfer gate 22q is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22q is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0192] The transfer efficiency can be improved by configuring the transfer gate 22q to include the vertical electrode.

[0193] Also in the fifteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0194] <Sixteenth embodiment> Fig. 37 depicts a planar configuration example of a large pixel group 50r according to the sixteenth embodiment, and Fig. 38 is a view depicting a cross-sectional configuration example of the large pixel group 50r taken along line A-A' in Fig. 37. In the large pixel group 50r according to the sixteenth embodiment illustrated in Figs. 37 and 38, portions similar to those of the large pixel group 50n according to the thirteenth embodiment illustrated in Figs. 31 and 32 are denoted by the similar reference numerals, and the description thereof will be omitted as appropriate.

[0195] The large pixel group 50r in the sixteenth embodiment illustrated in Figs. 37 and 38 is different from the large pixel group 50n in the thirteenth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0196] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0197] In cross-sectional view, as illustrated in Fig. 38, the STIs 71 are formed at both sides of the channel region 37 of the reset transistor 25, and are configured to be element separated from other elements.

[0198] Also in the sixteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0199] <Seventeenth embodiment> Fig. 39 depicts a planar configuration example of a large pixel group 50s according to the seventeenth embodiment, and Fig. 40 is a view depicting a cross-sectional configuration example of the large pixel group 50s taken along line A-A' in Fig. 39. In the large pixel group 50s in the seventeenth embodiment illustrated in Figs. 39 and 40, portions similar to those of the large pixel group 50p in the fourteenth embodiment illustrated in Figs. 33 and 34 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0200] The large pixel group 50s in the seventeenth embodiment illustrated in Figs. 39 and 40 is different from the large pixel group 50p in the fourteenth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0201] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0202] In cross-sectional view, as illustrated in Fig. 40, the STIs 71 are formed at both sides of the channel region 37 of the reset transistor 25, and are configured to be element separated from other elements. In addition, a transfer gate 22s has a vertical electrode.

[0203] Also in the seventeenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PE 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0204] <Eighteenth embodiment> Fig. 41 depicts a planar configuration example of the large pixel group 50t in the eighteenth embodiment, A of Fig. 42 depicts a cross-sectional configuration example of the large pixel group 50t taken along line A-A' in Fig. 41, and B of Fig. 42 is a view depicting a cross-sectional configuration example of the large pixel group 50t taken along line B-B' in Fig. 41. In the large pixel group 50t in the eighteenth embodiment illustrated in Figs. 41 and 42, portions similar to those of the large pixel group 50q in the fifteenth embodiment illustrated in Figs. 35 and 36 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0205] The large pixel group 50t in the eighteenth embodiment illustrated in Figs. 41 and 42 is different from the large pixel group 50q in the fifteenth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0206] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0207] In cross-sectional view, as illustrated in A of Fig. 42, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, the transfer gate 22t has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0208] Also in the eighteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the eleventh embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0209] <Nineteenth embodiment> Fig. 43 depicts a planar configuration example of a large pixel group 50u according to the nineteenth embodiment, and Fig. 44 is a view depicting a cross-sectional configuration example of the large pixel group 50u taken along line A-A' in Fig. 43. In the large pixel group 50u in the nineteenth embodiment illustrated in Figs. 43 and 44, portions similar to those of the large pixel group 50n in the thirteenth embodiment illustrated in Figs. 31 and 32 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0210] Also in the nineteenth embodiment illustrated in Fig. 43, the FD 23 is shared by 16 pixels 2. The pixels 2-1 to 2-4 of the small pixel group 20-1 include the transfer gates 22-1 to 22-4, respectively, and the FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0211] The pixels 2-5 to 2-8 of the small pixel group 20-2 include the transfer gates 22-5 to 22-8, respectively, and the FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0212] The pixels 2-9 to 2-12 of the small pixel group 20-3 include the transfer gates 22-9 to 22-12, respectively, and the FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0213] The pixels 2-13 to 2-16 of the small pixel group 20-4 include the transfer gates 22-13 to 22-16, respectively, and an FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0214] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. The wire 40 is also connected to the contact 24-6 of the amplification transistor 26 provided at the center of the large pixel group 50u. The wire 40 connecting the FDs 23-1 to 23-4 (the contacts 24-1 to 24-4) and the contact 24-6 is arranged in an H shape (a shape obtained by rotating H by 90 degrees in Fig. 43).

[0215] The wire 40 is also connected to the FD 23-5 provided left of the center of the large pixel group 50u in the drawing via the contact 24-5. In the example illustrated in Fig. 43, since the contact 24-1 and the contact 24-5 are connected, the wire 40 provided between the contact 24-1 and the contact 24-5 has a bent portion.

[0216] Also in the large pixel group 50u in the nineteenth embodiment, the FDs 23-1 to 23-5 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50u.

[0217] As illustrated in Fig. 43, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 are arranged in a line in the lateral direction at the central portion of the large pixel group 50. A contact connected to the power supply VDD 28 and a contact connected to the vertical signal line 9 (VSL region 29) are also arranged in a line in the lateral direction together with the transistor at the central portion of the large pixel group 50. As described above, the large pixel group 50u in the nineteenth embodiment is different from the large pixel group 50n in the thirteenth embodiment in that the transistors are arranged in the lateral direction, and the other points are basically the similar.

[0218] The description of cross-sectional configuration example taken along line A-A' in Fig. 43 will be continued with reference to Fig. 44. The pixel 2-5, the pixel 2-7, the amplification transistor 26, the pixel 2-13, and the pixel 2-15 taken along line A-A' are arranged in this order. In Fig. 43, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side. The inter-pixel separation portion 32 is provided between the PDs 31. The inter-pixel separation portion 32 can include an oxide film.

[0219] Above the inter-pixel separation portion 32 in the drawing, a cell well 35 and a FLAT separation portion 33 are provided. The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other.

[0220] Also in the large pixel group 50u illustrated in Figs. 43 and 44, the relationship of the distance between the adjacent FDs 23 described with reference to Figs. 5 and 6 is established. For example, the distance between the adjacent FDs 23 between the adjacent large pixel groups 50u is (2× length A), and the distance between the adjacent FDs 23 with the transistor in the large pixel group 50n interposed therebetween is (2× length B).

[0221] The FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor interposed therebetween are different from each other.

[0222] Although the FDs 23 are arranged so as to have different distances therebetween, the size of the PD 31 is configured to be equal as in the case described with reference to Fig. 6. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 44, the cell well 35-7 below the amplification transistor 26 is formed to be larger than the other cell wells 35, and the PD 31-7 and the PD 31-13 are adjusted so as not to be larger than the other PDs 31.

[0223] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0224] Also in the nineteenth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0225] <Twentieth embodiment> Fig. 45 depicts a planar configuration example of a large pixel group 50v in the twentieth embodiment, and Fig. 46 is a view depicting a cross-sectional configuration example of the large pixel group 50v taken along line A-A' in Fig. 45. In the large pixel group 50v in the nineteenth embodiment illustrated in Figs. 45 and 46, portions similar to those of the large pixel group 50u in the nineteenth embodiment illustrated in Figs. 43 and 44 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0226] The large pixel group 50v in the twentieth embodiment illustrated in Figs. 45 and 46 is different from the large pixel group 50u in the nineteenth embodiment in that a transfer gate 22v is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 46, the transfer gate 22v of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined.

[0227] As illustrated in Fig. 46, the vertical electrode of the transfer gate 22v is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0228] The transfer efficiency can be improved by configuring the transfer gate 22v to include the vertical electrode.

[0229] Also in the twentieth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0230] <Twenty-first embodiment> Fig. 47 depicts a planar configuration example of a large pixel group 50w in the twenty-first embodiment, A of Fig. 48 depicts a cross-sectional configuration example of the large pixel group 50w taken along line A-A' in Fig. 47, and B of Fig. 48 is a view depicting a cross-sectional configuration example of the large pixel group 50w taken along line B-B' in Fig. 47. In the large pixel group 50w in the twenty-first embodiment illustrated in Figs. 47 and 48, portions similar to those of the large pixel group 50u in the nineteenth embodiment illustrated in Figs. 43 and 44 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0231] The large pixel group 50w in the twenty-first embodiment illustrated in Figs. 47 and 48 is different from the large pixel group 50u in the nineteenth embodiment in that a transfer gate 22w is a transfer gate having a vertical structure, and the other points are similar.

[0232] As illustrated in Fig. 48, the transfer gate 22w of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Furthermore, the transfer gate 22w is formed in a shape (contact shape) so as to sandwich a portion corresponding to the inter-pixel separation portion. The transfer gate 22w is formed in a Π shape as in the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0233] Referring to A of Fig. 48, for example, an STI 61-7 is formed on a cell well 35-6 (substrate front face side) formed at an inter-pixel separation portion 32-6 provided between the PD 31-5 and the PD 31-7. A transfer gate 22w-5 of the PD 31-5 and a transfer gate 22w-7 of the PD 31-7 are formed so as to sandwich (contact) the STI 61-7. Another transfer gate 22w is also formed in a shape having a vertical electrode in contact with the STI 61.

[0234] B of Fig. 48 is a view depicting a cross-sectional configuration example of the large pixel group 50w along the line B-B' of Fig. 47. The pixel 2-1, the pixel 2-3, and the pixel 2-4 taken along line B-B' are arranged. As illustrated in B of Fig. 48, the STI 61-3 is formed on the substrate front face between the PD 31-1 included in the pixel 2-1 and the PD 31-3 included in the pixel 2-3, and a transfer gate 22w-1 of the transfer transistor of the pixel 2-1 and a transfer gate 22w-3 of the transfer transistor of the pixel 2-3 are configured in a shape having a vertical electrode so as to sandwich the STI 61-3.

[0235] As illustrated in B of Fig. 48, in the transfer gate 22w-3 arranged on the pixel 2-3, vertical electrodes are formed at both ends so as to sandwich the PD 31-3, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22w-3 is formed in a shape that looks like a Π shape in cross-sectional view.

[0236] In the twentieth embodiment, since the transfer gates 22w of the transfer transistors are configured to be close to each other, in order to reduce the influence, the STI 61 is provided between the transfer gates 22w, and the STI 61 can include an oxide film.

[0237] As illustrated in Fig. 47, the vertical electrode of the transfer gate 22w is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22w is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0238] The transfer efficiency can be improved by configuring the transfer gate 22w to include the vertical electrode.

[0239] Also in the twenty-first embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0240] <Twenty-second embodiment> Fig. 49 depicts a planar configuration example of a large pixel group 50x according to the twenty-second embodiment, and Fig. 50 is a view depicting a cross-sectional configuration example of the large pixel group 50x taken along line A-A' in Fig. 49. In the large pixel group 50x in the twenty-second embodiment illustrated in Figs. 49 and 50, portions similar to those of the large pixel group 50u in the nineteenth embodiment illustrated in Figs. 43 and 44 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0241] The large pixel group 50x in the twenty-second embodiment illustrated in Figs. 49 and 50 is different from the large pixel group 50u in the nineteenth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0242] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50x around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0243] In cross-sectional view, as illustrated in Fig. 50, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements.

[0244] Also in the twenty-second embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0245] <Twenty-third embodiment> Fig. 51 depicts a planar configuration example of a large pixel group 50y according to the twenty-third embodiment, and Fig. 52 is a view depicting a cross-sectional configuration example of the large pixel group 50y taken along line A-A' in Fig. 51. In the large pixel group 50y in the twenty-third embodiment illustrated in Figs. 51 and 52, portions similar to those of the large pixel group 50v in the twentieth embodiment illustrated in Figs. 45 and 46 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0246] The large pixel group 50y in the twenty-third embodiment illustrated in Figs. 51 and 52 is different from the large pixel group 50v in the twentieth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0247] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50x around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0248] In cross-sectional view, as illustrated in Fig. 52, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, a transfer gate 22y includes a vertical electrode.

[0249] Also in the twenty-second embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the eighteenth embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0250] <Twenty-fourth embodiment> Fig. 53 depicts a planar configuration example of a large pixel group 50z in the twenty-fourth embodiment, A of Fig. 54 depicts a cross-sectional configuration example of the large pixel group 50z taken along line A-A' in Fig. 53, and B of Fig. 54 is a view depicting a cross-sectional configuration example of the large pixel group 50z taken along line B-B' in Fig. 53. In the large pixel group 50z in the twenty-fourth embodiment illustrated in Figs. 53 and 54, portions similar to those of the large pixel group 50w in the twenty-first embodiment illustrated in Figs. 47 and 48 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0251] The large pixel group 50z in the twenty-fourth embodiment illustrated in Figs. 53 and 54 is different from the large pixel group 50w in the twenty-fourth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0252] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0253] In cross-sectional view, as illustrated in A of Fig. 54, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26, and are configured to be element separated from other elements. In addition, the transfer gate 22z has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0254] Also in the twenty-fourth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0255] <Twenty-fifth embodiment> Fig. 55 depicts a planar configuration example of a large pixel group 50aa in the twenty-fifth embodiment, and Fig. 56 is a view depicting a cross-sectional configuration example of the large pixel group 50aa taken along line A-A' in Fig. 55. In the large pixel group 50aa in the twenty-fifth embodiment illustrated in Figs. 55 and 56, portions similar to those of the large pixel group 50a in the first embodiment illustrated in Figs. 2 and 3 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0256] The large pixel group 50aa shown in Fig. 55 includes 16 pixels 2 of 2×8. In the twenty-fifth embodiment, the FD 23 is shared by 16 pixels. The large pixel group 50 in the first to twenty-fourth embodiments is different from the large pixel group 50 in the twenty-fifth and subsequent embodiments in that the large pixel group 50 in the first to twenty-fourth embodiments in which the small pixel group 20 of 2×2 is formed in 4 units of 2×2 includes 16 pixels 2, whereas the large pixel group 50 in the twenty-fifth and subsequent embodiments in which the small pixel group 20 of 2×2 is formed in 4 units of 1×4 includes 16 pixels 2.

[0257] The small pixel group 20 includes the 4 pixels 2 of 2×2, and the large pixel group 50aa includes the 4 small pixel groups 20. In the example illustrated in Fig. 55, the large pixel group 50aa includes four small pixel groups 20 arranged in the longitudinal direction.

[0258] A large pixel group 50aa-1 includes the small pixel group 20-1, the small pixel group 20-2, the small pixel group 20-3, and the small pixel group 20-4 from the top in this order in the drawing. A large pixel group 50aa-2 arranged right of the large pixel group 50aa-1 in the drawing includes the small pixel group 20-5, the small pixel group 20-6, the small pixel group 20-7, and the small pixel group 20-8 from the top in this order in the drawing.

[0259] In the following description, the large pixel group 50aa-1 will be mainly described as an example. The small pixel group 20-1 illustrated in the upper left part of the drawing includes a pixel 2-1, a pixel 2-2, a pixel 2-3, and a pixel 2-4. The small pixel group 20-2 arranged below in the drawing of the small pixel group 20-1 includes the pixel 2-5, the pixel 2-6, the pixel 2-7, and the pixel 2-8.

[0260] The small pixel group 20-3 arranged below in the drawing of the small pixel group 20-2 includes the pixel 2-9, the pixel 2-10, the pixel 2-11, and the pixel 2-12. The small pixel group 20-4 arranged below in the drawing of the small pixel group 20-3 includes the pixel 2-13, the pixel 2-14, the pixel 2-15, and the pixel 2-16.

[0261] As illustrated in Fig. 56, each pixel 2 includes the PD 31, and has a configuration in which the charge accumulated in the PD 31 is transferred to the FD 23 by the transfer gate 22 of the transfer transistor.

[0262] The pixels 2-1 to 2-4 of the small pixel group 20-1 includes a PD 31-1 to a PD 31-4 (not illustrated), and include transfer gates 22-1 to 22-4, respectively. An FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0263] The pixels 2-5 to 2-8 of the small pixel group 20-2 includes a PD 31-5 to a PD 31-8 (not illustrated), and include transfer gates 22-5 to 22-8, respectively. An FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0264] The pixels 2-9 to 2-12 of the small pixel group 20-3 includes a PD 31-9 to a PD 31-12 (not illustrated), and include transfer gates 22-9 to 22-12, respectively. An FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0265] The pixels 2-13 to 2-16 of the small pixel group 20-4 includes a PD 31-13 to a PD 31-16 (not illustrated), and include transfer gates 22-13 to 22-16, respectively. An FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0266] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. In the example illustrated in Fig. 55, since the FDs 23-1 to 23-4 are arranged in a straight line in the longitudinal direction, the wire 40 connecting the FDs 23-1 to 23-4 is also provided in a straight line in the longitudinal direction.

[0267] The wire 40 is also connected to the FD 23-11 provided between the large pixel group 50aa-1 and the large pixel group 50aa-2, and below the center in the drawing via the contact 24-11. Therefore, the FDs 23-1 to 23-4 and 23-11 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50. Hereinafter, in a case where it is not necessary to individually distinguish the FDs 23-1 to 23-4 and 23-11, or in a case where it is indicated that the FDs function as one FD, the FDs are simply referred to as the FD 23.

[0268] A reset transistor 25-2 is provided above the FD 23-11 in the drawing, and the FD 23 is reset by the reset transistor 25-2.

[0269] The amplification transistor 26-1 is provided near the center in Fig. 55, and a contact 24-12 is provided at the gate of the amplification transistor 26-1. The contact 24-12 is connected to the wire 40. The FD 23-1 to 23-4 and 23-11 are connected to the amplification transistor 26-2 via the wire 40.

[0270] The amplification transistor 26 has a transfer gate connected to the FD 23 and a drain connected to a power supply VDD 28, and serves as an input unit of a readout circuit that reads a signal corresponding to the charge held in the FD 23, a so-called source follower circuit. That is, the amplification transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via a selection transistor 27, so that it is possible to constitute a source follower circuit together with a constant current source (not illustrated) connected to one end of the vertical signal line 9.

[0271] As illustrated in Fig. 55, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 are arranged in a line in the longitudinal direction between the large pixel group 50aa-1 and the large pixel group 50aa-2. A contact connected to the power supply VDD 28 and a contact connected to the vertical signal line 9 (VSL region 29) are also arranged in a line in the longitudinal direction together with the transistor between the large pixel groups 50.

[0272] The description of cross-sectional configuration example taken along line A-A' in Fig. 55 will be continued with reference to Fig. 56. The pixel 2-7 and the pixel 2-8 included in the large pixel group 50aa-1, the amplification transistor 26, and the pixel 2-23 and the pixel 2-24 included in the large pixel group 50aa-2 taken along line A-A' are arranged in this order. In Fig. 56, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side.

[0273] An inter-pixel separation portion 32-7 for separating from the pixel 2 (not illustrated) is provided left of the PD 31-7, and an inter-pixel separation portion 32-8 for separating from the PD 31-8 is provided right of the PD 31-7. An inter-pixel separation portion 32-9 is provided between the PD 31-8 and the PD 31-23, an inter-pixel separation portion 32-10 is provided between the PD 31-23 and the PD 31-24, and an inter-pixel separation portion 32-11 is provided between the PD 31-24 and the PD 31 (not illustrated) of the adjacent pixel 2. The inter-pixel separation portion 32 can include an oxide film.

[0274] Above the inter-pixel separation portion 32-7 in the drawing, a cell well 35-7 and a FLAT separation portion 33-7 are provided. Above the inter-pixel separation portion 32-8 in the drawing, a cell well 35-8 and a FLAT separation portion 33-8 are provided. Above the inter-pixel separation portion 32-9 in the drawing, a cell well 35-9 is provided and above the cell well 35-9 in the drawing, a FLAT separation portion 33-9, a channel region 37 of the amplification transistor 26-1, and a FLAT separation portion 33-10 are provided.

[0275] Above the inter-pixel separation portion 32-10 in the drawing, a cell well 35-10 and a FLAT separation portion 33-11 are provided. Above the inter-pixel separation portion 32-11 in the drawing, a cell well 35-11 and a FLAT separation portion 33-12 are provided. The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other.

[0276] The transfer gate 22-7 is provided on the PD 31-7 located between the FLAT separation portion 33-7 and the FLAT separation portion 33-8. The transfer gate 22-8 is provided on the PD 31-8 located between the FLAT separation portion 33-8 and the FLAT separation portion 33-9. The transfer gate 22-23 is provided on the PD 31-23 located between the FLAT separation portion 33-10 and the FLAT separation portion 33-11. The transfer gate 22-24 is provided on the PD 31-24 located between the FLAT separation portion 33-11 and the FLAT separation portion 33-12.

[0277] The pixels 2 are separated by the inter-pixel separation portion 32, and the element separation portion is provided in an active region in the pixel 2. The element separation portion is, for example, the cell well 35 and the FLAT separation portion 33. Referring to Fig. 55, the reset transistor 25-1 is provided in the active region 70-1. In an active region 70-2, a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided. In an active region 70-3, a selection transistor 27-2 and an amplification transistor 26-2 are provided.

[0278] The active region 70-1 is formed across the large pixel group 50aa-1 and the large pixel group 50aa (not illustrated) arranged above the large pixel group 50aa-2. The active region 70-2 is arranged between the large pixel group 50aa-1 and the large pixel group 50aa-2. The active region 70-3 is formed across the large pixel group 50aa-1 and the large pixel group 50aa (not illustrated) arranged below the large pixel group 50aa-2.

[0279] Attention is paid to the large pixel group 50aa-1. The pixels 2-1 to 2-16 arranged in the large pixel group 50aa-1 use the selection transistor 27-1, the amplification transistor 26-1, and the reset transistor 25-2 arranged in the active region 70-2. The pixels 2 in the large pixel group 50aa-1 are configured to perform processing using a transistor arranged in an active region 70-2 formed in a region adjacent to the large pixel group 50aa-1 (a region included in the large pixel group 55aa-1).

[0280] With such a configuration, the transistor can be arranged such that the distance of the wire 40 is minimized (or alternatively, decreased).

[0281] Also in the large pixel group 50aa illustrated in Figs. 55 and 56, the relationship of the distance between the adjacent FDs 23 described with reference to Figs. 5 and 6 is established. For example, the distance between the adjacent FDs 23 with no transistor interposed between the adjacent large pixel groups 50aa is (2× length), and the distance between the adjacent FDs 23 with the transistor interposed between the large pixel groups 50aa is (2× length B).

[0282] The FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor interposed therebetween are different from each other.

[0283] Although the FDs 23 are arranged so as to have different distances therebetween, the size of the PD 31 is configured to be equal as in the case described with reference to Fig. 6. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 56, the cell well 35-9 below the amplification transistor 26 is formed to be larger than the other cell wells 35, and the PD 31-8 and the PD 31-23 are adjusted so as not to be larger than the other PDs 31.

[0284] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0285] Also in the twenty-fifth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0286] <Twenty-sixth embodiment> Fig. 57 depicts a planar configuration example of a large pixel group 50ab according to the twenty-sixth embodiment, and Fig. 58 is a view depicting a cross-sectional configuration example of the large pixel group 50ab taken along line A-A' in Fig. 57. In the large pixel group 50ab in the twenty-sixth embodiment illustrated in Figs. 57 and 58, portions similar to those of the large pixel group 50aa in the twenty-fifth embodiment illustrated in Figs. 55 and 56 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0287] The large pixel group 50ab in the twenty-sixth embodiment illustrated in Figs. 57 and 58 is different from the large pixel group 50aa in the twenty-fifth embodiment in that a transfer gate 22ab is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 58, the transfer gate 22ab of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined.

[0288] As illustrated in Fig. 57, the vertical electrode of the transfer gate 22ab is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0289] The transfer efficiency can be improved by configuring the transfer gate 22ab to include the vertical electrode.

[0290] Also in the twenty-sixth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0291] <Twenty-seventh embodiment> Fig. 59 depicts a planar configuration example of a large pixel group 50ac according to the twenty-seventh embodiment, A of Fig. 60 depicts a cross-sectional configuration example of the large pixel group 50ac taken along line A-A' in Fig. 59, and B of Fig. 60 is a view depicting a cross-sectional configuration example of the large pixel group 50ac taken along line B-B' in Fig. 59. In the large pixel group 50ac in the twenty-seventh embodiment illustrated in Figs. 59 and 60, portions similar to those of the large pixel group 50aa in the twenty-fifth embodiment illustrated in Figs. 55 and 56 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0292] The large pixel group 50ac in the twenty-seventh embodiment illustrated in Figs. 59 and 60 is different from the large pixel group 50aa in the twenty-fifth embodiment in that a transfer gate 22ac is a transfer gate having a vertical structure, and the other points are similar.

[0293] As illustrated in Fig. 60, the transfer gate 22ac of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Further, the transfer gate 22ac is formed in a shape so as to sandwich a portion corresponding to the inter-pixel separation portion.

[0294] Referring to A of Fig. 60, an STI 61-8 is formed on a cell well 35-12 (substrate front face side) provided between the PD 31-7 and the PD 31-8. A transfer gate 22-7ac of the PD 31-7 and a transfer gate 22-8ac of the PD 31-8 are formed so as to sandwich (contact) the STI 61-8. Similarly, the STI 61 is formed on the cell well 35 (substrate front face side) provided between the PDs 31, and the transfer gate 22ac of the PD 31 is formed so as to sandwich (contact) the STI 61.

[0295] B of Fig. 60 is a view depicting a cross-sectional configuration example of the large pixel group 50ac taken along line B-B' of Fig. 59. The pixel 2-1, the pixel 2-3, and the pixel 2-4 taken along line B-B' are arranged. As illustrated in B of Fig. 60, the STI 61-3 is formed on the substrate front face between the PD 31-1 included in the pixel 2-1 and the PD 31-3 included in the pixel 2-3. A transfer gate 22ac-1 of the transfer transistor of the pixel 2-1 and a transfer gate 22ac-3 of the transfer transistor of the pixel 2-3 are configured in a shape having a vertical electrode so as to sandwich (contact) the STI 61-3.

[0296] As illustrated in B of Fig. 60, in the transfer gate 22ac-3 arranged on the pixel 2-3, vertical electrodes are formed at both ends so as to sandwich the PD 31-3, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22ac-3 is formed in a shape that looks like a Π shape in cross-sectional view.

[0297] In the twenty-seventh embodiment, since the transfer gates 22ac of the transfer transistors are configured to be close to each other, in order to reduce the influence, the STI 61 is provided between the transfer gates 22ac, and the STI 61 can include an oxide film.

[0298] As illustrated in Fig. 59, the vertical electrode of the transfer gate 22ac is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22ac is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0299] The transfer efficiency can be improved by configuring the transfer gate 22ac to include the vertical electrode.

[0300] Also in the twenty-seventh embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0301] <Twenty-eighth embodiment> Fig. 61 depicts a planar configuration example of a large pixel group 50ad according to the twenty-eighth embodiment, and Fig. 62 is a view depicting a cross-sectional configuration example of the large pixel group 50ad taken along line A-A' in Fig. 61. In the large pixel group 50ad in the twenty-eighth embodiment illustrated in Figs. 61 and 62, portions similar to those of the large pixel group 50aa in the twenty-fifth embodiment illustrated in Figs. 55 and 56 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0302] The large pixel group 50ad in the twenty-eighth embodiment illustrated in Figs. 61 and 62 is different from the large pixel group 50aa in the twenty-fifth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0303] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0304] In cross-sectional view, as illustrated in Fig. 62, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-1, and are configured to be element separated from other elements.

[0305] Also in the twenty-eighth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0306] <Twenty-ninth embodiment> Fig. 63 depicts a planar configuration example of a large pixel group 50ae in the twenty-ninth embodiment, and Fig. 64 is a view depicting a cross-sectional configuration example of the large pixel group 50ae taken along line A-A' in Fig. 63. In the large pixel group 50ae in the twenty-ninth embodiment illustrated in Figs. 63 and 64, portions similar to those of the large pixel group 50ab in the twenty-sixth embodiment illustrated in Figs. 57 and 58 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0307] The large pixel group 50ae in the twenty-ninth embodiment illustrated in Figs. 63 and 64 is different from the large pixel group 50ab in the twenty-sixth embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0308] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0309] In cross-sectional view, as illustrated in Fig. 64, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-1, and are configured to be element separated from other elements. In addition, a transfer gate 22ae is configured to have a vertical electrode.

[0310] Also in the twenty-ninth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PE 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0311] <Thirtieth embodiment> Fig. 65 depicts a planar configuration example of a large pixel group 50af according to the thirtieth embodiment, A of Fig. 66 depicts a cross-sectional configuration example of the large pixel group 50af taken along line A-A' in Fig. 65, and B of Fig. 66 is a view depicting a cross-sectional configuration example of the large pixel group 50af taken along line B-B' in Fig. 65. In the large pixel group 50af in the thirtieth embodiment illustrated in Figs. 65 and 66, portions similar to those of the large pixel group 50ac in the twenty-seventh embodiment illustrated in Figs. 59 and 60 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0312] The large pixel group 50af in the thirtieth embodiment illustrated in Figs. 65 and 66 is different from the large pixel group 50ac in the twenty-seventh embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0313] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0314] In cross-sectional view, as illustrated in A of Fig. 66, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-1, and are configured to be element separated from other elements. In addition, the transfer gate 22af includes a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0315] Also in the thirtieth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0316] <Thirty-first embodiment> Fig. 67 depicts a planar configuration example of a large pixel group 50ag in the thirty-first embodiment, and A in Fig. 68 is a view depicting a cross-sectional configuration example of a large pixel group 50af taken along line A-A' in Fig. 67. In the large pixel group 50ag in the thirty-first embodiment illustrated in Figs. 67 and 68, portions similar to those of the large pixel group 50aa in the twenty-fifth embodiment illustrated in Figs. 55 and 56 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0317] The large pixel group 50ag illustrated in Fig. 67 includes 16 pixels 2 of 8×2. The small pixel group 20 includes 4 pixels 2 of 2×2, and the large pixel group 50ag includes 4 small pixel groups 20 of 4×1.

[0318] In the example illustrated in Fig. 67, the large pixel group 50ag includes four units of small pixel groups 20 arranged in the lateral direction. A large pixel group 50ag-1 includes the small pixel group 20-1, the small pixel group 20-2, the small pixel group 20-3, and the small pixel group 20-4 from the left in this order in the drawing. A large pixel group 50ag-2 arranged on the upper side in the drawing of the large pixel group 50ag-1 includes the small pixel group 20-5, the small pixel group 20-6, the small pixel group 20-7, and the small pixel group 20-8 from the left in this order in the drawing.

[0319] In the following description, the large pixel group 50ag-1 will be mainly described as an example. The small pixel group 20-1 illustrated on the left side in the drawing includes the pixel 2-1, the pixel 2-2, the pixel 2-3, and the pixel 2-4. The small pixel group 20-2 arranged right of the small pixel group 20-1 in the drawing includes the pixel 2-5, the pixel 2-6, the pixel 2-7, and the pixel 2-8.

[0320] The small pixel group 20-3 arranged right of the small pixel group 20-2 in the drawing includes the pixel 2-9, the pixel 2-10, the pixel 2-11, and the pixel 2-12. The small pixel group 20-4 arranged right of the small pixel group 20-3 in the drawing includes the pixel 2-13, the pixel 2-14, the pixel 2-15, and the pixel 2-16.

[0321] As illustrated in Fig. 68, each pixel 2 includes the PD 31, and has a configuration in which the charge accumulated in the PD 31 is transferred to the FD 23 by the transfer gate 22 of the transfer transistor.

[0322] The pixels 2-1 to 2-4 of the small pixel group 20-1 includes a PD 31-1 to a PD 31-4 (not illustrated), and include transfer gates 22-1 to 22-4, respectively. An FD 23-1 is provided at the center of the region where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wire 40 in a stacked wire layer (not illustrated).

[0323] The pixels 2-5 to 2-8 of the small pixel group 20-2 includes a PD 31-5 to a PD 31-8 (not illustrated), and include transfer gates 22-5 to 22-8, respectively. An FD 23-2 is provided at the center of the region where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0324] The pixels 2-9 to 2-12 of the small pixel group 20-3 includes a PD 31-9 to a PD 31-12 (not illustrated), and include transfer gates 22-9 to 22-12, respectively. An FD 23-3 is provided at the center of the region where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0325] The pixels 2-13 to 2-16 of the small pixel group 20-4 includes a PD 31-13 to a PD 31-16 (not illustrated), and include transfer gates 22-13 to 22-16, respectively. An FD 23-4 is provided at a position to be the center of the transfer gates 22-13 to 22-16. The FD 23-4 is provided with a contact 24-4, and the contact 24-4 is connected to the wire 40 in a stacked wire layer (not illustrated).

[0326] The FDs 23-1 to 23-4 provided in the small pixel groups 20-1 to 20-4, respectively, are connected to the wire 40. In the example illustrated in Fig. 67, since the FDs 23-1 to 23-4 are arranged in a straight line in the lateral direction, the wire 40 connecting the FDs 23-1 to 23-4 is also provided in a straight line in the lateral direction.

[0327] The wire 40 is also connected to the FD 23-11 provided between the large pixel group 50ag-1 and the large pixel group 50ag-2, and left of the center in the drawing via the contact 24-11. Therefore, the FDs 23-1 to 23-4 and 23-11 function as one FD, and are shared and used by the pixels 2-1 to 2-16 in the large pixel group 50.

[0328] The reset transistor 25-1 is provided right of the FD 23-11 in the drawing, and the FD 23 is reset by the reset transistor 25-1.

[0329] The amplification transistor 26-2 is provided right of the center in Fig. 67, and the contact 24-12 is provided at the gate of the amplification transistor 26-2. The contact 24-12 is connected to the wire 40. The FD 23-1 to 23-4 and 23-11 are connected to the amplification transistor 26-2 via the wire 40.

[0330] The amplification transistor 26-2 has a transfer gate connected to the FD 23 and a drain connected to the power supply VDD 28, and serves as an input unit of a readout circuit that reads a signal corresponding to the charge held in the FD 23, a so-called source follower circuit. That is, the amplification transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via the selection transistor 27-2, so that it is possible to constitute a source follower circuit together with a constant current source (not illustrated) connected to one end of the vertical signal line 9.

[0331] As illustrated in Fig. 67, the reset transistor 25-1, the amplification transistor 26-2, and the selection transistor 27-2 are arranged in the active region 70-2, and these transistors are arranged in a line in the lateral direction between the large pixel group 50ag-1 and the large pixel group 50ag-2. A contact connected to the power supply VDD 28 and a contact connected to the vertical signal line 9 (VSL region 29) are also arranged in a line in the lateral direction together with the transistor in a region between the large pixel groups 50ag.

[0332] The description of cross-sectional configuration example taken along line A-A' in Fig. 67 will be continued with reference to Fig. 68. The pixel 2-25 and the pixel 2-27 included in the large pixel group 50ag-2, the amplification transistor 26-2, and the pixel 2-9 and the pixel 2-11 included in the large pixel group 50ag-1 taken along line A-A' are arranged in this order. In Fig. 67, a light incident face is provided on the lower side, and a wire layer (not illustrated) is provided on the upper side. The inter-pixel separation portion 32 for separating from an adjacent PD 31 (pixel 2) is provided between the PDs 31. The inter-pixel separation portion 32 can include an oxide film.

[0333] Above the inter-pixel separation portion 32 in the drawing, a cell well 35 and a FLAT separation portion 33 are provided. The cell well 35 and the FLAT separation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements) from each other.

[0334] The pixels 2 are separated by the inter-pixel separation portion 32, and the element separation portion is provided in an active region in the pixel 2. The element separation portion is, for example, the cell well 35 and the FLAT separation portion 33. Referring to Fig. 67, the reset transistor 25-1 is provided in the active region 70-1. In an active region 70-2, a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided. In an active region 70-3, a selection transistor 27-2 and an amplification transistor 26-2 are provided.

[0335] The active region 70-1 is formed across the large pixel group 50ag-1 and the large pixel group 50ag (not illustrated) arranged left of the large pixel group 50ag-2. The active region 70-2 is arranged between the large pixel group 50ag-1 and the large pixel group 50ag-2. The active region 70-3 is formed across the large pixel group 50ag-1 and the large pixel group 50ag (not illustrated) arranged right of the large pixel group 50ag-2.

[0336] Attention is paid to the large pixel group 50ag-1. The pixels 2-1 to 2-16 arranged in the large pixel group 50ag-1 use the selection transistor 27-1, the amplification transistor 26-1, and the reset transistor 25-2 arranged in the active region 70-2. The pixels 2 in the large pixel group 50ag-1 are configured to perform processing using a transistor arranged in the active region 70-2 formed in a region adjacent to the large pixel group 50ag-1 (a region included in the large pixel group 50ag-1).

[0337] With such a configuration, the transistor can be arranged such that the distance of the wire 40 is minimized (or alternatively, decreased).

[0338] Also in the large pixel group 50ag illustrated in Figs. 67 and 68, the relationship of the distance between the adjacent FDs 23 described with reference to Figs. 5 and 6 is established. For example, the distance between the adjacent FDs 23 with no region where the transistor is arranged in the adjacent large pixel group 50ag disposed is (2× length A), and the distance between the adjacent FDs 23 with the region where the transistor is arranged in the large pixel group 50ag disposed is (2× length B).

[0339] The FDs 23 and the transistors are arranged such that the distance between the FDs 23 in the adjacent positional relationship with the transistor interposed therebetween and the distance between the FDs 23 in the adjacent positional relationship without the transistor interposed therebetween are different from each other.

[0340] Although the FDs 23 are arranged so as to have different distances therebetween, the size of the PD 31 is configured to be equal as in the case described with reference to Fig. 6. In order to equalize the size of each PD 31, for example, in the cross-sectional configuration example illustrated in Fig. 68, the cell well 35-27 below the amplification transistor 26-2 is formed to be larger than the other cell wells 35, and the PD 31-27 and the PD 31-9 are adjusted so as not to be larger than the other PDs 31.

[0341] With such a configuration, even in a case where the light detection device 1 is downsized, a charge transfer region can be secured while maintaining a region where the transistor is arranged, and both the characteristics of the transistor and the charge transfer characteristics can be achieved.

[0342] Also in the thirty-first embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0343] <Thirty-second embodiment> Fig. 69 depicts a planar configuration example of a large pixel group 50ah in the thirty-second embodiment, and Fig. 70 is a view depicting a cross-sectional configuration example of the large pixel group 50ah taken along line A-A' in Fig. 69. In the large pixel group 50ah in the thirty-second embodiment illustrated in Figs. 69 and 70, portions similar to those of the large pixel group 50ag in the thirty-first embodiment illustrated in Figs. 67 and 68 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0344] The large pixel group 50ah in the twenty-sixth embodiment illustrated in Figs. 69 and 70 is different from the large pixel group 50ag in the thirty-first embodiment in that a transfer gate 22ah is a transfer gate having a vertical structure, and the other points are similar. As illustrated in Fig. 70, the transfer gate 22ah of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined.

[0345] As illustrated in Fig. 69, the vertical electrode of the transfer gate 22ah is formed in a circular shape in plan view. The vertical electrode is formed in a circular shape or a polygonal shape.

[0346] The transfer efficiency can be improved by configuring the transfer gate 22ah to include the vertical electrode.

[0347] Also in the thirty-second embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0348] <Thirty-third embodiment> Fig. 71 depicts a planar configuration example of a large pixel group 50ai in the thirty-third embodiment, A of Fig. 72 depicts a cross-sectional configuration example of the large pixel group 50ai taken along line A-A' in Fig. 71, and B of Fig. 72 is a view depicting a cross-sectional configuration example of the large pixel group 50ai taken along line B-B' in Fig. 71. In the large pixel group 50ai in the thirty-third embodiment illustrated in Figs. 71 and 72, portions similar to those of the large pixel group 50ag in the thirty-first embodiment illustrated in Figs. 67 and 68 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0349] The large pixel group 50ai in the thirty-third embodiment illustrated in Figs. 71 and 72 is different from the large pixel group 50ag in the thirty-first embodiment in that a transfer gate 22ai is a transfer gate having a vertical structure, and the other points are similar.

[0350] As illustrated in Fig. 72, the transfer gate 22ai of the transfer transistor has a shape in which a planar electrode provided in a planar shape on the front face of the semiconductor substrate and a vertical electrode provided in a vertical shape in the semiconductor substrate are combined. Further, the transfer gate 22ai is formed in a shape so as to sandwich a portion corresponding to the inter-pixel separation portion. The transfer gate 22i is formed in a Π shape as in the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0351] As illustrated in B of Fig. 72, in the transfer gate 22ai-3 arranged on the pixel 2-3, vertical electrodes are formed at both ends so as to sandwich the PD 31-3, and a flat electrode provided on the substrate is formed at the upper portion. The transfer gate 22ai-3 is formed in a shape that looks like a Π shape in cross-sectional view.

[0352] In the thirty-third embodiment, since the transfer gates 22ai of the transfer transistors are configured to be close to each other, in order to reduce the influence, the STI 61 is provided between the transfer gates 22ai, and the STI 61 can include an oxide film.

[0353] As illustrated in Fig. 71, the vertical electrode of the transfer gate 22ai is formed in a trapezoidal shape in plan view, and the bottom thereof is formed close to the STI 61. Note that the vertical electrode of the transfer gate 22ai is not limited to having the trapezoidal shape in plan view, and may have another shape.

[0354] The transfer efficiency can be improved by configuring the transfer gate 22ai to include the vertical electrode.

[0355] Also in the thirty-third embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0356] <Thirty-fourth embodiment> Fig. 73 depicts a planar configuration example of a large pixel group 50aj according to the thirty-fourth embodiment, and Fig. 74 is a view depicting a cross-sectional configuration example of the large pixel group 50aj taken along line A-A' in Fig. 73. In the large pixel group 50aj in the thirty-fourth embodiment illustrated in Figs. 73 and 74, portions similar to those of the large pixel group 50ag in the thirty-first embodiment illustrated in Figs. 67 and 68 are denoted by the similar reference numerals, and the description thereof is appropriately omitted.

[0357] The large pixel group 50aj in the thirty-fourth embodiment illustrated in Figs. 73 and 74 is different from the large pixel group 50ag in the thirty-first embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0358] The STI 71 is formed in the lateral direction of the central region of the large pixel group 50aj around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0359] In cross-sectional view, as illustrated in Fig. 74, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-2, and are configured to be element separated from other elements.

[0360] Also in the thirty-fourth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0361] <Thirty-fifth embodiment> Fig. 75 depicts a planar configuration example of a large pixel group 50ak in the thirty-fifth embodiment, and Fig. 76 is a view depicting a cross-sectional configuration example of the large pixel group 50ak taken along line A-A' in Fig. 75. In the large pixel group 50ak in the thirty-fifth embodiment illustrated in Figs. 75 and 76, portions similar to those of the large pixel group 50ah in the thirty-second embodiment illustrated in Figs. 69 and 70 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0362] The large pixel group 50ak in the thirty-fifth embodiment illustrated in Figs. 75 and 76 is different from the large pixel group 50ah in the thirty-second embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0363] The STI 71 is formed in the longitudinal direction in the central region of the large pixel group 50ak around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0364] In cross-sectional view, as illustrated in Fig. 76, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-2, and are configured to be element separated from other elements. In addition, a transfer gate 22ak has a vertical electrode.

[0365] Also in the thirty-fifth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the thirty-first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0366] <Thirty-sixth embodiment> Fig. 77 depicts a planar configuration example of a large pixel group 50am in the thirty-sixth embodiment, A of Fig. 78 depicts a cross-sectional configuration example of the large pixel group 50am taken along line A-A' in Fig. 77, and B of Fig. 78 is a view depicting a cross-sectional configuration example of the large pixel group 50am taken along line B-B' in Fig. 77. In the large pixel group 50am in the thirty-sixth embodiment illustrated in Figs. 77 and 78, portions similar to those of the large pixel group 50ai in the thirty-third embodiment illustrated in Figs. 71 and 72 are denoted by the similar reference numerals, and the description thereof will be appropriately omitted.

[0367] The large pixel group 50am in the thirty-sixth embodiment illustrated in Figs. 77 and 78 is different from the large pixel group 50ai in the thirty-third embodiment in that element separation of a region where transistors are arranged is performed by the STI, and the other points are similar.

[0368] The STI 71 is formed in the longitudinal direction of the central region of the large pixel group 50 around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged.

[0369] In cross-sectional view, as illustrated in A of Fig. 78, the STIs 71 are formed at both sides of the channel region 37 of the amplification transistor 26-2, and are configured to be element separated from other elements. In addition, the transfer gate 22am has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0370] Also in the thirty-sixth embodiment, as in the first embodiment and the like, the distance between the adjacent FDs 23 is configured to be different between a portion where the transistor is sandwiched and a portion where the transistor is not sandwiched. The size of the PD 31 is adjusted so as to be the same in each pixel 2. Therefore, as in the first embodiment, even in a case where the light detection device 1 is downsized, it is possible to secure the charge transfer region while maintaining the region where the transistor is arranged, and it is possible to achieve both the characteristics of the transistor and the charge transfer characteristics.

[0371] <Application example to electronic apparatus> The present technology is not limited to application to an image pickup element. That is, the present technology can be applied to all electronic apparatuses including an image pickup element in an image capturer (photoelectric conversion unit), such as an imaging device like a digital still camera or a video camera, a mobile terminal device having an imaging function, and a copying machine including an image pickup element in an image reader. An image pickup element may be formed as one chip, or may be in a modular form having an imaging function in which an image pickup unit and a signal processing unit or an optical system are packaged together.

[0372] Fig. 79 is a block diagram depicting a configuration example of an imaging device as an electronic apparatus to which the present technology is applied.

[0373] An image pickup element 1000 in Fig. 79 includes an optical unit 1001 including a lens group and the like, an image pickup element (imaging device) 1002 to which the configuration of the light detection device 1 in Fig. 1 is used, and a digital signal processor (DSP) circuit 1003 that is a camera signal processing circuit. The image pickup element 1000 also includes a frame memory 1004, a display section 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display section 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to one another via a bus line 1009.

[0374] The optical unit 1001 captures incident light (image light) from an object, and forms an image on the imaging surface of the image pickup element 1002. The image pickup element 1002 converts the amount of the incident light the image of which is formed on the imaging surface by the optical unit 1001, into an electric signal on a pixel basis, to output the electric signal as a pixel signal. As the image pickup element 1002, the light detection device 1 in Fig. 1 can be used.

[0375] The display section 1005 is formed with a flat-panel display such as a liquid crystal display (LCD) or an organic electro luminescence (EL) display, for example, and displays a video image or a still image formed by the image pickup element 1002. The recording unit 1006 records the video image or the still image captured by the image pickup element 1002 in a recording medium such as a hard disk or a semiconductor memory.

[0376] The operation unit 1007 issues operation commands for various functions of the image pickup element 1000, being operated by the user. The power supply unit 1008 appropriately supplies various kinds of power that is the operating power supply for the DSP circuit 1003, the frame memory 1004, the display section 1005, the recording unit 1006, and the operation unit 1007, to these supply targets.

[0377] <Example application to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0378] Fig. 80 is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

[0379] In Fig. 80, a state is illustrated in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery for a patient 11132 on a patient bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a supporting arm apparatus 11120 which supports the endoscope 11100 thereon, and a cart 11200 on which various apparatus for endoscopic surgery are mounted.

[0380] The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.

[0381] The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.

[0382] An optical system and an image pickup element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU 11201.

[0383] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).

[0384] The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.

[0385] The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.

[0386] An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.

[0387] A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity in order to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.

[0388] It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head 11102 are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.

[0389] Further, the light source apparatus 11203 may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.

[0390] Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and / or excitation light suitable for special light observation as described above.

[0391] Fig. 81 is a block diagram depicting an example of a functional configuration of the camera head 11102 and the CCU 11201 depicted in Fig. 80.

[0392] The camera head 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.

[0393] The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0394] The number of image pickup elements which is included by the image pickup unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit 11402 may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pickup unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pickup elements.

[0395] Further, the image pickup unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pickup unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.

[0396] The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit 11402 can be adjusted suitably.

[0397] The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pickup unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

[0398] In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and / or information that a magnification and a focal point of a picked up image are designated.

[0399] It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0400] The camera head controlling unit 11405 controls driving of the camera head 11102 on the basis of a control signal from the CCU 11201 received through the communication unit 11404.

[0401] The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.

[0402] Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.

[0403] The image processing unit 11412 performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head 11102.

[0404] The control unit 11413 performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope 11100 and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.

[0405] Further, the control unit 11413 controls, on the basis of an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit 11413 may cause, when it controls the display apparatus 11202 to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.

[0406] The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.

[0407] Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0408] <Application example to mobile object> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure may be achieved in the form of a device to be mounted on a mobile object of any kind, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

[0409] Fig. 82 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile object control system to which the technology according to an embodiment of the present disclosure can be applied.

[0410] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 82, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0411] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0412] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0413] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0414] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0415] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0416] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0417] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0418] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0419] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 82, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0420] Fig. 83 is a view depicting an example of the installation position of the image pickup unit 12031.

[0421] In Fig. 83, the image pickup unit 12031 includes image pickup units 12101, 12102, 12103, 12104, and 12105.

[0422] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0423] Note that Fig. 83 depicts an example of photographing ranges of the image pickup units 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0424] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0425] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0426] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0427] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0428] In the present specification, the system represents the entire device including a plurality of devices.

[0429] Note that the effects described in the present description are merely examples and are not limited, and other effects may be provided.

[0430] Note that the embodiments of the present technology are not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present technology.

[0431] Note that the present technology can also have the following configurations. (1) A light detection device including a pixel including a photoelectric conversion unit, a charge holding unit that holds a charge generated by the photoelectric conversion unit, a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit, in which the charge holding unit is shared by four of the pixels and is arranged at a center of four of the transfer units, a first small pixel group including a first of the charge holding units, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including a second of the charge holding units, and a third small pixel group including a third of the charge holding units are arranged in this order, and a first distance between the first charge holding unit and the second charge holding unit is different from a second distance between the second charge holding unit and the third charge holding unit. (2) The light detection device according to Item (1), in which the small pixel group includes four pixels of 2×2, a large pixel group includes the small pixel group of four units of 2×2, and the first region is arranged in a longitudinal direction or a lateral direction of a central region of the large pixel group. (3) The light detection device according to Item (1), in which the small pixel group includes four pixels of 2×2, the large pixel group includes the small pixel group of four units of 4×1, and the first region is arranged between a first large pixel group and a second large pixel group adjacent to the first large pixel group. (4) The light detection device according to Item (1), in which the small pixel group includes four pixels of 2×2, the large pixel group includes the small pixel group of four units of 4×1, and the first region is arranged between a first large pixel group and a second large pixel group adjacent to the first large pixel group. (5) The light detection device according to any one of Items (2) to (4), in which a first to a fourth of the charge holding units included in the small pixel group are connected to a fifth of the charge holding units provided in the first region, and the first to the fifth charge holding units are shared by 16 pixels included in the large pixel group. (6) The light detection device according to any one of Items (2) to (5), in which the first small pixel group, the first region, and the second small pixel group are included in a first of the large pixel groups, and the third small pixel group is included in a second large pixel group adjacent to the first large pixel group. (7) The light detection device according to any one of Items (1) to (6), in which the transfer unit includes an electrode in the photoelectric conversion unit. (8) The light detection device according to any one of Items (1) to (7), in which a region in which P-type or N-type impurities are diffused is provided between the transfer units. (9) The light detection device according to any one of Items (1) to (7), in which an oxide film is provided between the transfer units. (10) The light detection device according to Item (9), in which the transfer unit includes an electrode in contact with the oxide film. (11) The light detection device according to any one of Items (1) to (10), in which the first region includes an element separation portion including an oxide film. (12) The light detection device according to Item (5), in which a transistor that processes a signal from a pixel included in the large pixel group is arranged in the first region provided across an inside of the large pixel group and an inside of another large pixel group, and the first to the fifth charge holding units are connected by a linear wire. (13) The light detection device according to Item (5), in which a transistor that processes a signal from a pixel included in the large pixel group is arranged in the first region provided in the large pixel group, and a wire connected to the fifth charge holding unit among wires connecting the first to the fifth charge holding units has a bent portion. (14) An electronic apparatus including a light detection device including a pixel including a photoelectric conversion unit, a charge holding unit that holds a charge generated by the photoelectric conversion unit, a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit, in which the charge holding unit is shared by four of the pixels and is arranged at a center of four of the transfer units, a first small pixel group including a first of the charge holding units, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including a second of the charge holding units, and a third small pixel group including a third of the charge holding units are arranged in this order, and a first distance between the first charge holding unit and the second charge holding unit is different from a second distance between the second charge holding unit and the third charge holding unit, and a processing unit that processes a signal from the light detection device. (15) A light detection device, comprising: a plurality of pixels, wherein each pixel includes: a photoelectric conversion unit; and a transfer transistor, the plurality of pixels including a first small pixel group, a second small pixel group, and a third small pixel group; a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group; and a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions, wherein: a first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group, and the second small pixel group is positioned between the first region and a third small pixel group. (16) The light detection device of (15), wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes the first small pixel group and the second small pixel group, and the first region is arranged in a central region of the large pixel group. (17) The light detection device of (15), wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a one-by-four grid, and the first region is arranged between the first large pixel group and a second large pixel group. (18) The light detection device of (15), wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a four-by-one grid, and the first region is arranged between the first large pixel group and a second large pixel group. (19) The light detection device of (15), wherein each small pixel group includes four floating diffusions connected to a floating diffusion provided in the first region, and the floating diffusion provided in the first region is shared by 16 pixels included in a large pixel group. (20) The light detection device of (15), wherein the first small pixel group, the first region, and the second small pixel group are included in a first large pixel group, and the third small pixel group is included in a second large pixel group adjacent to the first large pixel group. (21) The light detection device of (15), wherein the transfer transistor includes an electrode in the photoelectric conversion unit. (22) The light detection device of (15), wherein a region in which P-type or N-type impurities are diffused is provided between transfer transistors of two or more pixels. (23) The light detection device of (15), wherein an oxide film is provided between transfer transistors of two or more pixels. (24) The light detection device of (23), wherein the transfer transistor includes an electrode in contact with the oxide film. (25) The light detection device of (15), wherein the first region includes an element separation portion including an oxide film. (26) The light detection device of (15), wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided across a first large pixel group and across a second large pixel group, each small pixel group includes four floating diffusions connected by a respective linear wire to a floating diffusion provided in the first region. (27) The light detection device of (15), wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided in a large pixel group, and each small pixel group includes four floating diffusions connected by a respective wire to a floating diffusion provided in the first region, wherein one of the respective wires has a bent portion. (28) The light detection device of (15), wherein a first distance between a center of the first small pixel group and a center of the second small pixel group differs from a second distance between the center of the second small pixel group and a center of the third small pixel group. (29) The light detection device of (15), wherein the second small pixel group is adjacent to the third small pixel group. (30) The light detection device of (15), further comprising a second region including a second amplification transistor positioned between the third small pixel group and a fourth small pixel group, wherein the second amplification transistor is configured to amplify a signal voltage corresponding to a charge held in a floating diffusion associated with the third small pixel group. (31) The light detection device of (15), wherein: a first large pixel group includes the first small pixel group and a fourth small pixel group; a second large pixel group includes the second small pixel group and a fifth small pixel group; each of the first, second, fourth, and fifth small pixel groups include four pixels; each pixel of the first large pixel group shares one or more floating diffusions; each pixel of the second large pixel group shares one or more floating diffusions; and the first large pixel group is separated from the second large pixel group by the first region. (32) An electronic apparatus comprising: a light detection device including: a plurality of pixels, wherein each pixel includes: a photoelectric conversion unit; and a transfer transistor, the plurality of pixels including a first small pixel group, a second small pixel group, and a third small pixel group; a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group; and a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions, wherein: a first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group, and the second small pixel group is positioned between the first region and a third small pixel group.

[0432] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0433] 1 Light detection device 2 pixel 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 9 Vertical signal line 10 Pixel drive line 11 Horizontal signal line 13 Input / output terminal 20 Small pixel group 22 Transfer gate 24 Contact 25 Reset transistor 26 Amplification transistor 27 Selection transistor 29 VSL region 31 PD 32 Inter-pixel separation portion 33 FLAT separation portion 35 Cell well 37 Channel region 40 Wire 50 Large pixel group 70 Active region

Claims

1. A light detection device, comprising: a plurality of pixels, wherein each pixel includes: a photoelectric conversion unit; and a transfer transistor, the plurality of pixels including a first small pixel group, a second small pixel group, and a third small pixel group; a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group; and a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions, wherein: a first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group, and the second small pixel group is positioned between the first region and a third small pixel group.

2. The light detection device according to claim 1, wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes the first small pixel group and the second small pixel group, and the first region is arranged in a central region of the large pixel group.

3. The light detection device according to claim 1, wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a one-by-four grid, and the first region is arranged between the first large pixel group and a second large pixel group.

4. The light detection device according to claim 1, wherein each small pixel group includes four pixels arranged in a two-by-two grid, a first large pixel group includes four small pixel groups arranged in a four-by-one grid, and the first region is arranged between the first large pixel group and a second large pixel group.

5. The light detection device according to claim 1, wherein each small pixel group includes four floating diffusions connected to a floating diffusion provided in the first region, and the floating diffusion provided in the first region is shared by 16 pixels included in a large pixel group.

6. The light detection device according to claim 1, wherein the first small pixel group, the first region, and the second small pixel group are included in a first large pixel group, and the third small pixel group is included in a second large pixel group adjacent to the first large pixel group.

7. The light detection device according to claim 1, wherein the transfer transistor includes an electrode in the photoelectric conversion unit.

8. The light detection device according to claim 1, wherein a region in which P-type or N-type impurities are diffused is provided between transfer transistors of two or more pixels.

9. The light detection device according to claim 1, wherein an oxide film is provided between transfer transistors of two or more pixels.

10. The light detection device according to claim 9, wherein the transfer transistor includes an electrode in contact with the oxide film.

11. The light detection device according to claim 1, wherein the first region includes an element separation portion including an oxide film.

12. The light detection device according to claim 1, wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided across a first large pixel group and across a second large pixel group, each small pixel group includes four floating diffusions connected by a respective linear wire to a floating diffusion provided in the first region.

13. The light detection device according to claim 1, wherein a transistor that processes a signal from a pixel is arranged in the first region, wherein the first region is provided in a large pixel group, and each small pixel group includes four floating diffusions connected by a respective wire to a floating diffusion provided in the first region, wherein one of the respective wires has a bent portion.

14. The light detection device according to claim 1, wherein a first distance between a center of the first small pixel group and a center of the second small pixel group differs from a second distance between the center of the second small pixel group and a center of the third small pixel group.

15. The light detection device according to claim 1, wherein the second small pixel group is adjacent to the third small pixel group.

16. The light detection device according to claim 1, further comprising a second region including a second amplification transistor positioned between the third small pixel group and a fourth small pixel group, wherein the second amplification transistor is configured to amplify a signal voltage corresponding to a charge held in a floating diffusion associated with the third small pixel group.

17. The light detection device according to claim 1, wherein: a first large pixel group includes the first small pixel group and a fourth small pixel group; a second large pixel group includes the second small pixel group and a fifth small pixel group; each of the first, second, fourth, and fifth small pixel groups include four pixels; each pixel of the first large pixel group shares one or more floating diffusions; each pixel of the second large pixel group shares one or more floating diffusions; and the first large pixel group is separated from the second large pixel group by the first region.

18. An electronic apparatus comprising: a light detection device including: a plurality of pixels, wherein each pixel includes: a photoelectric conversion unit; and a transfer transistor, the plurality of pixels including a first small pixel group, a second small pixel group, and a third small pixel group; a plurality of floating diffusions, configured to hold a charge generated by the photoelectric conversion unit of each pixel of the first small pixel group and the second small pixel group; and a first amplification transistor configured to amplify a signal voltage corresponding to a charge held in one or more of the floating diffusions, wherein: a first region including the first amplification transistor and a reset transistor is positioned between the first small pixel group and the second small pixel group, and the second small pixel group is positioned between the first region and a third small pixel group.

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