Circuit board

Abstract

Circuit boards 1, 2, 3 include an insulating layer 10 containing a low-temperature co-fired ceramic material, and a via conductor 20 provided inside or on the surface of the insulating layer 10. The via conductor 20 has an exposed surface EX exposed from the insulating layer 10. The insulating layer 10 includes claw parts 15 extending to cover a part of the exposed surface EX of the via conductor 20.

Description

circuit board

[0001] The present invention relates to a circuit board.

[0002] 2. Description of the Related Art Circuit boards using low temperature co-fired ceramic (LTCC) material as an insulating material are known as circuit boards on which heat generating elements such as light emitting elements or semiconductor elements are mounted.

[0003] Patent Document 1 describes a circuit board in which wiring is provided on an insulating layer containing a low-temperature co-fired ceramic material, and the wiring has an area of ​​0.015 mm2 when viewed from above. ２ The present invention discloses a circuit board including a thermal via as described above, wherein the thermal via is formed by stacking multiple layers of tapered conductors each having a tapered end face, each end face of the tapered conductor being in contact with the insulating layer, and the tapered length in the cross section of the tapered conductor being 20 μm or more.

[0004] Patent Document 2 discloses an electronic element package which is composed of a ceramic base and a ceramic frame placed on the upper surface of the base, with a cavity formed inside the frame for accommodating an electronic element, with a via formed in the base below the cavity, penetrating from the upper surface to the lower surface of the base, and the via filled with a thermally conductive material, and which is characterized in that a protrusion is formed on the inner wall of the via, protruding toward the center of the via, and the length dimension of the protrusion along a direction perpendicular to the penetration direction of the via is greater than or equal to the thickness dimension along the penetration direction.

[0005] Japanese Patent No. 7243856 Japanese Patent Application Laid-Open No. 2010-171157

[0006] According to Patent Document 1, a thermal via is made up of multiple layers of tapered conductors with tapered end faces stacked together, and since each end face of the tapered conductor is in contact with an insulating layer, the bonding area between the end face of the tapered conductor and the insulating layer becomes large, creating an anchor effect and firmly bonding the thermal via to the insulating layer.

[0007] Furthermore, according to Patent Document 2, since the thermal conductive material and the protrusion are firmly interlocked with each other, even when a via is formed in the base, the reduction in the flexural strength of the base is suppressed, and as a result, the flexural strength of the electronic element package is maintained at a high level.

[0008] However, although the via conductor shapes described in Patent Documents 1 and 2 increase the bonding strength with the insulating layer, stress tends to concentrate in the tapered and protruding portions, which may result in a decrease in mechanical strength after firing.

[0009] The present invention has been made to solve the above problems, and aims to provide a circuit board in which via conductors are firmly held in an insulating layer and stress is less likely to concentrate on the via conductors.

[0010] The circuit board of the present invention includes an insulating layer containing a low-temperature co-fired ceramic material and a via conductor provided inside or on the surface of the insulating layer, the via conductor having an exposed surface exposed from the insulating layer, and the insulating layer including a claw portion extending to a portion of the exposed surface of the via conductor.

[0011] According to the present invention, it is possible to provide a circuit board in which via conductors are firmly held in an insulating layer and stress is not easily concentrated on the via conductors.

[0012] FIG. 1 is a cross-sectional view schematically showing an example of a circuit board according to a first embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views each showing an enlarged view of an exposed surface of a via conductor in the circuit board according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view schematically showing an example of a used state of the circuit board shown in FIG. 1. FIG. 4 is a cross-sectional view schematically showing an example of a circuit board according to a second embodiment of the present invention. FIG. 5 is a cross-sectional view schematically showing an example of a cross-sectional view showing an enlarged view of an exposed surface of a via conductor in the circuit board according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view schematically showing an example of a circuit board according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view schematically showing an example of a cross-sectional view showing an enlarged view of an exposed surface of a via conductor in the circuit board according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view schematically showing an example of a step of laminating ceramic green sheets. FIG. 9 is a cross-sectional view schematically showing an example of a step of forming a through hole in a laminate of ceramic green sheets. FIG. 10 is a cross-sectional view schematically showing an example of a step of disposing a metal material in a through hole. FIG. 11 is a cross-sectional view schematically showing an example of a step of disposing constraining layers above and below a laminate of ceramic green sheets. Fig. 12 is a cross-sectional view schematically showing an example of a step of firing a laminate of ceramic green sheets. Fig. 13 is a cross-sectional view schematically showing an example of a step of removing a constraining layer. Fig. 14 is an example of a cross-sectional photograph enlarging an exposed surface of a via conductor in a circuit board according to a first embodiment of the present invention. Fig. 15 is an example of a cross-sectional photograph enlarging an exposed surface of a via conductor in a circuit board according to a second embodiment of the present invention. Fig. 16 is a diagram showing the results of a simulation of stress acting on a via conductor.

[0013] The circuit board of the present invention will be described below. However, the present invention is not limited to the following embodiments, and can be appropriately modified and applied within the scope of the present invention. A combination of two or more of the individual desirable configurations of the present invention described in the following embodiments also constitutes the present invention.

[0014] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects due to similar configurations will not be mentioned in each embodiment.

[0015] In the following description, when no particular distinction is made between the embodiments, they will simply be referred to as "the circuit board of the present invention."

[0016] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, and other scales may differ from those of the actual product. In the drawings, the same or equivalent parts will be designated by the same reference numerals. In addition, the same elements will be designated by the same reference numerals in each drawing, and duplicate explanations will be omitted.

[0017] In this specification, terms indicating the relationship between elements (e.g., "perpendicular," "parallel," "orthogonal," etc.) and terms indicating the shape of elements are not expressions that only express a strict meaning, but are expressions that also include a range of substantial equivalence, for example, a difference of about a few percent.

[0018] First Embodiment In a circuit board according to a first embodiment of the present invention, the upper and lower surfaces of the via conductors are exposed from the insulating layer, and the side surfaces of the via conductors are covered with the insulating layer.

[0019] 1 is a cross-sectional view schematically illustrating an example of a circuit board according to a first embodiment of the present invention. In FIG. 1, the Z-axis direction is the thickness direction, and the positive side of the Z-axis is referred to as the top and the negative side as the bottom. This also applies to the other drawings.

[0020] Although the overall configuration is not shown in FIG. 1, the circuit board 1 includes an insulating layer 10 and via conductors 20 provided inside the insulating layer 10 .

[0021] 1 schematically shows a portion of a circuit board 1 where via conductors 20, which are part of wiring, are provided in an insulating layer 10. In this specification, detailed description of wiring other than the via conductors 20 will be omitted.

[0022] The insulating layer 10 includes a low-temperature co-fired ceramic material. The low-temperature co-fired ceramic material refers to a ceramic material that can be sintered at a firing temperature of 1000°C or less and can be co-fired with metals such as silver or copper that are preferably used as materials for forming wiring. The low-temperature co-fired ceramic material is a material such as SiO ２ -CaO-Al ２ O ３ -B ２ O ３ based glass ceramic or SiO ２ -MgO-Al ２ O ３ -B ２ O ３ It is preferred that the glass ceramic comprises a glass-based ceramic.

[0023] The via conductors 20 are preferably made of a metal with high conductivity, the main component of which is silver or copper.

[0024] The via conductors 20 may be wiring vias for electrically connecting wirings on different layers, or may be thermal vias for dissipating heat generated from a heat generating element. Also, the via conductors may serve as both wiring vias and thermal vias.

[0025] Via conductor 20 has an exposed surface EX (see FIG. 2A described below) exposed from insulating layer 10 .

[0026] 1, the via conductor 20 has an upper surface 20a and a lower surface 20b that face each other in the thickness direction of the insulating layer 10 (the Z-axis direction in FIG. 1), and a side surface 20c that connects the upper surface 20a and the lower surface 20b. As shown in FIG. 1, when the upper surface 20a and the lower surface 20b of the via conductor 20 are exposed from the insulating layer 10 and the side surface 20c of the via conductor 20 is covered by the insulating layer 10, the upper surface 20a and the lower surface 20b of the via conductor 20 become exposed surfaces EX.

[0027] The upper surface 20a of the via conductor 20 may be flush with the surface of the insulating layer 10, may be higher than the surface of the insulating layer 10, or may be lower than the surface of the insulating layer 10. Similarly, the lower surface 20b of the via conductor 20 may be flush with the surface of the insulating layer 10, may be higher than the surface of the insulating layer 10, or may be lower than the surface of the insulating layer 10.

[0028] 2A and 2B are enlarged cross-sectional views showing an example of an exposed surface of a via conductor in the circuit board according to the first embodiment of the present invention.

[0029] FIG. 2A schematically shows the range of the exposed surface EX of the via conductor 20.

[0030] As shown in FIG. 2B, the insulating layer 10 includes a tab 15 that extends to a portion of the exposed surface EX of the via conductor 20 (see FIG. 2A).

[0031] The claw portions 15 of the insulating layer 10 extend to a part of the exposed surface EX of the via conductor 20, thereby increasing the bonding area between the insulating layer 10 and the via conductor 20. As a result, the via conductor 20 is more likely to be firmly held in the insulating layer 10.

[0032] Furthermore, unlike Patent Documents 1 and 2, there is no need to form uneven portions in the via conductors 20 to increase the bonding strength with the insulating layer 10, which reduces the number of locations where stress concentrates in the via conductors 20. As a result, stress is less likely to concentrate in the via conductors 20, and residual stress in the circuit board 1 is reduced, which is expected to improve mechanical strength.

[0033] 2B , when the upper surface 20a and the lower surface 20b of the via conductor 20 are exposed from the insulating layer 10, it is preferable that claw portions 15 are provided on a part of the upper surface 20a and a part of the lower surface 20b of the via conductor 20. In this case, the claw portions 15 can restrain the via conductor 20 from above and below, making it even easier to hold the via conductor 20 in the insulating layer 10. The configuration of the claw portions 15 on the upper surface 20a and the lower surface 20b of the via conductor 20 may be the same or different.

[0034] In addition, when the upper surface 20a and the lower surface 20b of the via conductor 20 are exposed from the insulating layer 10, it is sufficient that the claw portion 15 is provided on a part of at least one of the upper surface 20a and the lower surface 20b of the via conductor 20.

[0035] When viewed from the thickness direction of the via conductor 20, the claw portion 15 may be provided on the entire outer periphery of the upper surface 20a of the via conductor 20, or the claw portion 15 may be provided on only a portion of the outer periphery of the upper surface 20a of the via conductor 20.

[0036] Similarly, when viewed from the thickness direction of the via conductor 20, the claw portion 15 may be provided on the entire outer periphery of the lower surface 20b of the via conductor 20, or the claw portion 15 may be provided on only a portion of the outer periphery of the lower surface 20b of the via conductor 20.

[0037] In a cross section taken along the thickness direction of the insulating layer 10, the density of the via conductors 20 is preferably 80% or more. In this case, the density of the via conductors 20 increases, thereby increasing the thermal conductivity and electrical conductivity of the via conductors 20. The density of the via conductors 20 may be 90% or more, 95% or more, 99% or more, or 99.5% or more. The density of the via conductors 20 may be 100% or less than 100%.

[0038] The density of the via conductor 20 means the occupancy rate of the via conductor 20, which can be determined, for example, by taking a photograph of a cross section such as that shown in Figure 1 using a scanning electron microscope (SEM) and analyzing the image, and can be calculated using the formula "density of via conductor (%) = 100 (%) - surface void ratio (%)".

[0039] The via conductors 20 are preferably made of metal blocks such as metal pillars or metal plates. That is, the via conductors 20 are preferably not made of a sintered metal paste. On the other hand, the wiring other than the via conductors 20 may be made of a sintered metal paste. Furthermore, the circuit board 1 may include via conductors made of a sintered metal paste.

[0040] The shape of the claw portion 15 is not particularly limited, but it is preferable that the thickness of the claw portion 15 decreases toward the tip of the claw portion 15 in a cross section along the thickness direction of the insulating layer 10. The exposed surface of the via conductor 20 may have a portion where the thickness of the claw portion 15 is constant. The shape of the claw portion 15 on the upper surface 20a and the lower surface 20b of the via conductor 20 may be the same or different.

[0041] From the viewpoint of holding the via conductors 20, the length of the claw portions 15 is preferably 10 μm or more in a cross section along the thickness direction of the insulating layer 10. On the other hand, the length of the claw portions 15 is, for example, 200 μm or less.

[0042] In a cross section taken along the thickness direction of the insulating layer 10, the length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 is preferably 10 μm or more. The length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 may be 20 μm or more, 50 μm or more, 75 μm or more, or 100 μm or more. On the other hand, the length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 is, for example, 200 μm or less.

[0043] Similarly, in a cross section taken along the thickness direction of the insulating layer 10, the length of the claw portion 15 provided on a portion of the lower surface 20b of the via conductor 20 is preferably 10 μm or more. The length of the claw portion 15 provided on a portion of the lower surface 20b of the via conductor 20 may be 20 μm or more, 50 μm or more, 75 μm or more, or 100 μm or more. On the other hand, the length of the claw portion 15 provided on a portion of the lower surface 20b of the via conductor 20 is, for example, 200 μm or less.

[0044] The lengths of the claw portions 15 on the upper surface 20a and the lower surface 20b of the via conductor 20 may be the same or different.

[0045] In a cross section along the thickness direction of the insulating layer 10, the ratio of the length of the claw portion 15 provided on a part of the upper surface 20a of the via conductor 20 to the length of the side surface 20c of the via conductor 20 is, for example, 10% or more and 200% or less.

[0046] Similarly, in a cross section along the thickness direction of the insulating layer 10, the ratio of the length of the claw portion 15 provided on a part of the lower surface 20b of the via conductor 20 to the length of the side surface 20c of the via conductor 20 is, for example, 10% or more and 200% or less.

[0047] The maximum thickness of the claw portion 15 is, for example, 5 μm or more and 15 μm or less in a cross section along the thickness direction of the insulating layer 10. The maximum thickness of the claw portion 15 on the upper surface 20 a and the lower surface 20 b of the via conductor 20 may be the same or different.

[0048] The height of the via conductor 20 is, for example, 20 μm or more. The height of the via conductor 20 may be 50 μm or more, 100 μm or more, or 150 μm or more. On the other hand, the height of the via conductor 20 may be 5000 μm or less, 3000 μm or less, or 1000 μm or less.

[0049] The cross-sectional area of ​​the via conductor 20 perpendicular to the thickness direction is, for example, 0.0025 mm ２ The cross-sectional area of ​​the via conductor 20 perpendicular to the thickness direction is 0.015 mm ２ It may be 0.25 mm or more. ２ On the other hand, the cross-sectional area of ​​the via conductor 20 perpendicular to the thickness direction is 100 mm ２ It may be less than 50 mm ２ It may be less than 25 mm ２ It may be less than 10 mm ２ It may be the following:

[0050] The cross-sectional shape of the via conductor 20 perpendicular to the thickness direction is not particularly limited, and examples thereof include a circle, an ellipse, and a polygon (such as a square or a rectangle).

[0051] The circle-equivalent diameter of the cross section perpendicular to the thickness direction of the via conductor 20 is preferably larger than the height of the via conductor 20. In this case, the aspect ratio, which is expressed as the circle-equivalent diameter of the cross section perpendicular to the thickness direction of the via conductor 20 / the height of the via conductor 20, is preferably 1 or more and 25 or less.

[0052] FIG. 3 is a cross-sectional view schematically showing an example of a state in which the circuit board shown in FIG. 1 is used.

[0053] FIG. 3 shows a highly thermally conductive ceramic substrate 30 in contact with the lower surface 20b of the via conductor 20 of the circuit board 1, and a heating element 40 mounted on the upper surface 20a of the via conductor 20 via solder 50.

[0054] 3 , the circuit board 1 may be provided with a high thermal conductivity ceramic substrate 30 in contact with the lower surfaces 20 b of the via conductors 20. By providing the high thermal conductivity ceramic substrate 30 in contact with the lower surfaces 20 b of the via conductors 20, heat from the via conductors 20 can be directly conducted to the high thermal conductivity ceramic substrate 30.

[0055] The highly thermally conductive ceramic substrate 30 is preferably a sintered ceramic substrate, and its material is preferably a ceramic such as silicon nitride, aluminum nitride, alumina, or silicon carbide.

[0056] The heat generating element 40 mounted on the upper surface 20a of the via conductor 20 is preferably at least one type of element selected from the group consisting of a power element, a control element, a passive component, and a light emitting element.

[0057] The power element is preferably an element made of a wide bandgap semiconductor, in which case the wide bandgap semiconductor is preferably silicon carbide or gallium nitride.

[0058] The light-emitting element is preferably at least one element selected from the group consisting of an LED element, an organic EL element, a LIDAR element, a RADAR element, and a millimeter-wave element.

[0059] By mounting a heating element 40 on the upper surface 20a of the via conductor 20, the circuit board 1 can be used as a heating element mounting board.

[0060] Second Embodiment In a circuit board according to a second embodiment of the present invention, the upper and side surfaces of the via conductors are exposed from the insulating layer, and the lower surfaces of the via conductors are covered with the insulating layer.

[0061] FIG. 4 is a cross-sectional view schematically showing an example of a circuit board according to a second embodiment of the present invention.

[0062] Although the overall configuration is not shown in FIG. 4, the circuit board 2 includes an insulating layer 10 and via conductors 20 provided on the surface of the insulating layer 10 .

[0063] FIG. 4 schematically shows a portion of the circuit board 2 where via conductors 20 , which are part of the wiring, are provided in the insulating layer 10 .

[0064] The via conductor 20 has an exposed surface exposed from the insulating layer 10 .

[0065] 4, the via conductor 20 has an upper surface 20a and a lower surface 20b that face each other in the thickness direction of the insulating layer 10 (the Z-axis direction in FIG. 4), and a side surface 20c that connects the upper surface 20a and the lower surface 20b. As shown in FIG. 4, when the upper surface 20a and the side surface 20c of the via conductor 20 are exposed from the insulating layer 10 and the lower surface 20b of the via conductor 20 is covered by the insulating layer 10, the upper surface 20a and the side surface 20c of the via conductor 20 are exposed surfaces.

[0066] The lower surface 20 b of the via conductor 20 may be flush with the surface of the insulating layer 10 , higher than the surface of the insulating layer 10 , or lower than the surface of the insulating layer 10 .

[0067] FIG. 5 is an example of an enlarged cross-sectional view of an exposed surface of a via conductor in a circuit board according to a second embodiment of the present invention.

[0068] As shown in FIG. 5 , the insulating layer 10 includes a tab 15 that extends to a portion of the exposed surface of the via conductor 20 .

[0069] As shown in FIG. 5 , when the upper surface 20 a and the side surface 20 c of the via conductor 20 are exposed from the insulating layer 10 , it is preferable that a claw portion 15 be provided on a part of the side surface 20 c of the via conductor 20 .

[0070] When viewed from the thickness direction of the via conductor 20, the claw portion 15 may be provided on the entire outer periphery of the side surface 20c of the via conductor 20, or the claw portion 15 may be provided on only a portion of the outer periphery of the side surface 20c of the via conductor 20.

[0071] Although the shape of the claw portion 15 is not particularly limited, it is preferable that the thickness of the claw portion 15 decreases toward the tip of the claw portion 15 in a cross section along the thickness direction of the insulating layer 10. On the exposed surface of the via conductor 20, there may be a portion where the thickness of the claw portion 15 is constant.

[0072] In a cross section taken along the thickness direction of the insulating layer 10, the length of the claw portion 15 provided on a portion of the side surface 20c of the via conductor 20 is preferably 15 μm or more. The length of the claw portion 15 provided on a portion of the side surface 20c of the via conductor 20 may be 20 μm or more, 30 μm or more, 40 μm or more, or 50 μm or more. On the other hand, the length of the claw portion 15 provided on a portion of the side surface 20c of the via conductor 20 is, for example, 200 μm or less.

[0073] In a cross section along the thickness direction of the insulating layer 10, the ratio of the length of the claw portion 15 provided on a part of the side surface 20c of the via conductor 20 to the length of the side surface 20c of the via conductor 20 is, for example, 10% or more and 100% or less.

[0074] In a cross section along the thickness direction of the insulating layer 10, the maximum thickness of the claw portion 15 is, for example, not less than 5 μm and not more than 15 μm.

[0075] Third Embodiment In a circuit board according to a third embodiment of the present invention, the upper surfaces of the via conductors are exposed from the insulating layer, and the side and lower surfaces of the via conductors are covered with the insulating layer.

[0076] FIG. 6 is a cross-sectional view schematically showing an example of a circuit board according to a third embodiment of the present invention.

[0077] Although the overall configuration is not shown in FIG. 6, the circuit board 3 includes an insulating layer 10 and via conductors 20 provided inside the insulating layer 10 .

[0078] FIG. 6 schematically shows a portion of the circuit board 3 where via conductors 20 , which are part of the wiring, are provided in the insulating layer 10 .

[0079] The via conductor 20 has an exposed surface exposed from the insulating layer 10 .

[0080] 6, the via conductor 20 has an upper surface 20a and a lower surface 20b that face each other in the thickness direction of the insulating layer 10 (the Z-axis direction in FIG. 6), and a side surface 20c that connects the upper surface 20a and the lower surface 20b. As shown in FIG. 6, when the upper surface 20a of the via conductor 20 is exposed from the insulating layer 10 and the side surface 20c and the lower surface 20b of the via conductor 20 are covered with an insulating layer, the upper surface 20a of the via conductor 20 is the exposed surface.

[0081] The upper surface 20 a of the via conductor 20 may be flush with the surface of the insulating layer 10 , may be higher than the surface of the insulating layer 10 , or may be lower than the surface of the insulating layer 10 .

[0082] FIG. 7 is an example of an enlarged cross-sectional view of an exposed surface of a via conductor in a circuit board according to a third embodiment of the present invention.

[0083] As shown in FIG. 7 , the insulating layer 10 includes a tab 15 that extends to a portion of the exposed surface of the via conductor 20 .

[0084] As shown in FIG. 7 , when the upper surface 20 a of the via conductor 20 is exposed from the insulating layer 10 , it is preferable that a claw portion 15 be provided on a part of the upper surface 20 a of the via conductor 20 .

[0085] When viewed from the thickness direction of the via conductor 20, the claw portion 15 may be provided on the entire outer periphery of the upper surface 20a of the via conductor 20, or the claw portion 15 may be provided on only a portion of the outer periphery of the upper surface 20a of the via conductor 20.

[0086] Although the shape of the claw portion 15 is not particularly limited, it is preferable that the thickness of the claw portion 15 decreases toward the tip of the claw portion 15 in a cross section along the thickness direction of the insulating layer 10. There may be a portion on the exposed surface of the via conductor 20 where the thickness of the claw portion 15 is constant.

[0087] In a cross section taken along the thickness direction of the insulating layer 10, the length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 is preferably 10 μm or more. The length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 may be 20 μm or more, 50 μm or more, 75 μm or more, or 100 μm or more. On the other hand, the length of the claw portion 15 provided on a portion of the upper surface 20a of the via conductor 20 is, for example, 200 μm or less.

[0088] In a cross section along the thickness direction of the insulating layer 10, the ratio of the length of the claw portion 15 provided on a part of the upper surface 20a of the via conductor 20 to the length of the side surface 20c of the via conductor 20 is, for example, 10% or more and 200% or less.

[0089] In a cross section along the thickness direction of the insulating layer 10, the maximum thickness of the claw portion 15 is, for example, not less than 5 μm and not more than 15 μm.

[0090] An example of a method for manufacturing the circuit board of the present invention will be described below. Figures 8 to 13 are cross-sectional views that schematically show an example of a manufacturing process for the circuit board according to the first embodiment of the present invention.

[0091] FIG. 8 is a cross-sectional view schematically showing an example of a process for laminating ceramic green sheets.

[0092] In the step shown in FIG. 8, ceramic green sheets 110 containing low-temperature co-fired ceramic material are laminated.

[0093] The ceramic green sheet 110 can be produced, for example, by adding a resin, a dispersant, a plasticizer, and a solvent to a ceramic powder, and forming the resulting slurry into a sheet of a predetermined thickness by a doctor blade method. As the inorganic solid content of the ceramic green sheet 110, a powder of the above-mentioned low-temperature co-fired ceramic material may be used, or a mixed powder obtained by mixing alumina powder with the powder of the above-mentioned low-temperature co-fired ceramic material may be used.

[0094] FIG. 9 is a cross-sectional view schematically showing an example of a process for forming through holes in a laminate of ceramic green sheets.

[0095] 9, through holes 150 are formed in a laminate of ceramic green sheets 110. The through holes 150 can be formed by a method such as laser processing. The radial dimensions of the through holes 150 may be constant or may vary in the thickness direction.

[0096] FIG. 10 is a cross-sectional view schematically showing an example of a step of placing a metal material in a through-hole.

[0097] 10 , a metal material 120 for the via conductor 20 is placed in the through hole 150. For example, a metal block such as a metal pillar or a metal plate is used as the metal material 120. It is preferable not to use a metal paste as the metal material 120 for the via conductor 20. On the other hand, to form wiring other than the via conductor 20, a metal paste containing, for example, silver or copper is used.

[0098] 10, the upper surface of the metal material 120 is exposed. Although not shown in FIG. 10, it is preferable to apply the slurry used to form the ceramic green sheet 110 to a part of the exposed surface of the metal material 120.

[0099] FIG. 11 is a cross-sectional view schematically showing an example of a process for arranging constraining layers above and below a laminate of ceramic green sheets.

[0100] As shown in FIG. 11, it is preferable to arrange constraining layers 130 above and below the laminate of ceramic green sheets 110.

[0101] The constraining layer 130 can be formed, for example, by forming a slurry by a doctor blade method, in which a resin, a dispersant, a plasticizer, and a solvent are added and mixed with ceramic powder that does not substantially sinter at the sintering temperature of the ceramic green sheet 110. Alumina powder is preferable as the ceramic powder used for the constraining layer 130. The thickness of the sheet-formed constraining layer 130 is preferably, for example, 0.2 mm.

[0102] FIG. 12 is a cross-sectional view schematically showing an example of a process for firing a laminate of ceramic green sheets.

[0103] In the step shown in FIG. 12, a laminate of ceramic green sheets 110 (see FIG. 11) with constraining layers 130 arranged above and below is fired.

[0104] The laminate is preferably fired at a temperature suitable for firing low-temperature co-fired ceramic materials. The firing temperature is preferably 1000°C or lower, and more preferably 850°C to 990°C. The firing time (holding time at the firing temperature) is preferably 10 minutes to 30 minutes. Pressure firing may be performed in which the laminate is pressed and fired. The firing atmosphere is preferably air.

[0105] 12 , by firing the laminate, the low-temperature co-fired ceramic material contained in the ceramic green sheets 110 is sintered to form the insulating layer 10. On the other hand, the constraining layers 130 are not substantially sintered during firing, and therefore do not shrink, and act to suppress shrinkage of the laminate of ceramic green sheets 110 in the direction of the main surfaces. As a result, the dimensional accuracy of the insulating layer 10 can be improved.

[0106] Furthermore, metal material 120 such as a metal pillar or a metal plate becomes via conductor 20 as it is. As described above, if slurry is applied to a portion of the exposed surface of metal material 120, claw portion 15 (see FIG. 2B ) is formed in that portion.

[0107] FIG. 13 is a cross-sectional view schematically illustrating an example of a step of removing the constraining layer.

[0108] 13, the remaining constraining layer 130 is removed. Methods that can be used to remove the constraining layer 130 include, for example, wet blasting, sand blasting, brushing, and the like.

[0109] Through the above steps, the circuit board 1 shown in Fig. 1 can be manufactured. The order of the above steps is not particularly limited, and the order may be changed as appropriate.

[0110] The circuit board 2 shown in FIG. 4 and the circuit board 3 shown in FIG. 6 can also be manufactured by the same method as above.

[0111] Fig. 14 is an example of a cross-sectional photograph enlarging an exposed surface of a via conductor in a circuit board according to a first embodiment of the present invention. Fig. 15 is an example of a cross-sectional photograph enlarging an exposed surface of a via conductor in a circuit board according to a second embodiment of the present invention.

[0112] For the circuit board according to the first embodiment of the present invention, the stress acting on the via conductors when the temperature was changed from room temperature to 150° C. was determined by simulation. The stress simulation was performed using Femtet (registered trademark) manufactured by Murata Software Co., Ltd.

[0113] FIG. 16 is a diagram showing the results of a simulation of stress applied to via conductors.

[0114] In Fig. 16, the maximum value of the stress applied to the via conductor was 0.76 GPa. It can be seen from Fig. 16 that stress is not concentrated on the via conductor and that stress is reduced with temperature changes.

[0115] The present specification discloses the following:

[0116] <1> A circuit board comprising: an insulating layer containing a low-temperature co-fired ceramic material; and a via conductor provided inside or on a surface of the insulating layer, wherein the via conductor has an exposed surface exposed from the insulating layer, and the insulating layer includes a claw portion extending to a portion of the exposed surface of the via conductor.

[0117] <2> The circuit board according to <1>, wherein the density of the via conductors is 80% or more in a cross section along the thickness direction of the insulating layer.

[0118] <3> The circuit board according to <1> or <2>, wherein the thickness of the claw portion decreases toward the tip of the claw portion in a cross section along the thickness direction of the insulating layer.

[0119] <4> The circuit board according to any one of <1> to <3>, wherein the via conductor has an upper surface and a lower surface that face each other in a thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface and the lower surface of the via conductor are exposed from the insulating layer, and the side surface of the via conductor is covered by the insulating layer, and the claw portion is provided on a part of at least one of the upper surface and the lower surface of the via conductor.

[0120] <5> The circuit board according to any one of <1> to <3>, wherein the via conductor has an upper surface and a lower surface that face each other in a thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface and the side surface of the via conductor are exposed from the insulating layer and the lower surface of the via conductor is covered by the insulating layer, and the claw portion is provided on a part of the side surface of the via conductor.

[0121] <6> The circuit board according to any one of <1> to <3>, wherein the via conductor has an upper surface and a lower surface that face each other in a thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface of the via conductor is exposed from the insulating layer, and the side surface and the lower surface of the via conductor are covered with the insulating layer, and the claw portion is provided on a part of the upper surface of the via conductor.

[0122] <7> The circuit board according to any one of <1> to <6>, wherein the length of the claw portion is 10 μm or more in a cross section along the thickness direction of the insulating layer.

[0123] <8> The circuit board according to any one of <1> to <7>, wherein the via conductors have a height of 20 μm or more.

[0124] REFERENCE SIGNS LIST 1, 2, 3 Circuit board 10 Insulating layer 15 Claw portion 20 Via conductor 20a Upper surface 20b Lower surface 20c Side surface 30 Highly thermally conductive ceramic substrate 40 Heat generating element 50 Solder 110 Ceramic green sheet 120 Metal material 130 Constraining layer 150 Through hole EX Exposed surface

Claims

1. A circuit board comprising: an insulating layer containing a low-temperature co-fired ceramic material; and a via conductor provided inside or on the surface of the insulating layer, wherein the via conductor has an exposed surface that is exposed from the insulating layer, and the insulating layer includes a claw portion that extends to a portion of the exposed surface of the via conductor.

2. The circuit board according to claim 1, wherein the density of the via conductors is 80% or more in a cross section along the thickness direction of the insulating layer.

3. The circuit board according to claim 1 or 2, wherein the thickness of the claw portion decreases toward the tip of the claw portion in a cross section along the thickness direction of the insulating layer.

4. The circuit board according to any one of claims 1 to 3, wherein the via conductor has an upper surface and a lower surface that face each other in the thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface and the lower surface of the via conductor are exposed from the insulating layer and the side surface of the via conductor is covered by the insulating layer, and the claw portion is provided on a part of at least one of the upper surface and the lower surface of the via conductor.

5. The circuit board according to any one of claims 1 to 3, wherein the via conductor has an upper surface and a lower surface that face each other in the thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface and the side surface of the via conductor are exposed from the insulating layer, and the lower surface of the via conductor is covered by the insulating layer, and the claw portion is provided on a part of the side surface of the via conductor.

6. The circuit board according to any one of claims 1 to 3, wherein the via conductor has an upper surface and a lower surface that face each other in the thickness direction of the insulating layer, and a side surface that connects the upper surface and the lower surface, the upper surface of the via conductor is exposed from the insulating layer, and the side surface and lower surface of the via conductor are covered by the insulating layer, and the claw portion is provided on a part of the upper surface of the via conductor.

7. The circuit board according to any one of claims 1 to 6, wherein the length of the claw portion is 10 μm or more in a cross section along the thickness direction of the insulating layer.

8. The circuit board according to any one of claims 1 to 7, wherein the height of the via conductor is 20 μm or more.

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