Imaging device

Abstract

A first pixel 10a includes a first plug px1. A second pixel 10b includes a second plug px2. The first pixel 10a and the second pixel 10b are adjacent to each other with a first well contact plug wx1 interposed therebetween. A distance Lx0 is the distance between the first plug px1 and the second plug px2. A distance Lx1 is the distance between the first plug px1 and the first well contact plug wx1. A distance Lx2 is the distance between the second plug px2 and the first well contact plug wx1. The distance Lx1 is smaller than the distance Lx0. The distance Lx2 is smaller than the distance Lx0.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Various studies have been conducted on imaging devices. Patent Documents 1 and 2 mention improvements in image quality. The improvement in image quality can be achieved by, for example, reducing dark current and coupling.

[0003] JP 10-256521 A JP 2014-170956 A

[0004] The present disclosure provides techniques suitable for improving image quality.

[0005] The present disclosure provides a semiconductor device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a first well contact plug that applies a potential to the semiconductor layer; a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween; a first signal line to which a first signal output by the first pixel is input; and a second signal line to which a second signal output by the second pixel is input, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer; and a first plug connected to the first impurity region and electrically connected to the first signal line; and the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer; and a second plug connected to the second impurity region and electrically connected to the second signal line, wherein the first impurity region and the second impurity region are adjacent to each other, The imaging device includes: a distance between the first plug and the first well contact plug that is smaller than a distance between the first plug and the second plug; and a distance between the second plug and the first well contact plug that is smaller than a distance between the second plug and the first plug.

[0006] From another viewpoint, the present disclosure provides a semiconductor device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a first well contact plug that applies a potential to the semiconductor layer; and a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer and in which the first signal charge is accumulated; and a first plug connected to the first impurity region; the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer and in which the second signal charge is accumulated; and a second plug connected to the second impurity region, wherein the first impurity region and the second impurity region are adjacent to each other, a distance between the first plug and the first well contact plug is smaller than a distance between the first plug and the second plug, and a distance between the second plug and the first well contact plug is smaller than a distance between the second plug and the first plug. An imaging device is provided.

[0007] The technology according to the present disclosure is suitable for improving image quality.

[0008] FIG. 1 is a circuit diagram of an imaging device according to Embodiment 1. FIG. 2 is a plan view of a pixel region according to Embodiment 1. FIG. 3A is a cross-sectional view parallel to the thickness direction of a semiconductor substrate taken along line 50A in FIG. 2. FIG. 3B is a cross-sectional view parallel to the thickness direction of a semiconductor substrate taken along line 50B in FIG. 2. FIG. 4 is an explanatory diagram of a guard ring. FIG. 5A is a layout diagram of plugs according to Reference Form 1. FIG. 5B is a layout diagram of well contact plugs according to Reference Form 2. FIG. 5C is a layout diagram of well contact plugs according to Embodiment 1. FIG. 5D is a layout diagram of well contact plugs according to Modification 1. FIG. 5E is a layout diagram of well contact plugs according to Modification 2. FIG. 5F is a layout diagram of well contact plugs according to Modification 3. FIG. 5G is a layout diagram of well contact plugs according to Modification 4. FIG. 6A is a diagram illustrating electric field lines when the layout of FIG. 5A is adopted. FIG. 6B is a diagram illustrating electric field lines when the layout of FIG. 5B is adopted. FIG. 6C is a diagram illustrating electric field lines when the layout of FIG. 5C is adopted. FIG. 6D is a diagram showing electric field lines when the arrangement of FIG. 5D is adopted. FIG. 7 is a diagram showing an arrangement of voltage plugs according to the first embodiment. FIG. 8 is a cross-sectional view parallel to the thickness direction of a semiconductor substrate. FIG. 9 is a circuit diagram of an imaging device according to the second embodiment. FIG. 10 is a plan view of a pixel region according to the second embodiment. FIG. 11 is a cross-sectional view parallel to the thickness direction of a semiconductor substrate, taken along a line 50C in FIG. 10 . FIG. 12 is a diagram showing an arrangement of well contact plugs according to the second embodiment. FIG. 13 is a plan view of a pixel region according to the third embodiment. FIG. 14 is a circuit diagram of an imaging device according to the fourth embodiment. FIG. 15 is a plan view of a pixel region according to the fourth embodiment. FIG. 16A is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16B is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16C is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16D is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16E is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16F is a process diagram illustrating an example of a manufacturing method of an imaging device. FIG. 16G is a process diagram for explaining an example of a method for manufacturing an imaging device.Fig. 16H is a process diagram for explaining an example of a method for manufacturing an imaging device. Fig. 16I is a process diagram for explaining an example of a method for manufacturing an imaging device. Fig. 16J is a process diagram for explaining an example of a method for manufacturing an imaging device. Fig. 16K is a process diagram for explaining an example of a method for manufacturing an imaging device. Fig. 17 is a schematic diagram of a configuration example of a camera system according to embodiment 6. Fig. 18 is an explanatory diagram of a configuration example of an insulating film.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component positions and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in the embodiments can be combined with each other unless a contradiction occurs. Furthermore, the components in the following embodiments are merely illustrative. In each drawing, components having substantially the same function are designated by the same reference numerals, and redundant explanations may be omitted or simplified.

[0010] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from those of the actual objects.

[0011] In the embodiments, terms such as "upper," "lower," "left," and "right" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use. In the embodiments, "planar view" refers to a view from the thickness direction of the semiconductor substrate.

[0012] In the embodiments, the impurity region may also be referred to as a diffusion region. The gate may also be referred to as a gate electrode. The substrate may also be referred to as a wafer. In the embodiments, the term "metal" encompasses alloys. The term "silicon" encompasses polysilicon.

[0013] In the embodiment, the phrase "the material of element A is the same as the material of element B" specifically refers to the fact that the composition of the material of element A is the same as the composition of the material of element B. The phrase "the material of element A is different from the material of element B" specifically refers to the fact that the composition of the material of element A is different from the composition of the material of element B.

[0014] In the embodiment, the expression "the impurity concentration of element A is lower than the impurity concentration of element B" may be used. Specifically, this expression means that the peak concentration of element A is lower than the peak concentration of element B. Here, the peak concentration of element A refers to the impurity concentration at the position in element A where the impurity concentration is highest. The peak concentration of element B refers to the impurity concentration at the position in element B where the impurity concentration is highest.

[0015] In the embodiment, the distance between element A and element B refers to the length of the shortest line segment connecting element A and element B.

[0016] In the embodiment, the expression "element A is connected to element B" may be used. This expression may mean that element A is in contact with element B.

[0017] In the embodiments, the expression "element A is electrically connected to element B" may be used. This expression is intended to encompass both a case where element A is electrically connected to element B, and a case where element A and element B are electrically connected at least for a certain period of time even though element C is interposed between them.

[0018] In this specification, the first conductivity type and the second conductivity type are conductivity types of opposite polarity. Specifically, one of the first conductivity type and the second conductivity type is n-type, and the other of the first conductivity type and the second conductivity type is p-type.

[0019] In the embodiments and their modifications, unless otherwise inconsistent, p-type elements may be replaced with n-type elements, and n-type elements may be replaced with p-type elements.

[0020] (Embodiment 1) Fig. 1 is a circuit diagram of an imaging device 90 according to embodiment 1. The imaging device 90 has a pixel region 91 and a peripheral region 92. The pixel region 91 includes a plurality of pixels 10. Each pixel 10 has a photoelectric conversion unit that converts incident light into a signal charge. In the pixel region 91, the plurality of pixels 10 are two-dimensionally arranged on a semiconductor substrate 100. Specifically, the plurality of pixels 10 are arranged in a row direction D1 and a column direction D2 to form a pixel array. In Fig. 1, two pixels 10 are representatively depicted.

[0021] A peripheral circuit 80 is provided in the peripheral region 92. The peripheral circuit 80 includes a horizontal circuit 81 and a vertical circuit 82. In the first embodiment, the peripheral region 92 includes a guard ring 30, but the guard ring 30 is not shown in FIG.

[0022] The horizontal circuit 81 applies a potential to the well of the semiconductor substrate 100 via the well control line 250. This stabilizes the potential of the well. Specifically, the horizontal circuit 81 applies a potential to a portion of the well of the semiconductor substrate 100 that belongs to the pixel region 91.

[0023] The horizontal circuit 81 selects the pixels 10 row by row and supplies a voltage to the pixels 10 in the selected row via the address control line 252. This causes a signal voltage to be read out from the pixels 10 in the selected row. The signal voltage is supplied to a signal line 260 as an output signal. Note that the "row" in "row by row" refers to a row in the pixel array. The signal line 260 may also be referred to as a vertical signal line.

[0024] The horizontal circuit 81 selects the pixels 10 on a row-by-row basis and supplies a voltage to the pixels 10 in the selected row via the reset control line 253. This resets the signal charges in the pixels 10 in the selected row. Here, the charges are generated by photoelectric conversion.

[0025] The vertical circuit 82 supplies voltages to the pixels 10 via a voltage line 221 , a voltage line 223 and a voltage line 224 .

[0026] An output signal is supplied from the pixel 10 to the vertical circuit 82 via a signal line 260. The vertical circuit 82 performs noise suppression signal processing, typically correlated double sampling, analog-to-digital conversion, etc. on the output signal. The output of the vertical circuit 82 is read out to the outside of the imaging device 90.

[0027] The pixel 10 includes a photoelectric conversion unit 150 , an amplification transistor 311 , a selection transistor 312 , a reset transistor 313 and an overflow transistor 314 .

[0028] The pixel 10 includes a charge accumulation node 330. The charge accumulation node 330 accumulates signal charges generated in the photoelectric conversion unit 150. The charge accumulation node 330 includes a charge accumulation region 166n, a pixel electrode 152, a gate of the amplification transistor 311, a gate of the overflow transistor 314, etc. The charge accumulation region 166n is an impurity region provided in the semiconductor substrate 100 (see FIG. 2).

[0029] In the first embodiment, one of the source and drain of the reset transistor 313 constitutes the charge storage region 166 n. Also, one of the source and drain of the overflow transistor 314 constitutes the charge storage region 166 n. In other words, the charge storage region 166 n is shared by the reset transistor 313 and the overflow transistor 314.

[0030] The photoelectric conversion unit 150 includes a photoelectric conversion film 151, a pixel electrode 152, and a counter electrode 153. The photoelectric conversion film 151 is disposed between the pixel electrode 152 and the counter electrode 153. The photoelectric conversion film 151 is located outside the semiconductor substrate 100. In this embodiment, the photoelectric conversion film 151 includes an organic material. That is, the photoelectric conversion film 151 is an organic film. The photoelectric conversion film 151 may also include an inorganic material. A predetermined voltage is applied to the counter electrode 153.

[0031] The photoelectric conversion unit 150 is connected to the charge accumulation region 166n, the gate of the overflow transistor 314, and the gate of the amplification transistor 311. Specifically, the pixel electrode 152 is connected to these.

[0032] One of the source and drain of the amplification transistor 311 and one of the source and drain of the selection transistor 312 are formed by a common impurity region.

[0033] The photoelectric conversion unit 150 converts light into signal charges. Specifically, when a voltage is applied between the pixel electrode 152 and the counter electrode 153, the photoelectric conversion film 151 converts light into signal charges, and the pixel electrode 152 collects the signal charges.

[0034] The charge is accumulated in the charge accumulation node 330. A power supply voltage is supplied to the other of the source and drain of the amplification transistor 311 through a voltage line 221. The amplification transistor 311 outputs a signal corresponding to the potential of the charge accumulation node 330 to a signal line 260 via a selection transistor 312. The selection transistor 312 determines the timing at which the signal is output from the amplification transistor 311.

[0035] Specifically, the horizontal circuit 81 is connected to the gates of the selection transistors 312 via the address control lines 252. A voltage is supplied from the horizontal circuit 81 to the gates of the selection transistors 312 in the pixels 10 in the row selected by the horizontal circuit 81 via the address control lines 252. This turns on the selection transistor 312, and a signal is output from the other of the source and drain thereof.

[0036] A reset voltage is supplied to the other of the source and drain of the reset transistor 313 through a voltage line 223. The reset transistor 313 resets the signal charge stored in the charge storage node 330.

[0037] Specifically, the horizontal circuit 81 is connected to the gate of the reset transistor 313 via a reset control line 253. A voltage is supplied from the horizontal circuit 81 to the gate of the reset transistor 313 in the pixel 10 in the row selected by the horizontal circuit 81 via the reset control line 253. This turns on the reset transistor 313, supplies a reset voltage to the charge storage node 330, and initializes the signal charge of the charge storage node 330.

[0038] A voltage is applied to the other of the source and drain of the overflow transistor 314 via the voltage line 224. As described above, the gate of the overflow transistor 314 is connected to the charge accumulation region 166n. When strong light is incident on the photoelectric conversion unit 150, the signal charge in the charge accumulation node 330 increases, and the overflow transistor 314 is turned on. As a result, the excess signal charge accumulated in the charge accumulation node 330 is discharged via the overflow transistor 314. This protects the various transistors and ensures the safety of the imaging device 90.

[0039] In the first embodiment, the amplification transistor 311, the selection transistor 312, the reset transistor 313, and the overflow transistor 314 are metal oxide semiconductor field effect transistors (MOSFETs). Specifically, the amplification transistor 311, the selection transistor 312, the reset transistor 313, and the overflow transistor 314 are n-type MOSFETs.

[0040] FIG. 2 is a plan view of the pixel region 91 according to the first embodiment.

[0041] In the pixel region 91, impurity regions 161n, 162n, 163n, 165n, charge storage region 166n, impurity region 167n, impurity region 170p, and a well 175p are provided on the semiconductor substrate 100. The impurity regions 161n, 162n, 163n, 165n, charge storage region 166n, impurity region 167n, and impurity region 170p are provided in the well 175p.

[0042] As can be seen from Figures 1 and 2, the impurity region 162n is an n-type impurity region that serves as one of the source and drain of the amplification transistor 311 and one of the source and drain of the selection transistor 312, the impurity region 161n is an n-type impurity region that constitutes the other of the source and drain of the amplification transistor 311, the impurity region 163n is an n-type impurity region that constitutes the other of the source and drain of the selection transistor 312, the charge accumulation region 166n is an n-type impurity region that serves as one of the source and drain of the reset transistor 313 and one of the source and drain of the overflow transistor 314, the impurity region 165n is an n-type impurity region that constitutes the other of the source and drain of the reset transistor 313, the impurity region 167n is an n-type impurity region that constitutes the other of the source and drain of the overflow transistor 314, and the well 175p is a p-type impurity region. The impurity region 170p is a p-type impurity region in which the concentration of p-type impurities is higher than the concentration of p-type impurities in the well 175p.

[0043] In FIG. 2 , the gate 311 e is the gate of the amplification transistor 311 , the gate 312 e is the gate of the selection transistor 312 , the gate 313 e is the gate of the reset transistor 313 , and the gate 314 e is the gate of the overflow transistor 314 .

[0044] In the pixel region 91, the plurality of pixels 10 includes a plurality of first pixels 10a and a plurality of second pixels 10b.

[0045] In each column of the pixel array, first pixels 10a and second pixels 10b are alternately arranged in the column direction D2. In one of two rows adjacent to each other in the column direction D2 in the pixel array, a plurality of first pixels 10a are arranged in the row direction D1. In the other of two rows adjacent to each other in the column direction D2 in the pixel array, a plurality of second pixels 10b are arranged in the row direction D1.

[0046] The first pixel 10a and the second pixel 10b adjacent in the column direction D2 are arranged in line symmetry with respect to a line 41 extending in the row direction D1. The first pixel 10a and the second pixel 10b adjacent in the column direction D2 are also arranged in line symmetry with respect to a line 42 extending in the row direction D1. A line symmetric arrangement may also be referred to as a flip arrangement. Note that in FIG. 2, the positions of the lines 41 and 42 are indicated by arrows for ease of illustration.

[0047] In a plan view, a unit configuration including, in this order: an impurity region 170p shared by the first pixel 10a and the second pixel 10b; and an impurity region 167n shared by the first pixel 10a and the second pixel 10b, appears repeatedly along a straight line 41 extending in the row direction D1.

[0048] In a plan view, unit structures including, in this order: an impurity region 161n shared by the first pixel 10a and the second pixel 10b; and an impurity region 165n shared by the first pixel 10a and the second pixel 10b, appear repeatedly along a straight line 42 extending in the row direction D1.

[0049] In a plan view, along a straight line 50A extending in the column direction D2, a unit configuration including, in this order, an impurity region 161n shared by the first pixel 10a and the second pixel 10b, a gate 311e of the first pixel 10a, an impurity region 162n of the first pixel 10a, a gate 312e of the first pixel 10a, an impurity region 163n of the first pixel 10a, an impurity region 170p shared by the first pixel 10a and the second pixel 10b, an impurity region 163n of the second pixel 10b, a gate 312e of the second pixel 10b, an impurity region 162n of the second pixel 10b, and a gate 311e of the second pixel 10b appears repeatedly.

[0050] In a plan view, a unit configuration including, in this order, an impurity region 165n shared by the first pixel 10a and the second pixel 10b, a gate 313e of the first pixel 10a, a charge storage region 166n of the first pixel 10a, a gate 314e of the first pixel 10a, an impurity region 167n shared by the first pixel 10a and the second pixel 10b, a gate 314e of the second pixel 10b, a charge storage region 166n of the second pixel 10b, and a gate 313e of the second pixel 10b appears repeatedly along a straight line 50B extending in the column direction D2.

[0051] Fig. 3A is a cross-sectional view parallel to the thickness direction of the semiconductor substrate 100 taken along a line 50A in Fig. 2. Fig. 3B is a cross-sectional view parallel to the thickness direction of the semiconductor substrate 100 taken along a line 50B in Fig. 2.

[0052] 3A and 3B illustrate a pixel region 91. In these figures, the block arrows indicate that the first pixel 10a and the second pixel 10b are flip-arranged. In FIG. 3A, the axis of the flip arrangement in the cross section of FIG. 3A is indicated by a bold dotted line. In FIG. 3B, the axis of the flip arrangement in the cross section of FIG. 3B is indicated by a bold dotted line.

[0053] 3A, in the pixel 10, the semiconductor substrate 100 includes an impurity region 161p. The impurity region 161p is provided in a well 175p. The impurity region 161p is a p-type impurity region that forms the channel region of the selection transistor 312 below the gate 312e.

[0054] 3B, in the pixel 10, the semiconductor substrate 100 includes an impurity region 162p. The impurity region 162p is provided in a well 175p. The impurity region 162p is a p-type impurity region that forms the channel region of the overflow transistor 314 below the gate 314e.

[0055] As shown in FIGS. 3A and 3B, the imaging device 90 includes an insulating film 401, an insulating film 402, an insulating film 403, an insulating film 404, and an insulating film 405.

[0056] The insulating film 401 is provided on the semiconductor substrate 100. The insulating film 402 is provided on the insulating film 401, the gate 311e, the gate 312e, the gate 313e, and the gate 314e. The insulating films 403 are provided on the left and right of the gate 311e, the left and right of the gate 312e, the left and right of the gate 313e, and the left and right of the gate 314e, sandwiching the insulating film 402. The insulating films 404 are provided on the left and right of the gate 311e, the left and right of the gate 312e, the left and right of the gate 313e, and the left and right of the gate 314e, sandwiching the insulating films 402 and 403. The insulating film 405 is provided so as to cover the insulating films 402, 403, and 404 from above.

[0057] A part of the insulating film 401 is a gate insulating film of the amplification transistor 311. A part of the insulating film 401 is a gate insulating film of the selection transistor 312. A part of the insulating film 401 is a gate insulating film of the reset transistor 313. A part of the insulating film 401 is a gate insulating film of the overflow transistor 314.

[0058] The insulating film 403 is an offset sidewall spacer. The offset sidewall spacer is also called an offset sidewall. The insulating film 404 is a sidewall spacer. The sidewall spacer is also called a sidewall. The insulating film 405 is a silicide block film.

[0059] The imaging device 90 includes a contact hole h0, a contact hole h1, a contact hole h2, a contact hole h3, a contact hole h4, and a contact hole h5.

[0060] As shown in Figures 3A and 3B, contact hole h0 penetrates insulating films 401, 402, and 405, contact hole h1 penetrates insulating films 401, 402, and 405, contact hole h2 penetrates insulating films 402 and 405, contact hole h3 penetrates insulating films 401, 402, and 405, contact hole h4 penetrates insulating films 402 and 405, and contact hole h5 penetrates insulating films 401, 402, and 405.

[0061] The imaging device 90 includes a contact plug cp1, a contact plug cp2, a contact plug cp3, a contact plug cp4, a contact plug cp5, a silicide layer sc1, a silicide layer sc2, a silicide layer sc3, a silicide layer sc4, a silicide layer sc5, a plug p0, a plug p1, a plug p2, a plug p3, a plug p4, a plug p5, a plug p6, and a wiring layer 551.

[0062] In the following, the well 175p will be referred to as the semiconductor layer 175p, the impurity region 163n of the first pixel 10a will be referred to as the first impurity region 163na, the impurity region 163n of the second pixel 10b will be referred to as the second impurity region 163nb, the charge accumulation region 166n of the first pixel 10a will be referred to as the first charge accumulation region 166na, the charge accumulation region 166n of the second pixel 10b will be referred to as the second charge accumulation region 166nb, the gate 314e of the first pixel 10a will be referred to as the first electrode 314ea, the gate 314e of the second pixel 10b will be referred to as the second electrode 314eb, and the signal charge generated in the photoelectric conversion unit 150 of the first pixel 10a will be referred to as the first signal charge, - The signal charge generated in the photoelectric conversion unit 150 of the second pixel 10b may be referred to as the second signal charge, - The signal line 260 connected to the first pixel 10a may be referred to as the first signal line 260a, - The signal line 260 connected to the second pixel 10b may be referred to as the second signal line 260b, - The output signal output by the first pixel 10a may be referred to as the first signal, and - The output signal output by the second pixel 10b may be referred to as the second signal.

[0063] As can be seen from Figures 1, 2 and 3A, - a first signal charge is accumulated in the first charge accumulation region 166na, - a second signal charge is accumulated in the second charge accumulation region 166nb, - a first signal corresponds to the first signal charge and is input to the first signal line 260a, - a second signal corresponds to the second signal charge and is input to the second signal line 260b, and - the plug p2 is electrically connected to the address control line 252.

[0064] In the first embodiment, the imaging device 90 includes a first well contact plug wx1. The first well contact plug wx1 applies a potential to the semiconductor layer 175p. The first well contact plug wx1 is connected to the impurity region 170p and is electrically connected to the well control line 250. In the examples of FIGS. 2 and 3A , the first well contact plug wx1 includes a plug p0 shared by the first pixel 10a and the second pixel 10b, specifically, the plug p0 shared by the first pixel 10a and the second pixel 10b. The plug p0 shared by the first pixel 10a and the second pixel 10b is connected to the impurity region 170p.

[0065] In the first embodiment, the imaging device 90 includes a second well contact plug wx2. The second well contact plug wx2 applies a potential to the semiconductor layer 175p. The second well contact plug wx2 is connected to the impurity region 170p and is electrically connected to the well control line 250. In the example of FIG. 2 , the second well contact plug wx2 includes a plug p6 shared by the first pixel 10a and the second pixel 10b, specifically, the plug p6 shared by the first pixel 10a and the second pixel 10b. The plug p6 shared by the first pixel 10a and the second pixel 10b is connected to the impurity region 170p.

[0066] In the first embodiment, the imaging device 90 includes a first plug px1. The first plug px1 is connected to the first impurity region 163na and is electrically connected to the first signal line 260a. In the example of FIG. 3A , the first plug px1 includes a contact plug cp1 in the first pixel 10a, a silicide layer sc1 in the first pixel 10a, and a plug p1 in the first pixel 10a. The contact plug cp1 in the first pixel 10a is connected to the first impurity region 163na.

[0067] In the first embodiment, the imaging device 90 includes a second plug px2. The second plug px2 is connected to the second impurity region 163nb and is electrically connected to the second signal line 260b. In the example of FIG. 3A , the second plug px2 includes a contact plug cp1 in the second pixel 10b, a silicide layer sc1 in the second pixel 10b, and a plug p1 in the second pixel 10b. The contact plug cp1 in the second pixel 10b is connected to the second impurity region 163nb.

[0068] In the first embodiment, the imaging device 90 includes a voltage plug vy1. The voltage plug vy1 is connected to the impurity region 167n and electrically connected to a constant voltage source. In the example of FIG. 3B , the voltage plug vy1 includes a contact plug cp3 shared by the first pixel 10a and the second pixel 10b, a silicide layer sc3 shared by the first pixel 10a and the second pixel 10b, and a plug p3 shared by the first pixel 10a and the second pixel 10b. The contact plug cp3 shared by the first pixel 10a and the second pixel 10b is connected to the impurity region 167n.

[0069] In the first embodiment, the constant voltage source is included in the vertical circuit 82. The constant voltage source is electrically connected to the impurity region 167n via the voltage line 224 and the voltage plug vy1 in this order. However, the constant voltage source may be provided outside the vertical circuit 82.

[0070] In the first embodiment, the imaging device 90 includes a first plug py1. The first plug py1 is connected to the first electrode 314ea and electrically connected to the first charge storage region 166na. In the example of FIG. 3B , the first plug py1 includes a contact plug cp4 in the first pixel 10a, a silicide layer sc4 in the first pixel 10a, and a plug p4 in the first pixel 10a. The contact plug cp4 in the first pixel 10a is connected to the first electrode 314ea.

[0071] In the first embodiment, the imaging device 90 includes a second plug py2. The second plug py2 is connected to the second electrode 314eb and electrically connected to the second charge storage region 166nb. In the example of FIG. 3B , the second plug py2 includes a contact plug cp4 in the second pixel 10b, a silicide layer sc4 in the second pixel 10b, and a plug p4 in the second pixel 10b. The contact plug cp4 in the second pixel 10b is connected to the second electrode 314eb.

[0072] The first impurity region 163na and the second impurity region 163nb are adjacent to each other. Specifically, in the column direction D2, the gate 312e of the first pixel 10a, the first impurity region 163na, the second impurity region 163nb, and the gate 312e of the second pixel 10b are arranged in this order.

[0073] The first electrode 314ea and the second electrode 314eb are adjacent to each other. Specifically, in the column direction D2, the charge storage region 166n of the first pixel 10a, the first electrode 314ea, the second electrode 314eb, and the charge storage region 166n of the second pixel 10b are arranged in this order.

[0074] No n-type impurity region exists between the first impurity region 163na and the second impurity region 163nb. In other words, no n-type impurity region exists on the line segment connecting the first impurity region 163na and the second impurity region 163nb in plan view.

[0075] The first pixel 10a and the second pixel 10b are: adjacent to each other in the column direction D2 with a first well contact plug wx1 sandwiched therebetween; adjacent to each other in the column direction D2 with a second well contact plug wx2 sandwiched therebetween; and adjacent to each other in the column direction D2 with a voltage plug vy1 sandwiched therebetween.

[0076] As shown in FIGS. 3A and 3B , the plug p0 is connected to the impurity region 170p through a contact hole h0, the contact plug cp1 is connected to the impurity region 163n through a contact hole h1, the silicide layer sc1 is provided on the contact plug cp1, the plug p1 is connected to the silicide layer sc1, the contact plug cp2 is connected to the gate 312e through a contact hole h2, the silicide layer sc2 is provided on the contact plug cp2, the plug p2 is connected to the silicide layer sc2, the contact plug cp3 is connected to the impurity region 167n through a contact hole h3, the silicide layer sc3 is provided on the contact plug cp3, the plug p3 is connected to the silicide layer sc3, and the contact plug cp4 is connected to the gate 314e through a contact hole h4. - The silicide layer sc4 is provided on the contact plug cp4, - The plug p4 is connected to the silicide layer sc4, - The contact plug cp5 is connected to the charge storage region 166n through the contact hole h5, - The silicide layer sc5 is provided on the contact plug cp5, - The plug p5 is connected to the silicide layer sc5, - The plugs p4 and p5 are connected via the wiring layer 551.

[0077] 2 is connected to the impurity region 170p through a contact hole, similar to the plug p0. The contact hole through which the plug p6 passes penetrates the insulating films 401, 402, and 405, similar to the contact hole h0.

[0078] The imaging device 90 includes an insulating film 406 and an insulating film 407 .

[0079] The insulating film 406 is provided to cover the insulating film 405, the contact plug cp1, the silicide layer sc1, the contact plug cp2, the silicide layer sc2, the contact plug cp3, the silicide layer sc3, the contact plug cp4, the silicide layer sc4, the contact plug cp5, and the silicide layer sc5 from above. The insulating film 407 is provided above the amplification transistor 311, the selection transistor 312, the reset transistor 313, and the overflow transistor 314.

[0080] The insulating film 406 is a pre-metal insulating film, and the insulating film 407 is a protective film.

[0081] The improvement of image quality will be further explained below.

[0082] 4 is an explanatory diagram of the guard ring 30. In the first embodiment, the pixel region 91 is surrounded by the guard ring 30 in a plan view. The guard ring 30 can suppress noise from entering the pixel region 91 from outside the guard ring 30. This can contribute to improving image quality.

[0083] In the first embodiment, a voltage is supplied from the horizontal circuit 81 to the impurity region 170p via the well control line 250 and the plugs p0 and p6. This stabilizes the potential of the well 175p. Specifically, the central portion 21 and the peripheral portion 22 of the pixel region 91 are different in distance from the guard ring 30, and therefore have different CR time constants. However, in the first embodiment, the voltage supply to the impurity region 170p stabilizes the potential of the well 175p. By stabilizing the potential of the well 175p, it is possible to suppress shading even under the above-described circumstances where the CR time constants differ. Suppressing shading can contribute to improving image quality.

[0084] In the first embodiment, in the pixel region 91, a voltage is supplied to the well 175p from the surface 100a side of the semiconductor substrate 100 by the plugs p0 and p6. This is advantageous from the viewpoint of realizing a small pixel 10 compared to a method of supplying a voltage to the well 175p by providing an implanted region that extends upward from a lower region in the semiconductor substrate 100 to the well 175p. The lower region is the region of the semiconductor substrate 100 on the opposite side from the surface 100a.

[0085] In the first embodiment, a flip arrangement is adopted for the first pixel 10a and the second pixel 10b. By adopting the flip arrangement, some components of the imaging device 90 are shared by the first pixel 10a and the second pixel 10b. This sharing is advantageous from the viewpoint of realizing a compact pixel 10. The shared components in the first embodiment include the impurity region 170p, the plug p0, the plug p3, the plug p6, the contact plug cp3, the silicide layer sc3, etc.

[0086] Furthermore, the above-described sharing reduces the overall number of components included in the first pixel 10 a and the second pixel 10 b, thereby alleviating congestion of the components and suppressing coupling between the components. This sharing also avoids the problem of coupling between the components that occurs when the same types of components are provided separately in the first pixel 10 a and the second pixel 10 b. The benefit of suppressing coupling based on this sharing is particularly likely to be enjoyed in small pixels.

[0087] Furthermore, in the first embodiment and its first to fourth modifications, the coupling between the first plug px1 and the second plug px2 can be suppressed by one or more well contact plugs. This coupling suppression effect will be described below with reference to FIGS. 5A is a layout diagram of plugs according to Reference Form 1; FIG. 5B is a layout diagram of well contact plugs wx1 and wx2 according to Reference Form 2; FIG. 5C is a layout diagram of well contact plugs wx1 and wx2 according to Embodiment 1; FIG. 5D is a layout diagram of well contact plugs wx1 and wx2 according to Modification 1; FIG. 5E is a layout diagram of well contact plug wx1 according to Modification 2; FIG. 5F is a layout diagram of well contact plug wx1 according to Modification 3; FIG. 6D is a diagram showing the electric field lines when the arrangement of FIG. 5D is adopted.

[0088] For convenience, the plug is depicted as a rectangular square in FIGS. 5A to 5G and as a circle in FIGS. 6A to 6D, but the shape of the plug in plan view is not particularly limited.

[0089] 5A, the first well contact plug wx1 and the second well contact plug wx2 are not present. When a potential difference occurs between the first plug px1 and the second plug px2 in the first embodiment, strong coupling may occur between the first plug px1 and the second plug px2, as can be seen from the electric field lines in FIG.

[0090] The first well contact plug wx1 is present in the second embodiment, the first embodiment, and the first to fourth modifications. Furthermore, the second embodiment, the first embodiment, and the first modification also have a second well contact plug wx2.

[0091] In Figures 5B to 5F, - distance Lx0 is the distance between the first plug px1 and the second plug px2, - distance Lx1 is the distance between the first plug px1 and the first well contact plug wx1, - distance Lx2 is the distance between the second plug px2 and the first well contact plug wx1, - distance Lx3 is the distance between the first plug px1 and the second well contact plug wx2, and - distance Lx4 is the distance between the second plug px2 and the second well contact plug wx2.

[0092] 5B , the first well contact plug wx1 and the second well contact plug wx2 are present. However, in the second reference form, the distance Lx1 is greater than the distance Lx0, the distance Lx2 is greater than the distance Lx0, the distance Lx3 is greater than the distance Lx0, and the distance Lx4 is greater than the distance Lx0. Therefore, as can be seen from the electric field lines in FIG. 6B , the first well contact plug wx1 and the second well contact plug wx2 cannot sufficiently suppress the coupling between the first plug px1 and the second plug px2.

[0093] In contrast, in the first embodiment, the first modification, the second modification, and the third modification shown in Figures 5C, 5D, 5E, and 5F, respectively, the distance Lx1 is smaller than the distance Lx0, and the distance Lx2 is smaller than the distance Lx0. Therefore, the first well contact plug wx1 can contribute to suppressing coupling between the first plug px1 and the second plug px2. This can be understood from the electric field lines in Figures 6C and 6D.

[0094] 5C and 5D , respectively, the distance Lx3 is smaller than the distance Lx0, and the distance Lx4 is smaller than the distance Lx0. Therefore, as can be seen from the electric field lines in FIGS. 6C and 6D , the second well contact plug wx2 can contribute to suppressing coupling between the first plug px1 and the second plug px2.

[0095] The positions of the first well contact plug wx1 and the second well contact plug wx2 in Modification 4 shown in Fig. 5G are the same as the positions of the first well contact plug wx1 and the second well contact plug wx2 in Embodiment 1 shown in Fig. 5C. Furthermore, Modification 4 adds a third well contact plug wx3. The position of the third well contact plug wx3 is the same as the position of the first well contact plug wx1 in Modification 1 shown in Fig. 5D.

[0096] In the first embodiment and the first modification shown in Figures 5C and 5D, the number of well contact plugs is 2. In the second and third modifications shown in Figures 5E and 5F, the number of well contact plugs is 1. In the fourth modification shown in Figure 5G, the number of well contact plugs is 3. The number of well contact plugs may be 4 or more.

[0097] 5C, 5E, and 5G, respectively, the first well contact plug wx1 is located between the first plug px1 and the second plug px2. Specifically, in a plan view, the first well contact plug wx1 is located on a line segment connecting the first plug px1 and the second plug px2. This is advantageous from the viewpoint of suppressing coupling between the first plug px1 and the second plug px2.

[0098] Fig. 7 is a layout diagram of the voltage plug vy1 according to embodiment 1. In Fig. 7, the distance Ly0 is the distance between the first plug py1 and the second plug py2, the distance Ly1 is the distance between the first plug py1 and the voltage plug vy1, and the distance Ly2 is the distance between the second plug py2 and the voltage plug vy1.

[0099] 7, in the first embodiment, the distance Ly1 is smaller than the distance Ly0, and the distance Ly2 is smaller than the distance Ly0. Therefore, the voltage plug vy1 can contribute to suppressing coupling between the first plug py1 and the second plug py2.

[0100] The arrangement and number of well contact plugs that can contribute to suppressing coupling between the first plug py1 and the second plug py2 are not limited to the example in FIG. 7 . For example, by appropriately reinterpreting the terms used in the explanation given with reference to FIGS. 5C to 5G and 6C and 6D , the explanation can be made to relate to suppression of coupling between the first plug py1 and the second plug py2. The reinterpretations include: reinterpreting "first well contact plug wx1" as "voltage plug vy1," reinterpreting "second well contact plug wx2" as "second voltage plug," reinterpreting "first plug px1" as "first plug py1," and reinterpreting "second plug px2" as "second plug py2."

[0101] 7 , in the first embodiment, the voltage plug vy1 is located between the first plug py1 and the second plug py2. Specifically, in a plan view, the voltage plug vy1 is located on a line segment connecting the first plug py1 and the second plug py2. This is advantageous from the viewpoint of suppressing coupling between the first plug py1 and the second plug py2.

[0102] 8 is a cross-sectional view parallel to the thickness direction of the semiconductor substrate 100. In FIG. 8, the guard ring 30 in the peripheral region 92 is depicted.

[0103] 8, in the guard ring 30, the semiconductor substrate 100 includes an impurity region 171p. The impurity region 171p is provided in a well 175p. The concentration of p-type impurities in the impurity region 171p is higher than the concentration of n-type impurities in the well 175p.

[0104] The imaging device 90 includes a contact hole h7, a silicide layer sc7, and a plug p7.

[0105] The silicide layer sc7 is provided on the impurity region 171p. An insulating film 406 is provided on the silicide layer sc7. An insulating film 407 is provided on the insulating film 406.

[0106] The contact hole h7 penetrates the insulating film 406. The plug p7 is connected to the silicide layer sc7 through the contact hole h7.

[0107] In the semiconductor substrate 100, an isolation 181 and an isolation 182 are provided to sandwich the impurity region 171p. The isolation 181 and the isolation 182 are structures formed in the semiconductor substrate 100 by, for example, an STI (shallow trench isolation) process.

[0108] A voltage is supplied to the well 175p via the plug p7, the silicide layer sc7, and the impurity region 171p in this order. This voltage supply can contribute to suppressing noise from entering the pixel region 91 from outside the guard ring 30.

[0109] The impurity region 161n, the impurity region 162n, the impurity region 163n, the impurity region 165n, the charge storage region 166n, and the impurity region 167n contain n-type impurities. The n-type impurities are, for example, phosphorus. The impurity region 161p, the impurity region 162p, the impurity region 170p, the impurity region 171p, and the well 175p contain p-type impurities. The p-type impurities are, for example, boron.

[0110] In the first embodiment, the concentration of p-type impurities in the impurity region 170p is lower than the concentration of p-type impurities in the impurity region 171p.

[0111] The low concentration of p-type impurities in the impurity region 170p belonging to the pixel region 91 is advantageous in terms of suppressing dark current, which can contribute to improving image quality.

[0112] On the other hand, a high concentration of p-type impurities in the impurity region 171p belonging to the guard ring 30 is advantageous from the viewpoint of reducing loss due to resistance between the plug p7 and the impurity region 171p. Reducing loss due to resistance reduces the voltage drop in the voltage supply to the well 175p, making it easier to apply an appropriate potential to the well 175p. This improves the noise reduction effect of the guard ring 30 in the pixel region 91, and can contribute to improving image quality.

[0113] The semiconductor substrate 100 may include a p-type impurity region in a portion of the peripheral region 92 that is different from the guard ring 30. The concentration of the p-type impurity in this p-type impurity region may be higher than the concentration of the p-type impurity in the impurity region 170p that belongs to the pixel region 91. This portion is, for example, a portion that corresponds to the peripheral circuit 80. In this way, circuit delay can be suppressed.

[0114] In the first embodiment, the same type of p-type impurity is contained in the impurity region 170p and the overlapping portion of the insulating film 401 that overlaps with the impurity region 170p in a planar view. This configuration may be a trace of the formation of the impurity region 170p by injecting p-type impurities into the semiconductor substrate 100 via the insulating film 401 so that the concentration of the p-type impurity in the impurity region 170p is low. The same type of p-type impurity is, for example, boron.

[0115] In the first embodiment, the contact plugs cp1, cp2, cp3, cp4, and cp5 include a contact plug material. The plugs p0, p1, p2, p3, p4, p5, p6, p7, and px include a plug material. The contact plug material is different from the plug material.

[0116] Specifically, in the first embodiment, the contact plugs cp1, cp2, cp3, cp4, and cp5 contain a semiconductor material containing n-type impurities. That is, the contact plug material is a semiconductor material containing n-type impurities. The n-type impurities are, for example, phosphorus. The semiconductor material is, for example, polysilicon. That is, the semiconductor material containing n-type impurities includes, for example, phosphorus-doped polysilicon.

[0117] Specifically, in the first embodiment, the plugs p0, p1, p2, p3, p4, p5, p6, p7, and px contain a metal. That is, the plug material is a metal. The metal includes, for example, at least one selected from the group consisting of copper and tungsten.

[0118] As described above, in the first embodiment, the impurity region 163n, the charge accumulation region 166n, the impurity region 167n, and the like are n-type impurity regions. Furthermore, the contact plugs cp1, cp5, cp3, and the like are made of semiconductor material doped with n-type impurities. This makes it easier to suppress dark current resulting from metal diffusion compared to using metal plugs. For example, it is possible to suppress dark current resulting from metal diffusion in the charge accumulation region 166n. On the other hand, the impurity region 170p is a p-type impurity region. Furthermore, the plugs p0 and p6 connected to the impurity region 170p are made of metal-containing plugs rather than semiconductor material doped with p-type impurities. This can avoid the need for additional masks and implantation processes during the manufacture of the imaging device 1.

[0119] In the first embodiment, the wiring layer 551 includes a metal, such as at least one selected from the group consisting of copper and tungsten.

[0120] In the first embodiment, the gates 311e, 312e, 313e, and 314e include a semiconductor material containing n-type impurities. Specifically, the n-type impurities are present in the gates 311e, 312e, 313e, and 314e at high concentrations by ion implantation. This reduces the resistance of the gates 311e, 312e, 313e, and 314e and provides them with conductivity. The semiconductor material is, for example, polysilicon.

[0121] Regarding the silicide layers sc1, sc2, sc3, sc4, sc5, and sc7, the silicide is a compound of metal and silicon. The metal includes, for example, at least one selected from the group consisting of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt). In the first embodiment, the silicide layers sc1, sc2, sc3, sc4, sc5, and sc7 are NiPt silicide layers.

[0122] In the first embodiment, the impurity region 170p is a non-silicide. Here, the non-silicide of an element means that the silicide content of the entire element is less than 10% by mass, and this content is typically less than 5% by mass, and this content may be zero% by mass.

[0123] As described above, in the first embodiment, the guard ring 30 has a silicide layer sc7 on the impurity region 171p, and the plug p7 is connected to the silicide layer sc7. The silicide serves to reduce loss due to resistance. This reduces the voltage drop in the voltage supply to the well 175p, making it easier to apply an appropriate potential to the well 175p. This improves the noise reduction effect of the guard ring 30 in the pixel region 91, and can contribute to improving image quality.

[0124] On the other hand, suppose a silicidation process is performed in the pixel region 91 to form a silicide layer. In this case, not all of the metal introduced in this process contributes to the formation of the silicide layer, and the metal that does not contribute to the formation of the silicide layer may diffuse into the charge accumulation region 166n during a subsequent heat treatment process. In this regard, in the first embodiment, the impurity region 170p is a non-silicide. Therefore, the metal is less likely to diffuse into the charge accumulation region 166n. This can suppress dark current and contribute to improving image quality.

[0125] In the first embodiment, the insulating films 401, 402, 403, 405, and 407 are oxide films. The insulating films 404 and 406 are nitride films. Specifically, the insulating films 401, 402, 405, and 407 contain silicon oxide. The insulating films 404 and 406 contain silicon nitride.

[0126] Other embodiments will be described below. In the following, elements common to the already described embodiment and its modified examples and the embodiment and its modified examples to be described later will be given the same reference numerals, and their description may be omitted. The descriptions of the embodiments and their modified examples may be mutually applicable unless technically inconsistent. The embodiments and their modified examples may be mutually combined unless technically inconsistent.

[0127] Second Embodiment Fig. 9 is a circuit diagram of an imaging device 90 according to a second embodiment. In Fig. 9, two pixels 10 are representatively depicted.

[0128] In the imaging device 90 according to the second embodiment, the pixel 10 does not include the overflow transistor 314 .

[0129] FIG. 10 is a plan view of a pixel region 91 according to the second embodiment.

[0130] In the pixel region 91, an impurity region 270p is provided in a well 175p of the semiconductor substrate 100. The impurity region 270p is a p-type impurity region in which the concentration of p-type impurities is higher than the concentration of p-type impurities in the well 175p.

[0131] In a plan view, a unit configuration including, in this order: an impurity region 170p shared by the first pixel 10a and the second pixel 10b; and an impurity region 270p shared by the first pixel 10a and the second pixel 10b, appears repeatedly along a straight line 41 extending in the row direction D1.

[0132] In a plan view, along a straight line 50C extending in the column direction D2, a unit configuration including, in this order: an impurity region 165n shared by the first pixel 10a and the second pixel 10b; a gate 313e of the first pixel 10a; a charge storage region 166n of the first pixel 10a; an impurity region 270p shared by the first pixel 10a and the second pixel 10b; a charge storage region 166n of the second pixel 10b; and a gate 313e of the second pixel 10b appears repeatedly.

[0133] FIG. 11 is a cross-sectional view taken along a line 50C in FIG. 10 and parallel to the thickness direction of the semiconductor substrate 100. In FIG.

[0134] 11 illustrates a pixel region 91. In FIG. 11, the fact that the first pixel 10a and the second pixel 10b are flip-arranged is indicated by a block arrow. In FIG. 11, the axis of the flip-arrangement in the cross section of FIG. 11 is indicated by a thick dotted line.

[0135] 11, in the pixel 10, the semiconductor substrate 100 includes an impurity region 163p. The impurity region 163p is provided in a well 175p. The impurity region 163p is a p-type impurity region that forms a channel region of the reset transistor 313 below the gate 312e.

[0136] The imaging device 90 includes contact holes h8, h9 and h10.

[0137] As shown in FIG. 11 , the contact hole h8 penetrates the insulating films 401, 402, and 405; the contact hole h9 penetrates the insulating films 402 and 405; and the contact hole h10 penetrates the insulating films 401, 402, and 405.

[0138] The imaging device 90 includes a contact plug cp9, a contact plug cp10, a silicide layer sc9, a silicide layer sc10, a plug p8, a plug p9, and a plug p10.

[0139] As can be seen from FIGS. 9, 10 and 11, the plug p9 is electrically connected to the reset control line 253, and the plug p10 is electrically connected to the voltage line 223.

[0140] In the second embodiment, the imaging device 90 includes a first well contact plug wz1. The first well contact plug wz1 applies a potential to the semiconductor layer 175p. The first well contact plug wz1 is connected to the impurity region 270p and is electrically connected to the well control line 250. In the examples of FIGS. 8 and 11 , the first well contact plug wz1 includes a plug p8 shared by the first pixel 10a and the second pixel 10b, specifically, the plug p8 shared by the first pixel 10a and the second pixel 10b. The plug p8 shared by the first pixel 10a and the second pixel 10b is connected to the impurity region 170p.

[0141] In the second embodiment, the imaging device 90 includes a first plug pz1. The first plug pz1 is connected to the first charge storage region 166na. In the example of Fig. 11, the first plug pz1 includes a contact plug cp5 in the first pixel 10a, a silicide layer sc5 in the first pixel 10a, and a plug p5 in the first pixel 10a. The contact plug cp5 in the first pixel 10a is connected to the first charge storage region 166na.

[0142] In the second embodiment, the imaging device 90 includes a second plug pz2. The second plug pz2 is connected to the second charge storage region 166nb. In the example of FIG. 11 , the second plug pz2 includes a contact plug cp5 in the second pixel 10b, a silicide layer sc5 in the second pixel 10b, and a plug p5 in the second pixel 10b. The contact plug cp5 in the second pixel 10b is connected to the second charge storage region 166nb.

[0143] The first charge storage region 166na and the second charge storage region 166nb are adjacent to each other. Specifically, in the column direction D2, the gate 313e of the first pixel 10a, the first charge storage region 166na, the second charge storage region 166nb, and the gate 313e of the second pixel 10b are arranged in this order.

[0144] No n-type impurity region exists between the first charge storage region 166na and the second charge storage region 166nb. In other words, in plan view, no n-type impurity region exists on the line segment connecting the first charge storage region 166na and the second charge storage region 166nb.

[0145] The first pixel 10a and the second pixel 10b are adjacent to each other in the column direction D2, with the first well contact plug wz1 sandwiched between them.

[0146] As shown in FIG. 11, the plug p8 is connected to the impurity region 270p through the contact hole h8, the contact plug cp9 is connected to the gate 313e through the contact hole h9, the silicide layer sc9 is provided on the contact plug cp9, the plug p9 is connected to the silicide layer sc9, the contact plug cp10 is connected to the impurity region 165n through the contact hole h10, the silicide layer sc10 is provided on the contact plug cp10, and the plug p10 is connected to the silicide layer sc10.

[0147] The insulating film 406 is provided so as to cover the insulating film 405, the contact plug cp9, the silicide layer sc9, the contact plug cp10, and the silicide layer sc10 from above.

[0148] 12 is a layout diagram of well contact plugs according to embodiment 2. In Fig. 12, the distance Lz0 is the distance between the first plug pz1 and the second plug pz2, the distance Lz1 is the distance between the first plug pz1 and the first well contact plug wz1, and the distance Lz2 is the distance between the second plug pz2 and the first well contact plug wz1.

[0149] 12 , in the second embodiment, the distance Lz1 is smaller than the distance Lz0, and the distance Lz2 is smaller than the distance Lz0. Therefore, the first well contact plug wz1 can contribute to suppressing coupling between the first plug pz1 and the second plug pz2.

[0150] The arrangement and number of well contact plugs that can contribute to suppressing coupling between the first plug pz1 and the second plug pz2 are not limited to the example in FIG. 12 . For example, the explanation of embodiment 2 can be achieved by appropriately reinterpreting the terms used in the explanation of embodiment 1 with reference to FIGS. 5C to 5G and 6C and 6D . The reinterpretations include: "first well contact plug wx1" to "first well contact plug wz1," "second well contact plug wx2" to "second well contact plug," "first plug px1" to "first plug pz1," and "second plug px2" to "second plug pz2."

[0151] 12, the first well contact plug wz1 is located between the first plug pz1 and the second plug pz2. Specifically, in a plan view, the first well contact plug wz1 is located on the line segment connecting the first plug pz1 and the second plug pz2.

[0152] The impurity region 270p and the impurity region 163p contain n-type impurities, such as phosphorus. The impurity region 270p contains p-type impurities, such as boron.

[0153] In the second embodiment, the concentration of the p-type impurity in the impurity region 270p is lower than the concentration of the p-type impurity in the impurity region 171p.

[0154] In the second embodiment, the same type of impurity is contained in the impurity region 270p and the overlapping portion of the insulating film 401 that overlaps with the impurity region 270p in a plan view. The same type of p-type impurity is, for example, boron.

[0155] In the second embodiment, the contact plugs cp9 and cp10 include a contact plug material. Specifically, the contact plugs cp9 and cp10 include a semiconductor material containing n-type impurities. That is, the contact plug material is a semiconductor material containing n-type impurities. The n-type impurities are, for example, phosphorus. The semiconductor material is, for example, polysilicon. That is, the semiconductor material containing n-type impurities includes, for example, phosphorus-doped polysilicon.

[0156] In the second embodiment, the plugs p8, p9, and p10 include a plug material. Specifically, the plugs p8, p9, and p10 include a metal. That is, the plug material is a metal. The metal includes, for example, at least one selected from the group consisting of copper and tungsten.

[0157] The description regarding silicide in the first embodiment can also be applied to the silicide layer sc9 and the silicide layer sc10 in the second embodiment. In the second embodiment, the silicide layer sc9 and the silicide layer sc10 are NiPt silicide layers.

[0158] In the second embodiment, the impurity region 270p is a non-silicide.

[0159] Third Embodiment FIG. 13 is a plan view of a pixel region 91 according to a third embodiment.

[0160] In a plan view, a unit configuration including, in this order: an impurity region 170p shared by the first pixel 10a and the second pixel 10b; and an impurity region 165n shared by the first pixel 10a and the second pixel 10b, appears repeatedly along a straight line 41 extending in the row direction D1.

[0161] In a plan view, a unit configuration including, in this order: an impurity region 161n shared by the first pixel 10a and the second pixel 10b; and an impurity region 270p shared by the first pixel 10a and the second pixel 10b, appears repeatedly along a straight line 42 extending in the row direction D1.

[0162] In the third embodiment, similarly to the second embodiment, in a plan view, along a straight line 50D extending in the column direction D2, a unit configuration including, in this order: an impurity region 165n shared by the first pixel 10a and the second pixel 10b; a gate 313e of the first pixel 10a; a charge storage region 166n of the first pixel 10a; an impurity region 270p shared by the first pixel 10a and the second pixel 10b; a charge storage region 166n of the second pixel 10b; and a gate 313e of the second pixel 10b appears repeatedly.

[0163] The cross-sectional view of the semiconductor substrate 100 taken along the line 50D in FIG. 13 and parallel to the thickness direction thereof is the same as the cross-sectional view of the semiconductor substrate 100 taken along the line 50C in FIG.

[0164] 14 is a circuit diagram of an imaging device 90 according to embodiment 4. In FIG. 14, two pixels 10 are representatively depicted.

[0165] In the imaging device 90 according to the fourth embodiment, the pixel 10 includes a transfer transistor 315. The photoelectric conversion unit 150 includes a photodiode 190. In the fourth embodiment, the transfer transistor 315 is a MOSFET.

[0166] The horizontal circuit 81 selects the pixels 10 on a row-by-row basis, and supplies a voltage to the pixels 10 in the selected row via the transfer control line 255. As a result, signal charges are transferred from the photodiodes 190 to the charge accumulation regions 166 n in the pixels 10 in the selected row.

[0167] The photodiode 190 is connected to one of the source and drain of the transfer transistor 315. The other of the source and drain of the transfer transistor 315 forms a charge accumulation region 166n. In addition, one of the source and drain of the reset transistor 313 forms the charge accumulation region 166n. In other words, the charge accumulation region 166n is shared by the reset transistor 313 and the transfer transistor 315. The charge accumulation region 166n is connected to the gate of the amplification transistor 311.

[0168] The photodiode 190 converts light into an electric charge, and the transfer transistor 315 transfers the electric charge from the photodiode 190 to the charge storage region 166n.

[0169] Specifically, the horizontal circuit 81 is connected to the gate of the transfer transistor 315 via a transfer control line 255. A voltage is supplied from the horizontal circuit 81 to the gate of the transfer transistor 315 in the pixel 10 in the row selected by the horizontal circuit 81 via the transfer control line 255. This turns on the transfer transistor 315, and charge is transferred from the photodiode 190 to the charge accumulation region 166 n via the transfer transistor 315.

[0170] FIG. 15 is a plan view of a pixel region 91 according to the fourth embodiment.

[0171] In the pixel region 91, a photodiode 190 and a transfer transistor 315 are provided on the semiconductor substrate 100. In FIG.

[0172] In the fourth embodiment, similarly to the second and third embodiments, in a plan view, a unit configuration including, in this order, the following appears repeatedly along a straight line 50E extending in the column direction D2: an impurity region 165n shared by the first pixel 10a and the second pixel 10b; a gate 313e of the first pixel 10a; a charge storage region 166n of the first pixel 10a; an impurity region 270p shared by the first pixel 10a and the second pixel 10b; a charge storage region 166n of the second pixel 10b; and a gate 313e of the second pixel 10b.

[0173] The cross-sectional view of the semiconductor substrate 100 taken along the line 50E in FIG. 15 and parallel to the thickness direction thereof is the same as the cross-sectional view of the semiconductor substrate 100 taken along the line 50C in FIG. 10 and parallel to the thickness direction thereof.

[0174] Embodiment 5 In Embodiment 5, a part of a method for manufacturing the imaging device 90 according to Embodiment 1 will be described. Figures 16A to 16K are process diagrams for explaining an example of a method for manufacturing the imaging device 90. Note that Figures 16A to 16K also show the formation of the guard ring 30 together with the pixel region 91 including the first pixel 10 a and the second pixel 10 b.

[0175] A structure 501 shown in FIG. 16A is fabricated. In the fifth embodiment, the insulating film 401 is a high temperature oxide (HTO) film obtained by thermally oxidizing silicon. The insulating film 402 is a silicon oxide film made from tetraethoxysilane (TEOS). The insulating film 404 is a silicon nitride film made from BTBAS (bis(tertiary-butyl-amino)silane, SiH(NH(C4H9))).

[0176] 16A , the structure 501 has the insulating film 401 in the pixel region 91. Specifically, the structure 501 has the insulating film 401 in the first pixel 10 a and the second pixel 10 b. In contrast, the structure 501 does not have the insulating film 401 in the guard ring 30. The structure 501 does not need to have the insulating film 401 in the entire peripheral region 92.

[0177] 16B, a mask 602 is used to implant p-type impurities toward the semiconductor substrate 100 of the structure 501. This results in a structure 502 having an impurity region 170p in the pixel region 91 and an impurity region 171p in the guard ring 30. In the fifth embodiment, the p-type impurity is boron.

[0178] The impurity region 170p in the pixel region 91 is formed by implanting p-type impurities into the semiconductor substrate 100 via the insulating film 401. On the other hand, the impurity region 171p in the guard ring 30 is formed by implanting p-type impurities into the semiconductor substrate 100 without implanting the insulating film 401. Therefore, the concentration of the p-type impurities in the impurity region 170p is lower than the concentration of the p-type impurities in the impurity region 171p. Furthermore, the implanted p-type impurities may also be introduced into an overlapping portion of the insulating film 401 in the structure 502 that overlaps with the impurity region 170p in a planar view. This p-type impurity may remain in the overlapping portion in the completed imaging device 90.

[0179] The semiconductor substrate 100 may include a p-type impurity region in a portion of the peripheral region 92 that is different from the guard ring 30. It is also possible to make the concentration of the p-type impurity in this p-type impurity region higher than the concentration of the p-type impurity in the impurity region 170p that belongs to the pixel region 91. To achieve this, as with the guard ring 30, p-type impurities may be implanted into the semiconductor substrate 100 without the insulating film 401 being present in the above-mentioned portion.

[0180] 16C, an insulating film 405 is formed. In this manner, a structure 503 is obtained. In the fifth embodiment, an NSG (Non-doped Silicate Glass) film is formed as the insulating film 405 by SA-CVD (Sub-Atmospheric-Chemical Vapor Deposition). The insulating film 405 is formed in both the pixel region 91 and the guard ring 30. As described above, the insulating film 405 is a silicide block film.

[0181] 16D, contact holes h1 and h2 are formed in the structure 503. In this way, a structure 504 is obtained. In the fifth embodiment, the contact holes h1 and h2 are formed by dry etching.

[0182] Next, as shown in Figure 16E, a contact plug material layer 410 is deposited on the structure 504, thus obtaining the structure 504. In the fifth embodiment, the contact plug material layer 410 is phosphorus-doped polysilicon. The deposition is performed by LPCVD (Low Pressure Chemical Vapor Deposition).

[0183] 16F, the contact plug material layer 410 in the structure 505 is processed by etching using a mask 606 so as to form contact plugs cp1 and cp2. In this way, a structure 506 is obtained.

[0184] 16G, wet etching is performed with the pixel region 91 covered with a mask 607. As a result, the insulating film 405 in the guard ring 30 is removed while the insulating film 405 in the pixel region 91 remains. In this way, a structure 507 is obtained.

[0185] Next, as shown in FIG. 16H, silicide layers sc1, sc2, and sc7 are formed. Thus, a structure 508 is obtained. In the fifth embodiment, a metal is deposited on the structure 507 by sputtering. After this deposition, a heat treatment is performed. As a result, the silicide layers sc1, sc2, and sc7 are formed. The deposited metal includes nickel and platinum. The silicide layers sc1, sc2, and sc7 are NiPt silicide layers.

[0186] 16I, an insulating film 406 is formed, followed by the formation of an insulating film 407. In this manner, a structure 509 is obtained. In the fifth embodiment, a silicon nitride film is formed as the insulating film 406 by ALD (Atomic Layer Deposition). An NSG (Non-doped Silicate Glass) film is formed as the insulating film 407 by HDP-CVD (High Density Plasma Chemical Vapor Deposition).

[0187] 16J, holes 710h0, 710h1, 710h2, and 710h7 are formed in the structure 509 by dry etching using the mask 610. In this manner, the structure 510 is obtained. The holes 710h0, 710h1, 710h2, and 710h7 reach the impurity region 170p, the silicide layer sc1, the silicide layer sc2, and the silicide layer sc7, respectively. The hole 710h0 includes a contact hole h0. The hole 710h7 includes a contact hole h7.

[0188] 16K, the holes 710h0, 710h1, 710h2, and 710h7 are filled with a plug material, thereby forming plugs p0, p1, p2, and p7, and thus obtaining a structure 511.

[0189] Sixth Embodiment A camera system 1000 according to this embodiment will be described with reference to FIG.

[0190] 17 schematically shows an example configuration of a camera system 1000 according to this embodiment. The camera system 1000 includes a lens optical system 1100, an imaging device 1200, a system controller 1300, and a camera signal processing circuit 1400. The camera system 1000 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0191] The lens optical system 1100 may include a lens group including, for example, an autofocus lens and a zoom lens, and an aperture. The lens optical system 1100 focuses light onto the imaging plane of the imaging device 1200. The imaging device 1200 can be any of the imaging devices 90 according to the first to fourth embodiments described above.

[0192] The system controller 1300 controls the entire camera system 1000. The system controller 1300 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0193] The camera signal processing circuit 1400 has a function of processing an output signal from the image capture device 1200. The camera signal processing circuit 1400 receives output data from the image capture device 1200 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The image capture device 1200 and the camera signal processing circuit 1400 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 1200 as a part thereof. The camera signal processing circuit 1400 is, for example, a DSP (Digital Signal Processor).

[0194] (Technology Applicable to Embodiments 1 to 6 and Their Modifications) In the above description, the thickness of the insulating film 401 is uniform. However, the thickness of the insulating film 401 may be non-uniform. Here, "uniform thickness" means that the minimum value of the thickness is 70% or more and 100% or less of the maximum value.

[0195] As described above, the impurity region 170p in the pixel region 91 can be formed by implanting p-type impurities into the semiconductor substrate 100 while the insulating film 401 remains. On the other hand, the impurity region 171p in the guard ring 30 can be formed by implanting p-type impurities into the semiconductor substrate 100 while the insulating film 401 does not remain. This allows the concentration of p-type impurities in the impurity region 170p to be lower than the concentration of p-type impurities in the impurity region 171p. The thickness of a portion of the insulating film 401 may be greater than the thickness of other portions of the insulating film 401. FIG. 18 is an explanatory diagram of a configuration example of the insulating film 401. In the example of FIG. 18, the thickness of the overlapping portion of the insulating film 401 that overlaps with the impurity region 170p in a plan view is greater than the thickness of the portion of the insulating film 401 surrounding the overlapping portion. This is advantageous from the perspective of lowering the concentration of p-type impurities in the impurity region 170p.

[0196] 18 illustrates a modified form of the insulating film 401 of the form in FIG. 3A , but it is also possible to modify other forms of the insulating film 401. Furthermore, the thickness of the overlapping portion of the insulating film 401 that overlaps with the impurity region 270p in plan view may be made larger than the thickness of the portion of the insulating film 401 surrounding the overlapping portion.

[0197] 18, the overlapping portion of the impurity region 170p and / or the impurity region 270p may include a plurality of insulating layers, although the overlapping portion may have a single-layer structure.

[0198] The contact plugs cp1, cp2, cp3, cp4, cp5, cp9, and cp10 may contain the same material or different materials. The plugs p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, and p10 may contain the same material or different materials. The silicide layers sc1, sc2, sc3, sc4, sc5, sc9, and sc10 may contain the same material or different materials.

[0199] In the above description, in a plan view, the guard ring 30 has a closed frame shape surrounding the pixel region 91. However, in a plan view, there may be a portion in the closed frame-shaped region surrounding the pixel region 91 where the guard ring 30 is not present. For example, in a plan view, the guard ring 30 may have an L-shape.

[0200] The imaging device 90 may be a front side illumination (FSI) type or a back side illumination (BSI) type.

[0201] (Additional Note) The present disclosure discloses the following techniques.

[0202] (Technology 1) A semiconductor device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a first well contact plug that applies a potential to the semiconductor layer; a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween; a first signal line to which a first signal output by the first pixel is input; and a second signal line to which a second signal output by the second pixel is input, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer; and a first plug connected to the first impurity region and electrically connected to the first signal line; and the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer; and a second plug connected to the second impurity region and electrically connected to the second signal line, wherein the first impurity region and the second impurity region are adjacent to each other, an imaging device, wherein a distance between the first plug and the first well contact plug is smaller than a distance between the first plug and the second plug; and a distance between the second plug and the first well contact plug is smaller than a distance between the second plug and the first plug.

[0203] and a first well contact plug configured to apply a potential to the semiconductor layer; and a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween, wherein the first pixel includes: a first photoelectric conversion unit configured to convert light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer and in which the first signal charge is accumulated; and a first plug connected to the first impurity region; the second pixel includes: a second photoelectric conversion unit configured to convert light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer and in which the second signal charge is accumulated; and a second plug connected to the second impurity region, wherein the first impurity region and the second impurity region are adjacent to each other, a distance between the first plug and the first well contact plug is smaller than a distance between the first plug and the second plug, and a distance between the second plug and the first well contact plug is smaller than a distance between the second plug and the first plug.

[0204] (Technology 3) The imaging device according to Technology 1 or 2, further comprising a second well contact plug that applies a potential to the semiconductor layer, wherein the distance between the first plug and the second well contact plug is smaller than the distance between the first plug and the second plug, and the distance between the second plug and the second well contact plug is smaller than the distance between the second plug and the first plug.

[0205] (Technology 4) The imaging device according to any one of Technologies 1 to 3, wherein the second conductivity type impurity region is not present between the first impurity region and the second impurity region.

[0206] (Technology 5) The imaging device according to any one of Technologies 1 to 4, wherein the first well contact plug is located between the first plug and the second plug.

[0207] (Technology 6) The imaging device according to any one of Techniques 1 to 5, wherein the first plug has a first structure connected to the first impurity region, the second plug has a second structure connected to the first impurity region, and the first well contact plug has a third structure connected to the semiconductor layer, the first structure including a first material, the second structure including a second material, and the third structure including a third material, the third material being different from the first material, and the third material being different from the second material. Note that in Technique 6, the first structure may correspond to contact plug cp1 of the first pixel 10a. The second structure may correspond to contact plug cp1 of the second pixel 10b. The third structure may correspond to plug p0. Also, in Technique 6, the first structure may correspond to contact plug cp5 of the first pixel 10a. The second structure may correspond to contact plug cp5 of the second pixel 10b. The third structure may correspond to plug p8.

[0208] (Technology 7) The imaging device according to Technology 6, wherein the first material is a semiconductor material containing impurities of the second conductivity type, the second material is a semiconductor material containing impurities of the second conductivity type, and the third material is a metal.

[0209] (Technology 8) A pixel includes a semiconductor substrate including a semiconductor layer of a first conductivity type; a voltage plug; first and second pixels adjacent to each other with the voltage plug sandwiched therebetween; and a constant voltage source, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first charge accumulation region of a second conductivity type located in the semiconductor layer and in which the first signal charge is accumulated; a first electrode; and a first plug connected to the first electrode and electrically connected to the first charge accumulation; the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second charge accumulation region of the second conductivity type located in the semiconductor layer and in which the second signal charge is accumulated; a second electrode; and a second plug connected to the second electrode and electrically connected to the second charge accumulation; the first pixel and the second pixel share an impurity region of the second conductivity type located in the semiconductor layer, and the voltage plug is connected to the impurity region and electrically connected to the constant voltage source, an imaging device, wherein the first electrode and the second electrode are adjacent to each other; a distance between the first plug and the voltage plug is smaller than a distance between the first plug and the second plug; and a distance between the second plug and the voltage plug is smaller than a distance between the second plug and the first plug.

[0210] (Technology 9) An imaging device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the pixel region includes: a photoelectric conversion unit that converts light into signal charges; a well contact plug that applies a potential to the semiconductor layer; and a first impurity region of the first conductivity type connected to the well contact plug and located in the semiconductor layer, wherein the peripheral region includes: a peripheral plug; and a second impurity region of the first conductivity type connected to the peripheral plug and located in the semiconductor layer, wherein a concentration of the impurity of the first conductivity type in the first impurity region is lower than a concentration of the impurity of the first conductivity type in the second impurity region. Note that in Techniques 9 and 10, the peripheral plug may include plug p7. The peripheral plug may be plug p7.

[0211] (Technology 10) An imaging device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the pixel region includes: a photoelectric conversion unit that converts light into signal charges; a well contact plug that applies a potential to the semiconductor layer; and a first impurity region of the first conductivity type connected to the well contact plug and located in the semiconductor layer, wherein the peripheral region includes: a peripheral plug; and a second impurity region of the first conductivity type located in the semiconductor layer, wherein the first impurity region is non-silicide, and the second impurity region includes a silicide layer connected to the peripheral plug.

[0212] (Technology 11) An imaging device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; and a pixel region, wherein the pixel region includes: a photoelectric conversion unit that converts light into signal charges; an insulating film located on the semiconductor substrate; a well contact plug that penetrates the insulating film and applies a potential to the semiconductor layer; and an impurity region of the first conductivity type that is connected to the well contact plug and is located in the semiconductor layer, wherein the impurity region and an overlapping portion of the insulating film that overlaps with the impurity region in a planar view contain the same kind of impurity of the first conductivity type.

[0213] The imaging device according to the present disclosure can be employed, for example, for mobile applications.

[0214] 1 Imaging device 10, 10a, 10b Second pixel 21 Central portion 22 Peripheral portion 30 Guard ring 80 Peripheral circuit 81 Horizontal circuit 82 Vertical circuit 90 Imaging device 91 Pixel region 92 Peripheral region 100 Semiconductor substrate 100a Surface 150 Photoelectric conversion portion 151 Photoelectric conversion film 152 Pixel electrode 153 Counter electrode 161n, 161p, 162n, 162p, 163n, 163p, 165n, 167n, 170p, 171p, 270p Impurity region 163na First impurity region 163nb Second impurity region 166n Charge storage region 166na First charge storage region 166nb Second charge storage region 175p Well (semiconductor layer) 181, 182 Element isolation 190 Photodiode 221, 223, 224 Voltage line 250 Well control line 252 Address control line 253 Reset control line 255 Transfer control line 260 Signal line 260a First signal line 260b Second signal line 311 Amplification transistor 312 Selection transistor 313 Reset transistor 314 Overflow transistor 315 Transfer transistor 311e, 312e, 313e, 314e, 315e Gate 314ea First electrode 314eb Second electrode 330 Charge storage node 401, 402, 403, 404, 405, 406, 407 Insulating film 410 Contact plug material layer 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511 Structure 551 Wiring layer 602, 606, 607, 610 Mask 710h0, 710h1, 710h2, 710h7 Hole 1000 Camera system 1100 Lens optical system 1200 Imaging device 1300 System controller 1400 Camera signal processing circuit D1 Row direction D2 Column direction cp1, cp2, cp3, cp4, cp5, cp9, cp10 Contact plug h0, h1, h2, h3, h4, h5, h7, h8, h9, h10 Contact hole p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10 plugssc1, sc2, sc3, sc4, sc5, sc7, sc9, sc10: silicide layers wx1, wx2, wx3, wz1: well contact plug vy1: voltage plug px1, py1, pz1: first plug px2, py2, pz2: second plug

Claims

1. A semiconductor substrate including a semiconductor layer of a first conductivity type; a first well contact plug that applies a potential to the semiconductor layer; a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween; a first signal line to which a first signal output by the first pixel is input; and a second signal line to which a second signal output by the second pixel is input, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer; and a first plug connected to the first impurity region and electrically connected to the first signal line; and the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer; and a second plug connected to the second impurity region and electrically connected to the second signal line, wherein the first impurity region and the second impurity region are adjacent to each other, an imaging device, wherein a distance between the first plug and the first well contact plug is smaller than a distance between the first plug and the second plug; and a distance between the second plug and the first well contact plug is smaller than a distance between the second plug and the first plug.

2. An imaging device comprising: a semiconductor substrate including a semiconductor layer of a first conductivity type; a first well contact plug that applies a potential to the semiconductor layer; and a first pixel and a second pixel adjacent to each other with the first well contact plug sandwiched therebetween, wherein the first pixel includes: a first photoelectric conversion unit that converts light into a first signal charge; a first impurity region of a second conductivity type located in the semiconductor layer and in which the first signal charge is accumulated; and a first plug connected to the first impurity region; the second pixel includes: a second photoelectric conversion unit that converts light into a second signal charge; a second impurity region of the second conductivity type located in the semiconductor layer and in which the second signal charge is accumulated; and a second plug connected to the second impurity region, wherein the first impurity region and the second impurity region are adjacent to each other, the distance between the first plug and the first well contact plug is smaller than the distance between the first plug and the second plug, and the distance between the second plug and the first well contact plug is smaller than the distance between the second plug and the first plug.

3. The imaging device described in claim 1 or 2, further comprising a second well contact plug that applies a potential to the semiconductor layer, wherein the distance between the first plug and the second well contact plug is smaller than the distance between the first plug and the second plug, and the distance between the second plug and the second well contact plug is smaller than the distance between the second plug and the first plug.

4. The imaging device according to claim 1 or 2, wherein the second conductivity type impurity region does not exist between the first impurity region and the second impurity region.

5. The imaging device according to claim 1 or 2, wherein the first well contact plug is located between the first plug and the second plug.

6. The imaging device of claim 1 or 2, wherein the first plug has a first structure connected to the first impurity region, the second plug has a second structure connected to the first impurity region, the first well contact plug has a third structure connected to the semiconductor layer, the first structure includes a first material, the second structure includes a second material, the third structure includes a third material, the third material is different from the first material, and the third material is different from the second material.

7. The imaging device according to claim 6, wherein the first material is a semiconductor material containing impurities of the second conductivity type, the second material is a semiconductor material containing impurities of the second conductivity type, and the third material is a metal.

Images