Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a base build-up insulating layer including a through-via electrode passing through a plurality of base insulating layers; a lower build-up insulating layer that includes a plurality of first wiring layers and a plurality of first via electrodes; and an upper build-up insulating layer that includes a plurality of second wiring layers and a plurality of second via electrodes, wherein the through-via electrode comprises: a first portion having a horizontal width that gradually decreases from the first wiring layers toward the second wiring layers; a second portion having a horizontal width that gradually increases from the first wiring layers toward the second wiring layers; and a protruding portion protruding in the horizontal direction in an area between the first portion and the second portion.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulating structure including a plurality of insulating layers stacked along a vertical direction, and a circuit structure disposed on the plurality of insulating layers on the build-up insulating structure. For example, the circuit board may mean that a circuit structure connected to at least one semiconductor element is disposed on each insulating layer of the build-up insulating structure. The circuit structure includes a wiring layer disposed on a surface of each insulating layer of the build-up insulating structure, and a via electrode for vertically connecting each wiring layer. The semiconductor element is mounted on the circuit board, and can transmit and receive signals through the circuit structure.

[0005] On the other hand, a circuit board according to the prior art has pads of a wiring layer provided between a plurality of via electrodes spaced apart from each other in a vertical direction. Accordingly, a signal flowing through the circuit structure passes through the pads between the plurality of via electrodes, which causes a problem of an increased signal transmission distance or an increased signal transmission loss. In addition, according to the prior art, the formation of the via electrodes reduces the rigidity of the circuit board, resulting in a warpage problem, or a void problem in which at least a portion of the hole is not filled with a conductive material during the process of forming the via electrodes.

[0006] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0007] Additionally, the embodiment provides a circuit board and a semiconductor package including the same, wherein physical reliability and / or electrical reliability are disclosed.

[0008] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0009] A circuit board according to an embodiment comprises a build-up insulating structure including a base build-up insulating layer including a plurality of base insulating layers, a lower build-up insulating layer disposed on a lower surface of the base build-up insulating layer and including a plurality of lower insulating layers, and an upper build-up insulating layer disposed on an upper surface of the base build-up insulating layer and including a plurality of upper insulating layers; a plurality of first wiring layers disposed on a lower surface of the base build-up insulating layer and a lower surface of each of the plurality of lower insulating layers; a plurality of second wiring layers disposed on an upper surface of the base build-up insulating layer and a lower surface of each of the plurality of upper insulating layers; a plurality of first via electrodes disposed between the plurality of first wiring layers and penetrating at least a portion of the plurality of lower insulating layers along a vertical direction; a second via electrode disposed between the plurality of second wiring layers and penetrating at least a portion of the plurality of upper insulating layers along the vertical direction; A through-via electrode is included that penetrates the plurality of base insulating layers along the vertical direction, and the through-via electrode includes a first portion whose width in the horizontal direction becomes narrower as it moves from the first wiring layer toward the second wiring layer, a second portion whose width in the horizontal direction becomes wider as it moves from the first wiring layer toward the second wiring layer, and a protrusion portion that protrudes in the horizontal direction in an area between the first portion and the second portion.

[0010] Additionally, the lower surface of the first portion of the through-via electrode is directly connected to the first wiring layer disposed on the lower surface of the base build-up insulating layer, and the upper surface of the second portion of the through-via electrode is directly connected to the second wiring layer disposed on the upper surface of the base build-up insulating layer.

[0011] Additionally, the protrusion of the through via electrode is disposed at the interface between the plurality of base insulating layers.

[0012] In addition, the first width in the horizontal direction of the through-via electrode in the protrusion is different from the second width in the horizontal direction of the through-via electrode on the lower surface of the first portion or the third width in the horizontal direction of the through-via electrode on the upper surface of the second portion.

[0013] In addition, the difference value between the first width and the second width or the third width is smaller than the difference value between the horizontal width of the first wiring layer and the second width or the difference value between the horizontal width of the second wiring layer and the third width.

[0014] Additionally, the first width in the horizontal direction of the through via electrode in the protrusion is smaller than the width in the horizontal direction of each of the plurality of first wiring layers or the width in the horizontal direction of each of the plurality of second wiring layers.

[0015] Additionally, each of the plurality of first via electrodes has the same slope as the slope of the first portion of the through via electrode.

[0016] Additionally, each of the plurality of second via electrodes has the same slope as the slope of the second portion of the through via electrode.

[0017] Additionally, the horizontal central axis of the first portion of the through-via electrode is aligned with the horizontal central axis of the second portion of the through-via electrode.

[0018] Additionally, the horizontal central axis of the first portion of the through-via electrode is misaligned with the horizontal central axis of the second portion of the through-via electrode.

[0019] In addition, the through-via electrode includes at least one of a first through-via electrode in which a horizontal central axis of the first portion is aligned with a horizontal central axis of the second portion of the through-via electrode; a second through-via electrode in which a horizontal central axis of the first portion and a horizontal central axis of the second portion of the through-via electrode are misaligned in a first misalignment direction; and a third through-via electrode in which a horizontal central axis of the first portion and a horizontal central axis of the second portion of the through-via electrode are misaligned in a second misalignment direction different from the first misalignment direction.

[0020] Additionally, the vertical thickness of the first portion of the through-via electrode and the vertical thickness of the second portion of the through-via electrode are different.

[0021] A circuit board according to an embodiment includes a base build-up insulating layer including a plurality of base insulating layers, and includes a through-via electrode integrally penetrating the plurality of base insulating layers of the base build-up insulating layer. That is, the through-via electrode is provided integrally penetrating the plurality of base insulating layers, thereby removing a wiring layer such as a pad portion provided at an interface between the plurality of base insulating layers. Through this, the embodiment can remove a wiring layer disposed between the plurality of base insulating layers, thereby reducing a signal transmission distance and further improving signal transmission characteristics.

[0022] Through this, the embodiment can further improve the electrical and / or physical reliability of the circuit board. Furthermore, the embodiment can ensure the stable operation of electronic components placed on the circuit board, thereby further improving product reliability. Furthermore, the embodiment can improve the operating characteristics of products, such as servers, to which the semiconductor package is applied.

[0023] Furthermore, the embodiment provides a through via electrode that integrally penetrates multiple base insulating layers, thereby simplifying the process of manufacturing a circuit board and further improving product yield.

[0024] At this time, the through-via electrode may be provided with a plurality of parts. For example, the through-via electrode may include a first part having a narrow width in the horizontal direction, a second part having a wide width in the horizontal direction, and a protrusion positioned in a region between the first part and the second part. Through this, the embodiment may have the function of improving the physical reliability and / or electrical reliability of the circuit board by providing the protrusion in the through-via electrode.

[0025] For example, the protrusion of the through-via electrode can increase the width of the through-via electrode in the horizontal direction between the first portion and the second portion of the through-via electrode. Through this, the embodiment can reduce the difference between the horizontal width of the upper or lower surface of the through-via electrode and the horizontal width in the area between the upper and lower surfaces of the through-via electrode. Through this, the embodiment can minimize signal transmission loss that occurs as the difference between the maximum and minimum widths of the through-via electrode increases. Therefore, the embodiment can improve the electrical reliability of the circuit board.

[0026] Additionally, the protrusion of the through-via electrode can serve as an anchor function to improve the adhesion between the through-via electrode and the underlying build-up insulating layer. In particular, the embodiment can use the protrusion to firmly anchor the through-via electrode within the underlying build-up insulating layer. Therefore, the embodiment can improve the physical reliability of the circuit board.

[0027] In addition, the embodiment may provide a through-via electrode having a protrusion, so that, in a process of forming the through-via electrode, a region of the through-hole corresponding to the protrusion may function as a plating bridge. Through this, the embodiment may enable the interior of the through-hole penetrating the base build-up insulating layer to be densely filled with a conductive material, thereby improving the electrical reliability and / or physical reliability of the through-via electrode.

[0028] Additionally, the horizontal central axis of the first portion of the through-via electrode and the horizontal central axis of the second portion may be misaligned with each other. For example, the embodiment can control the direction in which the horizontal central axis of the first portion of the through-via electrode and the horizontal central axis of the second portion are misaligned with each other based on the bending state of the circuit board.

[0029] Through this, the embodiment can prevent the circuit board from bending in a specific direction, avoid excessive stress applied to the circuit board, and thereby improve the mechanical reliability and / or electrical reliability of the circuit board. In addition, the embodiment can alleviate the bending of the circuit board, thereby allowing the semiconductor device to be stably attached to the circuit board. Therefore, the embodiment can enable the semiconductor device to operate stably, thereby improving product reliability. Furthermore, the embodiment can enable the stable operation of products such as servers to which the semiconductor package is applied.

[0030] In addition, the embodiment may allow the vertical thickness of the first portion of the through-via electrode to be different from the vertical thickness of the second portion. Through this, the embodiment may further improve the degree of design freedom. Furthermore, the embodiment may allow the vertical thickness of the first portion of the through-via electrode to be different from the vertical thickness of the second portion, taking into account the direction in which the circuit board is bent, thereby further alleviating the overall warpage of the circuit board.

[0031] Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0032] Figure 2 is an enlarged cross-sectional view of the through via electrode of Figure 1.

[0033] Figure 3 is a perspective view illustrating the through via electrode of Figure 2 in three dimensions.

[0034] FIG. 4 is an enlarged cross-sectional view of the through via electrode of FIG. 1 according to the second embodiment.

[0035] FIG. 5 is an enlarged cross-sectional view of the through via electrode of FIG. 1 according to the third embodiment.

[0036] FIG. 6 is an enlarged cross-sectional view of the through via electrode of FIG. 1 according to the fourth embodiment.

[0037] FIG. 7 is an enlarged cross-sectional view of the through via electrode of FIG. 1 according to the fifth embodiment.

[0038] FIG. 8 is an enlarged cross-sectional view of the through via electrode of FIG. 1 according to the sixth embodiment.

[0039] FIG. 9 is a cross-sectional view illustrating a semiconductor package according to the first embodiment.

[0040] Fig. 10 is a cross-sectional view illustrating a semiconductor package according to the second embodiment.

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0042] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0043] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0044] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0045] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0046] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0047] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0049]

[0050] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0051]

[0052] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0053] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor element, a bonding member for electrically connecting the semiconductor element and the circuit board, a resin portion that fills the space between the semiconductor element and the circuit board, and a molding portion that entirely encloses the semiconductor element.

[0054] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0055] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0056]

[0057] FIG. 1 is a cross-sectional view illustrating a circuit board according to a first embodiment, FIG. 2 is an enlarged cross-sectional view of a through-via electrode of FIG. 1, FIG. 3 is a three-dimensional perspective view of a through-via electrode of FIG. 2, FIG. 4 is an enlarged cross-sectional view of a through-via electrode of FIG. 1 according to a second embodiment, FIG. 5 is an enlarged cross-sectional view of a through-via electrode of FIG. 1 according to a third embodiment, FIG. 6 is an enlarged cross-sectional view of a through-via electrode of FIG. 1 according to a fourth embodiment, FIG. 7 is an enlarged cross-sectional view of a through-via electrode of FIG. 1 according to a fifth embodiment, FIG. 8 is an enlarged cross-sectional view of a through-via electrode of FIG. 1 according to a sixth embodiment, FIG. 9 is a cross-sectional view illustrating a semiconductor package according to the first embodiment, and FIG. 10 is a cross-sectional view illustrating a semiconductor package according to the second embodiment.

[0058] Referring to FIG. 1, the circuit board (100) includes a build-up insulating structure (110), a wiring structure (120, 130), a via structure (140, 150, 160), a lower protective layer (170), and an upper protective layer (180).

[0059] The build-up insulating structure (110) includes a plurality of insulating layers stacked along the vertical direction.

[0060] The build-up insulation structure (110) includes a base build-up insulation layer (110-1), a lower build-up insulation layer (110-2), and an upper build-up insulation layer (110-3). The lower build-up insulation layer (110-2) may be disposed on the lower surface of the base build-up insulation layer (110-1), and the upper build-up insulation layer (110-3) may be disposed on the upper surface of the base build-up insulation layer (110-1). Here, the meaning of being disposed on the upper surface and the lower surface is not limited to a configuration in direct contact with the upper surface and the lower surface, but should also be understood to mean that there are other configurations between the upper surface of the base build-up insulation layer (110-1) and the upper build-up insulation layer (110-3), and between the lower surface of the base build-up insulation layer (110-1) and the lower build-up insulation layer (110-2).

[0061] At this time, the base build-up insulation layer (110-1), the lower build-up insulation layer (110-2), and the upper build-up insulation layer (110-3) of the build-up insulation structure (110) can be distinguished by the via structure (140, 150, 160) described later.

[0062] For example, the base build-up insulating layer (110-1), the lower build-up insulating layer (110-2), and the upper build-up insulating layer (110-3) of the build-up insulating structure (110) may be distinguished by their shapes in the vertical cross-section of the via structures (140, 150, 160) and / or the slopes of the sides. For example, the base build-up insulating layer (110-1) may have a via electrode that includes a first slope in which the width in the horizontal direction increases along a vertical direction toward the upper build-up insulating layer (110-3) (e.g., a direction from the lower surface to the upper surface of the build-up insulating structure (110)) and a second slope in which the width in the horizontal direction decreases. In addition, the lower build-up insulating layer (110-2) may have a via electrode that is configured with a first slope in which the width in the horizontal direction decreases along a vertical direction toward the base build-up insulating layer (110-1). In addition, a via electrode configured with a second slope whose width decreases in the horizontal direction along the vertical direction toward the base build-up insulating layer (110-1) may be arranged on the upper build-up insulating layer (110-3). Accordingly, the build-up insulating structure (110), the upper build-up insulating layer (110-3), and the lower build-up insulating layer (110-2) may be distinguished based on the difference in the shape of the above-described via structure (140, 150, 160) and / or the slope of the side surface.

[0063] The base build-up insulating layer (110-1) includes a plurality of base insulating layers (111, 112). For example, the base build-up insulating layer (110-1) includes a first base insulating layer (111) and a second base insulating layer (112) disposed on the first base insulating layer (111). The base build-up insulating layer (110-1) may refer to an insulating layer that is sequentially laminated on a carrier member (not shown) while the carrier member is disposed during a process of manufacturing a circuit board (100).

[0064] The base build-up insulating layer (110-1) is provided as an insulating layer in the vertical direction of the circuit structure including the wiring structure (120, 130) and the via structure (140, 150, 160). At this time, the first base insulating layer (111) and the second base insulating layer (112) of the base build-up insulating layer (110-1) may each use a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and the first base insulating layer (111) and the second base insulating layer (112) of the base build-up insulating layer (110-1) may use a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern.

[0065] Additionally, at least one of the first base insulation layer (111) and the second base insulation layer (112) of the base build-up insulation layer (110-1) may include a reinforcing member (not shown). In one embodiment, the reinforcing member may mean glass fiber, and in another embodiment, it may mean GCP (Glass Core Primer).

[0066] A lower build-up insulation layer (110-2) is arranged on the lower surface of the base build-up insulation layer (110-1). The lower build-up insulation layer (110-2) includes a plurality of lower insulation layers (113, 114, 115) laminated along a vertical direction on the lower surface of the base build-up insulation layer (110-1).

[0067] For example, the lower build-up insulation layer (110-2) may include a first lower insulation layer (113) positioned closest to the base build-up insulation layer (110-1), a second lower insulation layer (114) positioned further away from the base build-up insulation layer (110-1) than the first lower insulation layer (113), and a third lower insulation layer (115) positioned further away from the base build-up insulation layer (110-1) than the second lower insulation layer (114).

[0068] The first to third lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2) may be formed using a thermosetting insulating material containing an inorganic filler, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and the first to third lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2) may be formed using a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern. In addition, at least one of the first to third lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2) may include a reinforcing member including glass fiber and / or GCP.

[0069] An upper build-up insulation layer (110-3) is arranged on the upper surface of the base build-up insulation layer (110-1). The upper build-up insulation layer (110-3) includes a plurality of upper insulation layers (116, 117, 118) laminated along a vertical direction on the upper surface of the base build-up insulation layer (110-1).

[0070] For example, the upper build-up insulation layer (110-3) may include a first upper insulation layer (116) positioned closest to the base build-up insulation layer (110-1), a second upper insulation layer (117) positioned further away from the base build-up insulation layer (110-1) than the first upper insulation layer (116), and a third upper insulation layer (118) positioned further away from the base build-up insulation layer (110-1) than the second upper insulation layer (117).

[0071] The first to third upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3) may be formed of a thermosetting insulating material containing an inorganic filler, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and the first to third upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3) may be formed of a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern. In addition, at least one of the first to third upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3) may include a reinforcing member including glass fiber and / or GCP.

[0072] Wiring structures (120, 130) and via structures (140, 150, 160) are arranged on the base build-up insulating layer (110-1), the upper build-up insulating layer (110-3), and the lower build-up insulating layer (110-2).

[0073] For example, a first wiring layer (120) may be arranged on the lower surface of the base build-up insulating layer (110-1) and the lower surface of each of the first to third lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2).

[0074] The first wiring layer (120) may include a first-first wiring layer (121) disposed on the lower surface of the base build-up insulating layer (110-1) and closest to the base build-up insulating layer (110-1), a first-second wiring layer (122) disposed on the lower surface of the first lower insulating layer (113) and further away from the base build-up insulating layer (110-1) than the first-first wiring layer (121), a first-third wiring layer (123) disposed on the lower surface of the second lower insulating layer (114) and further away from the base build-up insulating layer (110-1) than the first-second wiring layer (122), and a first-fourth wiring layer (124) disposed on the lower surface of the third lower insulating layer (115) and further away from the base build-up insulating layer (110-1) than the first-third wiring layer (123).

[0075] The first wiring layer (120) including the first to fourth wiring layers (121, 122, 123, 124) can function to electrically connect to a semiconductor element placed on a circuit board (100). Each of the first wiring layers (120) including the first to fourth wiring layers (121, 122, 123, 124) can be freely designed in consideration of impedance.

[0076] Additionally, a second wiring layer (130) may be arranged on the upper surface of the base build-up insulating layer (110-1) and the upper surface of each of the first to third upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3).

[0077] The second wiring layer (130) may include a 2-1 wiring layer (131) disposed on the upper surface of the base build-up insulating layer (110-1) and most adjacent to the base build-up insulating layer (110-1), a 2-2 wiring layer (132) disposed on the upper surface of the first upper insulating layer (116) and further away from the base build-up insulating layer (110-1) than the 2-1 wiring layer (131), a 2-3 wiring layer (133) disposed on the upper surface of the second upper insulating layer (117) and further away from the base build-up insulating layer (110-1) than the 2-2 wiring layer (132), and a 2-4 wiring layer (134) disposed on the upper surface of the third upper insulating layer (118) and further away from the base build-up insulating layer (110-1) than the 2-3 wiring layer (133).

[0078] The second wiring layer (130) including the 2-1 to 2-4 wiring layers (131, 132, 133, 134) can function to electrically connect with a semiconductor element placed on a circuit board (100). Each of the second wiring layers (130) including the 2-1 to 2-4 wiring layers (131, 132, 133, 134) can be freely designed in consideration of impedance.

[0079] The via structure (140, 150, 160) includes a first via electrode (140) penetrating at least a portion of a plurality of lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2), a second via electrode (150) penetrating at least a portion of a plurality of upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3), and a through via electrode (160) penetrating at least a portion of a plurality of base insulating layers (111, 112) of the base build-up insulating layer (110-1).

[0080] Specifically, the first via electrode (140) may be provided to electrically connect the first wiring layers (120) arranged in different layers.

[0081] For example, the first via electrode (140) includes a first via electrode (141) that is disposed between the first-first wiring layer (121) and the first-second wiring layer (122) and penetrates at least a portion of the first lower insulating layer (113) along the vertical direction. In addition, the first via electrode (140) includes a first-second via electrode (142) that is disposed between the first-second wiring layer (122) and the first-third wiring layer (123) and penetrates at least a portion of the second lower insulating layer (114) along the vertical direction. In addition, the first via electrode (140) includes a first-third via electrode (143) that is disposed between the first-third wiring layer (123) and the first-fourth wiring layer (124) and penetrates at least a portion of the third lower insulating layer (115) along the vertical direction.

[0082] The first via electrode (140) including the first to third via electrodes (141, 142, 143) is a blind via formed in a state where one side is blocked, and thus may have a slope in one direction. The first via electrode (140) including the first to third via electrodes (141, 142, 143) is formed by filling a via hole formed in a state where the base build-up insulating layer (110-1) is arranged with a conductive material, and thus may have a slope in which the width in the horizontal direction decreases along the direction from the lower build-up insulating layer (110-2) toward the base build-up insulating layer (110-1).

[0083] Furthermore, the first to third via electrodes (141, 142, 143) are formed in a state where the first wiring layer (120) is arranged on the lower build-up insulating layer (110-2). Accordingly, the first via electrode (140) including the first to third via electrodes (141, 142, 143) can be arranged to penetrate a portion of the plurality of lower insulating layers (113, 114, 115) of the lower build-up insulating layer (110-2) along the vertical direction.

[0084] The second via electrode (150) includes a second-first via electrode (151) that is disposed between the second-first wiring layer (131) and the second-second wiring layer (132) and penetrates at least a portion of the first upper insulating layer (116) along the vertical direction. In addition, the second via electrode (150) includes a second-second via electrode (152) that is disposed between the second-second wiring layer (132) and the second-third wiring layer (123) and penetrates at least a portion of the second upper insulating layer (117) along the vertical direction. In addition, the second via electrode (150) includes a second-third via electrode (153) that is disposed between the second-third wiring layer (133) and the second-fourth wiring layer (134) and penetrates at least a portion of the third upper insulating layer (118) along the vertical direction.

[0085] The second via electrode (150) including the 2-1 to 2-3 via electrodes (151, 152, 153) is a blind via formed in a state where one side is blocked, and thus may have a slope in one direction. The second via electrode (150) including the 2-1 to 2-3 via electrodes (151, 152, 153) is formed by filling a via hole formed in a state where the base build-up insulating layer (110-1) is arranged with a conductive material, and thus may have a slope in which the width in the horizontal direction decreases along the direction from the upper build-up insulating layer (110-3) toward the base build-up insulating layer (110-1).

[0086] Furthermore, the second via electrode (150) including the 2-1 to 2-3 via electrodes (151, 152, 153) is formed in a state in which the second wiring layer (130) is arranged on the upper build-up insulating layer (110-3). Accordingly, the second via electrode (150) including the 2-1 to 2-3 via electrodes (151, 152, 153) can be arranged to penetrate a portion of the plurality of upper insulating layers (116, 117, 118) of the upper build-up insulating layer (110-3) along the vertical direction.

[0087] At this time, the first via electrode (140) and the second via electrode (150) are formed in different directions with respect to the base build-up insulating layer (110-1), and thus may have different inclinations. For example, the inclinations of the first via electrode (140) and the second via electrode (150) may be different, and for example, may have inclinations that are inclined in opposite directions.

[0088] The through-via electrode (160) is disposed between the first wiring layer (120) and the second wiring layer (130). That is, the through-via electrode (160) is disposed between the 1-1 wiring layer (121) and the 2-1 wiring layer (131) that are closest to the base build-up insulating layer (110-1) in each of the first wiring layer (120) and the second wiring layer (130).

[0089] The through-via electrode (160) may have a shape different from the shape of the first via electrode (140) and the shape of the second via electrode (150). That is, the first via electrode (140) and the second via electrode (150) are disposed within a blind via hole that partially penetrates the insulating layer along the vertical direction. In contrast, the through-via electrode (160) is disposed within a through hole that entirely penetrates the plurality of base insulating layers (111, 112) along the vertical direction. Furthermore, the above-described through holes are formed respectively at the upper and lower sides of the base build-up insulating layer (110-1), and accordingly, the inner wall of the through hole may have a plurality of slopes that are inclined in different directions. Accordingly, the through-via electrode (160) may have a plurality of slopes that are inclined in different directions.

[0090] At this time, the through-via electrode (160) penetrates the upper surface of the base build-up insulating layer (110-1) and the lower surface of the base build-up insulating layer (110-1) along the vertical direction. For example, the through-via electrode (160) integrally penetrates the first base insulating layer (111) and the second base insulating layer (112) of the base build-up insulating layer (110-1).

[0091] That is, the circuit board according to the prior art has a structure in which a blind base via electrode is formed on each base insulating layer, and accordingly, a base wiring layer is arranged between a plurality of blind base via electrodes. Accordingly, according to the prior art, a process of forming a blind base via electrode on each base insulating layer and a process of forming a base wiring layer connecting the blind base via electrodes must be performed, and there is a problem in that the manufacturing process becomes complicated.

[0092] Furthermore, the blind base via electrode and the base wiring layer function to electrically connect between the first wiring layer (120), the second wiring layer (130), the first via electrode (140), and the second via electrode (150). Accordingly, the structure has only the pads of the wiring layer connected to the blind base via electrodes between the plurality of base insulating layers. Accordingly, since the structure in the related art has the base wiring layer arranged between the blind base via electrodes, signals are transmitted through a path including the base wiring layer. Due to this, there is a problem in the related art that the signal transmission distance increases, and thus signal transmission loss increases. In particular, in a circuit board that transmits a signal in a high-frequency band, a skin effect occurs in which a signal is transmitted along the surface of the wiring layer. Accordingly, in the related art, there is a problem that signals are transmitted along a path including the surface of the base wiring layer, and thus signal loss increases.

[0093] Accordingly, the embodiment provides a through via electrode (160) that integrally penetrates a base build-up insulating layer (110-1) including a first base insulating layer (111) and a second base insulating layer (112) along a vertical direction. Accordingly, the embodiment can eliminate a wiring layer disposed between the first base insulating layer (111) and the second base insulating layer (112), thereby reducing a signal transmission distance and further improving signal transmission characteristics.

[0094] Through this, the embodiment can further improve the electrical and / or physical reliability of the circuit board. Furthermore, the embodiment can ensure the stable operation of electronic components placed on the circuit board, thereby further improving product reliability. Furthermore, the embodiment can improve the operating characteristics of products, such as servers, to which the semiconductor package is applied.

[0095] Furthermore, the embodiment provides a through via electrode (160) that integrally penetrates the first base insulating layer (111) and the second base insulating layer (112), thereby simplifying the process of manufacturing a circuit board and further improving the product yield.

[0096] A lower protective layer (170) is disposed on the lower surface of the lower build-up insulating layer (110-2). In addition, an upper protective layer (180) is disposed on the upper surface of the upper build-up insulating layer (110-3). The lower protective layer (170) and the upper protective layer (180) can protect the build-up insulating structure (110) and the wiring structure (120, 130) from external moisture or contaminants. Preferably, the lower protective layer (170) can protect the first wiring layer (120), and the upper protective layer (180) can protect the second wiring layer (130). In addition, when a semiconductor element is bonded to a circuit board (100) with a material such as solder, the lower protective layer (170) and the upper protective layer (180) function to prevent short circuits between solders due to low wettability with the solder. The lower protective layer (170) and the upper protective layer (180) may be formed of a photocurable insulating material, and for example, a solder resist may be used.

[0097] Below, the through via electrode (160) according to the embodiment is described in more detail.

[0098] Referring to FIG. 2, the through-via electrode (160) penetrates the upper and lower surfaces of the base build-up insulating layer (110-1). A plurality of through-via electrodes (160) may be provided in the base build-up insulating layer (110-1) and are spaced apart from each other in the horizontal direction.

[0099] The through-via electrode (160) integrally penetrates the first base insulating layer (111) and the second base insulating layer (112) of the base build-up insulating layer (110-1). Accordingly, the through-via electrode (160) does not overlap with the wiring structures (120, 130) provided on the circuit board (100) in the horizontal direction. For example, the circuit board (100) is not provided with a wiring layer, such as a pad portion and a trace, that overlaps the through-via electrode (160) in the horizontal direction. For example, only the through-via electrode (160) is provided in the base build-up insulating layer (110-1), and no wiring layer is formed.

[0100] The through-via electrode (160) may include a first portion (161) whose width in the horizontal direction becomes narrower as it moves from the first wiring layer (120) to the second wiring layer (130). For example, the first portion (161) of the through-via electrode (160) may have a slope such that the width in the horizontal direction gradually decreases as it moves from the first wiring layer (120) to the second wiring layer (130). For example, the first portion (161) of the through-via electrode (160) may have a slope corresponding to the slope of the first via electrode (140). In particular, the side surface of the first portion (161) of the through-via electrode (160) may be inclined in the same direction as the side surface of the first via electrode (140) is inclined.

[0101] The first portion (161) of the through-via electrode (160) may be disposed within the first base insulating layer (111) of the base build-up insulating layer (110-1). Preferably, the first portion (161) of the through-via electrode (160) may penetrate at least a portion of the first base insulating layer (111) from the lower surface of the first base insulating layer (111) of the base build-up insulating layer (110-1) toward the upper surface of the first base insulating layer (111).

[0102] The through-via electrode (160) may include a second portion (162) disposed on the first portion (161). At this time, the slope of the second portion (162) of the through-via electrode (160) may be different from the slope of the first portion (161). For example, the through-via electrode (160) may include a second portion (162) whose width in the horizontal direction increases as it moves from the first wiring layer (120) to the second wiring layer (130). For example, the second portion (162) of the through-via electrode (160) may have a slope in which the width in the horizontal direction gradually increases as it moves from the first wiring layer (120) to the second wiring layer (130). For example, the second portion (162) of the through-via electrode (160) may have a slope corresponding to the slope of the second via electrode (150). In particular, the side surface of the second portion (162) of the through via electrode (160) can be inclined in the same direction as the side surface of the second via electrode (150).

[0103] The second portion (162) of the through-via electrode (160) may be disposed within the second base insulating layer (112) of the base build-up insulating layer (110-1). Preferably, the second portion (162) of the through-via electrode (160) may penetrate at least a portion of the second base insulating layer (112) from the upper surface of the second base insulating layer (112) of the base build-up insulating layer (110-1) toward the lower surface of the second base insulating layer (112).

[0104] The through-via electrode (160) may include a protrusion (163) arranged in a region between the first portion (161) and the second portion (162). For example, the protrusion (163) of the through-via electrode (160) may be provided so as to protrude along a horizontal direction toward the outside of the through-via electrode (160). At this time, referring to FIG. 3, the protrusion (163) of the through-via electrode (160) may be provided along the circumferential direction of the through-via electrode (160) in a region between the first portion (161) and the second portion (162) of the through-via electrode (160). For example, the protrusion (163) of the through-via electrode (160) may be provided along the circumferential direction of the upper surface of the first portion (161) or the circumferential direction of the lower surface of the second portion (162) in the region between the first portion (161) and the second portion (162) of the through-via electrode (160).

[0105] The protrusion (163) of the through via electrode (160) may have the function of improving the physical reliability and / or electrical reliability of the circuit board (100).

[0106] For example, the protrusion (163) of the through-via electrode (160) can increase the width of the through-via electrode (160) in the horizontal direction between the first portion (161) and the second portion (162) of the through-via electrode (160). Through this, the embodiment can reduce the difference between the width of the upper or lower surface of the through-via electrode (160) in the horizontal direction and the width in the horizontal direction in the area between the upper and lower surfaces of the through-via electrode (160). For example, the embodiment can reduce the difference between the width of the area having the maximum width and the width of the area having the minimum width in the entire area of ​​the through-via electrode (160) in the vertical direction by providing the protrusion (163) between the first portion (161) and the second portion (162) of the through-via electrode (160). Through this, the embodiment can minimize signal transmission loss that occurs as the difference between the maximum width and the minimum width of the through-via electrode (160) increases. Therefore, the embodiment can improve the electrical reliability of the circuit board (100).

[0107] In addition, the protrusion (163) of the through-via electrode (160) is disposed between the first portion (161) and the second portion (162) of the through-via electrode (160), and may be provided particularly at an interface (110-1S) between a plurality of base insulating layers of the base build-up insulating layer (110-1). For example, the protrusion (163) of the through-via electrode (160) may protrude in a horizontal direction at the interface (110-1S) between the upper surface of the first base insulating layer (111) and the lower surface of the second base insulating layer (112). Through this, the protrusion (163) may increase the width of the through-via electrode (160) at the interface (110-1S) of the base build-up insulating layer (110-1). At this time, the protrusion (163) can serve as an anchor function to improve the adhesion between the through-via electrode (160) and the base build-up insulating layer (110-1). In particular, the embodiment provides the protrusion (163) at the interface (110-1S) between the upper surface of the first base insulating layer (111) of the base build-up insulating layer (110-1) and the lower surface of the second base insulating layer (112), and thereby, the through-via electrode (160) can be firmly fixed within the base build-up insulating layer (110-1) by using the protrusion (163). Therefore, the embodiment can improve the physical reliability of the circuit board (100).

[0108] In addition, the embodiment can improve the filling property in the process of filling the interior of the through hole penetrating the first base insulating layer (111) and the second base insulating layer (112) of the base build-up insulating layer (110-1) with a conductive material.

[0109] For example, when the through-via electrode (160) does not have the protrusion (163), the through-via electrode (160) may have an hourglass shape based on the vertical cross-section. That is, the hourglass shape may mean a shape in which the width increases horizontally toward each of the upper and lower surfaces of the through-via electrode based on the midpoint between the upper and lower surfaces of the through-via electrode. In this case, when the through-hole having the above-described hourglass shape is filled with a conductive material, it may be difficult to provide a uniform plating current to the above-described midpoint having a relatively small width, and thus, an empty space such as a void may be formed in the through-via electrode. In addition, the above-described empty space may act as a factor that lowers the physical reliability and / or electrical reliability of the circuit board.

[0110] At this time, the embodiment is such that the through-via electrode (160) has a protrusion (163). Specifically, the through-hole penetrating the base build-up insulating layer (110-1) of the embodiment may have a vertical cross-sectional shape corresponding to the vertical cross-sectional shape of the through-via electrode (160). For example, the through-hole may have a protrusion area corresponding to the protrusion area (163). In addition, the above-described protrusion area may function to provide a uniform plating current in the process of filling the above-described through-hole with a conductive material. For example, the protrusion area may reduce the difference in width between the upper and lower regions of the through-hole and may serve as a plating bridge connecting them in the plating process. Through this, the embodiment may allow the interior of the through-hole penetrating the base build-up insulating layer (110-1) to be densely filled with a conductive material, thereby improving the electrical reliability and / or physical reliability of the through-via electrode (160).

[0111] Furthermore, the through via electrode (160) may have a width that varies in the horizontal direction along the vertical direction.

[0112] For example, the through-via electrode (160) may have a first width (W1) in the horizontal direction at the protrusion (163). In addition, the through-via electrode (160) may have a second width (W2) in the horizontal direction at the lower surface of the first portion (161). In addition, the through-via electrode (160) may have a third width (W3) in the horizontal direction at the upper surface of the second portion (162).

[0113] At this time, the first width (W1) may be different from the second width (W2) or the third width (W3). For example, the first width (W1) may be larger than the second width (W2) or the third width (W3). Through this, the embodiment can maximize the effect exhibited by the protrusion (163).

[0114] Here, the difference between the first width (W1) and the second width (W2) or the third width (W3) can be controlled. For example, the embodiment can control the difference between the first width (W1) and the second width (W2) or the difference between the first width (W1) and the third width (W3).

[0115] Specifically, the first wiring layer (120) may have a fourth width (W4) in the horizontal direction that is greater than each of the first width (W1), the second width (W2), and the third width (W3). In addition, the second wiring layer (130) may have a fifth width (W5) in the horizontal direction that is greater than each of the first width (W1), the second width (W2), and the third width (W3).

[0116] At this time, the difference between the first width (W1) and the second width (W2) or the difference between the first width (W1) and the third width (W3) may be smaller than the difference between the fourth width (W4) and the second width (W2) of the first wiring layer (120). Alternatively, the difference between the first width (W1) and the second width (W2) or the difference between the first width (W1) and the third width (W3) may be smaller than the difference between the fifth width (W5) and the third width (W3) of the second wiring layer (130). Alternatively, the first width (W1) may be smaller than the fourth width (W4) and the fifth width (W5).

[0117] Through this, the embodiment can minimize signal transmission loss due to an increase in signal transmission distance caused by the through via electrode (160) having a protrusion (163), thereby further improving the electrical characteristics of the circuit board and semiconductor package.

[0118] At this time, the horizontal central axis of the first part (161) of the through-via electrode (160) according to the embodiments of FIGS. 1 to 3 and the horizontal central axis of the second part (162) of the through-via electrode (160) can be aligned.

[0119] In contrast, according to the embodiment of FIG. 4, the through via electrode (160A) may include a first portion (161A), a second portion (162A), and a protrusion (163A).

[0120] At this time, the horizontal central axis (x1) of the first part (161A) of the through-via electrode (160A) and the horizontal central axis (x2) of the second part (162A) of the through-via electrode (160A) may be misaligned. At this time, when the upper and lower surfaces of the through-via electrode (160A) each have a circular or elliptical shape, the above-described central axes (x1, x2) may mean the intersection point where the major and minor axes of the upper and lower surfaces of the through-via electrode (160A) meet. In addition, when the upper and lower surfaces of the through-via electrode (160A) each have a square shape, the above-described central axes (x1, x2) may mean the intersection point where the opposing vertices of the upper and lower surfaces of the through-via electrode (160A) meet.

[0121] The horizontal central axis (x1) of the first portion (161A) of the through-via electrode (160A) and the horizontal central axis (x2) of the second portion (162A) of the through-via electrode (160A) are misaligned with each other, and for example, as shown in FIG. 4, the central axis (x2) of the second portion (162A) may have a first misalignment state in which the central axis (x1) of the first portion (161A) is misaligned to the left.

[0122] Additionally, according to the embodiment of FIG. 5, the through via electrode (160B) may include a first portion (161B), a second portion (162B), and a protrusion (163B).

[0123] At this time, the horizontal central axis (x1) of the first part (161B) of the through-via electrode (160B) and the horizontal central axis (x2) of the second part (162B) of the through-via electrode (160B) may be misaligned. For example, the horizontal central axis (x1) of the first part (161B) of the through-via electrode (160B) and the horizontal central axis (x2) of the second part (162B) of the through-via electrode (160B) may be misaligned with each other, and for example, as shown in FIG. 5, the second misalignment state may be present in which the central axis (x2) of the second part (162A) is misaligned to the right with respect to the central axis (x1) of the first part (161B).

[0124] At this time, the embodiment can provide a circuit board (100) including a through-via electrode (160A) having a first misalignment state of FIG. 4 or a through-via electrode (160B) having a second misalignment state of FIG. 5 based on a bending state of the circuit board.

[0125] For example, circuit boards may warp in certain directions due to thermal stresses caused by various factors during the manufacturing process and / or during operation. For example, the circuit board may have a concave warpage (∪) corresponding to a smiling state or a convex warpage (∩) corresponding to a crying state. In addition, the embodiment may include a through-via electrode (160A) having a first misalignment state of FIG. 4 or a through-via electrode (160B) having a second misalignment state of FIG. 5 on the circuit board (100) based on whether the circuit board (100) is in a concave warpage (∪) state or a convex warpage (∩) state. Through this, the embodiment may prevent the circuit board (100) from being bent in a specific direction, avoid excessive stress applied to the circuit board, and improve mechanical reliability and / or electrical reliability of the circuit board accordingly. In addition, the embodiment may alleviate the bending of the circuit board so that a semiconductor device can be stably attached on the circuit board. At this time, when the circuit board is bent in a specific direction, a height deviation between a plurality of bonding portions provided on the circuit board may occur, and a plurality of The terminal of the semiconductor element may not be stably bonded on the bonding portion. In contrast, the embodiment can alleviate the overall warpage of the circuit board by using the through-via electrode (160A) having the first misalignment state of FIG. 4 or the through-via electrode (160B) having the second misalignment state of FIG. 5 described above, and can enable the semiconductor element to be stably attached on the circuit board. Therefore, the embodiment can enable the semiconductor element to operate stably, thereby improving product reliability. Furthermore, the embodiment can enable the stable operation of products such as servers to which the semiconductor package is applied.

[0126] Also, referring to FIG. 6, the circuit board (100) may include a plurality of through via electrodes (160, 160A, 160B) having different misalignment states.

[0127] For example, a plurality of through via electrodes (160, 160A, 160B) spaced apart from each other in the horizontal direction may be provided within the base build-up insulating layer (110-1).

[0128] At this time, the plurality of through-via electrodes (160, 160A, 160B) may include a first through-via electrode (160), a second through-via electrode (160A), and a third through-via electrode (160B).

[0129] Specifically, the plurality of through via electrodes (160, 160A, 160B) may have different misalignment states depending on their respective placement positions.

[0130] For example, the first through-via electrode (160) may be a through-via electrode that is closest to the horizontal central axis of the base build-up insulating layer (110-1) among the plurality of through-via electrodes (160, 160A, 160B). In addition, the second through-via electrode (160A) may be a through-via electrode that is located further to the left from the horizontal central axis of the base build-up insulating layer (110-1) than the first through-via electrode (160). In addition, the second through-via electrode (160B) may be a through-via electrode that is located further to the right from the horizontal central axis of the base build-up insulating layer (110-1) than the first through-via electrode (160).

[0131] Accordingly, the first through-via electrode (160) may have a structure in which the horizontal central axis of the first portion (161) illustrated in FIGS. 1 to 3 and the horizontal central axis of the second portion (162) are aligned with each other. In addition, the second through-via electrode (160A) may have a structure in which the horizontal central axis of the first portion (161A) illustrated in FIG. 4 and the horizontal central axis of the second portion (162A) are misaligned in a first misalignment state. In addition, the third through-via electrode (160B) may have a structure in which the horizontal central axis of the second portion (161B) illustrated in FIG. 5 and the horizontal central axis of the second portion (162B) are misaligned in a second misalignment state.

[0132] Through this, the embodiment can further alleviate overall warpage of the circuit board and enable more stable attachment of semiconductor devices on the circuit board. Therefore, the embodiment can ensure stable operation of the semiconductor devices, thereby improving product reliability. Furthermore, the embodiment can ensure stable operation of products such as servers to which the semiconductor package is applied.

[0133] At this time, the vertical thickness of the first part (161) of the through-via electrode (160) according to the embodiments of FIGS. 1 to 3 and the vertical thickness of the second part (162) of the through-via electrode (160) may be the same.

[0134] In contrast, according to the embodiment of FIG. 7, the through via electrode (160C) may include a first portion (161C), a second portion (162C), and a protrusion (163C). The first portion (161C) may penetrate at least a portion of the first base insulating layer (111) along the vertical direction. In addition, the second portion (162C) may penetrate at least a portion of the second base insulating layer (112) along the vertical direction. At this time, the thickness (T1) of the first base insulating layer (111) in the vertical direction and the thickness (T2) of the second base insulating layer (112) in the vertical direction may be different from each other. For example, the thickness (T1) of the first base insulating layer (111) in the vertical direction may be greater than the thickness (T2) of the second base insulating layer (112) in the vertical direction.

[0135] Accordingly, the vertical thickness (T3) of the first portion (161C) of the through-via electrode (160C) and the vertical thickness (T4) of the second portion (162C) of the through-via electrode (160C) may be different from each other. Preferably, the vertical thickness (T3) of the first portion (161C) of the through-via electrode (160C) may be greater than the vertical thickness (T4) of the second portion (162C) of the through-via electrode (160C).

[0136] Alternatively, according to the embodiment of FIG. 8, the through via electrode (160D) may include a first portion (161D), a second portion (162D), and a protrusion (163D). The first portion (161D) may penetrate at least a portion of the first base insulating layer (111) along the vertical direction. In addition, the second portion (162D) may penetrate at least a portion of the second base insulating layer (112) along the vertical direction. At this time, the thickness (T1) of the first base insulating layer (111) in the vertical direction and the thickness (T2) of the second base insulating layer (112) in the vertical direction may be different from each other. For example, the thickness (T1) of the first base insulating layer (111) in the vertical direction may be smaller than the thickness (T2) of the second base insulating layer (112) in the vertical direction.

[0137] Accordingly, the vertical thickness (T3) of the first portion (161D) of the through-via electrode (160D) and the vertical thickness (T4) of the second portion (162D) of the through-via electrode (160D) may be different from each other. Preferably, the vertical thickness (T3) of the first portion (161D) of the through-via electrode (160D) may be greater than the vertical thickness (T4) of the second portion (162D) of the through-via electrode (160D).

[0138] That is, the embodiment can make the vertical thickness of the first portion of the through-via electrode different from the vertical thickness of the second portion. Through this, the embodiment can further improve the degree of design freedom. Furthermore, the embodiment can make the vertical thickness of the first portion of the through-via electrode different from the vertical thickness of the second portion in consideration of the direction in which the circuit board is bent, thereby further alleviating the overall warpage of the circuit board.

[0139]

[0140] Also, referring to FIG. 9, a plurality of semiconductor elements may be arranged on the circuit board of the embodiment. For example, the semiconductor package according to the first embodiment may include a semiconductor element (220) arranged on the circuit board (100).

[0141] For this purpose, the circuit board may further include a bonding portion (190). The bonding portion (190) may be positioned within an opening of the upper protective layer and may protrude with a certain height above the upper surface of the upper protective layer.

[0142] A connection part (210) may be arranged on the bonding part (190). The connection part (210) may be a bonding member for mounting a semiconductor element (220) on a circuit board, and may be, for example, solder, but is not limited thereto.

[0143] The semiconductor element (220) may have a terminal (230), and the terminal (230) may be electrically connected to the circuit board (100) through a connection portion (210).

[0144]

[0145] Additionally, according to the embodiment of FIG. 10, the circuit board described above can be used as an interposer provided between the semiconductor package substrate and the semiconductor element of the semiconductor package.

[0146] A semiconductor package may include a circuit board (100), a semiconductor element (200), a first connection portion (210), a second connection portion (310), and a semiconductor package substrate (300).

[0147] The circuit board (100) may refer to the circuit board described in the previous embodiment, which may function as an interposer. Accordingly, the circuit board (100) will be described as an interposer (100).

[0148] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer and a semiconductor package board (300) and used. The circuit board described above may be used as a semiconductor package board, or alternatively, may be used as an interposer.

[0149] A semiconductor element (220) is arranged on the interposer (100). The semiconductor elements (220) may be provided in multiple numbers on the interposer (100) while being spaced apart from each other in the horizontal direction, but the present invention is not limited thereto. For example, the semiconductor elements (220) may be arranged to be stacked not only in the horizontal direction but also in the vertical direction on the interposer (100). A connecting member for electrically connecting the semiconductor elements (220) is arranged on the interposer (100).

[0150] A semiconductor package substrate (300) is placed on the lower surface of the interposer (100). The semiconductor package substrate (300) can electrically connect the main board of an electronic device and the interposer (100).

[0151] At this time, a second connection portion (310) may be placed between the interposer (100) and the semiconductor package substrate (300), through which the interposer (100) and the semiconductor package substrate (300) may be electrically coupled.

[0152]

[0153] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0154] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0155] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0156] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up insulation structure including a base build-up insulation layer including a plurality of base insulation layers, a lower build-up insulation layer disposed on a lower surface of the base build-up insulation layer and including a plurality of lower insulation layers, and an upper build-up insulation layer disposed on an upper surface of the base build-up insulation layer and including a plurality of upper insulation layers; A plurality of first wiring layers arranged on the lower surface of the base build-up insulating layer and the lower surface of each of the plurality of lower insulating layers; A plurality of second wiring layers arranged on the upper surface of the base build-up insulating layer and the lower surface of each of the plurality of upper insulating layers; A plurality of first via electrodes each disposed between the plurality of first wiring layers and penetrating at least a portion of the plurality of lower insulating layers along a vertical direction; A second via electrode disposed between the plurality of second wiring layers and penetrating at least a portion of the plurality of upper insulating layers along the vertical direction; Including a through via electrode penetrating the plurality of base insulating layers along the vertical direction, The above through via electrode is, A circuit board comprising a first portion having a width in a horizontal direction that becomes narrower as it moves from the first wiring layer toward the second wiring layer, a second portion having a width in the horizontal direction that becomes wider as it moves from the first wiring layer toward the second wiring layer, and a protrusion that protrudes in the horizontal direction in an area between the first portion and the second portion.

2. In paragraph 1, The lower surface of the first portion of the above-mentioned through via electrode is directly connected to the first wiring layer arranged on the lower surface of the base build-up insulating layer, A circuit board, wherein the upper surface of the second portion of the above-mentioned through via electrode is directly connected to the second wiring layer disposed on the upper surface of the base build-up insulating layer.

3. In paragraph 1, A circuit board, wherein the protrusion of the above through via electrode is disposed at the interface between the plurality of base insulating layers.

4. In paragraph 1, The first width in the horizontal direction of the through via electrode in the above protrusion is, A circuit board, wherein the second width in the horizontal direction of the through-via electrode on the lower surface of the first portion is different from the third width in the horizontal direction of the through-via electrode on the upper surface of the second portion.

5. In paragraph 4, A circuit board, wherein the difference value between the first width and the second width or the third width is smaller than the difference value between the horizontal width of the first wiring layer and the second width or the horizontal width of the second wiring layer and the third width.

6. In paragraph 4, A circuit board, wherein the first width in the horizontal direction of the through via electrode in the protrusion is smaller than the width in the horizontal direction of each of the plurality of first wiring layers or the width in the horizontal direction of each of the plurality of second wiring layers.

7. In paragraph 1, A circuit board, wherein each of the plurality of first via electrodes has a slope identical to the slope of the first portion of the through via electrode.

8. In paragraph 1, A circuit board, wherein each of the plurality of second via electrodes has the same slope as the slope of the second portion of the through via electrode.

9. In paragraph 1, A circuit board, wherein the horizontal central axis of the first portion of the through-via electrode is aligned with the horizontal central axis of the second portion of the through-via electrode.

10. In paragraph 1, A circuit board in which the horizontal central axis of the first portion of the through-via electrode is misaligned with the horizontal central axis of the second portion of the through-via electrode.

Images