Memory apparatus, memory system, memory controller, and operation method

Abstract

Disclosed in the embodiments of the present application are a memory apparatus, a memory system, a memory controller and an operation method. The memory apparatus comprises: a memory cell array, which comprises a plurality of memory blocks, wherein each memory block comprises a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, a plurality of memory cells coupled to the same word line form a physical page, and one physical page comprises one or more code words; and a peripheral circuit, which is coupled to the memory cell array and is configured to: acquire a predicted initial read voltage of a code word on the basis of the position of a word line, which is coupled to the code word, in a partially-filled memory block and the position of the first blank physical page in the partially-filled memory block, and obtain a target valley voltage of the code word on the basis of a first result corresponding to the code word under the predicted initial read voltage, wherein the first result comprises the number of flipped bits in the code word between two read results under a first read voltage and a second read voltage.

Description

Memory device, memory system, memory controller and operation method Technical Field

[0001] The present application relates to, but is not limited to, a memory device, a memory system, a memory system, and an operating method. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells can change due to factors such as age, repeated read operations, and cross-temperature fluctuations, thus affecting the accuracy of data reads.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, comprising: a memory cell array, comprising a plurality of memory blocks, the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, the plurality of memory cells coupled to the same word line forming a physical page, and a physical page comprising one or more code words; a peripheral circuit, coupled to the memory cell array and configured to: obtain a predicted initial read voltage of the code word based on a position of the word line to which the code word is coupled in an unfilled memory block and a position of a first blank physical page in the unfilled memory block; obtain a target valley voltage of the code word based on a first result corresponding to the code word at the predicted initial read voltage; the first result comprising a representation of the number of bits flipped in two read results of the code word at a first read voltage and a second read voltage, the difference between the first read voltage and the second read voltage being less than a preset voltage; and the target valley voltage being used as a read voltage for the code word when performing a read operation.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices described in any one of the first aspects; and a memory controller coupled to and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, wherein the memory device includes multiple memory blocks, the memory blocks include multiple word lines and multiple memory cells coupled to the multiple word lines, the multiple memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; the memory controller includes: a control unit, configured to: obtain a predicted initial read voltage of the code word based on a position of the word line coupled to the code word in an unfilled memory block and a position of the first blank physical page in the unfilled memory block; obtain a target valley voltage of the code word based on a first result corresponding to the code word under the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the code word under a first read voltage and a second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage for the code word when performing a read operation.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, wherein the memory device includes multiple memory blocks, the memory blocks include multiple word lines and multiple memory cells coupled to the multiple word lines, the multiple memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; the operating method includes: obtaining a predicted initial read voltage of the code word based on a position of the word line coupled to the code word in an unfilled memory block and a position of the first blank physical page in the unfilled memory block; obtaining a target valley voltage of the code word based on a first result corresponding to the code word under the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the code word under a first read voltage and a second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage for the code word when performing a read operation.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: a memory controller in the memory system sends a data acquisition instruction, wherein the data acquisition instruction indicates acquisition of a target valley voltage; a memory device in the memory system receives the data acquisition instruction, acquires the target valley voltage according to the operating method of the memory device described in the fourth aspect, and sends information including the target valley voltage to the memory controller; the memory controller performs a read operation on data stored in the memory device according to the target valley voltage in the information.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method for a memory controller, wherein the memory controller is coupled to at least one memory device, the memory device including multiple memory blocks, the memory blocks including multiple word lines and multiple memory cells coupled to the multiple word lines, the multiple memory cells coupled to the same word line forming a physical page, and a physical page including one or more code words; the operating method includes: obtaining a predicted initial read voltage of the code word based on a position of the word line coupled to the code word in an unfilled memory block and a position of the first blank physical page in the unfilled memory block; obtaining a target valley voltage of the code word based on a first result corresponding to the code word under the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the code word under a first read voltage and a second read voltage, the difference between the first read voltage and the second read voltage being less than a preset voltage; the target valley voltage is used as a read voltage for the code word when performing a read operation.

[0010] In the seventh aspect, an embodiment of the present application provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of any one of the operating methods provided in the fourth aspect, the fifth aspect, and the sixth aspect can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0012] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0013] FIG2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0014] FIG2B is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0016] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0019] FIG7 is a schematic diagram illustrating a flowchart of an implementation of an operation method performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0020] FIG8 is a schematic diagram of data state distribution of physical pages corresponding to each word line in an incomplete memory block according to an embodiment of the present application;

[0021] FIG9 is a schematic diagram of a threshold voltage distribution of a memory cell when obtaining a first result according to an embodiment of the present application;

[0022] FIG10A is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including two memory bits provided in one embodiment of the present application;

[0023] FIG10B is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0024] FIG10C is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0025] FIG11 is a flowchart of a method for operating a memory device according to an embodiment of the present application;

[0026] FIG12 is a second flowchart of a method for operating a memory device according to an embodiment of the present application;

[0027] FIG13 is a schematic diagram of an exemplary structure of a memory system provided in one embodiment of the present application;

[0028] FIG14 is a block diagram of a memory system provided by an embodiment of the present application;

[0029] FIG15 is a timing diagram of an exemplary start-up single-stage read mode operation provided by the present application;

[0030] FIG16 is a timing diagram of determining a target valley voltage and performing a read operation according to an embodiment of the present application;

[0031] FIG17 is a block diagram of a storage medium provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0032] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0033] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0034] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0035] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0038] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a control unit of an electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)). Host 108 can be configured to send data to or receive data from memory device 104.

[0039] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0040] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0041] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0042] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0043] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0044] In one example as shown in FIG2 a , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ).

[0045] In another example, as shown in FIG2 b , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0046] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each word line constitute a physical page.

[0047] FIG3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0048] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0049] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0050] As shown in FIG3 , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and an upper select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0051] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0052] 3 , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318 , and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding select transistor (eg, top select transistor (TSG) 312 ).

[0053] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0054] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0055] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0056] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] Referring back to FIG3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0058] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage obtained from the voltage generator 510.

[0059] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages obtained from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to obtain word line voltages (e.g., read voltages, program voltages, pass voltages, channel boosting voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0060] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0061] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient error correction algorithm is typically employed during data reading.

[0062] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error rate exceeds the error correction capability, data read failures can occur.

[0063] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0064] In some embodiments, a reread operation can typically be performed by querying a retry table (or trial and error table) provided by the manufacturer. The essence of the reread operation is an error correction mechanism. The reread table can provide a reference voltage for reading data. By querying the reread table, an attempt is made to read each storage cell again using a read voltage that deviates from the normal threshold voltage and perform error correction in conjunction with an error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the query to the reread table is stopped. If the read error data cannot be corrected, the reread table is continuously queried until the entire reread table is traversed.

[0065] The aforementioned reread operation method requires querying the reread table line by line, which inevitably increases the number of trial and error cycles and is time-consuming. Furthermore, the reread table provided by the manufacturer is only a reference value for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's reread table does not cover many scenarios. Consequently, even after traversing the reread table, data may not be corrected, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the reread table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0066] Based on one or more of the above problems, in a first aspect, embodiments of the present application provide a memory device.

[0067] As shown in FIG7 , the memory device includes: a memory cell array including a plurality of memory blocks, each memory block including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, wherein the plurality of memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; and a peripheral circuit coupled to the memory cell array and configured to perform the following steps:

[0068] Step S10: obtaining a predicted initial read voltage of the codeword according to a position of a word line coupled to the codeword in the unfilled memory block and a position of a first blank physical page in the unfilled memory block;

[0069] Step S20: Obtaining a target valley voltage for the codeword based on a first result corresponding to the codeword at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the codeword at the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage when performing a read operation on the codeword.

[0070] Here, the structure of the memory device is referred to above FIG3 and will not be described in detail here.

[0071] In some embodiments, a memory device includes a memory cell array, the memory cell array including multiple memory blocks, each memory block including multiple word lines and multiple memory cells coupled to each word line. All memory cells coupled to a word line form a physical page. A predetermined number of memory cells form a code word (CW). A physical page includes one or more code words.

[0072] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0073] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0074] Different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits. It is understood that a codeword may include multiple memory cells, and the number of memory cells included in a codeword may be adjusted based on actual conditions.

[0075] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0076] Here, an unfilled storage block (Open Block) includes a storage block having two data states, a programming state and an erased state. An unfilled storage block is activated or turned on for programming operations. In the embodiment of the present application, the storage block where the at least one codeword to be read is located is an unfilled storage block. The position of the word line coupled to the codeword in the unfilled storage block can be understood as the position of the word line coupled to the at least one codeword to be read among all the word lines of the unfilled storage block. The at least one codeword to be read is a storage unit in the unfilled storage block to which data has been written.

[0077] Here, the first blank physical page can be understood as the first physical page in the unfilled memory block whose data state is all in the erased state according to the programming order. The position of the first blank physical page in the unfilled memory block can be understood as the position of the word line coupled to the first blank physical page in the unfilled memory block (the word line coupled to the first blank physical page is called Open WL) of the word line coupled to at least one codeword to be read.

[0078] Here, the predicted initial read voltage is related to the position of the word line coupled to the codeword to be read in the unfilled memory block and the position of the first blank physical page in the unfilled memory block, and is specifically used to form the subsequent target valley voltage. Here, the target valley voltage is used as the read voltage when performing a read operation on the codeword. Compared to directly using the default read voltage (the default read voltage corresponds to an offset value of 0) to perform multiple loop iterations to obtain the target valley voltage, the predicted initial read voltage obtained after considering the aforementioned two positions can reduce the number of loop iterations, thereby obtaining the target valley voltage more quickly.

[0079] The following provides a specific implementation method for obtaining a predicted initial read voltage of a codeword based on the position of a word line coupled to the codeword in an unfilled memory block and the position of the first blank physical page in the unfilled memory block.

[0080] In some embodiments, the peripheral circuit is configured to: obtain an offset value corresponding to the predicted initial read voltage of the codeword based on a first offset value corresponding to a full storage block whose write time difference with the unfull storage block is less than a preset time length, a second offset value corresponding to the position of the word line coupled to the first blank physical page in all word lines of the unfull storage block, and a third offset value corresponding to the distance of the word line coupled to the codeword from the word line coupled to the first blank physical page in the unfull storage block; and obtain the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage.

[0081] Here, a full storage block (Close Block) is relative to an unfull storage block, and a full storage block includes a storage block whose data state is all in a programming state. A full storage block is closed to programming operations. The full storage block in the embodiment of the present application refers to a full storage block whose write time difference with the unfull storage block where the codeword to be read is located is less than a preset time length. Here, the preset time length can be set according to actual conditions. In some embodiments, the preset time length can be 1ms-10s. That is to say, the full storage block in the embodiment of the present application is a full storage block whose write time difference with the unfull storage block where the codeword to be read is located is very small, and because they are in the same memory device, the application scenarios subsequently experienced are similar.

[0082] It can be understood that in the implementation of the present application, the offset value corresponding to the initial read voltage corresponding to the codeword to be read in the unfilled storage block is obtained on the basis of the first offset value corresponding to the full storage block, further considering the second offset value corresponding to the position of the word line coupled to the aforementioned first blank physical page in all word lines of the unfilled storage block, and the third offset value corresponding to the distance between the word line coupled to the codeword to be read and the word line coupled to the first blank physical page in the unfilled storage block.

[0083] In some embodiments, the word line coupled to the first blank physical page has different positions among all the word lines of the partially written memory block, and the corresponding absolute values ​​of the second offset values ​​are different.

[0084] In some embodiments, when the distances between the word lines coupled to the codeword to be read and the word lines coupled to the first blank physical page in the partially filled memory block are different, the corresponding third offset values ​​are different. The word lines coupled to all memory cells in the programmed state contained in the partially filled memory block are divided into inner word lines (Inner WL) and edge word lines (Edge WL); wherein the edge word line is the word line closest to the word line coupled to the first blank physical page (Open WL), and the inner word line is the word line, excluding the edge word lines, of all word lines coupled to memory cells to which data has been written. In other words, the inner word line is farther from the word line coupled to the first blank physical page (Open WL) than the edge word line.

[0085] In some embodiments, an absolute value of the third offset value corresponding to the edge word line is greater than an absolute value of the third offset value corresponding to the middle word line.

[0086] In some embodiments, the third offset values ​​corresponding to all intermediate word lines may be the same, or may be partially or completely different depending on the distance from the word line (Open WL) coupled to the first blank physical page. In some specific embodiments, the third offset values ​​corresponding to all intermediate word lines may be determined based on the specific offset characteristics of memory devices of different models or batches.

[0087] FIG8 is a schematic diagram of data state distribution of physical pages corresponding to each word line in an incomplete memory block according to an embodiment of the present application.

[0088] As shown in Figure 8, the partially written memory block (Open Block) includes 232 word lines, which are numbered WL0, WL1...WL231 according to the programming order. Among them, all memory cells coupled to word lines numbered WL0 to WL17 have data written to them, that is, they are all in the programmed state; all memory cells coupled to word lines numbered WL18 to WL231 have no data written to them, that is, they are all in the erased state. Here, word line numbered WL18 is the word line coupled to the first blank page (Open WL) mentioned above; word line numbered WL17 is the edge word line (Edge WL) mentioned above, and word lines numbered WL0 to WL16 are the inner word lines (Inner WL) mentioned above. It can be understood that at least one codeword to be read is located in the memory cells coupled to word lines numbered WL0 to WL17.

[0089] It should be noted that all memory cells coupled to the edge word lines may all be in the programmed state (this is the case shown in FIG8 ), or all memory cells coupled to the edge word lines may be in the programmed state according to the first half of the programming sequence.

[0090] It should be noted that each rectangular cell shown in FIG8 can be understood as a logical page. Generally, a physical page is mapped to multiple logical pages. A logical page is the smallest unit of read and write operations. The number of logical pages in each row shown in FIG8 is for illustration only and is not intended to limit the number of logical pages in each row in the embodiments of the present application.

[0091] For example, if the word line coupled to at least one codeword performing a read operation is word line numbered WL7, then the total offset value A1 corresponding to the initial read voltage is calculated as follows: Base shift + factor * open_wl(8) / 232 + inner_factor1. Here, Base shift corresponds to the first offset value, factor * open_wl(8) / 232 corresponds to the second offset value, and inner_factor1 corresponds to the third offset value.

[0092] For example, if the word line coupled to at least one codeword performing a read operation is word line numbered WL10, then the total offset value corresponding to the initial read voltage is A2 = Base shift + factor * open_wl(11) / 232 + inner_factor2. Here, Base shift can be understood as corresponding to the aforementioned first offset value, factor * open_wl(11) / 232 can be understood as corresponding to the aforementioned second offset value, and inner_factor2 can be understood as corresponding to the aforementioned third offset value.

[0093] It should be noted that the third offset values ​​inner_factor1 and inner_factor2 in the above two examples may be the same or different. In some cases, the absolute value of inner_factor1 is smaller than the absolute value of inner_factor2.

[0094] For example, if the word line coupled to at least one codeword performing a read operation is word line numbered WL17, then the total offset value corresponding to the initial read voltage is A3 = Base shift + factor * open_wl(18) / 232 + edge_factor. Here, Base shift can be understood as corresponding to the aforementioned first offset value, factor * open_wl(18) / 232 can be understood as corresponding to the aforementioned second offset value, and edge_factor can be understood as corresponding to the aforementioned third offset value.

[0095] In some embodiments, the first offset value, the second offset value, and the third offset value are obtained respectively; the first offset value, the second offset value, and the third offset value are summed to obtain a total offset value; and the default read voltage and the total offset value are summed to obtain a predicted initial read voltage of the codeword.

[0096] Here, the default read voltage may be a read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage immediately after writing, in which case the corresponding offset value is 0. In some embodiments, the first offset value can be obtained by adjusting the default read voltage multiple times. In some embodiments, the second and third offset values ​​can be obtained by calculation using the formulas in the aforementioned examples.

[0097] In some embodiments, the first offset value, the second offset value, and the third offset value are all negative numbers, that is, the three offset values ​​are all offset in a decreasing direction relative to the default read voltage.

[0098] The following provides a specific implementation method for obtaining the target valley voltage of a codeword according to a first result corresponding to the predicted value of the predicted initial read voltage according to the codeword of the to-be-performed read operation.

[0099] In some embodiments, the peripheral circuit is configured to: based on the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, use the predicted initial read voltage as the target valley voltage of the codeword; based on the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjust the predicted initial read voltage at least once, and obtain the first result corresponding to the adjusted read voltage after each adjustment; and based on the first result corresponding to the adjusted read voltage satisfying a preset condition, determine the target valley voltage of the codeword.

[0100] Here, we first introduce the meaning of the first result and the specific method of obtaining the first result.

[0101] Here, the first result represents the number of bits flipped in two reading results of the codeword of the to-be-read operation at the corresponding read voltage and a voltage close to the corresponding read voltage.

[0102] In some embodiments, during the reading of the memory device, a read operation may read out data of a physical page. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a physical page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a physical page can correspond to 4 codewords, and the page buffer hardware operation can count the Fail Bit Count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page. The subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of a physical page, and a physical page can include multiple codewords.

[0103] Here, the first read voltage and the second read voltage are both general terms, and the difference between the first read voltage and the second read voltage is less than a preset voltage. In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5mV to 20mV. For example, the difference between the first read voltage and the second read voltage can be 5mV, 10mV, 15mV, or 20mV. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5mV to -20mV. For example, the difference between the first read voltage and the second read voltage can be -5mV, -10mV, -15mV, or -20mV.

[0104] In some embodiments, the peripheral circuit is configured to: read the stored data of the codeword at a first read voltage to obtain a second result; perform a third adjustment on the first read voltage with a third step size to obtain the second read voltage, and read the stored data of the codeword at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent that the third result is flipped compared to the second result to obtain the first result.

[0105] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0106] Here, the first read voltage and the second read voltage are contextually related, that is, the second read voltage is obtained after a third adjustment is made based on the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the third step size. The fact that the difference between the first read voltage and the second read voltage is less than the preset voltage can be understood as the first read voltage and the second read voltage having a smaller voltage difference. The preset voltage is related to the third step size and can be a voltage slightly larger than the third step size. In some specific embodiments, the preset voltage is set to a range of 6mV to 21mV. Exemplarily, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other specific embodiments, the preset voltage is set to a range of -6mV to -21mV. Exemplarily, the preset voltage can be -6mV, -10mV, -15mV, or -21mV.

[0107] As mentioned earlier, the first read voltage and the second read voltage are general concepts. The target read voltage and the read voltage obtained after adjusting the target read voltage (for example, the first adjustment or the second adjustment) can both be called the first read voltage, and the read voltage obtained after the third adjustment of the first read voltage can both be called the second read voltage.

[0108] In each embodiment of the present application, the first result corresponding to a specific voltage can be understood as: a third adjustment is performed on a specific voltage, and the number of bits flipped in the two reading results of the codeword to be read at a specific voltage and under the third adjustment of the specific voltage can be used as the first result corresponding to the specific voltage.

[0109] In some specific embodiments, the stored data of the codeword is read at a first read voltage to obtain a second result; the second result is stored in a first latch of the memory device. For example, as shown in FIG9 , the stored data of at least one codeword is read at a first read voltage V0 to obtain a second result. Specifically, memory cells with a threshold voltage less than a target read voltage V0 are marked as bit 1, and memory cells with a threshold voltage greater than the target read voltage V0 are marked as bit 0, to obtain the second result, which is then stored in the first latch of the memory device.

[0110] Next, a third adjustment is made to the first read voltage to obtain a second read voltage. The stored data of the codeword is read at this second read voltage to obtain a third result. The third result is stored in the second latch of the memory device. For example, as shown in FIG9 , a third adjustment is made to the first read voltage V0. The stored data of the codeword is read at the adjusted second read voltage V1 to obtain a third result. Specifically, memory cells with a threshold voltage less than the second read voltage V1 are marked as bit 1, and memory cells with a threshold voltage greater than the second read voltage V1 are marked as bit 0. This results in a third result, which is then stored in the second latch of the memory device.

[0111] Next, a logical operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in the third latch of the memory device. For example, as shown in FIG9 , an exclusive-OR operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in the third latch of the memory device. It should be noted that the exclusive-OR operation is one of the basic logical operations. In binary, if two binary numbers at the same position are the same, the result is "0", and if two binary numbers at the same position are different, the result is "1" (i.e., if they are the same, the result is 0, and if they are different, the result is 1).

[0112] Next, the number of bits in the fourth result representing the flipped bits in the third result compared to the second result is counted to obtain a first result. For example, as shown in FIG9 , the bits in the fourth result that are 1 represent the number of memory cells whose threshold voltages differ between the target read voltage V0 and the adjusted target read voltage V1. In other words, the bits in the fourth result that are 1 represent the number of bits in the codeword that are flipped between the two read results at the target read voltage V0 and the adjusted target read voltage V1. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the memory cell of the codeword, the bits in the fourth result that are 1 represent the number of memory cells whose codewords are flipped between the two read results at the target read voltage V0 and the adjusted target read voltage V1. This number is recorded as the first result Y1 corresponding to the target read voltage.

[0113] In embodiments of the present application, the first result corresponding to the codeword to be read at the predicted initial read voltage can be obtained using the aforementioned method. That is, the predicted initial read voltage is used as the first read voltage to obtain the corresponding first result. If the first result corresponding to the predicted initial read voltage is less than a preset threshold, the predicted initial read voltage is used as the target valley voltage for the codeword to be read. Here, the preset threshold can serve as a judgment threshold for determining the target valley voltage. That is, when the first result is less than the preset threshold, it indicates that the read voltage corresponding to the first result is used as the target valley voltage, resulting in a low error rate and high reliability of the read result. The value of the preset threshold depends on the type and storage density of the memory device. The preset threshold can be set based on empirical values ​​or as a default value configured at the factory for the memory device after extensive simulation experiments. For example, the preset threshold ranges from 5 to 30. More specifically, the preset threshold can be 5, 10, 15, 20, 25, or 30.

[0114] When the first result corresponding to the predicted initial read voltage is greater than or equal to the preset threshold, the predicted initial read voltage is adjusted at least once, and the first result corresponding to the adjusted read voltage is obtained after each adjustment; then, when the first result corresponding to the adjusted read voltage meets a preset condition, the target valley voltage of the codeword is determined. It can be understood that the read voltage after each adjustment of the predicted initial read voltage is used as the first read voltage, and the first result corresponding to each adjusted read voltage is obtained using the aforementioned method for obtaining the first result.

[0115] It should be noted that the step size corresponding to the adjustment of the predicted initial read voltage here is larger than the third step size corresponding to the third adjustment. The specific adjustment method will be described in detail later. The preset conditions here can include multiple judgment methods, and exemplary judgment methods are described in detail later.

[0116] In some embodiments, the memory cell array includes memory cells with a storage bit number of P bits, the P storage bits correspond to P pages respectively, and the P-bit memory cells read their P-bit storage data through a Q-level read voltage; P and Q are both integers greater than 1, and Q=2 P -1.

[0117] For example, when the number of storage bits of a memory cell includes two, the corresponding storage states include states 0 to 4. Referring to FIG10A , the four states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, and state 3 (also called the third storage state) P3. The binary data corresponding to these four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, a lower page (LP) and an upper page (UP).

[0118] Taking the memory cell shown in FIG10A as an example, the two-bit memory cell reads its two-bit four-state storage data through three-level read voltages (first level read voltage L1, second level read voltage L2 and third level read voltage L3 shown in FIG10A).

[0119] For example, one page corresponds to multiple read voltages, and the other page corresponds to a single read voltage. As shown in FIG10A , the binary data corresponding to the lower page is 1001, and reading the lower page requires the corresponding first read voltage L1 and third read voltage L3. The binary data corresponding to the upper page is 1100, and reading the upper page requires the corresponding second read voltage L2.

[0120] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG10B , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: a lower page, a middle page (MP), and an upper page.

[0121] Taking the memory cell shown in FIG10B as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7 shown in FIG10B ).

[0122] For example, each page corresponds to multiple read voltage levels. As shown in FIG10B , the binary data corresponding to the lower page are 10000111, and reading the lower page requires corresponding to the first read voltage L1 and the fifth read voltage L5. The binary data corresponding to the middle page are 11001100, and reading the middle page requires corresponding to the second read voltage L2, the fourth read voltage L4, and the sixth read voltage L6. The binary data corresponding to the upper page are 11100001, and reading the upper page requires corresponding to the third read voltage L3 and the seventh read voltage L7.

[0123] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG10C , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four pages, namely, a lower page, a middle page, an upper page, and an extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0124] Taking the memory cell shown in Figure 10C as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 10C).

[0125] Exemplarily, each page corresponds to multiple read voltage levels. As shown in FIG10C , the binary data corresponding to the lower page are 1100000011111100, and reading the lower page requires corresponding read voltages L2, L8, and L14. The binary data corresponding to the middle page are 1110000110000111, and reading the middle page requires corresponding read voltages L3, L7, L9, and L13. The binary data corresponding to the upper page are 1111100000110001, and reading the upper page requires corresponding read voltages L5, L10, L12, and L15. The binary data corresponding to the extra pages are 1000110000011111. Reading the extra pages requires corresponding first-level read voltage L1, fourth-level read voltage L4, sixth-level read voltage L6 and eleventh-level read voltage L11.

[0126] In the embodiment of the present application, the target valley voltage for each level of the multi-level read voltage corresponding to each page is determined sequentially. Since the lower page is typically closest to the source / drain, prioritizing the determination of each level of the read voltage corresponding to the lower page results in the fastest access speed and the shortest response time, ensuring balanced performance and durability during data access.

[0127] It should be noted that the method of preferentially determining each level of read voltage corresponding to the next page is only an example and is not used to limit the order of determining each level of read voltage in the multi-level read voltage corresponding to at least part of the pages in the embodiment of the present application.

[0128] In some embodiments, at least some pages correspond to multi-level read voltages, the multi-level read voltages including a first-level read voltage and a second-level read voltage, wherein the second-level read voltage is lower than the first-level read voltage. For example, the first-level read voltage can be understood as the highest read voltage among the multi-level read voltages for each page, and the second-level read voltage can be understood as other read voltages lower than the highest read voltage among the multi-level read voltages for each page.

[0129] It should be noted that the first and second levels are used to distinguish between a high-level read voltage and a low-level read voltage among the multiple-level read voltages corresponding to at least a portion of the page, with the low-level read voltage being lower than the high-level read voltage. For a memory cell containing multiple storage bits, a page corresponding to one storage bit may include one or more levels, and one level may include one or more levels.

[0130] For example, referring to FIG10A , a memory device includes a lower page and an upper page, wherein the lower page corresponds to multiple levels, and the multiple levels corresponding to the lower page include a first level and a third level, and a first level read voltage L1 is less than a third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first level, and the first level read voltage L1 corresponds to the read voltage of the second level.

[0131] For example, referring to FIG. 10B , a memory device includes a lower page, a middle page, and an upper page, wherein each page corresponds to multiple levels. The multiple levels corresponding to the lower page include a first level and a fifth level, where a first level read voltage L1 is less than a fifth level read voltage L5. The multiple levels corresponding to the middle page include a second level, a fourth level, and a sixth level, where a second level read voltage L2 and a fourth level read voltage L4 are both less than a sixth level read voltage L6. The multiple levels corresponding to the upper page include a third level and a seventh level, where a third level read voltage L3 is less than a seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively. The first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0132] Exemplarily, referring to Figure 10C, the memory device includes a lower page, a middle page, an upper page and an extra page, wherein each page corresponds to multiple levels, the multiple levels corresponding to the lower page include the second level, the eighth level and the fourteenth level, the second level read voltage L2 and the eighth level read voltage L8 are both less than the fourteenth level read voltage L14, the multiple levels corresponding to the middle page include the third level, the seventh level, the ninth level and the thirteenth level, the third level read voltage L3, the seventh level read voltage L7 and the ninth level read voltage L9 are all less than the thirteenth level read voltage L13, the multiple levels corresponding to the upper page include the fifth level, the tenth level, the twelfth level and the fifteenth level, the fifth level read voltage L5, the tenth level read voltage L10 and the twelfth level read voltage L12 are less than the fifteenth level read voltage L15, the multiple levels corresponding to the extra page include the first level, the fourth level, the sixth level and the eleventh level, the first level read voltage L1, the fourth level read voltage L4 and the sixth level read voltage L6 are less than the eleventh level read voltage L11. Here, the fourteenth-level read voltage L14, the thirteenth-level read voltage L13, the fifteenth-level read voltage L15 and the eleventh-level read voltage L11 correspond to the first-level read voltages of the lower page, middle page, upper page and extra page respectively, the second-level read voltage L2 and the eighth-level read voltage L8 correspond to the second-level read voltage of the lower page, the third-level read voltage L3, the seventh-level read voltage L7 and the ninth-level read voltage L9 correspond to the second-level read voltage of the middle page, the fifth-level read voltage L5, the tenth-level read voltage L10 and the twelfth-level read voltage L12 correspond to the second-level read voltage of the upper page, the first-level read voltage L1, the fourth-level read voltage L4 and the sixth-level read voltage L6 correspond to the second-level read voltage of the extra page.

[0133] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the peripheral circuit is configured to: obtain the predicted initial read voltage of the codeword at the target level, the predicted offset direction of the initial read voltage, and the predicted boundary voltage based on the position of the word line coupled to the codeword in the unfilled storage block, the position of the first blank physical page in the unfilled storage block, and the level number of the target level in the multiple levels; and in the process of adjusting the predicted initial read voltage at least once, change the current offset direction based on the adjusted predicted initial read voltage exceeding the range limited by the predicted boundary voltage.

[0134] Here, the target level can be understood as a level in the target page whose target valley voltage is currently being determined. As previously mentioned, in the present embodiment, the target valley voltage for each level in each level corresponding to each page is determined sequentially. After determining the target valley voltage for the codeword in the target level, the target valley voltages for the other levels in the multiple levels, excluding the target level, are determined.

[0135] Here, when obtaining the predicted initial read voltage for the pending read operation, the position of the word line coupled to the codeword to be read in the unfilled memory block and the position of the first blank physical page in the unfilled memory block are considered, and the target level number also needs to be considered. Simultaneously, when obtaining the predicted initial read voltage for the codeword to be read at the target level, the predicted offset direction and predicted boundary voltage of the read voltage to be adjusted are also obtained.

[0136] In some embodiments, the predicted offset direction of the predicted initial read voltage is a direction that reduces the default read voltage. Therefore, the total offset value of the predicted initial read voltage is actually a negative number. Adding the default read voltage to the total offset value is actually subtracting the total offset value from the default read voltage.

[0137] Exemplarily, taking TLC as an example, the predicted offset directions of the predicted initial read voltages corresponding to the seven levels of read voltages corresponding to TLC may all be negative.

[0138] Here, the predicted boundary voltage corresponds to the limit value of the memory cell threshold voltage offset. The predicted boundary voltage may include a left boundary voltage and a right boundary voltage; wherein the left boundary voltage is less than the right boundary voltage. The limit value of the memory cell offset can generally be obtained based on a large amount of experimental data on the offset performance of the memory cell. By considering the position of the word line coupled to the codeword to be read in the unfilled memory block and the position of the first blank physical page in the unfilled memory block, a limit value of the memory cell threshold voltage offset can be specifically obtained. When the first result after predicting the initial read voltage is greater than or equal to a preset threshold and the predicted initial read voltage needs to be adjusted at least once, if the voltage range defined by the predicted boundary voltage is touched or exceeded during the adjustment process, the current offset direction needs to be adjusted. For example, if the predicted initial read voltage is currently being adjusted in a decreasing direction or in a leftward direction, the predicted initial read voltage needs to be adjusted in an increasing direction or in a rightward direction instead. For example, if the predicted initial read voltage is currently being adjusted in an increasing direction or in a rightward direction, the predicted initial read voltage needs to be adjusted in a decreasing direction or in a leftward direction instead.

[0139] The following examples illustrate how to continue determining the target valley voltage when the first result after predicting the initial read voltage is greater than or equal to a preset threshold. It should be noted that the following two methods for determining the target valley voltage are also applicable to determining the target valley voltage in a fully written memory block. In a fully written memory block, the predicted initial read voltage can be replaced with a default read voltage.

[0140] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the peripheral circuit is configured to: obtain the predicted valley voltage of the codeword at the target level based on the first result corresponding to the predicted initial read voltage of the target level and the level number of the target level; and determine the target valley voltage of the target level based on the predicted valley voltage of the target level.

[0141] The relationship between the storage bit and the multi-level read voltage (multi-level read voltage) will not be described in detail here. It should be noted that the level number of the current level can be understood as the aforementioned level number.

[0142] A predicted valley voltage of the target step is obtained based on the first result corresponding to the predicted initial read voltage, the step number of the target step, and the first mapping function. The first mapping function is related to the performance of the memory device (particularly the shift performance of the memory cell threshold voltage). The first mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device.

[0143] In some embodiments, a plurality of first mapping functions with different mapping relationships may be stored in the memory device, so as to obtain predicted valley voltages of a plurality of target steps.

[0144] In some embodiments, the first mapping function can be used for cyclic iteration. Specifically, the predicted valley voltage obtained at the last target level is used as the input value of the first mapping function for obtaining the predicted valley voltage at the next target level, thereby iteratively obtaining the predicted valley voltages of multiple target levels.

[0145] It is understood that when any of the multiple predicted valley voltages for the target step satisfies a preset condition, the predicted valley voltage for the target step that satisfies the preset condition can be used as the target valley voltage for the target step. Obtaining multiple predicted valley voltages for the target step increases the probability that the predicted valley voltage for the target step satisfies the preset condition, thereby accelerating the determination of the target valley voltage.

[0146] In some embodiments, the preset condition may be that the first result corresponding to the predicted valley voltage is less than a preset threshold.

[0147] In some embodiments, the preset condition may be that the data read at the valley voltage is predicted to be successfully decoded.

[0148] If the aforementioned method of using a mapping function to obtain a predicted valley voltage cannot effectively determine the target valley voltage, the following method can be used to continue determining the target valley voltage. Alternatively, the aforementioned method of using a mapping function to obtain a predicted valley voltage can be skipped and the target valley voltage can be directly determined using the following two types of adjustment methods.

[0149] In other embodiments, the peripheral circuit is configured to: adjust the predicted initial read voltage M times, and during the M adjustments, perform M first adjustments on the read voltage to be adjusted with the first step size, and obtain M first results corresponding to the read voltage after the M first adjustments; take the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; perform N second adjustments on the inflection point voltage with a second step size, and obtain N first results corresponding to the read voltage after the N second adjustments; the second step size is smaller than the first step size; M and N are both positive integers greater than 1; and determine the target valley voltage based on the N first results obtained.

[0150] Here, the first adjustment can be understood as a large-step adjustment, or a rough adjustment. The second adjustment can be understood as a small-step adjustment, or a fine adjustment. The core idea of ​​this adjustment scheme is to perform a rough adjustment first and then a fine adjustment.

[0151] Here, the first step length is greater than the second step length, and the second step length is greater than the third step length. The first step length can be a larger step length. In some embodiments, the first step length can range from 50mV to 150mV. Exemplarily, the first step length can be 50mV, 80mV, 100mV, 120mV, or 150mV. The second step length can be a smaller step length. In some embodiments, the second step length can range from 20mV to 40mV. Exemplarily, the second step length can be 20mV, 30mV, or 40mV. The third step length can be an even smaller step length. The third step length ranges from 5mV to 20mV. Exemplarily, the third step length can be 5mV, 10mV, 15mV, or 20mV.

[0152] Here, the adjusted read voltage is used as the horizontal axis, and the first result at the corresponding adjusted target read voltage is used as the vertical axis. These two axes form a point. The inflection point can be understood as a point close to the valley bottom. The valley bottom point is the point corresponding to the target valley bottom voltage as the horizontal axis.

[0153] It should be noted that during the first adjustment and the second adjustment process, adjustments need to be made in both the positive direction (rightward) and the negative direction (leftward). In some embodiments, during multiple first adjustment processes, the predicted boundary voltages on the left and right sides can be reached. In some embodiments, during multiple second adjustment processes, the predicted boundary voltages on the left and right sides can be reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. After the second adjustment is completed, the adjusted read voltage corresponding to the minimum first result is used as the target valley voltage.

[0154] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the peripheral circuit is configured to: after determining the target valley voltage of the codeword in the target level, separately determine the target valley voltages of other levels in the multiple levels except the target level.

[0155] An alternative example of determining other orders is provided below.

[0156] In some embodiments, multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages; the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the peripheral circuit is configured as follows: when the stage corresponding to the determined target valley voltage belongs to the first stage, according to the determined target valley voltage, obtain the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltage of the remaining first stages with lower read voltage; according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltage of the remaining first stages with lower read voltage, obtain the target valley voltages of the second stage and the remaining first stages.

[0157] Here, the first and second orders have been introduced above and will not be repeated here. In the embodiment of the present application, the target valley voltage / predicted valley voltage of the high order (first order) can be used to obtain the predicted valley voltage of the low order (second order) and the predicted valley voltage of the remaining high orders. Specifically, the predicted valley voltage of the order to be predicted (the second order and the remaining first orders) can be obtained based on the target valley voltage / predicted valley voltage of the high order, the order number of the order to be predicted (the second order and the remaining first orders) and the second mapping function. Here, the second mapping function is related to the performance of the memory device (especially the offset performance of the memory cell threshold voltage). The second mapping function can be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Unlike the first mapping function, the second mapping function does not support loop iteration. The target valley voltage can then be determined based on the predicted valley voltage through the two types of adjustment methods mentioned above.

[0158] In some embodiments, the peripheral circuit is configured to perform a read operation according to the codewords of all first-stage and second-stage target valley voltages / predicted valley voltages.

[0159] It can be understood that after the target valley voltages of all levels of all pages are determined, the read operation can be performed using the target valley voltages.

[0160] In some embodiments, in order to speed up the entire reading process, the predicted valley voltages of all levels of all pages can be used to directly perform a read operation. Then, when the decoding operation of the read operation fails, the target valley voltage can be determined using the two types of adjustment methods mentioned above, and then the read operation and decoding operation can be re-performed.

[0161] First, in each memory device provided by the embodiments of the present application, a first result (the first result can be several bytes in size) is transmitted without transmitting at least one codeword (for example, the codeword can be 4KB in size), thereby reducing the amount of data transmitted and the transmission time of the output port. The process of obtaining the first result is integrated within the memory device, does not occupy space in, for example, a memory controller, and has a low degree of dependence on, for example, the memory controller. Furthermore, in the embodiments of the present application, taking into account the charge difference between memory cells with written data and memory cells without written data in a partially filled memory block, based on a filled memory block in the same application scenario, the position of the open WL and the distance between the word line coupled to the memory cell to be read and the open WL are taken into account to specifically obtain a predicted initial read voltage, and then determine the target valley voltage based on the predicted initial read voltage. Compared to a method of directly using a default read voltage and performing multiple loop iterations to obtain the target valley voltage, the predicted initial read voltage obtained after considering the aforementioned two positions in the embodiments of the present application can reduce the number of loop iterations (the predicted initial read voltage can even directly determine the target valley voltage), thereby enabling a faster acquisition of the target valley voltage.

[0162] FIG11 is a flowchart of a method for operating a memory device according to an embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below using FIG11. It should be noted that, herein and hereinafter, the target valley voltage refers to the voltage used to perform a read operation on the data to be read.

[0163] In step S101, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S102 is executed.

[0164] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage for each level of the at least one level of read voltage corresponding to each of the multiple pages is determined sequentially. In step S103, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, using TLC as an example, the target valley voltages for the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S103 is executed.

[0165] In step S103, the main task is to determine the type of the target level. Here, the target level can be divided into two categories, the first level (also called high level) and the second level (also called low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the lower page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, that is, the low level; if L5 is selected as the target level in step S104, the target level is the first level, that is, the high level. According to the target level being the low level, execute step S104; according to the target level being the high level, execute step S106.

[0166] In step S104, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S106 is executed.

[0167] In step S105, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the first mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the second mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S121 is executed. If the hard decoding fails, the two-step prediction is failed. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S107 is continued.

[0168] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jump from step S105 to S107.

[0169] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S106, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S107 is executed after step S106.

[0170] It should be noted that here and below, the conversion relationship between DAC and the aforementioned mv is 1DAC=10mv.

[0171] In step S107, the target valley voltage is determined by searching or looping. After step S107, step S108 is executed.

[0172] For the first execution loop, in step S108, a first result at the target read voltage is obtained. It is understood that for subsequent execution loops, in step S108, a first result at an adjusted target read voltage is obtained. After step S108, step S109 is executed.

[0173] In step S109, the first threshold TH1 is determined or adjusted based on the first result at the target read voltage. It is understandable that when performing a read operation, the further the threshold voltage of the memory cell deviates from the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result at the default read voltage can be used to confirm the first threshold TH1. The first threshold TH1 is used to characterize the change (increase) in the valley voltage caused by the memory cell threshold voltage deviation. Step S110 is executed after step S109. The first threshold here can be further understood with reference to the relevant description of the preset threshold in the aforementioned embodiment.

[0174] It should be noted that step S109 is mainly for the first execution of the loop process, and can be skipped for subsequent execution of the loop process.

[0175] In step S110, a predicted valley voltage is obtained, and a determination is made as to whether the first result corresponding to the predicted valley voltage is less than the aforementioned first threshold TH1. Based on the first result corresponding to the target read voltage after the previous adjustment and a related mapping function (such as the aforementioned first mapping function), the predicted read voltage after the next adjustment is obtained, and the first result corresponding to the predicted valley voltage obtained is compared with the first threshold TH1. If the determination result of step S110 is negative, it indicates that the first result corresponding to the predicted valley voltage obtained at this time is greater than or equal to the first threshold TH1. The loop continues with step S108, adjusting the target read voltage and re-obtaining the predicted valley voltage. The first result corresponding to each re-obtained predicted valley voltage is compared with the first threshold TH1 until the first result corresponding to the obtained predicted read voltage is less than the first threshold TH1. In other words, the prediction is iterated using the aforementioned prediction formula or related mapping function until the first result corresponding to the obtained predicted read voltage is less than the first threshold TH1. When the judgment result of step S110 is yes, it means that the first result corresponding to the predicted valley voltage obtained at this time is less than the first threshold TH1, and the process goes to the next step S111.

[0176] In step S111, an inflection point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. The inflection point can be understood as a point relatively close to the bottom of the valley. In some embodiments, it is possible to start from the near-valley point with a coarser step size (first step size), and search to the left and right boundaries respectively until the left and right boundaries are reached, and the point corresponding to the minimum first result in the search process is used as the inflection point. Here, the inflection point is a point that is closer to the bottom of the valley than the near-valley point. The point that is less than the first threshold in the aforementioned step can be used as the near-valley point. For example, the near-valley point can be the point that is less than the first threshold that appears for the first time in the aforementioned step. The first step size can be a larger step size. In some embodiments, the first step size can be 5DAC-15DAC. Exemplarily, the first step size can be 5DAC, 10DAC or 15DAC. Step S112 is performed after step S111.

[0177] In step S112, it is determined whether an inflection point has been found. If no inflection point has been found, the search continues, and step S111 is continued until an inflection point is found. After the inflection point is found, step S113 is executed.

[0178] In step S113 and step S114, the search can be performed starting from the near-valley point with a finer step size (second step size) to the left boundary and the right boundary respectively until the left boundary and the right boundary are reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. It should be noted that the positions of step S113 and step S114 can be interchanged. The second step size can be a smaller step size. In some embodiments, the second step size can be 2DAC-4DAC. Exemplarily, the second step size can be 2DAC, 3DAC or 4DAC.

[0179] When the searches in step S113 and step S114 satisfy the aforementioned conditions (reaching the boundary or the statistics showing an upward trend exceed the preset number of times), step S115 is executed.

[0180] In step S115, the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S115, step S116 is executed.

[0181] In step S116, it is determined whether the target valley voltage is valid. The method for determining whether the target valley voltage is valid may be to read data using the target valley voltage and decode the read data via the memory controller. Successful decoding indicates whether the target valley voltage is valid. If the result of step S116 is yes, step S121 is executed; if the result of step S116 is no, step S117 is executed.

[0182] In step S117, it is determined whether the loop has ended. If the determination result of step S117 is yes, step S119 is executed; if the determination result of step S117 is no, step S118 is executed.

[0183] In step S118, the process enters the next loop and continues searching. Step S118 jumps to step S107.

[0184] In step S119, it is determined whether the target order is a high order. If the determination result of step S119 is yes, step S120 is executed; if the determination result of step S119 is no, step S121 is executed.

[0185] In step S120, the predicted valley voltage of the low-order is obtained based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be obtained by using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the second mapping function described above). Step S121 is executed after step S120.

[0186] In step S121, it is determined whether the corresponding target valley voltages for all the read voltage levels included in the page have been determined. If the determination result in step S121 is yes, it means that the target valley voltages for all the read voltage levels included in the page have been determined, and step S123 can be executed. If the determination result in step S121 is no, it means that the target valley voltages for all the read voltage levels included in the page have not yet been determined, and step S122 can be executed.

[0187] In step S122, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S122 jumps to step S102.

[0188] In step S123 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S123 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0189] FIG12 is a second flowchart of the operating method of the memory device provided in one embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG12.

[0190] In step S201, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S202 is executed.

[0191] In step S202, in some embodiments, the memory device is set to a single-level read mode (SLR). Here, the SLR mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage. Next, step S203 is executed.

[0192] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level of read voltage corresponding to each page in the multiple pages is determined in sequence. In step S203, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, taking TLC as an example, the target valley voltages of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S204 is executed.

[0193] In step S204, the main task is to determine the type of the target order. Here, the target order can be divided into two categories, the first order (also called high order) and the second order (also called low order), wherein the read voltage of the first order is greater than the read voltage of the second order. For example, still taking the lower page of TLC as an example, L5 is the first order and L1 is the second order. If L1 is selected as the target order in step S203, the target order is the second order, that is, the low order; if L5 is selected as the target order in step S204, the target order is the first order, that is, the high order. According to the target order being the low order, execute step S205; according to the target order being the high order, execute step S207.

[0194] In step S205, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S206 is executed.

[0195] In step S206, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the first mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the second mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is performed directly using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding succeeds, the two-step prediction is successful. The search for the target valley voltage is then stopped, and step S245 is executed. If the hard decoding fails, the two-step prediction fails. The point corresponding to the predicted valley voltage is used as the near-valley point for subsequent iterations, and step S220 is continued. Step S220 will be described in detail in the subsequent description.

[0196] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jumping from step S206 to S208; or the point corresponding to the predicted valley voltage can be directly used as the near-valley point of the subsequent iteration, that is, jumping from step S206 (S219) to S220.

[0197] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S207, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S208 is executed after step S207.

[0198] In step S208, the target valley voltage is determined by searching or looping. After step S208, step S209 is executed.

[0199] During the first execution of the loop, step S209 is to obtain the first result at the target read voltage. It is understood that during subsequent execution of the loop, step S209 is to obtain the first result at the adjusted target read voltage. Step S210 is executed after step S209.

[0200] In step S210, various parameters are determined or adjusted based on the first result under the target read voltage. Here, the various parameters may include at least a first threshold, a first boundary voltage (the position corresponding to the first boundary voltage is also called the left boundary) and a second boundary voltage (the position corresponding to the second boundary voltage is also called the right boundary). It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts compared to the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result under the default read voltage can be used to confirm the first threshold value. The first threshold value is used to characterize the change (lift) in the valley voltage caused by the shift of the threshold voltage of the memory cell. Here, the initial first boundary voltage and the initial second boundary voltage can be set based on empirical values, such as initially setting an initial first boundary voltage and an initial second boundary voltage with a relatively large range. Then, based on the first result under the target read voltage, the initial first boundary voltage and the initial second boundary voltage are adjusted, such as narrowing the range of the first boundary voltage and the second boundary voltage to obtain the first boundary voltage and the second boundary voltage. Step S211 is performed after step S210.

[0201] It should be noted that step S210 is mainly for the first execution cycle process, and can be skipped for subsequent execution cycles.

[0202] During the first execution of the loop, step S211 determines whether the first result at the target read voltage is less than the first threshold. It is understood that during subsequent executions of the loop, step S211 determines whether the first result at the adjusted target read voltage is less than the first threshold. If the determination result in step S211 is yes, it can be assumed that the first result corresponding to the adjusted target read voltage basically meets the requirements for read data decoding. The process then jumps to step S242, terminating the loop and outputting the corresponding target valley voltage. If the determination result in step S211 is no, the loop continues to step S212.

[0203] In step S212, it is determined whether the target memory block is a partially written memory block. Here, the target memory block is the memory block where at least one codeword to be read is located. A partially written memory block includes a memory block that has both a programmed state and an erased state. If the result of step S212 is yes, step S213 is executed; if the result of step S212 is no, step S214 is executed.

[0204] It should be noted that step S212 is mainly for the first execution of the loop process, and for subsequent execution of the loop process, this step can be skipped. After skipping this step, step S214 is continued.

[0205] In step S213, considering that the offset of the threshold voltage of the storage cell in the underfilled storage block is more complex than the offset of the threshold voltage of the storage cell in the filled storage block (the filled storage block can be understood as a storage block with a write time difference less than a preset time length in the same application scenario as the underfilled storage block), the offset of the threshold voltage of the storage cell in the underfilled storage block is also related to the position of the first blank physical page in the underfilled storage block (the first blank physical page can be understood as the physical page in which the first data state appearing in the underfilled storage block is all erased according to the programming order) and the position of the physical page to be read (the physical page where the at least one codeword to be read is located). Based on this, the predicted valley voltage can be obtained based on the first offset corresponding to the filled storage block, the second offset corresponding to the position of the first blank physical page in the underfilled storage block, and the third offset corresponding to the position of the physical page to be read, and then the process proceeds to step S214. It is understandable that the obtained predicted valley voltage is more targeted than blindly adjusting the target read voltage, and can shorten the search time to a certain extent and determine the target valley voltage more quickly.

[0206] In step S214, determine whether a near-valley point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. In the process of adjusting the target read voltage multiple times, the point corresponding to the multiple first results corresponding to the multiple adjusted target read voltages that is first less than the near-valley threshold can be used as the near-valley point. The near-valley threshold is used to characterize the maximum value of the first result corresponding to the voltage close to the bottom of the valley. It should be noted that the near-valley threshold is different from the aforementioned first threshold. When the first result is less than the near-valley threshold, it means that a more refined search can be carried out next; when the first result is less than the first threshold, it means that the search can be stopped next. When the judgment result of step S214 is yes, execute step S219; when the judgment result of step S214 is no, execute step S215.

[0207] If no near-valley point is found in step S215, the process proceeds to step S215, where the predicted read voltage after the next adjustment is obtained based on the first result corresponding to the target read voltage after the previous adjustment and the related mapping function (such as the first mapping function described above). That is, the prediction is iterated using the aforementioned prediction formula or mapping function. After step S215, step S216 is executed.

[0208] In step S216, a determination is made as to whether the next adjusted predicted read voltage hits a boundary. The boundary here can be either the left boundary or the right boundary, and hitting the boundary can be understood as being exactly on the boundary or crossing the boundary. If the determination result in step S216 is yes, step S217 is executed; if the determination result in step S216 is no, step S218 is executed.

[0209] In step S217, the adjustment direction is changed. There are two adjustment directions for adjusting the target read voltage: positive (rightward) and negative (leftward). Adjusting the offset direction can be understood as: previously adjusting to the right, then adjusting to the left after hitting the right boundary; or previously adjusting to the left, then adjusting to the right after hitting the left boundary. After step S217, step S218 is executed.

[0210] In step S218, the first result of the adjusted target read voltage is obtained. After step S218, step S214 is executed. That is, after each target voltage adjustment and the corresponding first result is obtained, a determination is made as to whether the latest adjustment point is a near-valley point. One or more adjustments are performed until a near-valley point is found.

[0211] It should be noted that if the next cycle is entered after the step of finding the near valley point because the subsequent conditions are not met, steps S215 to S218 can be skipped.

[0212] In step S219, you can refer to the description in step S206. When the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the point corresponding to the predicted valley bottom voltage can be directly used as the near-valley point of the subsequent iteration, that is, jump from step S219 to S220.

[0213] In step S220, it is determined whether the predicted valley voltage at the current point (the latest adjusted target read voltage) is valid. In some embodiments, the predicted valley voltage can be determined to be valid by the first result corresponding to the latest adjusted target read voltage being less than the first threshold. It should be noted that although in step S211, when the first result under the (adjusted) target read voltage is not less than the first threshold, S212 and subsequent steps are entered, but before the judgment result of step S214 is yes, the target read voltage is adjusted at least once, so the new adjusted target read voltage may be less than the first threshold at this time. When the judgment result of step S220 is yes, step S224 is executed; when the judgment result of step S220 is no, step S221 is executed.

[0214] In step S221, a determination is made as to whether the first result fbc of the current point is greater than the fbc of the previous point. After finding the near-valley point, a rough search for an inflection point begins to the left. Generally, the magnitude of fbc decreases and then increases. When the first result fbc of the current point is greater than the fbc of the previous point, this indicates that fbc will increase further during the subsequent leftward adjustment, and the previous point was a relatively small point. In this case, the previous point is set as the inflection point. In some embodiments, the step size used for the rough search can be a larger step size, for example, 5DAC-15DAC, or more specifically, 5DAC, 10DAC, or 15DAC. Based on this, if the determination result of step S221 is yes, step S223 is executed; if the determination result of step S221 is no, step S222 is executed.

[0215] In step S222, a rough search is performed to the left starting from the point near the valley, and each search is compared with the fbc of the previous search until a point is found where the value stops decreasing and starts increasing. Once this point is found, step S222 is completed and the process goes to step S223.

[0216] In step S223, the previous point (i.e., the point where the decrease stops and the increase begins) is set as the inflection point, and a fine search is performed to the right starting from the inflection point. In some embodiments, the step size used in the fine search can be a smaller step size, for example, 1DAC-4DAC, more specifically, 2DAC or 3DAC. After step S223, step S225 is executed.

[0217] In step S224, the current point is set as the inflection point, and a fine search is started from the inflection point to the right. In some embodiments, the step size used in the fine search can refer to step S223. After step S224, step S225 is executed.

[0218] In step S225 , it is determined whether the target read voltage is adjusted to the left. If the determination result of step S225 is yes, step S229 is executed; if the determination result of step S225 is no, step S226 is executed.

[0219] In step S226, the target read voltage is adjusted rightward. During the adjustment, a determination is made as to whether the right boundary is hit or whether the rise count (also known as an upward trend count, where an upward trend count is performed when the first result corresponding to the next adjusted target read voltage is greater than the first result corresponding to the previous adjusted target read voltage) exceeds a preset number TH2. In some embodiments, the preset number is 3-7 times, and illustratively, the preset number can be 3, 5, or 7 times. If the determination in step S226 is yes, step S228 is executed; if the determination in step S226 is no, step S227 is executed.

[0220] In step S227, if the right boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the right boundary, and a judgment is made after each search until the right boundary is hit or the lift count exceeds the preset number TH2. In other words, when step S227 is completed, jump to step S228.

[0221] In step S228 , the target read voltage starts to be adjusted leftward.

[0222] In step S229, while adjusting the target read voltage to the left, it is determined whether the left boundary or lift count is hit. The lift count here can be understood with reference to the aforementioned step S226. The thresholds for the left and right lift counts are generally set to the same value. If the judgment result of step S229 is yes, step S231 is executed; if the judgment result of step S229 is no, step S230 is executed.

[0223] In step S230, if the left boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the left boundary, and a judgment is made after each search until the left boundary is hit or the lift count exceeds the preset number TH2. That is, when step S230 is completed, jump to step S231.

[0224] In step S231, a determination is made as to whether the most recent first result is the minimum. Here, the most recent first result refers to whether the first result at the adjusted target read voltage after the last target read voltage adjustment is the minimum. At this point, it is necessary to traverse all search points in at least this loop to find the adjusted target read voltage corresponding to the point with the minimum first result. If the determination result in step S231 is yes, step S233 is executed; if the determination result in step S231 is no, step S232 is executed.

[0225] In step S232, the latest first result is updated using the found minimum first result. Step S233 is executed after step S232.

[0226] In step S233, it is determined whether the near-valley count exceeds the preset number TH3. Here, the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value. If the number of the remaining multiple first results whose difference from the reference value is less than the second threshold is greater than the preset number, the search is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage. In some embodiments, the second threshold and the preset number can be set together according to actual conditions. Generally, if the second threshold is set slightly larger, the preset number is also relatively larger; generally, if the second threshold is set slightly smaller, the preset number is also relatively smaller. If the judgment result of step S233 is yes, the search is stopped and step S237 is executed. If the judgment result of step S233 is no, the next judgment is entered and step S234 is executed.

[0227] In step S234, a determination is made as to whether the repeated valley count exceeds a preset number TH4. Here, during multiple adjustments to the target read voltage, different adjustment methods may be employed. If the adjusted target read voltages corresponding to the different adjustment methods exceeding the preset number are the same, and the first result corresponding to the same target read voltage is the minimum value among all first results, the same target read voltage is used as the target valley voltage. In some embodiments, the preset number is 2-4, and illustratively, the preset number may be 2, 3, or 4. If the determination result in step S234 is yes, the search is terminated and step S237 is executed. If the determination result in step S234 is no, the process proceeds to the next determination step, executing step S235.

[0228] It should be noted that step S233 and step S234 belong to different judgment methods and their positions can be interchanged. In other words, the repeated valley count can be judged first, and then the approximate estimate can be judged when the repeated valley count does not meet the conditions. It is understandable that other judgments can also be performed here to determine whether the loop has ended.

[0229] In step S235, it is determined whether the loop has ended. If the determination result of step S235 is yes, step S237 is executed; if the determination result of step S235 is no, step S236 is executed.

[0230] In step S236, the process enters the next loop and continues searching. Step S236 jumps to step S209.

[0231] In step S237, the target step search is completed, and the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S237, step S238 is executed.

[0232] In step S238, it is determined whether the target order is a high order. If the determination result of step S238 is yes, step S239 is executed; if the determination result of step S238 is no, step S240 is executed.

[0233] In step S239, the predicted valley voltage of the low-order is obtained based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be obtained by using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the second mapping function described above). Step S240 is executed after step S239.

[0234] In step S240, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S240 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S242 can be executed. If the determination result in step S240 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S241 can be executed.

[0235] In step S241, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S236 jumps to step S202.

[0236] In step S242 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S242 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0237] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0238] It should be noted that the execution entity of the specific implementation process of each step in Figures 11 and 12 can be a peripheral circuit or a memory controller.

[0239] In a second aspect, an embodiment of the present application provides a memory system, as shown in Figures 13 and 14, the memory system 102 includes: one or more memory devices 104 as provided in the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0240] As shown in FIG13 , in some embodiments, a memory system 102 is coupled to a host, responding to host instructions and performing various feedback operations. The memory system 102 may include a memory controller 106 and a memory device 104 . The memory controller 106 is configured to control the memory device 104 to perform operations such as read, write, and erase operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0241] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole. The specific steps executed by the memory controller described above are mainly executed and completed by the control unit 1063 here. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The ROM 1069 generally contains the firmware or firmware program code of the memory controller 106, which is used to initialize and operate the various components of the memory controller. The RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0242] The garbage collection module 1065 is used to read valid data from some storage blocks, rewrite it, and then mark these storage blocks as new backup storage blocks after the storage space of the memory device reaches a certain threshold. Garbage collection is generally implemented in three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new backup storage block. The wear leveling module 1066 is used to maintain a balanced wear (number of erases) on each storage block in the memory system through data statistics and algorithms. Wear leveling is generally implemented in two steps: selecting a source storage block containing cold data; reading valid data from the source storage block and writing it to a storage block with a relatively high erase count. At this point, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0243] In some specific embodiments, the memory controller 106 is configured to control the memory device 104 to perform a read operation on at least one codeword.

[0244] In some embodiments, the memory controller 106 is configured to: send a data acquisition instruction, the data acquisition instruction instructing to obtain a target valley voltage; the memory device 104 is configured to: receive the data acquisition instruction, obtain the target valley voltage, and send information including the target valley voltage to the memory controller 106; the memory controller 106 is further configured to: perform a read operation on the data stored in the memory device according to the target valley voltage in the information.

[0245] In some embodiments, the memory controller 106 is further configured to perform an error correction code decoding operation on the read result of the read operation. In some implementations, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0246] In some specific embodiments, as shown in FIG. 14 , the memory controller 106 is configured to send a data acquisition instruction instructing to acquire a target valley voltage; and the memory device 104 is configured to acquire the target valley voltage and send information including the target valley voltage to the memory controller 106 .

[0247] Secondly, in each memory system provided by the embodiments of the present application, the first result (the first result can be several bytes in size) is transmitted without transmitting at least one codeword (for example, the codeword can be 4KB in size), thereby reducing the amount of data transmitted and the transmission time of the output port. The process of obtaining the first result is integrated within the memory device, does not occupy space in, for example, a memory controller, and has a low degree of dependence on, for example, the memory controller. At the same time, in the embodiments of the present application, considering the charge difference between the memory cells with data written and the memory cells without data written in the partially filled memory block, based on the filled memory block in the same application scenario, the position of the open WL and the distance between the word line coupled to the memory cell to be read and the open WL are taken into account, and a predicted initial read voltage is obtained in a targeted manner. The target valley voltage is then determined based on the predicted initial read voltage. Compared to the method of directly using the default read voltage and performing multiple loop iterations to obtain the target valley voltage, the predicted initial read voltage obtained after considering the aforementioned two positions in the embodiments of the present application can reduce the number of loop iterations (the predicted initial read voltage can even directly determine the target valley voltage), thereby achieving a faster target valley voltage.

[0248] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, wherein the memory device includes multiple memory blocks, the memory blocks include multiple word lines and multiple memory cells coupled to the multiple word lines, the multiple memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; the memory controller includes: a control unit, configured to: obtain a predicted initial read voltage of the code word based on a position of the word line coupled to the code word in an unfilled memory block and a position of the first blank physical page in the unfilled memory block; and obtain a target valley voltage of the code word based on a first result corresponding to the code word at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the code word at a first read voltage and a second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage for the code word when performing a read operation.

[0249] Here, the control unit can be understood in conjunction with the control unit 1063 shown in Figure 13. Other components included in the memory controller can also be understood in conjunction with Figure 13. It should be noted that in this embodiment of the present application, the execution subject is replaced by the aforementioned peripheral circuit with the control unit in the memory controller. That is, in this embodiment of the present application, the memory device obtains at least one first result; at the same time, the control unit uses the at least one first result to perform analysis and processing, and determines the target valley voltage based on the analysis and processing results.

[0250] In some embodiments, the control unit is configured to: obtain an offset value corresponding to the predicted initial read voltage of the codeword based on a first offset value corresponding to a full storage block whose write time difference with the unfull storage block is less than a preset time length, a second offset value corresponding to the position of the word line coupled to the first blank physical page in all word lines of the unfull storage block, and a third offset value corresponding to the distance of the word line coupled to the codeword from the word line coupled to the first blank physical page in the unfull storage block; and obtain the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage.

[0251] In some embodiments, the control unit is configured to: obtain the first offset value, the second offset value and the third offset value respectively; sum the first offset value, the second offset value and the third offset value to obtain a total offset value; and sum the default read voltage and the total offset value to obtain a predicted initial read voltage of the codeword.

[0252] In some embodiments, the control unit is configured to: based on the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, use the predicted initial read voltage as the target valley voltage of the codeword; based on the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjust the predicted initial read voltage at least once, and obtain the first result corresponding to the adjusted read voltage after each adjustment; and based on the first result corresponding to the adjusted read voltage satisfying a preset condition, determine the target valley voltage of the codeword.

[0253] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the control unit is configured to: obtain the predicted initial read voltage, the predicted offset direction and the predicted boundary voltage of the codeword at the target level according to the position of the word line coupled to the codeword in the unfilled storage block, the position of the first blank physical page in the unfilled storage block and the level number of the target level in the multiple levels; and in the process of adjusting the predicted initial read voltage at least once, change the current offset direction according to the adjusted predicted initial read voltage exceeding the range limited by the predicted boundary voltage.

[0254] In some embodiments, the predicted offset direction of the predicted initial read voltage is a direction that reduces the default read voltage.

[0255] In some embodiments, the control unit is configured to: adjust the predicted initial read voltage M times, and during the M adjustments, perform M first adjustments on the read voltage to be adjusted with the first step size, and obtain M first results corresponding to the read voltage after the M first adjustments; take the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; perform N second adjustments on the inflection point voltage with a second step size, and obtain N first results corresponding to the read voltage after the N second adjustments; the second step size is smaller than the first step size; M and N are both positive integers greater than 1; and determine the target valley voltage based on the N first results obtained.

[0256] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the control unit is configured to: obtain the predicted valley voltage of the codeword at the target level based on the first result corresponding to the predicted initial read voltage of the target level and the level number of the target level; and determine the target valley voltage of the target level based on the predicted valley voltage of the target level.

[0257] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the control unit is configured to: after determining the target valley voltage of the codeword in the target level, separately determine the target valley voltages of other levels in the multiple levels except the target level.

[0258] In some embodiments, multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages; the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the control unit is configured to: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtain the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages according to the determined target valley voltage; and obtain the target valley voltages of the second stage and the remaining first stages according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages.

[0259] In some embodiments, the control unit is configured to perform a read operation on the codeword according to target valley voltages / predicted valley voltages of all first-level and second-level levels.

[0260] It should be noted that the execution subject of the specific implementation process of the aforementioned Figures 11 and 12 can be the control unit in the memory control.

[0261] Thirdly, in each memory controller provided in the embodiments of the present application, the first result (the first result can be several bytes in size) is transmitted without transmitting at least one codeword (for example, the codeword can be 4KB in size), thereby reducing the amount of data transmitted and the transmission time of the output port. The process of obtaining the first result is integrated within the memory device, does not occupy space in, for example, the memory controller, and has a low degree of dependence on, for example, the memory controller. At the same time, in the embodiments of the present application, considering the charge difference between the memory cells with written data and the memory cells without written data in the partially filled memory block, based on the filled memory block in the same application scenario, the position of the open WL and the distance between the word line coupled to the memory cell to be read and the open WL are taken into account, and a predicted initial read voltage is obtained in a targeted manner. The target valley voltage is then determined based on the predicted initial read voltage. Compared to the method of directly using the default read voltage to perform multiple loop iterations to obtain the target valley voltage, the predicted initial read voltage obtained after considering the aforementioned two positions in each embodiment of the present application can reduce the number of loop iterations (the predicted initial read voltage can even directly determine the target valley voltage), thereby enabling a faster acquisition of the target valley voltage.

[0262] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, wherein the memory device includes multiple memory blocks, the memory blocks include multiple word lines and multiple memory cells coupled to the multiple word lines, the multiple memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; the operating method includes: obtaining a predicted initial read voltage of the code word based on a position of the word line coupled to the code word in an unfilled memory block and a position of the first blank physical page in the unfilled memory block; obtaining a target valley voltage of the code word based on a first result corresponding to the code word under the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the code word under a first read voltage and a second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage for the code word when performing a read operation.

[0263] In some embodiments, the obtaining of the predicted initial read voltage of the codeword based on the position of the word line coupled to the codeword in the unfilled storage block and the position of the first blank physical page in the unfilled storage block includes: obtaining an offset value corresponding to the predicted initial read voltage of the codeword based on a first offset value corresponding to a full storage block whose write time difference with the unfilled storage block is less than a preset time length, a second offset value corresponding to the position of the word line coupled to the first blank physical page in all word lines of the unfilled storage block, and a third offset value corresponding to the distance between the word line coupled to the codeword and the word line coupled to the first blank physical page in the unfilled storage block; and obtaining the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage.

[0264] In some embodiments, obtaining the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage includes: obtaining the first offset value, the second offset value, and the third offset value respectively; summing the first offset value, the second offset value, and the third offset value to obtain a total offset value; and summing the default read voltage and the total offset value to obtain the predicted initial read voltage of the codeword.

[0265] In some embodiments, obtaining the target valley voltage of the codeword based on the first result corresponding to the codeword at the predicted initial read voltage includes: based on the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, using the predicted initial read voltage as the target valley voltage of the codeword; based on the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjusting the predicted initial read voltage at least once, and obtaining the first result corresponding to the adjusted read voltage after each adjustment; and determining the target valley voltage of the codeword based on the first result corresponding to the adjusted read voltage satisfying a preset condition.

[0266] In some embodiments, the storage bit number of the memory cell is multiple bits, and the multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: obtaining the predicted initial read voltage of the codeword at the target level, the predicted offset direction of the predicted initial read voltage, and the predicted boundary voltage based on the position of the word line coupled to the codeword in the unfilled storage block, the position of the first blank physical page in the unfilled storage block, and the level number of the target level in the multiple levels; and in the process of adjusting the predicted initial read voltage at least once, changing the current offset direction based on the adjusted predicted initial read voltage exceeding the range limited by the predicted boundary voltage.

[0267] In some embodiments, the predicted offset direction of the predicted initial read voltage is a direction that reduces the default read voltage.

[0268] In some embodiments, the operating method also includes: adjusting the predicted initial read voltage M times, and during the M adjustments, performing M first adjustments on the read voltage to be adjusted with the first step length, and respectively obtaining M first results corresponding to the read voltage after the M first adjustments; taking the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determining the target valley voltage based on the N first results obtained.

[0269] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: obtaining the predicted valley voltage of the codeword at the target level based on the first result corresponding to the predicted initial read voltage of the target level and the level number of the target level; and determining the target valley voltage of the target level based on the predicted valley voltage of the target level.

[0270] In some embodiments, the storage unit has multiple storage bits, and the multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: after determining the target valley voltage of the codeword in the target level, respectively determining the target valley voltages of the other levels in the multiple levels except the target level.

[0271] In some embodiments, multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages; the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the operating method also includes: when the stage corresponding to the determined target valley voltage belongs to the first stage, according to the determined target valley voltage, obtaining the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages; and according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages, obtaining the target valley voltages of the second stage and the remaining first stages.

[0272] In some embodiments, the operating method further includes: performing a read operation on the codeword according to the target valley voltages / predicted valley voltages of all first-stage and second-stage voltages.

[0273] In some embodiments, the operation method for obtaining the first result also includes: reading the stored data of the codeword at a first read voltage to obtain a second result; performing a third adjustment on the first read voltage with a third step size to obtain the second read voltage, and reading the stored data of the codeword at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0274] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: a memory controller in the memory system sends a data acquisition instruction, wherein the data acquisition instruction indicates acquisition of a target valley voltage; a memory device in the memory system receives the data acquisition instruction, acquires the target valley voltage according to the operating method of the memory device described in the fourth aspect of the embodiment of the present application, and sends information including the target valley voltage to the memory controller; the memory controller performs a read operation on data stored in the memory device according to the target valley voltage in the information.

[0275] In some embodiments, the operating method further includes: the memory controller performing an error correction code decoding operation on a read result of the read operation.

[0276] In a sixth aspect, an embodiment of the present application provides an operating method of a memory controller, wherein the memory controller is coupled to at least one memory device, wherein the memory device includes a plurality of memory blocks, wherein the memory blocks include a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, wherein the plurality of memory cells coupled to the same word line form a physical page, and a physical page includes one or more preset numbers of the memory cells forming a code word; the operating method comprises: determining the position of the word line coupled to the code word in an unfilled memory block and determining the first blank physical page word in the unfilled memory block; The method comprises the steps of: determining the position of a line, obtaining a predicted initial read voltage of the codeword, and obtaining a target valley voltage of the codeword according to a first result corresponding to the codeword under the predicted value of the predicted initial read voltage; obtaining the target valley voltage of the codeword according to the first result; the first result including a representation of the number of bits flipped in two read results of the first codeword under the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than the number of bits flipped in two read results under a read voltage corresponding to a preset voltage and a voltage near the corresponding read voltage; and the target valley voltage is used as a read voltage when performing a read operation on the codeword.

[0277] In some embodiments, the obtaining of the predicted initial read voltage of the codeword based on the position of the word line coupled to the codeword in the unfilled storage block and the position of the first blank physical page in the unfilled storage block includes: obtaining an offset value corresponding to the predicted initial read voltage of the codeword based on a first offset value corresponding to a full storage block whose write time difference with the unfilled storage block is less than a preset time length, a second offset value corresponding to the position of the word line coupled to the first blank physical page in all word lines of the unfilled storage block, and a third offset value corresponding to the distance between the word line coupled to the codeword and the word line coupled to the first blank physical page in the unfilled storage block; and obtaining the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage.

[0278] In some embodiments, obtaining the predicted initial read voltage of the codeword based on the offset value corresponding to the predicted initial read voltage includes: obtaining the first offset value, the second offset value, and the third offset value respectively; summing the first offset value, the second offset value, and the third offset value to obtain a total offset value; and summing the default read voltage and the total offset value to obtain the predicted initial read voltage of the codeword.

[0279] In some embodiments, obtaining the target valley voltage of the codeword based on the first result corresponding to the codeword at the predicted initial read voltage includes: based on the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, using the predicted initial read voltage as the target valley voltage of the codeword; based on the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjusting the predicted initial read voltage at least once, and obtaining the first result corresponding to the adjusted read voltage after each adjustment; and determining the target valley voltage of the codeword based on the first result corresponding to the adjusted read voltage satisfying a preset condition.

[0280] In some embodiments, the storage bit number of the memory cell is multiple bits, and the multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: obtaining the predicted initial read voltage of the codeword at the target level, the predicted offset direction of the predicted initial read voltage, and the predicted boundary voltage based on the position of the word line coupled to the codeword in the unfilled storage block, the position of the first blank physical page in the unfilled storage block, and the level number of the target level in the multiple levels; and in the process of adjusting the predicted initial read voltage at least once, changing the current offset direction based on the adjusted predicted initial read voltage exceeding the range limited by the predicted boundary voltage.

[0281] In some embodiments, the predicted offset direction of the predicted initial read voltage is a direction that reduces the default read voltage.

[0282] In some embodiments, the operating method also includes: adjusting the predicted initial read voltage M times, and during the M adjustments, performing M first adjustments on the read voltage to be adjusted with the first step length, and respectively obtaining M first results corresponding to the read voltage after the M first adjustments; taking the smallest first result among the M first results as the inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; performing N second adjustments on the inflection point voltage with a second step length, and respectively obtaining N first results corresponding to the read voltage after the N second adjustments; the second step length is smaller than the first step length; M and N are both positive integers greater than 1; and determining the target valley voltage based on the N first results obtained.

[0283] In some embodiments, the storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: obtaining the predicted valley voltage of the codeword at the target level based on the first result corresponding to the predicted initial read voltage of the target level and the level number of the target level; and determining the target valley voltage of the target level based on the predicted valley voltage of the target level.

[0284] In some embodiments, the storage unit has multiple storage bits, and the multiple storage bits correspond to multiple levels of read voltages; the operating method also includes: after determining the target valley voltage of the codeword in the target level, respectively determining the target valley voltages of the other levels in the multiple levels except the target level.

[0285] In some embodiments, multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages; the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the operating method also includes: when the stage corresponding to the determined target valley voltage belongs to the first stage, according to the determined target valley voltage, obtaining the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages; and according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages, obtaining the target valley voltages of the second stage and the remaining first stages.

[0286] In some embodiments, the operating method further includes: performing a read operation on the codeword according to the target valley voltages / predicted valley voltages of all first-stage and second-stage voltages.

[0287] In some embodiments, the operation method for obtaining the first result also includes: reading the stored data of the codeword at a first read voltage to obtain a second result; performing a third adjustment on the first read voltage with a third step size to obtain the second read voltage, and reading the stored data of the codeword at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0288] Figure 15 is an exemplary timing diagram for starting a single-stage read mode operation provided by the present application. DQx can be represented as a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0289] As shown in FIG15 , the set function command may include, for example, a sub-command (e.g., EFh). Exemplarily, the memory device starts the single-level read mode upon receiving a sub-command EFh. In the single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer first, and then the data DATA may be read on demand. It should be noted that in the above embodiment, when performing a reread operation, the data corresponding to a page (e.g., Dn) needs to be frequently transmitted (Din / Dout) between the memory device and the memory controller, and the transmission of the data takes a long time.

[0290] FIG16 is a timing diagram for determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG17 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). For example, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives sub-command 30h, within the read time, the corresponding data DATA (e.g., Dn) in the page of the received address may be cached in the page buffer, and then the data DATA may be read on demand.

[0291] In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received subcommands 00h and 30h. After receiving subcommand 30h, the memory device 104 receives subcommands EBh and xxh of the data acquisition instruction. Under the instruction of the data acquisition instruction, the memory device 104 acquires the first result corresponding to the codeword at the corresponding read voltage and sends the acquired first result to the memory controller. The memory controller determines a target valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device according to the target valley voltage.

[0292] It should be noted that the data acquisition instruction provided in the embodiment of the present application is only an example and should not unduly limit the scope of protection of the present application.

[0293] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the target valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0294] In a seventh aspect, an embodiment of the present application further provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of the operating method in the above-mentioned embodiment of the present application can be implemented.

[0295] In some specific embodiments, the storage medium can be a memory such as Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, magnetic surface storage, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM); it can also be various devices including one or any combination of the above memory devices.

[0296] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0297] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, e.g., in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0298] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0299] In some specific embodiments, referring to Figure 17, Figure 17 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instruction is executed by the memory device, the first storage medium can be used to implement the steps of the operating method of the memory device described in the above embodiment of the present application; when the executable instruction is executed by the memory controller, the second storage medium can be used to implement the steps of the operating method of the memory controller described in the above embodiment of the present application; when the executable instruction is executed by the memory system, the third storage medium can be used to implement the steps of the operating method of the memory system described in the above embodiment of the present application.

[0300] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0301] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory device comprising: A memory cell array includes a plurality of memory blocks, each of which includes a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, wherein the plurality of memory cells coupled to the same word line form a physical page, and a physical page includes one or more code words; A peripheral circuit is coupled to the memory cell array and is configured to: Obtaining a predicted initial read voltage of the codeword according to a position of a word line coupled to the codeword in an unfilled memory block and a position of a first blank physical page in the unfilled memory block; and A target valley voltage of the codeword is obtained based on a first result corresponding to the codeword at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the codeword at the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage when performing a read operation on the codeword.

2. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Obtaining an offset value corresponding to a predicted initial read voltage of the codeword based on a first offset value corresponding to a full memory block having a write time difference with the incomplete memory block that is less than a preset time length, a second offset value corresponding to a position of a word line coupled to a first blank physical page among all word lines of the incomplete memory block, and a third offset value corresponding to a distance between a word line coupled to the codeword and a word line coupled to the first blank physical page in the incomplete memory block; and The predicted initial read voltage of the codeword is obtained according to the offset value corresponding to the predicted initial read voltage.

3. The memory device according to claim 2, wherein The peripheral circuit is configured as follows: respectively obtaining the first offset value, the second offset value, and the third offset value; Add the first offset value, the second offset value, and the third offset value to obtain a total offset value; and The default read voltage is summed with the total offset value to obtain the predicted initial read voltage of the codeword.

4. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: According to the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, the predicted initial read voltage is used as the target valley voltage of the codeword; According to the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjusting the predicted initial read voltage at least once, and obtaining the first result corresponding to the adjusted read voltage after each adjustment; The target valley voltage of the codeword is determined based on that the first result corresponding to the adjusted read voltage meets a preset condition.

5. The memory device according to claim 4, wherein The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The peripheral circuit is configured as follows: Obtaining a predicted initial read voltage of the codeword at the target level, a predicted offset direction of the predicted initial read voltage, and a predicted boundary voltage according to a position of a word line coupled to the codeword in an unfilled memory block, a position of a first blank physical page in the unfilled memory block, and a level number of a target level in the multiple levels; and In the process of adjusting the predicted initial read voltage at least once, the current offset direction is changed according to the adjusted predicted initial read voltage exceeding the range defined by the predicted boundary voltage. The memory device according to claim 5 , wherein: The predicted offset direction of the predicted initial read voltage is a direction in which the default read voltage is reduced.

7. The memory device according to claim 4, wherein The peripheral circuit is configured as follows: Adjusting the predicted initial read voltage M times, performing M first adjustments on the read voltage to be adjusted with the first step length during the M adjustments, and obtaining M first results corresponding to the read voltages after the M first adjustments; taking the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step size, and obtaining N first results corresponding to the read voltage after the N second adjustments, respectively; the second step size is smaller than the first step size; and both M and N are positive integers greater than 1; and The target valley voltage is determined according to the obtained N first results.

8. The memory device according to claim 4, wherein The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; the peripheral circuit is configured as follows: Obtaining a predicted valley voltage of the codeword at the target level according to a first result corresponding to the codeword at the predicted initial read voltage of the target level and the level number of the target level; and A target valley voltage of the target step is determined based on the predicted valley voltage of the target step.

9. The memory device according to claim 4, wherein: The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The peripheral circuit is configured as follows: After determining the target valley voltage of the codeword at the target level, target valley voltages of other levels in the multiple levels except the target level are determined respectively.

10. The memory device according to claim 9, wherein The plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels; the plurality of levels include a first level and a second level, and a read voltage of the second level is less than a read voltage of the first level; The peripheral circuit is configured as follows: When the stage corresponding to the determined target valley voltage belongs to the first stage, obtaining, according to the determined target valley voltage, a predicted valley voltage of the second stage among the multiple stages and / or predicted valley voltages of the remaining first stages with lower reading voltages; and The target valley voltages of the second stage and the remaining first stages are obtained according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages. The memory device according to claim 10 , wherein: The peripheral circuit is configured as follows: A read operation is performed on the codeword according to the target valley voltages / predicted valley voltages of all first-stage and second-stage voltages.

12. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Reading the stored data of the codeword at a first read voltage to obtain a second result; performing a third adjustment on the first read voltage with a third step length to obtain the second read voltage, and reading the stored data of the codeword at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and The first result is obtained by counting the number of bits in the fourth result that represent that the third result is flipped compared with the second result.

13. The memory device according to claim 12, wherein: The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to: store the second result; The second latch is configured to: store the third result; The third latch is configured to store the fourth result.

14. A memory system comprising: One or more memory devices according to any one of claims 1 to 13; as well as A memory controller is coupled to the memory device and controls the memory device.

15. The memory system according to claim 14, wherein: The memory controller is configured to: send a data acquisition instruction, wherein the data acquisition instruction instructs acquisition of a target valley voltage; The memory device is configured to: receive the data acquisition instruction, acquire a target valley voltage, and send information including the target valley voltage to the memory controller; The memory controller is further configured to perform a read operation on data stored in the memory device according to the target valley voltage in the information.

16. The memory system according to claim 15, wherein: The memory controller is further configured to perform an error correction code decoding operation on a read result of the read operation.

17. A memory controller coupled to at least one memory device, the memory device comprising a plurality of memory blocks, the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, the plurality of memory cells coupled to the same word line forming a physical page, and a physical page comprising one or more code words; The memory controller includes: The control unit is configured to: Obtaining a predicted initial read voltage of the codeword according to a position of a word line coupled to the codeword in an unfilled memory block and a position of a first blank physical page in the unfilled memory block; and A target valley voltage of the codeword is obtained based on a first result corresponding to the codeword at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the codeword at the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage when performing a read operation on the codeword.

18. The memory controller according to claim 17, wherein: The control unit is configured to: Obtaining an offset value corresponding to a predicted initial read voltage of the codeword based on a first offset value corresponding to a full memory block having a write time difference with the incomplete memory block that is less than a preset time length, a second offset value corresponding to a position of a word line coupled to a first blank physical page among all word lines of the incomplete memory block, and a third offset value corresponding to a distance between a word line coupled to the codeword and a word line coupled to the first blank physical page in the incomplete memory block; and The predicted initial read voltage of the codeword is obtained according to the offset value corresponding to the predicted initial read voltage.

19. The memory controller according to claim 18, wherein: The control unit is configured to: respectively obtaining the first offset value, the second offset value, and the third offset value; Add the first offset value, the second offset value, and the third offset value to obtain a total offset value; and The default read voltage is summed with the total offset value to obtain the predicted initial read voltage of the codeword.

20. The memory controller according to claim 17, wherein: The control unit is configured to: According to the first result corresponding to the codeword at the predicted initial read voltage being less than a preset threshold, the predicted initial read voltage is used as the target valley voltage of the codeword; According to the first result corresponding to the codeword at the predicted initial read voltage being greater than or equal to the preset threshold, adjusting the predicted initial read voltage at least once, and obtaining the first result corresponding to the adjusted read voltage after each adjustment; The target valley voltage of the codeword is determined based on that the first result corresponding to the adjusted read voltage meets a preset condition.

21. The memory controller according to claim 20, wherein: The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The control unit is configured to: Obtaining a predicted initial read voltage, a predicted offset direction, and a predicted boundary voltage of the codeword at the target level according to a position of a word line coupled to the codeword in an unfilled memory block, a position of a first blank physical page in the unfilled memory block, and a level number of a target level in the multiple levels; and In the process of adjusting the predicted initial read voltage at least once, the current offset direction is changed according to the adjusted predicted initial read voltage exceeding the range defined by the predicted boundary voltage.

22. The memory controller according to claim 21, wherein: The predicted offset direction of the predicted initial read voltage is a direction in which the default read voltage is reduced.

23. The memory controller according to claim 20, wherein: The control unit is configured to: Adjusting the predicted initial read voltage M times, performing M first adjustments on the read voltage to be adjusted with the first step length during the M adjustments, and obtaining M first results corresponding to the read voltages after the M first adjustments; taking the smallest first result among the M first results as an inflection point value, and the read voltage corresponding to the inflection point value as the inflection point voltage; Performing N second adjustments on the knee point voltage with a second step size, and obtaining N first results corresponding to the read voltage after the N second adjustments, respectively; the second step size is smaller than the first step size; and both M and N are positive integers greater than 1; and The target valley voltage is determined according to the obtained N first results.

24. [Corrected 01.03.2024 under Rule 91] The memory controller according to claim 20, wherein The storage unit has multiple storage bits, and the multiple storage bits correspond to multiple levels of read voltages; the control unit is configured to: Obtaining a predicted valley voltage of the codeword at the target level according to a first result corresponding to the codeword at the predicted initial read voltage of the target level and the level number of the target level; and A target valley voltage of the target step is determined based on the predicted valley voltage of the target step.

25. [Corrected 01.03.2024 under Rule 91] The memory controller according to claim 20, wherein: The storage unit has multiple storage bits, and multiple storage bits correspond to multiple levels of read voltages; The control unit is configured to: After determining the target valley voltage of the codeword at the target level, target valley voltages of other levels in the multiple levels except the target level are determined respectively.

26. The memory controller according to claim 25, wherein: The plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels; the plurality of levels include a first level and a second level, and a read voltage of the second level is less than a read voltage of the first level; The control unit is configured to: When the stage corresponding to the determined target valley voltage belongs to the first stage, obtaining, according to the determined target valley voltage, a predicted valley voltage of the second stage among the multiple stages and / or predicted valley voltages of the remaining first stages with lower reading voltages; and The target valley voltages of the second stage and the remaining first stages are obtained according to the predicted valley voltage of the second stage in the multiple stages and / or the predicted valley voltages of the remaining first stages with lower read voltages.

27. The memory controller according to claim 26, wherein: The control unit is configured to: A read operation is performed on the codeword according to the target valley voltages / predicted valley voltages of all first-stage and second-stage voltages.

28. A method for operating a memory device, the memory device comprising a plurality of memory blocks, the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, the plurality of memory cells coupled to the same word line forming a physical page, the physical page comprising one or more code words; the method comprising: Obtaining a predicted initial read voltage of the codeword according to a position of a word line coupled to the codeword in an unfilled memory block and a position of a first blank physical page in the unfilled memory block; A target valley voltage of the codeword is obtained based on a first result corresponding to the codeword at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the codeword at the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage when performing a read operation on the codeword.

29. A method for operating a memory system, comprising: A memory controller in the memory system sends a data acquisition instruction, wherein the data acquisition instruction instructs acquisition of a target valley voltage; The memory device in the memory system receives the data acquisition instruction, The operating method of the memory device according to claim 28, acquiring a target valley voltage, and sending information including the target valley voltage to the memory controller; The memory controller performs a read operation on data stored in a memory device according to the target valley voltage in the information.

30. A method for operating a memory controller, the memory controller being coupled to at least one memory device, the memory device comprising a plurality of memory blocks, the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, the plurality of memory cells coupled to the same word line forming a physical page, a physical page comprising one or more code words; the method comprising: Obtaining a predicted initial read voltage of the codeword according to a position of a word line coupled to the codeword in an unfilled memory block and a position of a first blank physical page in the unfilled memory block; A target valley voltage of the codeword is obtained based on a first result corresponding to the codeword at the predicted initial read voltage; the first result includes a representation of the number of bits flipped in two read results of the codeword at the first read voltage and the second read voltage, and the difference between the first read voltage and the second read voltage is less than a preset voltage; the target valley voltage is used as a read voltage when performing a read operation on the codeword.

31. A storage medium having executable instructions stored thereon, wherein when the executable instructions are executed, the steps of the operating method according to any one of claims 28 to 30 can be implemented.

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