Capacitor structure and manufacturing method for capacitor structure

Abstract

Disclosed in the present invention are a capacitor structure and a manufacturing method therefor. The capacitor structure comprises a substrate that has passivation regions spaced apart, and a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer that are formed in sequence on a surface of the substrate, wherein the second conductive layer and the substrate communicate with each other between adjacent passivation regions to form a first electrode layer, the first conductive layer and the third conductive layer communicate with each other to form a second electrode layer, and the first dielectric layer and the second dielectric layer communicate with each other and the first dielectric layer is in contact with the passivation regions to isolate the first electrode layer from the second electrode layer; a first electrode is formed on the surface of the substrate away from the passivation regions; and a second electrode is formed on a surface of the third conductive layer. In the capacitor structure and the manufacturing method for a capacitor structure of the present invention, the contact area between dielectric layers and electrode layers is increased, and the use of an electrode guard ring to lead out one of the electrode layers is also avoided, thereby greatly reducing the ESR and ESL.

Description

Capacitor structure and method for manufacturing capacitor structure

[0001] The present invention claims priority to Chinese patent application No. 2024101984374, filed with the Patent Office of China on February 22, 2024, entitled “Capacitor Structure and Method for Manufacturing Capacitor Structure”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a capacitor structure and a method for manufacturing the capacitor structure. Background Art

[0003] Referring to Figures 1 and 2, for the out-of-plane electrodes of multi-layer DTC (deep trench) capacitors, the conventional technology is to lead out the electrode protection ring A-sealring at the edge of the chip. The fundamental function of the electrode protection ring A-sealring is to define the chip area and prevent the chip from being mechanically damaged during cutting. The electrode protection ring A-sealring is used as an intermediate medium to connect the polysilicon layer PS1 to the chip substrate and the lower electrode M2 ​​on the back of the chip. The center area of ​​the chip directly leads the electrodes of the N++ layer and the polysilicon layer PS2 to the front to form the upper electrode M1, and M1 and the electrode protection ring A-sealring are finally in the same plane. Among them, the inclined shadows in Figures 1 and 2 are all insulating layers.

[0004] In order to directly lead out the N++ layer and the polysilicon layer PS2 in the central area of ​​the front side of the chip, multiple through holes need to be opened on the polysilicon layer PS1 and the dielectric layers D1 and D2. However, this setting greatly reduces the contact area between the polysilicon layer PS1 and the polysilicon layer PS2 serving as electrode layers and the dielectric layers D1 and D2, affecting the capacitance density.

[0005] Moreover, the presence of the electrode guard ring A will result in larger ESR (equivalent series resistance) and ESL (equivalent series inductance); the presence of the electrode guard ring A will also occupy the surface area of ​​the front side of the chip, sacrificing part of the capacitance density; and the design of the electrode guard ring A is very easy to cause misalignment due to wire bonding deviation during wire bonding, which in turn causes the electrode guard ring A-sealring to short-circuit the upper electrode M1 of the chip front electrode, causing the upper electrode M1 and the lower electrode M2 ​​to be short-circuited, resulting in device failure.

[0006] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art.

[0007] Summary of the Invention

[0008] The object of the present invention is to provide a capacitor structure and a method for manufacturing the capacitor structure, which can increase the contact area between the dielectric layer (the first dielectric layer and the second dielectric layer) and the electrode layer (the first conductive layer and the third conductive layer, the second conductive layer and the substrate) by connecting adjacent dielectric layers, while avoiding the use of an electrode guard ring to lead out one of the electrode layers, greatly reducing ESR (equivalent series resistance) and ESL (equivalent series inductance), and different electrodes are located on different surfaces, which will not cause short circuits during subsequent wiring and thus cause device failure.

[0009] To achieve the above-mentioned purpose, a specific embodiment of the present invention provides a capacitor structure, comprising a substrate having spaced-apart passivation regions, and a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer sequentially formed on the surface of the substrate, wherein the second conductive layer is connected to the substrate in a non-passivation region between adjacent passivation regions to form a first electrode layer, the first conductive layer is connected to the third conductive layer to form a second electrode layer, the first dielectric layer is connected to the second dielectric layer and the first dielectric layer is in contact with the passivation region to isolate the first electrode layer and the second electrode layer; a first electrode is formed on a surface of the substrate facing away from the passivation region; and a second electrode is formed on a surface of the third conductive layer.

[0010] In one or more embodiments of the present invention, the substrate includes a first region, a second region, and a third region, wherein the second region surrounds the first region, and the third region surrounds the second region.

[0011] The non-passivation region between adjacent passivation regions is located in the first region, the second conductive layer is connected to the substrate in the first region, and the first dielectric layer is in contact with the passivation region in the first region;

[0012] The first dielectric layer and the second dielectric layer are arranged in communication with each other in the second region;

[0013] The first conductive layer and the third conductive layer are arranged in communication with each other in the third region.

[0014] In one or more embodiments of the present invention, the substrate has a first surface and a second surface arranged opposite to each other, the passivation region extends from the first surface to the second surface, a groove is formed in the passivation region on the first surface, and the groove has several discrete columnar structures composed of part of the substrate.

[0015] In one or more embodiments of the present invention, the first conductive layer, the first dielectric layer, the second conductive layer, the second dielectric layer and the third conductive layer all cover or partially cover the first surface of the substrate, the inner wall of the trench and the outer surface of the columnar structure.

[0016] In one or more embodiments of the present invention, the first conductive layer is formed on the first surface of the substrate, the inner wall of the groove and the outer surface of the columnar structure, and a first window corresponding to the non-passivation area is opened on the first conductive layer, and the first window exposes the substrate of the non-passivation area and part of the substrate of the passivation area.

[0017] In one or more embodiments of the present invention, the first dielectric layer is formed on the surface of the first conductive layer and contacts the passivation area at the first window to isolate the substrate and the first conductive layer, wherein the first window and the non-passivation area still expose a portion of the substrate in the non-passivation area; and a second window is opened on the first dielectric layer, and the second window exposes a portion of the first conductive layer.

[0018] In one or more embodiments of the present invention, the second window is located at the first surface of the edge of the substrate, and the second window is filled with a conductive material communicating with the first conductive layer.

[0019] In one or more embodiments of the present invention, the second conductive layer is formed on the surface of the first dielectric layer and in the first window and the non-passivation area to be connected with the substrate to form the first electrode layer, and a third window is opened on the second conductive layer, and the third window exposes a portion of the first dielectric layer.

[0020] In one or more embodiments of the present invention, the third window is located at the first surface of the edge of the substrate and is surrounded by the second window.

[0021] In one or more embodiments of the present invention, the second dielectric layer is formed on the surface of the second conductive layer and is connected to the first dielectric layer at the third window to isolate the first conductive layer from the second conductive layer, and a fourth window corresponding to the second window is opened on the second dielectric layer.

[0022] In one or more embodiments of the present invention, the third conductive layer is formed on the surface of the second dielectric layer and in the fourth window and is connected to the first conductive layer through the conductive material in the second window to form the second electrode layer.

[0023] In one or more embodiments of the present invention, the substrate is a P-type heavily doped substrate.

[0024] In one or more embodiments of the present invention, the passivation region is an N-type diffusion region.

[0025] In one or more embodiments of the present invention, the first conductive layer is an N-type heavily doped polysilicon layer or TiN deposited by ALD.

[0026] In one or more embodiments of the present invention, the first dielectric layer is made of SiN, SiO2, ONO or high K material.

[0027] In one or more embodiments of the present invention, the second conductive layer is a polysilicon layer or TiN deposited by ALD.

[0028] In one or more embodiments of the present invention, the second dielectric layer is made of SiN, SiO2, ONO or high K material.

[0029] In one or more embodiments of the present invention, the third conductive layer is a polysilicon layer or TiN deposited by ALD.

[0030] A specific embodiment of the present invention further provides a method for manufacturing a capacitor structure, comprising:

[0031] Providing a substrate having a first surface and a second surface disposed opposite to each other;

[0032] forming spaced-apart passivation regions on the first surface of the substrate, with non-passivation regions exposing the substrate between adjacent passivation regions;

[0033] forming a trench in the passivation region of the first surface, wherein the trench has a plurality of discrete columnar structures formed by portions of the substrate;

[0034] forming a first conductive layer on the first surface of the substrate, the inner wall of the trench, and the outer surface of the columnar structure, wherein the first conductive layer exposes a portion of the substrate at a non-passivation area of ​​the substrate;

[0035] forming a first dielectric layer on the surface of the first conductive layer, wherein the first dielectric layer contacts the passivation region in the non-passivation region and acts together to isolate the first conductive layer from the substrate;

[0036] forming a second conductive layer connected to the substrate on a surface of the first dielectric layer;

[0037] forming a second dielectric layer on the surface of the second conductive layer and communicating with the first dielectric layer, wherein the second dielectric layer and the first dielectric layer cooperate to isolate the second conductive layer from the first conductive layer;

[0038] forming a third conductive layer on a surface of the second dielectric layer and connected to the first conductive layer;

[0039] forming a first electrode on the second surface of the substrate;

[0040] A second electrode is formed on the surface of the third conductive layer.

[0041] In one or more embodiments of the present invention, forming a first dielectric layer on a surface of the first conductive layer in contact with the passivation region includes:

[0042] Opening a first window corresponding to the non-passivation area on the first conductive layer, wherein the first window exposes the substrate of the non-passivation area and a portion of the substrate of the passivation area;

[0043] A first dielectric layer is formed on the surface of the first conductive layer, wherein the first dielectric layer contacts the exposed passivation region at the first window to isolate the substrate from the first conductive layer.

[0044] In one or more embodiments of the present invention, a second window is opened on the first dielectric layer, and the second window exposes a portion of the first conductive layer;

[0045] A second conductive layer connected to the substrate is formed on the surface of the first dielectric layer and in the first window.

[0046] In one or more embodiments of the present invention, a third window is opened on the second conductive layer, and the third window exposes a portion of the first dielectric layer;

[0047] A second dielectric layer communicating with the first dielectric layer is formed on the surface of the second conductive layer and in the third window to isolate the first conductive layer from the second conductive layer.

[0048] In one or more embodiments of the present invention, a fourth window corresponding to the second window is opened on the second dielectric layer;

[0049] A third conductive layer is formed on the surface of the second dielectric layer and in the fourth window. The third conductive layer is connected to the first conductive layer through the conductive material in the second window.

[0050] In one or more embodiments of the present invention, the non-passivation region is located in the middle of the substrate and is surrounded by the second window and the third window;

[0051] The second window is located at the first surface of the edge of the substrate;

[0052] The third window is located at the first surface of the edge of the substrate and is surrounded by the second window.

[0053] Compared with the prior art, the capacitor structure and the method for manufacturing the capacitor structure of the present invention increase the contact area between the dielectric layer (first dielectric layer, second dielectric layer) and the first electrode layer (second conductive layer and substrate) and the second electrode layer (first conductive layer and third conductive layer) by opening holes in the second conductive layer to connect the adjacent first dielectric layer and the second dielectric layer, thereby improving the capacitance density.

[0054] The capacitor structure and the method for manufacturing the capacitor structure of the present invention only lead out the first conductive layer and the third conductive layer as the second electrode layer. The second conductive layer is directly led out through the substrate to form the first electrode layer, avoiding the use of an electrode guard ring to lead out the first electrode layer, effectively increasing the area of ​​the second electrode and improving the capacitance density.

[0055] In the capacitor structure and the method for manufacturing the capacitor structure of the present invention, the first electrode and the second electrode are formed on different surfaces respectively, and thus the problem of short circuit between the electrodes during subsequent wiring will not be caused, thereby preventing the device from failing.

[0056] The capacitor structure and the method for manufacturing the capacitor structure of the present invention optimize the current flow path through structural design, thereby significantly reducing ESR (equivalent series resistance) and ESL (equivalent series inductance). BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0058] FIG1 is a cross-sectional schematic diagram of a capacitor structure in the prior art;

[0059] FIG. 2 is a top view of a capacitor structure in the prior art.

[0060] FIG3 is a cross-sectional schematic diagram of a capacitor structure according to an embodiment of the present invention;

[0061] FIG4 is a top view of a capacitor structure according to an embodiment of the present invention;

[0062] 5a-5j are schematic diagrams of the process steps of a method for manufacturing a capacitor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0064] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0065] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0066] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0067] In the description of this application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0068] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0069] As mentioned in the background, existing multilayer DTC (deep trench) capacitors typically feature an electrode guard ring (A-sealring) at the chip edge. This serves as an intermediary, connecting the polysilicon layer PS1 to the chip substrate and the lower electrode M2 ​​on the chip's backside. In the center of the chip, electrodes from the N++ layer and polysilicon layer PS2 are directly extended to the front surface to form the upper electrode M1, ultimately aligning M1 with the electrode guard ring (A-sealring).

[0070] However, this design has many disadvantages. For example, in order to directly lead out the N++ layer and the polysilicon layer PS2 in the central area of ​​the front side of the chip, multiple through holes need to be opened on the polysilicon layer PS1 and the dielectric layers D1 and D2. This setting will greatly reduce the contact area between the polysilicon layer PS1 and the polysilicon layer PS2 as the electrode layers and the dielectric layers D1 and D2, affecting the capacitance density. For example, the presence of the electrode guard ring A will lead to a larger ESR (equivalent series resistance) and ESL (equivalent series inductance), and will also occupy the surface area of ​​the front side of the chip, sacrificing part of the capacitance density. At the same time, it is easy to cause misalignment due to wire bonding deviation during wire bonding, which will lead to a short circuit between the electrode guard ring A-sealring and the upper electrode M1 of the chip front electrode, causing the upper electrode M1 and the lower electrode M2 ​​to be short-circuited and causing device failure.

[0071] Based on this, the present application provides a capacitor structure and a method for manufacturing a capacitor structure, which can increase the contact area between the dielectric layer (the first dielectric layer and the second dielectric layer) and the electrode layer (the first conductive layer and the third conductive layer, the second conductive layer and the substrate) by connecting adjacent dielectric layers, while avoiding the use of an electrode guard ring to lead out one of the electrode layers, greatly reducing ESR (equivalent series resistance) and ESL (equivalent series inductance), and different electrodes are located on different surfaces, which will not cause short circuits during subsequent wiring and thus cause device failure.

[0072] Referring to FIG3 , a capacitor structure in one embodiment of the present invention includes a substrate 11, a passivation region 20 formed on the substrate 11 and spaced apart, a first conductive layer 31, a first dielectric layer 41, a second conductive layer 12, a second dielectric layer 42, and a third conductive layer 32 sequentially formed on the surface of the substrate 11. A first electrode 51 is formed on the surface of the substrate 11 facing away from the passivation region 20, and a second electrode 52 is formed on the surface of the third conductive layer 32. The second conductive layer 12 is connected to the substrate 11 in the non-passivation region 21 between adjacent passivation regions 20 to form a first electrode layer, which is led out by the first electrode 51; the first conductive layer 31 is connected to the third conductive layer 32 to form a second electrode layer, which is led out by the second electrode 52; the first dielectric layer 41 is connected to the second dielectric layer 42, and the passivation region 20 is in contact with the first dielectric layer 41 to separate the first electrode layer from the second electrode layer.

[0073] In the above technical solution, by connecting the adjacent first dielectric layer 41 and second dielectric layer 42, the contact area between the first dielectric layer 41, the second dielectric layer 42 and the first electrode layer (second conductive layer 12 and substrate 11), and the second electrode layer (first conductive layer 31 and third conductive layer 32) is increased, thereby improving the capacitance density. The first electrode 51 and the second electrode 52 are formed on different surfaces, preventing the problem of short circuits between the electrodes during subsequent bonding, which could lead to device failure.

[0074] In a preferred embodiment, the substrate 11 includes a first region B, a second region C, and a third region D. The first region B is located in the center of the substrate 11. The second region C is located at the edge of the substrate 11 and surrounds the first region B. The third region D is located at the outermost edge of the substrate 11 and surrounds the second region C. The non-passivation region between adjacent passivation regions 20 is located within the first region B. The second conductive layer 12 is disposed in communication with the substrate 11 within the first region B; the first dielectric layer 41 is also disposed in contact with the passivation region 20 within the first region B, and preferably, the two connection locations are aligned. The first dielectric layer 41 and the second dielectric layer 42 are disposed in communication with each other within the second region C; and the first conductive layer 31 and the third conductive layer 32 are disposed in communication with each other within the third region D.

[0075] The first electrode 51 is disposed on the side of the substrate 11 facing away from the passivation region 20 and completely covers the first region B, the second region C, and the third region D. As shown in FIG.

[0076] In the above technical solution, the second conductive layer 31 is directly electrode-leaded out through the substrate 11, avoiding the use of traditional electrode guard rings to lead out the electrode layer, so that the coverage area of ​​the second electrode 52 is the same as the coverage area of ​​the first electrode 51, effectively increasing the area of ​​the second electrode 52, improving the capacitance density, and optimizing the current flow path, thereby greatly reducing ESR and ESL.

[0077] To further increase the contact area between the dielectric layer (first dielectric layer 41, second dielectric layer 42) and the electrode layer (first electrode layer, second electrode layer), in a preferred embodiment of the present application, a groove may be formed on one surface of the substrate 11, and the groove is located within the passivation region 20. The first conductive layer 31, the first dielectric layer 41, the second conductive layer 12, the second dielectric layer 42, and the third conductive layer 32 all cover or partially cover the side of the substrate 11 where the groove is formed.

[0078] For example, referring to FIG3 , substrate 11 has a first surface 11a and a second surface 11b disposed opposite each other. Passivation region 20 extends from first surface 11a to second surface 11b. Passivation region 20 is preferably an N-type diffusion region formed by performing N-type diffusion on substrate 11. Non-passivation region 21 is located between adjacent passivation regions 20. Non-passivation region 21 can be formed by masking during the N-type diffusion on substrate 11.

[0079] A trench 111 is formed on the first surface 11a of the substrate 11 within the passivation region 20. The trench 111 contains a plurality of discrete columnar structures 112 formed from portions of the substrate 11. The columnar structures 112 are arranged in an array. The columnar structures 112 are preferably cylindrical. When the number of columnar structures 112 is the same, the use of a long-strip grid structure maximizes the spacing between adjacent columnar structures 112, accommodating more dielectric layers and increasing capacitance. The substrate 11 is preferably a heavily doped P-type, low-resistance substrate.

[0080] The first conductive layer 31 is formed on the first surface 11a of the substrate 11, the inner wall of the groove 111, and the outer surface of the columnar structure 112. The first conductive layer 31 is an N-type heavily doped polysilicon layer, which can be grown by LPCVD. Alternatively, the first conductive layer 31 is a TiN layer, which can be deposited by ALD. A first window 311 corresponding to the non-passivation area 21 is provided on the first conductive layer 31, and the projection of the first window 311 in the thickness direction of the substrate 11 partially overlaps with the non-passivation area 21. The first window 311 exposes the substrate 11 in the non-passivation area 21 and the substrate 11 in the partial passivation area 20 surrounding the non-passivation area 21.

[0081] A first dielectric layer 41 is formed on the surface of the first conductive layer 31 and contacts the exposed passivation region 20 at the first window 311 to isolate the substrate 11 from the first conductive layer 31. The first dielectric layer 41 is grown by LPCVD or deposited by ALD. The material of the first dielectric layer 41 can be SiN, SiO2, ONO, or a high-K material.

[0082] It can be understood that the non-passivation area 21 of the substrate 11 and part of the first window 311 will be filled with the first dielectric layer 41, but there is still a certain space in the first window 311 and on the non-passivation area 21 to expose part of the substrate 11, so that the subsequent second conductive layer 12 can be connected to the substrate 11 through the space for electrode extraction.

[0083] A second window 411 is defined in the first dielectric layer 41. The second window 411 is located at the first surface 11a at the edge of the substrate 11, preferably within the third region D of the substrate 11. The second window 411 exposes a portion of the first conductive layer 31. The second window 411 is filled with a conductive material that communicates with the first conductive layer 31 and also facilitates subsequent communication with the third conductive layer 32.

[0084] The second conductive layer 12 is formed on the surface of the first dielectric layer 41 and in the first window 311 to communicate with the substrate 11 in the non-passivation region 21 to form a first electrode layer. The second conductive layer 12 is preferably a polysilicon layer, which can be grown by LPCVD. Alternatively, the second conductive layer 12 is a TiN layer, which can be deposited by ALD. A third window 121 is provided on the second conductive layer 12. The third window 121 is located at the first surface 11a at the edge of the substrate 11 and within the range enclosed by the second window 411. Preferably, the third window 121 is located in the second region C of the substrate 11. The third window 121 exposes a portion of the first dielectric layer 41.

[0085] Second dielectric layer 42 is formed on the surface of second conductive layer 12 and communicates with first dielectric layer 41 at third window 121, isolating first conductive layer 31 from second conductive layer 12. This allows first conductive layer 31 to function as part of the second electrode layer, and second conductive layer 12 to function as part of the first electrode layer. Second dielectric layer 42 is grown by LPCVD or deposited by ALD. The material of second dielectric layer 42 may be SiN, SiO2, ONO, or a high-K material.

[0086] A fourth window 421 corresponding to the second window 411 is formed on the second dielectric layer 42. The fourth window 421 is also located on the first surface 11a at the edge of the substrate 11, preferably in the third region D of the substrate 11. The fourth window 421 exposes a portion of the conductive material in the second window 411.

[0087] The third conductive layer 32 is formed on the surface of the second dielectric layer 42 and in the fourth window 421. It is connected to the first conductive layer 31 through the conductive material in the second window 411 to form a second electrode layer. The third conductive layer 32 is preferably a polysilicon layer and can be grown by LPCVD. Alternatively, the third conductive layer 32 is a TiN layer and can be deposited by ALD.

[0088] The second electrode 52 is formed on the surface of the third conductive layer 32 . Both the first electrode 51 and the second electrode 52 can be formed by depositing metals such as Au, Al—Cu, AlTiNiAg, etc.

[0089] Compared with the prior art, the capacitor structure of the present invention increases the contact area between the dielectric layer (first dielectric layer, second dielectric layer) and the first electrode layer (second conductive layer and substrate) and the second electrode layer (first conductive layer and third conductive layer) by connecting the adjacent first dielectric layer and second dielectric layer, thereby improving the capacitance density.

[0090] In the capacitor structure of the present invention, only the first conductive layer and the third conductive layer are led out as the second electrode layer. The second conductive layer is directly led out through the substrate to form the first electrode layer, avoiding the use of an electrode guard ring to lead out the first electrode layer, effectively increasing the area of ​​the second electrode and improving the capacitance density.

[0091] In the capacitor structure of the present invention, the first electrode and the second electrode are formed on different surfaces, and thus the problem of short circuit between the electrodes during subsequent wiring will not be caused, thereby preventing the device from failing.

[0092] The capacitor structure of the present invention optimizes the current flow path through structural design, thereby significantly reducing ESR (equivalent series resistance) and ESL (equivalent series inductance).

[0093] 5a to 5j , an embodiment of the present invention further provides a method for manufacturing the capacitor structure, which specifically includes the following steps.

[0094] Referring to FIG5a , a substrate 11 is provided. The substrate 11 is preferably a P-type heavily doped low-resistance substrate. The substrate 11 has a first surface 11a and a second surface 11b arranged opposite to each other. N-type diffusion is performed on the first surface 11a of the substrate 11 to form a plurality of passivation regions 20 (two passivation regions 20 in this embodiment) spaced apart, and a non-passivation region 21 is formed between adjacent passivation regions 20. During diffusion, a mask can be used to block the non-passivation region 21, which is an area that does not require diffusion, so as to form a non-passivation region 21 at a corresponding position on the substrate 11. The substrate 11 is divided into a first region B, a second region C, and a third region D from the middle to the edge. The second region C is located at the edge of the substrate 11 and surrounds the first region B. The third region D is located at the outermost edge of the substrate 11 and surrounds the second region C.

[0095] As shown in FIG5b , trenches 111 are formed in the passivation region 20 on the first surface 11a of the substrate 11 by deep silicon etching. Several discrete columnar structures 112 formed from portions of the substrate are located in the trenches 111. The columnar structures 112 are arranged in an array. The columnar structures 112 are preferably cylindrical. When the number of columnar structures 112 is the same, using a long-strip grid structure can maximize the spacing between adjacent columnar structures 112, accommodating more dielectric layers and increasing capacitance.

[0096] As shown in Figure 5c, a first conductive layer 31 is grown by LPCVD on the first surface 11a of the substrate 11, the inner wall of the trench 111, and the outer surface of the columnar structure 112. The first conductive layer 31 is an N-type heavily doped polysilicon layer. Alternatively, the first conductive layer 31 is a TiN layer, which can be deposited by ALD. A first window 311 corresponding to the non-passivation region 21 is opened on the first conductive layer 31 by reactive ion etching (RIE). The projection of the first window 311 in the thickness direction of the substrate 11 partially overlaps with the non-passivation region 21. The first window 311 exposes the substrate 11 in the non-passivation region 21 and the substrate 11 in the passivation region 20 surrounding the non-passivation region 21.

[0097] Referring to FIG5 d , a first dielectric layer 41 is deposited on the surface of the first conductive layer 31 by LPCVD or ALD. The material of the first dielectric layer 41 can be SiN, SiO2, ONO, or a high-K material. It is understood that when the first dielectric layer 41 is deposited, it will fill the first window 311 so as to contact the exposed passivation region 20 through the first window 311, thereby isolating the substrate 11 and the first conductive layer 31. However, in order to allow the subsequent second conductive layer 12 to be connected to the substrate 11 without being connected to the first conductive layer 31, the first dielectric layer 41 can be opened at the location of the first window 311 and the non-passivation region 21 by reactive ion etching (RIE), so as to form a space E of the substrate 11 at the location of the first window 311 that only exposes the non-passivation region 21. Similarly, in order to allow the subsequent third conductive layer 32 to be connected to the first conductive layer 31, a second window 411 is formed by opening the first dielectric layer 41 at the first surface 11a at the edge of the substrate 11 by reactive ion etching (RIE). Preferably, the second window 411 is located in the third region D of the substrate 11 . The second window 411 exposes a portion of the first conductive layer 31 .

[0098] As shown in FIG5e , a second conductive layer 12 is formed on the first dielectric layer 41 and within the space E between the first window 311 and the non-passivation region 21 by LPCVD. The second conductive layer 12 is preferably a polysilicon layer. Alternatively, the second conductive layer 12 is a TiN layer, which can be deposited by ALD. The second conductive layer 12 is connected to the substrate 11 through the space E to form a first electrode layer.

[0099] It is understandable that during the formation of the second conductive layer 12 , conductive material will also be deposited in the second window 411 of the first dielectric layer 41 , and the conductive material can serve as a medium connecting the first conductive layer 31 and the third conductive layer 32 in subsequent steps.

[0100] As shown in FIG5f , reactive ion etching (RIE) is performed on the second conductive layer 12 at the first surface 11a at the edge of the substrate 11 to form a third window 121. The third window 121 is located within the area enclosed by the second window 411. Preferably, the third window 121 is located within the second region C of the substrate 11. The third window 121 exposes a portion of the first dielectric layer 41.

[0101] As shown in FIG5g , a second dielectric layer 42 is deposited on the surface of the second conductive layer 12 and within the third window 121 by LPCVD or ALD. The material of the second dielectric layer 42 can be SiN, SiO2, ONO, or a high-K material. The second dielectric layer 42 is connected to the first dielectric layer 41 through the third window 121 to isolate the first conductive layer 31 from the second conductive layer 12. It also isolates the second conductive layer 12 from the conductive material within the second window 411. As a result, the conductive material within the first conductive layer 31 and the second window 411 functions as part of the second electrode layer, and the second conductive layer 12 functions as part of the first electrode layer.

[0102] 5h , a fourth window 421 corresponding to the second window 411 is formed on the second dielectric layer 42 by reactive ion etching (RIE). The fourth window 421 is also located at the first surface 11a at the edge of the substrate 11, preferably within the third region D of the substrate 11. The fourth window 421 exposes part or all of the conductive material within the second window 411.

[0103] As shown in FIG5i , a third conductive layer 32 is formed on the surface of the second dielectric layer 42 and within the fourth window 421 by LPCVD. The third conductive layer 32 is preferably a polysilicon layer. Alternatively, the third conductive layer 32 can be deposited by ALD and is a TiN layer. The third conductive layer 32 is connected to the first conductive layer 31 through the conductive material within the second window 411 to form a second electrode layer.

[0104] At this step, the first electrode layer formed by the second conductive layer 12 connected to the substrate 11 and the second electrode layer formed by the first conductive layer 31 , the conductive material in the second window 411 and the third conductive layer 32 connected to each other are completely isolated.

[0105] 5j, a second electrode 52 is formed on the surface of the third conductive layer 32 by metal deposition. The material of the second electrode 52 can be Au, Al-Cu, AlTiNiAg or the like.

[0106] 3 , a first electrode 51 is formed on the surface of the substrate 11 away from the passivation region 20 (the second surface 11b) by metal deposition. The material of the second electrode 51 may also be Au, Al-Cu, AlTiNiAg, or the like.

[0107] It can be understood that the number of the non-passivation area, the first window, the second window, the third window, and the fourth window in the present application is preferably one each, so as to minimize the surface area consumption of the dielectric layer and the conductive layer and increase the contact area.

[0108] Compared with the prior art, the method for manufacturing a capacitor structure of the present invention increases the contact area between the dielectric layer (first dielectric layer, second dielectric layer) and the first electrode layer (second conductive layer and substrate) and the second electrode layer (first conductive layer and third conductive layer) by opening holes in the second conductive layer to connect the adjacent first dielectric layer and the second dielectric layer, thereby improving the capacitance density.

[0109] The manufacturing method of the capacitor structure of the present invention only leads out the first conductive layer and the third conductive layer as the second electrode layer. The second conductive layer is directly led out through the substrate to form the first electrode layer, avoiding the use of an electrode guard ring to lead out the first electrode layer, effectively increasing the area of ​​the second electrode and improving the capacitance density; optimizing the current flow path, thereby greatly reducing ESR (equivalent series resistance) and ESL (equivalent series inductance).

[0110] In the method for manufacturing the capacitor structure of the present invention, the first electrode and the second electrode are formed on different surfaces respectively, and the problem of short circuit between the electrodes during subsequent wiring will not be caused, thereby preventing the device from failing.

[0111] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0112] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A capacitor structure, characterized in that: The invention comprises a substrate having passivation regions arranged at intervals, and a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer formed in sequence on the surface of the substrate, wherein the second conductive layer is connected to the substrate in a non-passivation region between adjacent passivation regions to form a first electrode layer, the first conductive layer is connected to the third conductive layer to form a second electrode layer, the first dielectric layer is connected to the second dielectric layer and the first dielectric layer is in contact with the passivation region to isolate the first electrode layer from the second electrode layer; a first electrode is formed on a surface of the substrate facing away from the passivation region; and a second electrode is formed on a surface of the third conductive layer.

2. The capacitor structure according to claim 1, wherein: The substrate includes a first region, a second region, and a third region, wherein the second region surrounds the first region, and the third region surrounds the second region. The non-passivation region between adjacent passivation regions is located in the first region, the second conductive layer is connected to the substrate in the first region, and the first dielectric layer is in contact with the passivation region in the first region; The first dielectric layer and the second dielectric layer are arranged in communication with each other in the second region; The first conductive layer and the third conductive layer are arranged in communication with each other in the third region.

3. The capacitor structure according to claim 1, wherein: The substrate has a first surface and a second surface opposite to each other. The passivation region extends from the first surface to the second surface. A groove is formed in the passivation region on the first surface. The groove has a plurality of discrete columnar structures formed by part of the substrate.

4. The capacitor structure according to claim 3, wherein: The first conductive layer, the first dielectric layer, the second conductive layer, the second dielectric layer and the third conductive layer all cover or partially cover the first surface of the substrate, the inner wall of the trench and the outer surface of the columnar structure.

5. The capacitor structure according to claim 3, characterized in that: The first conductive layer is formed on the first surface of the substrate, the inner wall of the groove and the outer surface of the columnar structure. A first window corresponding to the non-passivation area is opened on the first conductive layer, and the first window exposes the substrate of the non-passivation area and part of the substrate of the passivation area.

6. The capacitor structure according to claim 5, characterized in that: The first dielectric layer is formed on the surface of the first conductive layer and contacts the passivation region at the first window to isolate the substrate from the first conductive layer, wherein the first window still exposes a portion of the substrate in the non-passivation region; A second window is formed on the first dielectric layer, and the second window exposes a portion of the first conductive layer.

7. The capacitor structure according to claim 6, characterized in that: The second window is located at the first surface of the edge of the substrate, and the second window is filled with a conductive material communicating with the first conductive layer.

8. The capacitor structure according to claim 6, wherein: The second conductive layer is formed on the surface of the first dielectric layer and in the first window to communicate with the substrate to form the first electrode layer. A third window is opened on the second conductive layer to expose a portion of the first dielectric layer.

9. The capacitor structure according to claim 8, characterized in that: The third window is located at the first surface of the edge of the substrate and is surrounded by the second window.

10. The capacitor structure according to claim 8, characterized in that: The second dielectric layer is formed on the surface of the second conductive layer and is connected to the first dielectric layer at the third window to isolate the first conductive layer from the second conductive layer. A fourth window corresponding to the second window is opened on the second dielectric layer.

11. The capacitor structure according to claim 10, wherein: The third conductive layer is formed on the surface of the second dielectric layer and in the fourth window and is connected with the first conductive layer through the conductive material in the second window to form the second electrode layer.

12. The capacitor structure according to claim 1, wherein: The substrate is a P-type heavily doped substrate; and / or, The passivation region is an N-type diffusion region; and / or, The first conductive layer is an N-type heavily doped polysilicon layer or ALD deposited TiN; and / or, The first dielectric layer is made of SiN, SiO2, ONO or high K material; and / or, The second conductive layer is a polysilicon layer or TiN deposited by ALD; and / or, The second dielectric layer is made of SiN, SiO2, ONO or high K material; and / or, The third conductive layer is a polysilicon layer or TiN deposited by ALD.

13. A method for manufacturing a capacitor structure, characterized in that: include: Providing a substrate having a first surface and a second surface disposed opposite to each other; forming spaced-apart passivation regions on the first surface of the substrate, with non-passivation regions exposing the substrate between adjacent passivation regions; forming a trench in the passivation region of the first surface, wherein the trench has a plurality of discrete columnar structures formed by portions of the substrate; forming a first conductive layer on the first surface of the substrate, the inner wall of the trench, and the outer surface of the columnar structure, wherein the first conductive layer exposes a portion of the substrate at a non-passivation area of ​​the substrate; forming a first dielectric layer on the surface of the first conductive layer, wherein the first dielectric layer contacts the passivation region in the non-passivation region and acts together to isolate the first conductive layer from the substrate; forming a second conductive layer connected to the substrate on a surface of the first dielectric layer; forming a second dielectric layer on the surface of the second conductive layer and communicating with the first dielectric layer, wherein the second dielectric layer and the first dielectric layer cooperate to isolate the second conductive layer from the first conductive layer; forming a third conductive layer on a surface of the second dielectric layer and connected to the first conductive layer; forming a first electrode on the second surface of the substrate; A second electrode is formed on the surface of the third conductive layer.

14. The method for manufacturing a capacitor structure according to claim 13, wherein: A first dielectric layer in contact with the passivation region is formed on a surface of the first conductive layer, comprising: Opening a first window corresponding to the non-passivation area on the first conductive layer, wherein the first window exposes the substrate of the non-passivation area and a portion of the substrate of the passivation area; A first dielectric layer is formed on the surface of the first conductive layer, wherein the first dielectric layer contacts the exposed passivation region at the first window to isolate the substrate from the first conductive layer.

15. The method for manufacturing a capacitor structure according to claim 14, wherein: opening a second window on the first dielectric layer, wherein the second window exposes a portion of the first conductive layer; A second conductive layer connected to the substrate is formed on the surface of the first dielectric layer and in the first window.

16. The method for manufacturing a capacitor structure according to claim 15, wherein: opening a third window on the second conductive layer, wherein the third window exposes a portion of the first dielectric layer; A second dielectric layer communicating with the first dielectric layer is formed on the surface of the second conductive layer and in the third window to isolate the first conductive layer from the second conductive layer.

17. The method for manufacturing a capacitor structure according to claim 16, wherein: A fourth window corresponding to the second window is opened on the second dielectric layer; A third conductive layer is formed on the surface of the second dielectric layer and in the fourth window. The third conductive layer is connected to the first conductive layer through the conductive material in the second window.

18. The method for manufacturing a capacitor structure according to claim 17, wherein: The non-passivation area is located in the middle of the substrate and is surrounded by the second window and the third window; The second window is located at the first surface of the edge of the substrate; The third window is located at the first surface of the edge of the substrate and is surrounded by the second window.

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