Storage array and preparation method therefor, storage device, and electronic apparatus

Abstract

The present application relates to the technical field of semiconductors, and provides a storage array and a preparation method therefor, a storage device, and an electronic apparatus, for use in solving the problem of how to improve the performance of a storage device. The storage array comprises a plurality of electrode layers, a plurality of insulating dielectric layers, a first electrode, and a first interposer; the plurality of electrode layers and the plurality of insulating dielectric layers are alternately stacked; the first electrode penetrates the plurality of electrode layers and the plurality of insulating dielectric layers; a storage layer surrounds the first electrode; the first interposer comprises a plurality of first sub-interposers which are arranged at intervals in the stacking direction, and the first sub-interposers surround the storage layer and are arranged between an electrode layer and the storage layer. The storage array is used for storing data.

Description

Storage array and preparation method thereof, storage device, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 20, 2024, with application number 202410192838.9 and application name “Memory Array and Preparation Method thereof, Storage Device, Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a storage array and a preparation method thereof, a storage device, and an electronic device. Background Art

[0003] In recent years, technologies like the Internet of Things and artificial intelligence have entered a golden age of rapid development. The implementation of these emerging technologies has ushered in an era of intelligent connectivity. They not only bring new and convenient experiences to people's lives, but also significantly improve production efficiency in industrial applications, thereby generating higher-quality and efficient economic benefits. The further application and integration of these emerging technologies require massive amounts of data, which places higher demands on the performance of storage devices, one of the most critical components in modern information systems.

[0004] However, existing storage devices have shortcomings. For example, while the read and write speeds of dynamic random access memory (DRAM) are sufficient for most applications, DRAM requires constant refreshing during use, resulting in high power consumption. Furthermore, because DRAM memory cells include capacitors, these capacitors limit further DRAM scaling, resulting in relatively small storage capacities.

[0005] Therefore, how to improve the performance of storage devices is an urgent problem to be solved.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a storage array and a method for manufacturing the same, a storage device, and an electronic device to solve the problem of how to improve the performance of the storage device.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, an embodiment of the present application provides a storage array comprising a plurality of electrode layers, a plurality of insulating dielectric layers, a first electrode, and a first intercalation layer, wherein the plurality of electrode layers and the plurality of insulating dielectric layers are alternately stacked; the first electrode runs through the plurality of electrode layers and the plurality of insulating dielectric layers; the storage layer surrounds the first electrode; the first intercalation layer comprises a plurality of first sub-intercalation layers spaced apart along a stacking direction, the first sub-intercalation layers surround the storage layer and are arranged between the electrode layer and the storage layer.

[0010] In this way, the memory array forms multiple capacitors along the stacking direction. A capacitor may include an electrode layer, a first sub-intercalation layer surrounded by the electrode layer, and a storage layer and a first electrode surrounded by the first sub-intercalation layer. Multiple capacitors can store data separately. Because the first sub-intercalation layers of the multiple capacitors are spaced apart from each other, the formation of a current path between the stacked multiple electrode layers due to the conductivity of the first intercalation layer can be avoided. Therefore, when a voltage is applied to one electrode layer to perform a read or write operation on the corresponding capacitor, the data stored in other capacitors can be avoided from being affected, thereby improving the stability of the stored data of each capacitor and further improving the performance of the storage device formed by the memory array.

[0011] In one possible implementation of the first aspect, multiple insulating dielectric layers and multiple first sub-intercalation layers are alternately arranged along the stacking direction. This increases the number of first sub-intercalation layers formed, allowing each capacitor to include a first sub-intercalation layer, thereby improving the read and write performance of the memory array.

[0012] In one possible implementation of the first aspect, the side surfaces of the plurality of first sub-intercalation layers closest to the first electrode are designated as first sides, and the side surface of the insulating dielectric layer closest to the first electrode is designated as second sides. The first sides are flush with the second sides, or the first sides are further away from the first electrode than the second sides. In this manner, the insulating dielectric layer can cut off the first sides of two adjacent first sub-intercalation layers, ensuring that the two adjacent first sub-intercalation layers do not contact each other, thereby preventing the formation of a current path.

[0013] In one possible implementation of the first aspect, the first sub-intercalation layer has a polygonal, circular, or elliptical ring-shaped cross-section perpendicular to the stacking direction. In this manner, a suitable shape can be selected during the fabrication process based on practical circumstances, allowing for the arrangement of more first sub-intercalation layers on the plane of the electrode layer, thereby forming more capacitors and improving the integration density of the memory array.

[0014] In one possible implementation of the first aspect, the material of the first intercalation layer includes one or more of metal, oxide, nitride, and oxynitride. Thus, a suitable material for the first intercalation layer can be selected based on the material of the storage layer to improve storage performance.

[0015] In one possible implementation of the first aspect, the first intercalation layer includes a first film layer and a second film layer, both of which surround the storage layer, with the first film layer being further away from the first electrode than the second film layer. Thus, the first intercalation layer can include multiple film layers, thereby increasing the data storage performance of the storage layer.

[0016] In one possible implementation of the first aspect, the material of the first film layer and the second film layer includes one of NbO, TiO, NbO, LaO, SiN, WO, MoO, NbN, TaO, NbO, and WN, and the first film layer and the second film layer are made of different materials. By forming the first film layer and the second film layer with different materials, the performance of the storage layer can be improved.

[0017] In one possible implementation of the first aspect, the storage layer includes multiple sub-storage layers, and the multiple sub-storage layers and the multiple insulating dielectric layers are arranged alternately along the stacking direction. In this manner, the storage layers of the multiple capacitors arranged along the stacking direction can be spaced apart to prevent mutual interference after data is stored in the storage layers, thereby improving the storage performance of the memory array.

[0018] In one possible implementation of the first aspect, the memory array further includes a second intercalation layer disposed between the memory layer and the first electrode, the second intercalation layer surrounding the first electrode; the second intercalation layer includes a plurality of second sub-intercalation layers, and the plurality of second sub-intercalation layers are alternately arranged with the plurality of insulating dielectric layers along the stacking direction. In this manner, the second sub-intercalation layers of the plurality of capacitors arranged in the stacking direction can also be spaced apart.

[0019] In one possible implementation of the first aspect, the storage layer penetrates the multiple electrode layers and the multiple insulating dielectric layers along the stacking direction. Since the storage layer penetrates the multiple electrode layers and the multiple insulating dielectric layers, the storage layer is continuously arranged in the stacking direction, thereby simplifying the process of forming the storage layer.

[0020] In a second aspect, an embodiment of the present application provides a method for preparing a memory array, comprising: forming a plurality of electrode layers and a plurality of insulating dielectric layers that are alternately stacked; forming a through hole, the through hole penetrating the plurality of electrode layers and the plurality of insulating dielectric layers; removing a portion of the electrode layer through the through hole, so that the electrode layer is recessed relative to the insulating dielectric layers adjacent to both sides of the electrode layer to form a groove; forming a first intercalation layer, the first intercalation layer comprising a plurality of first sub-intercalation layers spaced apart along a stacking direction, the first sub-intercalation layer being formed in the groove; and sequentially forming a memory layer and a first electrode in the through hole, the memory layer surrounding the first electrode.

[0021] In this way, the first sub-intercalation layer is located in a groove formed by the electrode layer being recessed relative to the adjacent insulating dielectric layers on either side of the electrode layer. In other words, the first sub-intercalation layers are spaced apart along the stacking direction of the multiple electrode layers and the multiple insulating dielectric layers. This prevents the first sub-intercalation layer from being conductive and forming a current path between the multiple electrode layers. This improves the performance of read and write operations on the corresponding storage layer through each electrode layer, thereby improving the performance of the storage device formed by this storage array.

[0022] In one possible implementation of the second aspect, forming the first intercalation layer includes: forming an initial first intercalation layer in the through-hole, the initial first intercalation layer filling a recess and covering the side surfaces of the multiple insulating dielectric layers; removing portions of the initial first intercalation layer covering the side surfaces of the multiple insulating dielectric layers, and forming multiple first sub-intercalation layers with portions of the initial first intercalation layer remaining in the recess. In this manner, the initial first intercalation layer can be formed directly in the through-hole through a deposition process. After removing portions of the initial first intercalation layer covering the side surfaces of the multiple insulating dielectric layers, multiple first sub-intercalation layers can be formed spaced apart, ensuring that the multiple sub-intercalation layers do not contact each other.

[0023] In one possible implementation of the second aspect, the first intercalation layer includes a first film layer and a second film layer, and forming the first intercalation layer includes: forming an initial first film layer in the through hole, the initial first film layer filling the groove and covering the sides of multiple insulating dielectric layers, removing portions of the initial first film layer covering the sides of the multiple insulating dielectric layers, and forming multiple first sub-film layers from the portions of the initial first film layer remaining in the groove; forming an initial second film layer in the through hole, the initial second film layer filling the groove and covering the sides of multiple insulating dielectric layers, removing portions of the initial second film layer covering the sides of the multiple insulating dielectric layers, and forming multiple second sub-film layers from the portions of the initial second film layer remaining in the groove; wherein the first sub-film layer and the second sub-film layer in the same groove form a first sub-intercalation layer. In this way, by forming the first sub-film layer and the second sub-film layer spaced apart, multiple first sub-intercalation layers spaced apart can be formed.

[0024] In one possible implementation of the second aspect, the process for forming the first intercalation layer includes an atomic layer deposition process or a chemical vapor deposition process. Atomic layer deposition can form a higher-quality first intercalation layer, while chemical vapor deposition can improve the efficiency of forming the first intercalation layer. Thus, the appropriate process can be selected based on actual circumstances.

[0025] In a third aspect, the present application provides a storage device comprising: a controller and the storage array according to any one of the first aspects, wherein the storage array is electrically connected to the controller. Thus, since the storage array employed in the storage device has good performance, the storage device also has good performance.

[0026] In a fourth aspect, the present application provides an electronic device comprising the storage device of the third aspect and a printed circuit board, wherein the storage device is electrically connected to the printed circuit board. Thus, due to the good performance of the storage device, the electronic device also has good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0028] FIG2 is a schematic structural diagram of a storage device provided in an embodiment of the present application;

[0029] FIG3 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0030] FIG4 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0031] FIG5 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0032] FIG6 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0033] FIG7 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0034] FIG8 is a schematic structural diagram of another storage array provided in an embodiment of the present application;

[0035] FIG9 is a flow chart of a method for preparing a memory array according to an embodiment of the present application;

[0036] 10 to 18 are schematic structural diagrams of the storage array preparation process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0038] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0039] FIG1 is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 may be a terminal device such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0040] The system on chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system on chip 210 may include one or more processors, such as an application processor (AP) 211 for processing applications and a graphics processing unit (GPU) 212 for processing image data. The system on chip 210 may also include a first random access memory (RAM) 213 for caching high-speed data. The first random access memory 213 may be electrically connected to the processor of the system on chip 210. The first random access memory 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash).

[0041] The application processor 211 , the image processing unit 212 and the first random access memory device 213 may be integrated into one die, or may be separately provided in multiple die.

[0042] The electronic device 200 may further include a second random access memory device 220 electrically connected to the system-on-chip 210 via the bus 205. The second random access memory device 220 may be a dynamic random access memory device (DRAM). The second random access memory device 220 may be used to store volatile data, such as temporary data generated by the system-on-chip 210. The second random access memory device 220 typically has a larger storage capacity than the first random access memory device 213, but typically has a slower read speed than the first random access memory device 213.

[0043] In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the system-on-chip 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 240 may be used to power other chips. In one embodiment, the system-on-chip 210 and the second random access memory device 220 may be packaged in a package structure, such as a 2.5D (dimension) or 3D package, to achieve a faster data transmission rate between chips.

[0044] Figure 2 is a schematic diagram of the structure of a storage device 300 provided in an embodiment of the present application. In one embodiment, the storage device 300 can be the first random access storage device 213 shown in Figure 1 or the second random access storage device 220. This application does not limit the application scenario of the storage device 300.

[0045] The memory device 300 includes the memory array 100 and a controller. The controller may include one or more peripheral circuits such as a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 , or an input / output driver 360 .

[0046] In one embodiment, the memory array 100 includes a plurality of memory cells 400 arranged in an array. For example, the memory cells 400 may be arranged in a three-dimensional array. The memory cell 400 may include a capacitor. For example, the capacitor may be charged and discharged to store 1 bit (bit) or multiple bits of data. The memory array 100 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to a corresponding signal line. One or more of the above signal lines can be used to select a memory cell 400 to be read or written in the memory array by receiving a control level output by a controller, so as to change the charge and discharge state of the capacitor in the memory cell 400, thereby realizing data read and write operations.

[0047] Decoder 320 is used to decode the address of storage cell 400. Decoder 320 decodes the received address to determine the storage cell 400 to be accessed. Driver 330 controls the signal line level based on the decoding result generated by decoder 320, thereby enabling access to the specified storage cell 400. Buffer 350 caches read data, for example, using a FIFO (first-in, first-out) buffering mechanism. Timing controller 340 controls the timing of buffer 350 and controls driver 330 to drive signal lines in storage array 100. Input / output driver 360 drives transmission signals, such as received data signals and transmitted data signals, allowing data signals to be transmitted over long distances. The storage array 100, decoder 320, driver 330, timing controller 340, buffer 350, and input / output driver 360 can be integrated into a single chip or integrated into multiple chips.

[0048] To improve the performance of a storage device 300, the present application proposes a storage array 100. Referring to FIG. 3 , FIG. 3 is a schematic diagram of a partial three-dimensional structure of the storage array 100. A three-dimensional rectangular coordinate system is established as shown in the figure, wherein the YZ plane formed by the Y and Z directions coincides with the bottom surface of the storage array 100, and the X direction coincides with the thickness direction of the storage array 100.

[0049] The memory array 100 includes a plurality of electrode layers 110 , a plurality of insulating dielectric layers 120 , a first electrode 130 , and a memory layer 134 .

[0050] The plurality of electrode layers 110 and the plurality of insulating dielectric layers 120 are alternately stacked. The first electrode 130 and the storage layer 134 both penetrate the plurality of electrode layers 110 and the plurality of insulating dielectric layers 120 , and the storage layer 134 is disposed around the first electrode 130 .

[0051] Thus, multiple capacitors 410 are formed. Each capacitor 410 includes an electrode layer 110, a first electrode 130 surrounded by the electrode layer 110 and located between the upper and lower surfaces of the electrode layer 110, and a portion of the storage layer 134. The state of the capacitor 410 can represent different storage states. For example, the amount of charge stored in the capacitor 410 can represent the stored data as "0" or "1." In this way, a three-dimensional memory array 100 can be formed using a stacked structure, thereby improving the storage density of the memory array 100.

[0052] For example, to read and write to the memory array 100, the electrode layer 110 of each capacitor 410 can be connected to the drain of a transistor, the gate of the transistor can be connected to the word line WL, and the source of the transistor can be connected to the bit line BL. A gate voltage is applied to the gate of the transistor via the word line WL, thereby selecting the capacitor 410 connected to the transistor. A source voltage is applied to the source of the transistor via the bit line BL, thereby writing data to the selected capacitor 410. The data stored in the capacitor 410 is read by detecting the voltage at the drain of the transistor. The transistor can be a MOS (Metal Oxide Semiconductor) transistor or other type of transistor. The first electrode 130 of each capacitor 410 can be connected to a plate line PL, which can be connected to a fixed voltage. For example, the plate line PL can be grounded. A voltage difference is formed between the electrode layer 110 and the first electrode 130 of the capacitor 410 to enable reading and writing of the capacitor 410. As shown in Figure 3 , first electrode 130 extends through multiple electrode layers 110 and multiple insulating dielectric layers 120 . Multiple capacitors 410 can share a single first electrode 130 . This simplifies the layout of plate lines PL. While only a 1T1C (1 Transistor 1 Capacitor) memory architecture is described here, it's readily understood that memory array 100 can also employ 1TnC, 2TnC, and other memory architectures.

[0053] In some embodiments, the storage layer 134 may include a ferroelectric film. For example, the ferroelectric film may be a hafnium oxide-based ferroelectric film. The hafnium oxide-based ferroelectric film not only has a wide band gap but is also compatible with CMOS processes. At the same time, when the thickness of the hafnium oxide-based ferroelectric film is reduced to below 10 nm, it still has excellent ferroelectric properties. Therefore, the storage array 100 in which the storage layer 134 includes a ferroelectric film has the advantages of low power consumption and good cycle characteristics.

[0054] When the storage layer 134 comprises a ferroelectric thin film, to read data from the capacitor 410, the transistor is turned on and a read voltage, which can be in the form of an electric pulse, is applied to the storage layer 134 via the first electrode 130 and the electrode layer 110. If the direction of the electric field generated between the first electrode 130 and the electrode layer 110 is the same as the polarization direction of the storage layer 134, the polarization direction of the storage layer 134 remains unchanged; if the direction of the electric field is the same as the polarization direction of the storage layer 134, the polarization direction of the storage layer 134 is reversed. In these two cases, the capacitor 410 will output different electrical signals. By detecting these signals, the polarization direction of the storage layer 134 can be determined, and the data stored in the capacitor 410 can be obtained. Furthermore, since the polarization direction of the storage layer 134 remains consistent with the direction of the electric field generated by the read voltage after the data is read, in some cases, it may be necessary to rewrite the data after reading, even if the polarization direction of the storage layer 134 is restored to the direction before the data was read.

[0055] When writing data to capacitor 410, the transistor is turned on, and a voltage level is applied between first electrode 130 and electrode layer 110. When the voltage levels applied between first electrode 130 and electrode layer 110 are in different directions, electric fields with different directions are generated between first electrode 130 and electrode layer 110. This electric field can cause the polarization direction of storage layer 134 to be the same as the voltage level, thereby controlling the polarization direction of storage layer 134. The different polarization directions of storage layer 134 can be used to indicate whether the stored data is "0" or "1," thereby achieving data writing.

[0056] The performance of the memory array 100 can be improved by increasing the ferroelectricity of the memory layer 134. For example, an intercalation layer can be provided on one or both surfaces of the memory layer 134 to increase the ferroelectricity of the ferroelectric film and enhance read and write performance. For example, referring again to FIG. 3 , a first intercalation layer 132 can be provided on the surface of the memory layer 134 on the side closest to the electrode layer 110.

[0057] However, the first intercalation layer 132 may not be completely insulating. Moreover, since the first intercalation layer 132 penetrates the multiple electrode layers 110 and the multiple insulating dielectric layers 120 that are alternately stacked along the X direction, the first intercalation layer 132 may form a conductive channel between the multiple electrode layers 110, resulting in a short circuit between the multiple electrode layers 110. As a result, when performing read and write operations on a certain capacitor 410, the ferroelectric switching of the corresponding storage layer 134 cannot reach an ideal state, and may cause interference to the storage layers 134 of other capacitors 410, making it impossible to achieve accurate read and write operations, thereby affecting the performance of the storage device.

[0058] 4 , some embodiments of the present application provide a memory array 100 , which includes a plurality of electrode layers 110 , a plurality of insulating dielectric layers 120 , a first electrode 130 , a memory layer 134 , and a first insertion layer 132 .

[0059] Multiple electrode layers 110 and multiple insulating dielectric layers 120 are alternately stacked, that is, an insulating dielectric layer 120 is provided between adjacent electrode layers 110. Exemplarily, multiple electrode layers 110 and multiple insulating dielectric layers 120 may be alternately stacked on a substrate. Multiple electrode layers 110 and multiple insulating dielectric layers 120 may extend in a plane parallel to the YZ plane. Exemplarily, the stacking direction of multiple electrode layers 110 and multiple insulating dielectric layers 120 is along the X direction. For ease of explanation, the following examples are all based on the stacking direction along the X direction. The material of the electrode layer 110 may be a metal or a metal compound, such as titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc. The insulating dielectric layer 120 may be made of silicon oxide (SiO), aluminum oxide (AlO), silicon nitride (SiN), or the like.

[0060] The first electrode 130 passes through the multiple electrode layers 110 and the multiple insulating dielectric layers 120. For example, the first electrode 130 may extend along the X direction. The cross-section of the first electrode 130 parallel to the YZ plane may be circular, elliptical, or polygonal. The material of the first electrode 130 may also be a metal or a metal compound. The material of the first electrode 130 may be the same as or different from the material of the electrode layer 110. The first electrode 130 may also include multiple layers. For example, the first electrode 130 includes a contact layer and a metal layer (not shown in the figure), wherein the material of the contact layer may be TiN, and the material of the metal layer may be W. The contact layer can improve the conductivity between the metal layer and the semiconductor material.

[0061] The storage layer 134 surrounds the first electrode 130 and can be made of a ferroelectric material. For example, along the X direction, the storage layer 134 can penetrate the multiple electrode layers 110 and the multiple insulating dielectric layers 120. In this way, the storage layer 134 can be formed directly through a deposition process, reducing the number of process steps required to form the storage layer 134. Exemplarily, the material of the storage layer 134 is a hafnium oxide-based ferroelectric material, for example, may include one or more of hafnium zirconium oxide (HZO), La-doped HZO, Ti-doped HZO, Y-doped HZO, Sr-doped HZO, Gd-doped HZO, Ce-doped HZO, Nb-doped HZO, Ti and La co-doped HZO, Ti and Nb co-doped HZO, Gd and La co-doped HZO, Si-doped HfO2, Al-doped HfO2, La-doped HfO2, Y-doped HfO2, Gd-doped HfO2, Ce-doped HfO, Nb-doped HfO, and Sr-doped HfO2.

[0062] The first interlayer 132 surrounds the storage layer 134 and is disposed between the electrode layer 110 and the storage layer 134, that is, the electrode layer 110 also surrounds the first interlayer 132. Exemplarily, through holes along the X direction are provided on the electrode layer 110, and the first interlayer 132 can be formed in the through holes by a deposition process, so as to achieve the electrode layer 110 surrounding the first interlayer 132. The first interlayer 132 includes a plurality of first sub-interlayers 131 spaced along the X direction. Exemplarily, the first interlayer 132 can be disposed between two adjacent insulating dielectric layers 120.

[0063] In this way, a plurality of capacitors 410 are formed along the X direction. The capacitor 410 can include an electrode layer 110, the first sub-interlayer 131 surrounded by the electrode layer 110, and a part of the first electrode 130 and the storage layer 134 surrounded by the first sub-interlayer 131. The plurality of first sub-interlayers 131 are spaced apart. Since the first sub-interlayers 131 of the plurality of capacitors 410 are spaced from each other, it is possible to avoid the existence of a current path between the plurality of electrode layers 110 due to the conductivity of the first sub-interlayer 131, and to avoid the mutual influence between the capacitors 410 during the reading and writing processes.

[0064] In addition, since the plurality of first sub-interlayers 131 are spaced apart, a current path will not be formed between the plurality of electrode layers 110 due to the conductivity of the first sub-interlayer 131. That is to say, the spaced arrangement of the plurality of first sub-interlayers 131 can reduce the limitation on the conductivity of the material of the first interlayer 132, which is beneficial to selecting a suitable material for the first interlayer 132, thereby increasing the ferroelectricity of the storage layer 134. Exemplarily, the material of the first interlayer 132 can include one or more materials, and these materials can be metals, oxides, nitrides, oxynitrides. For example, the metal materials can include W, Mo, Pt, Pd, etc., and the oxide materials can include TiO2, Nb2O5, Ta2O5, WO x (0 < x < 3), Al2O3, MgO, CeO2, NbTiO, NbTaO, NbCeO, NbHfO, NbLaO, NbZrO, ITO, STO, LSMO, IGZO, etc., and the nitride materials can include TiN, TaN, HfN, ZrN, WN, AlN, TiSiN, TiAlN, TaSiN, TaAlN, TiCN, etc., and the oxynitride materials can include TiON, SiON, etc.

[0065] In some embodiments, along the X direction, the first intercalation layer 132 includes multiple first sub-intercalation layers 131 and multiple insulating dielectric layers 120 arranged alternately. That is, along the X direction, an insulating dielectric layer 120 is provided between any two adjacent first sub-intercalation layers 131, and a first sub-intercalation layer 131 is provided between any two adjacent insulating dielectric layers 120. In this way, the density of the stacked capacitors 410 in the X direction can be increased.

[0066] In some embodiments, the storage layer 134 extends longitudinally along the X-direction, and both the first sub-intercalation layer 131 and the insulating dielectric layer 120 are in contact with the storage layer 134. If the side surfaces of the plurality of first sub-intercalation layers 131 close to the first electrode 130 are defined as the first side surfaces 151, and the side surfaces of the insulating dielectric layer 120 close to the first electrode 130 are defined as the second side surfaces 152, then the first side surfaces 151 are in contact with the storage layer 134, and the second side surfaces 152 are also in contact with the storage layer 134. For example, the first side surfaces 151 may be flush with the second side surfaces 152. For example, the first side surfaces 151 may be further away from the first electrode 130 than the second side surfaces 152. This increases the thickness of a portion of the storage layer 134 surrounded by the first sub-intercalation layers 131 and located between the upper and lower surfaces of the first sub-intercalation layers 131, thereby facilitating miniaturization of the capacitor 410 and improving the integration density of the memory array 100. Furthermore, the above two configurations of the first side surface 151 and the second side surface 152 can ensure that the first sub-intercalation layers 131 are disposed at intervals, thereby preventing a current path from being formed between adjacent electrode layers 110 .

[0067] Referring to Figure 5 , in some embodiments, the cross-section of the first sub-intercalation layer 131 along a direction perpendicular to the X-direction is annular. For example, the cross-section may be a polygonal ring, a circular ring, or an elliptical ring. Exemplarily, the shape of the inner and outer boundaries of the cross-section of the first sub-intercalation layer 131 is the same as the cross-section of the first electrode 130 along a direction perpendicular to the X-direction. For example, if the cross-section of the first electrode 130 is circular, the cross-section of the first sub-intercalation layer 131 is annular. Exemplarily, the cross-sections of the multiple first sub-intercalation layers 131 arranged along the X-direction and surrounding the same first electrode 130 are the same.

[0068] Referring to Figure 6 , in some embodiments, the first sub-intercalation layer 131 may include multiple film layers, which may interact with each other, thereby facilitating adjustment of the stress exerted by the multiple film layers on the storage layer 134, thereby improving the ferroelectricity of the storage layer 134 and the read / write performance of the memory array 100. For example, the first sub-intercalation layer 131 includes a first film layer 132a and a second film layer 132b . Both the first film layer 132a and the second film layer 132b surround the storage layer 134, and the first film layer 132a is further away from the first electrode 130 than the second film layer 132b.

[0069] The materials of the first film layer 132a and the second film layer 132b may be the same or different. When the first film layer 132a and the second film layer 132b are disposed adjacent to each other, the materials of the first film layer 132a and the second film layer 132b are different. When there are other film layers between the first film layer 132a and the second film layer 132b, the materials of the first film layer 132a and the second film layer 132b may be the same or different. For example, the material of the first film layer 132a and the second film layer 132b may include one of NbO, TiO, NbO, LaO, SiN, WO, MoO, NbN, TaO, NbO, and WN.

[0070] Referring to Figure 7, in some embodiments, the storage layer 134 may also include a plurality of sub-storage layers 134 spaced apart. Along the X direction, the plurality of sub-storage layers 133 may be alternately arranged with the plurality of insulating dielectric layers 120. That is, along the X direction, an insulating dielectric layer 120 is provided between any two adjacent storage layers 134, and a storage layer 134 is provided between any two adjacent insulating dielectric layers 120. Exemplarily, the sub-storage layers 134 and the first sub-intercalation layers 131 are provided in a one-to-one correspondence, that is, each first sub-intercalation layer 131 corresponds to a sub-storage layer 134. The first sub-intercalation layer 131 and the corresponding sub-storage layer 134 may have the same size along the X direction. In this way, the storage layer 134 of each capacitor 410 is separated from the storage layers 134 of other capacitors 410, thereby avoiding mutual influence between the storage layers 134 of adjacent capacitors 410 and improving the accuracy of reading and writing data.

[0071] 4 and 8 , in some embodiments, to further enhance the ferroelectricity of the memory layer 134, the memory array 100 may further include a second intercalation layer 136. The second intercalation layer 136 surrounds the first electrode 130, and the memory layer 134 surrounds the second intercalation layer 136. In other words, the second intercalation layer 136 is disposed between the first electrode 130 and the second intercalation layer 136.

[0072] For example, as shown in FIG. 4 , the second insertion layer 136 may extend along the X direction and penetrate the plurality of stacked electrode layers 110 and insulating dielectric layers 120 .

[0073] For example, as shown in FIG8 , the second intercalation layer 136 may also include a plurality of second sub-intercalation layers 135 spaced apart. Along the X-direction, the plurality of sub-storage layers 133 may be arranged alternately with the plurality of insulating dielectric layers 120. That is, along the X-direction, an insulating dielectric layer 120 is disposed between any two adjacent second sub-intercalation layers 135, and a second sub-intercalation layer 135 is disposed between any two adjacent insulating dielectric layers 120. In this case, one second sub-intercalation layer 135 may be disposed correspondingly to one sub-storage layer 134 and one first sub-intercalation layer 131, that is, one second sub-intercalation layer 135, one sub-storage layer 134, and one first sub-intercalation layer 131 may be disposed simultaneously between any two adjacent insulating dielectric layers 120. Furthermore, along a direction perpendicular to the X-direction, the cross-sections of the second sub-intercalation layer 135, the sub-storage layer 134, and the first sub-intercalation layer 131 may all be annular, and the second sub-intercalation layer 135, the sub-storage layer 134, and the first sub-intercalation layer 131 may be nested sequentially from the inside out.

[0074] In addition, this application also proposes a method for preparing a memory array 100. The materials used in preparing the various components of the memory array 100 in this method can be found in the aforementioned disclosure. See Figure 9 for a flow chart of this method. The specific steps of this method are described below in conjunction with Figures 10 to 18.

[0075] S100 , referring to FIG. 10 , a plurality of electrode layers 110 and a plurality of insulating dielectric layers 120 that are alternately stacked are formed.

[0076] The insulating dielectric layer 120 and the electrode layer 110 can be sequentially and cyclically formed on a substrate (not shown) using a deposition process, thereby forming a plurality of electrode layers 110 and a plurality of insulating dielectric layers 120 alternately stacked on the substrate, with the stacking direction being along the X-direction. For example, the insulating dielectric layer 120 can be made of silicon oxide, which can be deposited using a chemical vapor deposition (CVD) process to form the insulating dielectric layer 120. The electrode layer 110 can be made of tungsten, which can be deposited using a physical vapor deposition (PVD) process to form the electrode layer 110.

[0077] The substrate may be formed of silicon, or may be formed of other Group III, Group IV, and / or Group V elements (e.g., silicon, germanium, gallium, arsenic, and combinations thereof). The substrate may also be in the form of a silicon-on-insulator (SOI) substrate. A SOI substrate may include a layer of semiconductor material (e.g., silicon, germanium, and / or the like) formed on an insulator layer (e.g., buried oxide and / or the like), the insulator layer being formed on a bulk silicon substrate.

[0078] In some embodiments, transistors may be formed on the substrate. After a memory array is formed, the transistors may be used to control read and write operations on capacitors in the memory array.

[0079] S200 , referring to FIG. 11 , a through hole 140 is formed. The through hole 140 penetrates the plurality of electrode layers 110 and the plurality of insulating dielectric layers 120 .

[0080] The through hole 140 can be formed by using a photolithography process and an etching process. For example, a mask layer and a photoresist can be sequentially formed on the substrate, and a pattern can be formed on the photoresist by a photolithography process. The pattern defines the position and shape of the through hole 140. The pattern is then transferred to the mask layer, and a portion of the material of the electrode layer 110 and the insulating dielectric layer 120 in the exposed area is removed by an etching process, thereby forming the through hole 140. The through hole 140 here refers to a through hole that passes through multiple electrode layers 110 and multiple insulating dielectric layers 120, and does not necessarily pass through the substrate. In other words, the through hole 140 may pass through the substrate or not. The direction of the through hole 140 may be along the X direction or not along the X direction, as long as it passes through multiple electrode layers 110 and multiple insulating dielectric layers 120. The etching process can use a plasma etching process.

[0081] S300 , referring to FIG. 12 , a portion of the electrode layer 110 is removed through the through hole 140 , so that the electrode layer 110 is recessed relative to the insulating dielectric layers 120 adjacent to both sides of the electrode layer 110 to form a groove 141 .

[0082] Based on the difference between the materials of the electrode layer 110 and the insulating dielectric layer 120, a selective etching process can be used to remove a portion of the electrode layer 110 through the through hole 140. This selective etching process can remove only the material of the electrode layer 110 without removing the material of the insulating dielectric layer 120, or the electrode layer 110 can be removed at a faster rate than the insulating dielectric layer 120. In this way, the electrode layer 110 can be recessed relative to the insulating dielectric layers 120 adjacent to both sides of the electrode layer 110, thereby forming the groove 141.

[0083] S400 , referring to FIG. 14 , a first intercalation layer 132 is formed. The first intercalation layer 132 includes a plurality of first sub-intercalation layers 131 spaced apart along the X direction. The first sub-intercalation layers 131 are formed in the grooves 141 .

[0084] In some embodiments, forming the first intercalation layer 132 may include the following steps:

[0085] S401 , referring to FIG. 13 , an initial first intercalation layer 142 is formed in the through hole 140 . The initial first intercalation layer 142 fills the groove 141 and covers the side surfaces of the plurality of insulating dielectric layers 120 .

[0086] An initial first intercalation layer 142 can be formed in the through-hole 140 and fill the groove 141 through a deposition process. The material of the deposited initial first intercalation layer 142 can completely fill the groove 141 and protrude from the insulating dielectric layer 120 adjacent to both sides of the groove 141. Alternatively, the material of the deposited initial first intercalation layer 142 may not completely fill the groove 141. The deposition of the initial first intercalation layer 142 can be performed using an atomic layer deposition process or a chemical vapor deposition process. As will be readily understood, the chemical vapor deposition process is faster than the atomic layer deposition process in forming the initial first intercalation layer 142, thereby improving production efficiency.

[0087] In addition, regardless of whether the deposited initial first intercalation layer 142 material fills the groove 141 , the initial first intercalation layer 142 material may be formed on the side surface of the insulating dielectric layer 120 , that is, the initial first intercalation layer 142 covers the side surface of the insulating dielectric layer 120 .

[0088] S402 , referring to FIG. 14 , remove the portion of the initial first intercalation layer 142 covering the side surfaces of the plurality of insulating dielectric layers 120 , and the portion of the initial first intercalation layer 142 remaining in the groove 141 forms a plurality of first sub-intercalation layers 131 .

[0089] Because the deposited initial first intercalation layer 142 extends continuously along the X-direction, in order to form the multiple spaced-apart first sub-intercalation layers 131, it is necessary to remove the portion of the initial first intercalation layer 142 covering the side surfaces of the insulating dielectric layer 120. After this removal, only the portion of the initial first intercalation layer 142 within the grooves 141 remains. The portion within each groove 141 forms a first sub-intercalation layer 131, and the multiple first sub-intercalation layers 131 arranged along the X-direction form the first intercalation layer 132. Exemplarily, a plasma etching process can be used to remove portions of the initial first intercalation layer 142.

[0090] In some embodiments, the first intercalation layer 132 may include a first film layer 132a and a second film layer 132b. In this case, forming the first intercalation layer 132 may include the following steps:

[0091] S411, please refer to Figure 16, an initial first film layer 142a is formed in the through hole 140, the initial first film layer 142a fills the groove 141, and covers the sides of multiple insulating dielectric layers 120, and the portion of the initial first film layer 142a covering the sides of multiple insulating dielectric layers 120 is removed, and the portion of the initial first film layer 142a remaining in the groove forms multiple first film layers 132a.

[0092] Referring to FIG. 15 , when initial first film layer 142a is formed in through-hole 140, the thickness of initial first film layer 142a is relatively thin. Therefore, the deposited material of initial first film layer 142a does not completely fill recess 141. However, the formed initial first film layer 142a still covers the side surfaces of insulating dielectric layer 120. As will be readily understood, due to the relatively thin thickness of initial first film layer 142a, initial first film layer 142a may not be formed on the upper surface of recess 141. In other words, initial first film layer 142a may not be formed on the lower surface of insulating dielectric layer 120 exposed by recess 141.

[0093] 16 , after the initial first film layer 142 a is formed, the portion of the initial first film layer 142 a covering the side surfaces of the plurality of insulating dielectric layers 120 may be removed by an anisotropic etching process, thereby forming the first film layer 132 a .

[0094] S412, please refer to Figure 18, an initial second film layer 142b is formed in the through hole 140, the initial second film layer 142b fills the groove 141, and covers the sides of multiple insulating dielectric layers 120, and the portion of the initial second film layer 142b covering the sides of multiple insulating dielectric layers 120 is removed, and the portion of the initial second film layer 142b remaining in the groove 141 forms multiple second film layers 132b.

[0095] Similarly, referring to FIG. 17 , a deposition process continues to form an initial second film layer 142b in the through-hole 140 and fill the recess 141. After removing the portion of the initial second film layer 142b covering the sides of the multiple insulating dielectric layers 120, the second film layer 132b is formed. Thus, the first film layer 132a and the second film layer 132b are simultaneously formed in the same recess 141. The first film layer 132a and the second film layer 132b in the same recess 141 form the first sub-intercalation layer 131. Furthermore, the multiple first sub-intercalation layers 131 arranged along the X-direction constitute the first intercalation layer 132.

[0096] In some embodiments, the first intercalation layer 132 may be formed using a selective atomic layer deposition process. That is, the first sub-intercalation layer 131 may be formed only in the groove 141 through the atomic layer deposition process. That is, when the first intercalation layer 132 is formed through the selective atomic layer deposition process, the deposited material of the first intercalation layer 132 is formed only in the groove 141 and not on the side of the insulating dielectric layer 120. For example, the interface conditions on the side of the electrode layer 110 may be changed so that, during the selective atomic layer deposition process, the reactive gas is adsorbed only on the side of the electrode layer 110, and the material of the first intercalation layer 132 deposited through the reaction is also formed only on the side of the electrode layer 110, thereby directly forming the first sub-intercalation layer 131 through the selective atomic layer deposition process.

[0097] Since the plurality of grooves 141 are spaced apart along the X direction, the plurality of first sub-intercalation layers 131 formed in the plurality of grooves 141 are also spaced apart along the X direction, so that the plurality of first sub-intercalation layers 131 arranged along the X direction constitute the first intercalation layer 132 .

[0098] S500 , referring to FIG. 4 , a storage layer 134 and a first electrode 130 are sequentially formed in the through hole 140 , and the storage layer 134 surrounds the first electrode 130 .

[0099] After forming the first intercalation layer 132, the memory layer 134 and the first electrode 130 can be sequentially formed in the through-hole 140. By forming the memory layer 134 first and then the first electrode 130, the memory layer 134 can surround the first electrode 130. When the first electrode 130 includes multiple materials, these materials can be formed separately using a deposition process. For example, when the first electrode 130 includes both TiN and tungsten, TiN can be deposited first, followed by tungsten.

[0100] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: Multiple electrode layers and multiple insulating medium layers are alternately stacked; a first electrode passing through the plurality of electrode layers and the plurality of insulating dielectric layers; a storage layer surrounding the first electrode; The first intercalation layer includes a plurality of first sub-intercalation layers spaced apart along a stacking direction, wherein the first sub-intercalation layers surround the storage layer and are disposed between the electrode layer and the storage layer.

2. The storage array according to claim 1, wherein: Along the stacking direction, the plurality of insulating dielectric layers and the plurality of first sub-intercalation layers are arranged alternately.

3. The storage array according to claim 1 or 2, wherein: The side of the multiple first sub-intercalation layers close to the first electrode is the first side, and the side of the insulating dielectric layer close to the first electrode is the second side. The first side is flush with the second side, or the first side is farther away from the first electrode than the second side.

4. The storage array according to any one of claims 1 to 3, wherein: The cross section of the first sub-intercalation layer along the direction perpendicular to the stacking direction is in the shape of a polygonal ring, a circular ring or an elliptical ring.

5. The storage array according to any one of claims 1 to 4, wherein: The material of the first intercalation layer includes one or more of metal, oxide, nitride, and oxynitride.

6. The storage array according to any one of claims 1 to 5, wherein: The first intercalation layer includes a first film layer and a second film layer. Both the first film layer and the second film layer surround the storage layer, and the first film layer is farther away from the first electrode than the second film layer.

7. The storage array according to claim 6, wherein: The materials of the first film layer and the second film layer include one of NbO, TiO, NbO, LaO, SiN, WO, MoO, NbN, TaO, NbO, and WN, and the materials of the first film layer and the second film layer are different.

8. The storage array according to any one of claims 1 to 7, wherein: The storage layer includes a plurality of sub-storage layers, and along the stacking direction, the plurality of sub-storage layers and the plurality of insulating dielectric layers are arranged alternately.

9. The storage array according to claim 8, wherein: Also included is a second intercalation layer disposed between the storage layer and the first electrode, the second intercalation layer surrounding the first electrode; The second intercalation layer includes a plurality of second sub-intercalation layers. Along the stacking direction, the plurality of second sub-intercalation layers and the plurality of insulating dielectric layers are arranged alternately.

10. The storage array according to any one of claims 1 to 7, wherein: Along the stacking direction, the storage layer penetrates the multiple electrode layers and the multiple insulating dielectric layers.

11. A method for preparing a memory array, characterized in that: include: forming a plurality of electrode layers and a plurality of insulating dielectric layers that are alternately stacked; forming a through hole, wherein the through hole penetrates the plurality of electrode layers and the plurality of insulating dielectric layers; removing a portion of the electrode layer through the through hole, so that the electrode layer is recessed relative to the insulating dielectric layers adjacent to both sides of the electrode layer to form a groove; forming a first intercalation layer, wherein the first intercalation layer includes a plurality of first sub-intercalation layers spaced apart along a stacking direction, and the first sub-intercalation layers are formed in the groove; A storage layer and a first electrode are sequentially formed in the through hole, and the storage layer surrounds the first electrode.

12. The preparation method according to claim 11, characterized in that The forming of the first intercalation layer comprises: forming an initial first intercalation layer in the through hole, wherein the initial first intercalation layer fills the groove and covers the side surfaces of the plurality of insulating dielectric layers; The portion of the initial first intercalation layer covering the side surfaces of the plurality of insulating dielectric layers is removed, and the portion of the initial first intercalation layer remaining in the groove forms the plurality of first sub-intercalation layers.

13. The preparation method according to claim 11, wherein The first intercalation layer includes a first film layer and a second film layer, and forming the first intercalation layer includes: An initial first film layer is formed in the through hole, the initial first film layer fills the groove and covers the plurality of insulating dielectric layers. side, removing a portion of the initial first film layer on the side covering the multiple insulating dielectric layers, and forming the multiple first sub-film layers with a portion of the initial first film layer remaining in the groove; forming an initial second film layer in the through hole, the initial second film layer filling the groove and covering the side surfaces of the plurality of insulating dielectric layers, removing portions of the initial second film layer covering the side surfaces of the plurality of insulating dielectric layers, and forming the plurality of second sub-film layers with portions of the initial second film layer remaining in the groove; The first sub-membrane layer and the second sub-membrane layer in the same groove form the first sub-intercalation layer.

14. The preparation method according to any one of claims 11 to 13, characterized in that The process of forming the first intercalation layer includes an atomic layer deposition process or a chemical vapor deposition process.

15. A storage device, characterized in that: include: A controller and the storage array according to any one of claims 1 to 10, wherein the storage array is electrically connected to the controller.

16. An electronic device, characterized in that: The device comprises the storage device according to claim 15 and a printed circuit board, wherein the storage device is electrically connected to the printed circuit board.

Images