Semiconductor device, semiconductor device packaging structure and electronic apparatus

Abstract

Provided in the present application are a semiconductor device, a semiconductor device packaging structure, a preparation method for a semiconductor device, and an electronic apparatus. The present application relates to the technical field of deep-trench capacitors of semiconductors. Provided is a deep-trench capacitor structure which can reduce the number of instances of photolithography and etching. The semiconductor device comprises a substrate and a capacitor disposed in the substrate, wherein a plurality of trenches are provided in the substrate, the plurality of trenches having different widths; wider trenches can serve as functional trenches for accommodating electrodes and a capacitive dielectric layer of the capacitor, and narrower trenches can accommodate some electrodes, that is, by means of providing the trenches having different widths, the electrodes in the different trenches have different thicknesses; thus, after a single instance of photolithography and etching, the electrodes in the narrow trenches can be exposed. Compared with multiple instances of photolithography and etching, the present application can significantly reduce the number of instances of photolithography and etching, and especially, when the number of electrode layers increases, the advantage of simplifying the process preparation flow becomes more prominent.

Description

Semiconductor devices, semiconductor device packaging structures, electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 19, 2024, with application number 202410186840.5 and invention name “Semiconductor device, semiconductor device packaging structure, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a packaging structure including a semiconductor device, an electronic device, and a method for preparing a semiconductor device. Background Art

[0003] In semiconductor device circuits, capacitors have the characteristics of blocking DC, passing AC, and blocking low frequencies, thus playing an important role in circuit coupling, bypass decoupling, tuning, and frequency stabilization.

[0004] Compared with planar capacitors, deep trench capacitors have the advantage of being compatible with semiconductor processing technology and have higher capacitance. For example, they can bring better tuning performance to the chip.

[0005] To further enhance semiconductor device performance, capacitance density can be increased, leading to a continuous increase in the number of dielectric and electrode layers in deep trench capacitor structures. This increase in the number of dielectric and electrode layers increases the number of photolithography, etching, and other related processes, sometimes even doubling the process flow. This not only complicates the manufacturing process but also reduces product yield, limiting the improvement of deep trench capacitor capacitance density.

[0006] Summary of the Invention

[0007] The present application provides a semiconductor device including a deep trench capacitor, a method for manufacturing the semiconductor device, a packaging structure including the semiconductor device, and an electronic device. The purpose is to provide a novel deep trench capacitor structure that reduces the number of photolithography steps required for manufacturing the capacitor. Multiple electrodes can be exposed through a single photolithography step, significantly reducing the number of process steps and compressing the manufacturing process.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] On the one hand, the present application provides a semiconductor device, which may be a transfer board including a passive device capacitor, or a chip including a capacitor.

[0010] The semiconductor device includes a substrate and a circuit layer disposed on the substrate; the semiconductor device also includes a capacitor, which includes multiple electrodes, such as a first electrode and a second electrode, and a capacitor dielectric layer. A first groove, a second groove, and a third groove are provided in the substrate. The arrangement direction of the first groove, the second groove, and the third groove is parallel to the surface of the substrate, and adjacent two grooves of the first groove, the second groove, and the third groove are connected. Some of these grooves are used to set capacitors, that is, the capacitors in the examples of this application are deep trench capacitors.

[0011] The width of the first and third slots is smaller than that of the second slot, and the width of the first slot is larger than that of the third slot. The slot width is the dimension perpendicular to the length of the slot. The first and second slots include stacked first and second electrodes, and a capacitor dielectric layer located between the first and second electrodes, with the first electrode being closer to the inner wall of the slot than the second electrode. The third slot includes the first electrode. The circuit layer includes a first conductive via and a second conductive via. The first conductive via extends through the second electrode in the first slot and is electrically connected to the second electrode in the first slot. The second conductive via extends through the first electrode in the third slot and is electrically connected to the first electrode in the third slot.

[0012] In the above structure, the second slot with a larger slot width is filled with multiple electrodes and a capacitor dielectric layer of the capacitor to contribute to the capacitance density; the third slot with a narrower slot width is filled with one electrode of the capacitor, which can be connected to the lead-out electrode through a conductive via. Another electrode in the first slot with a narrower slot width can also be connected to the lead-out electrode through a conductive via. It can be understood that this application uses a wide slot to accommodate the capacitor and a narrow slot to lead out the capacitor electrode.

[0013] When preparing the above-mentioned deep trench capacitor, multiple trenches of different widths can be prepared. After multiple electrodes and capacitor dielectric layers are prepared in the trenches of different widths, the thickness of the electrodes in different trenches can be made inconsistent. For example, the third trench with a narrower trench width will be filled with one first electrode, and the first trench with a narrower trench width will be filled with two electrodes and the capacitor dielectric layer. In this way, the second electrode in the first trench and the first electrode in the third trench can be fully exposed through a single photolithography etching process. Compared with the existing photolithography etching process of at least two times, the number of etchings can be reduced, simplifying the process flow. In some deep trench capacitors, when more electrodes are included, for example, 5 electrodes or even more electrodes, multiple electrodes can still be exposed through a single photolithography etching process, and the simplified process flow is more obvious.

[0014] In one achievable manner, the length of the first groove and the length of the third groove are both smaller than the length of the second groove.

[0015] In this example, the width of the first groove and the width of the third groove are both smaller than the width of the second groove, and the length of the first groove and the length of the third groove are both smaller than the length of the second groove. In a feasible process, when preparing the first electrode, the third groove with the smallest groove area is first filled with the first electrode, and the first groove with a smaller groove area is filled with the first electrode, the capacitor dielectric layer and the second electrode. In this way, through one photolithography etching, the first electrode in the third groove and the second electrode in the first groove can be completely exposed.

[0016] In one achievable manner, in the thickness direction of the substrate, the groove depth of the first groove and the groove depth of the third groove are both smaller than the groove depth of the second groove, and the groove depth of the first groove is greater than the groove depth of the third groove.

[0017] In one achievable manner, the thickness of the first electrode in the third groove is greater than the thickness of the first electrode in the second groove; the thickness of the first electrode in the second groove is equal to the thickness of the first electrode in the first groove; the thickness is the dimension along the groove width direction.

[0018] By setting different groove widths, different groove depths, and different groove lengths, the thickness of the electrodes can be made inconsistent. In this way, each electrode in the narrow groove can be exposed through a single photolithography etching.

[0019] In one possible implementation, the second groove is located between the first groove and the third groove, and the first groove and the second groove are communicated with each other, and the second groove and the third groove are communicated with each other.

[0020] In some other examples, the first slot, the second slot, and the third slot may be arranged in other arrangements, for example, the third slot is located between the first slot and the second slot.

[0021] In one achievable manner, the second electrode in the second slot is connected to the second electrode in the first slot to form an integral body, and the first conductive through-hole is connected to the integrated second electrode.

[0022] There is no need to provide a conductive through-hole on the second slot, and the second electrode of the capacitor can be led out through the conductive through-hole in the first slot.

[0023] In one possible implementation, there are multiple second grooves, which are arranged along a first direction parallel to the substrate surface. The second grooves extend along a second direction parallel to the substrate surface, and the first direction is perpendicular to the second direction. The first groove is located at one end of the second groove, and the third groove is located at the other end of the second groove.

[0024] In one possible implementation, a plurality of second grooves are arranged along the second direction; the plurality of second grooves arranged along the first direction are a first array, and the plurality of second grooves arranged along the second direction are a second array; the first array is arranged between two adjacent second arrays; a first groove is arranged between one of the two adjacent second arrays and the first array, and a third groove is arranged between the other of the two adjacent second arrays and the first array.

[0025] In this implementation structure, the narrow slot is arranged between two adjacent wide slot arrays, making full use of the space between the wide slot arrays and improving the capacitance density.

[0026] In one possible implementation, there are multiple second grooves, and the multiple second grooves are arranged along a first direction parallel to the substrate surface. The second grooves extend along a second direction parallel to the substrate surface. The first groove and the third groove are arranged along the second direction. The first groove and the third groove both extend along the first direction, and the first direction is perpendicular to the second direction. The first groove connects two adjacent second grooves, and the third groove connects two adjacent second grooves.

[0027] In this implementation structure, the narrow slots are arranged in the wide slot array to fully utilize the space of the wide slot array. In this way, more wide slot arrays can be integrated on a unit area of ​​the substrate, thereby improving the capacitance density.

[0028] In one possible implementation, multiple second grooves are arranged along the second direction; the multiple second grooves arranged along the first direction are a first array, and the multiple second grooves arranged along the second direction are a second array; the first array and the second array are separated by a substrate.

[0029] Since each adjacent array is isolated by the substrate, each array works independently, and the utilization yield of the capacitor can be improved.

[0030] In one achievable method, the capacitor further includes a third electrode and a second capacitor dielectric layer; a fourth groove and a fifth groove are further provided in the substrate, the groove width of the fifth groove and the groove width of the first groove are both smaller than the groove width of the fourth groove, and the groove width of the fifth groove is larger than the groove width of the first groove; the fifth groove, the fourth groove and the second groove include a first electrode, a second electrode and a third electrode stacked in sequence, and a first capacitor dielectric layer located between the first electrode and the second electrode, and a second capacitor dielectric layer located between the second electrode and the third electrode, the first electrode being closer to the inner wall of the groove than the second electrode; the circuit layer further includes a third conductive through-hole, the third conductive through-hole passes through to the third electrode in the fifth groove and is electrically connected to the third electrode.

[0031] The above example shows a deep trench capacitor with three electrodes. The capacitors in the second and fourth trenches primarily contribute to the capacitance density, while the first, third, and fifth trenches are used to lead out the electrodes. In this example, by providing trenches of varying widths, all electrodes in the narrow trenches can be exposed in a single photolithography process, reducing the number of photolithography steps and simplifying the fabrication process.

[0032] In one possible implementation, the fifth groove, the fourth groove, the first groove, the second groove, and the third groove are arranged in sequence along a direction parallel to the surface of the substrate, and every two adjacent grooves among the fifth groove, the fourth groove, the first groove, the second groove, and the third groove are connected.

[0033] In one achievable manner, in a direction from the fifth groove to the third groove, the groove width of the fifth groove, the groove width of the first groove, and the groove width of the third groove decrease in sequence.

[0034] In one achievable manner, the width of the second groove is equal to the width of the fourth groove.

[0035] It can be understood that, in some examples, the widths of the slots that primarily contribute to the capacitance density may be equal.

[0036] In one achievable manner, in a direction from the fifth groove to the third groove, in a thickness direction of the substrate, the groove depth of the fifth groove, the groove depth of the first groove, and the groove depth of the third groove decrease in sequence.

[0037] In one achievable manner, the thickness of the first electrode in the third groove is greater than the thickness of the first electrode in the first groove and the fifth groove; the thickness of the second electrode in the first groove is greater than the thickness of the second electrode in the fifth groove, and the thickness is the dimension along the groove width direction.

[0038] In this way, after one photolithography etching, all electrodes in the narrow groove that need to be electrically connected to the lead-out electrode can be exposed.

[0039] In one possible implementation, the semiconductor device is a transfer board, or the semiconductor device is a chip.

[0040] On the other hand, the present application also provides a semiconductor device packaging structure, which includes a substrate and a semiconductor device in any of the above implementations, wherein the semiconductor device is arranged on the substrate.

[0041] In the semiconductor device packaging structure provided in the present application, since groove structures of different widths are set in the semiconductor device, after depositing each electrode and capacitor dielectric layer, the electrodes in the narrow grooves can be completely exposed through a single photolithography and etching process. In this way, the electrodes in the narrow grooves can be electrically connected to the lead-out electrodes, and the capacitors in the wide grooves are mainly used to contribute to the capacitance density.

[0042] In one possible implementation, the semiconductor device is an adapter board; the semiconductor device packaging structure further includes a first chip and a second chip; and the first chip and the second chip are disposed on the adapter board.

[0043] On the other hand, the present application also provides an electronic device, which includes a circuit board and a semiconductor device packaging structure in any of the above implementations, and the semiconductor device packaging structure is arranged on the circuit board.

[0044] The electronic device provided in the present application includes a semiconductor device in any of the above-mentioned implementation methods. When manufacturing the semiconductor device, grooves of different widths are etched, and then, after electrodes and capacitor dielectric layers are formed in each groove, the electrodes in the narrow grooves can be exposed through a single photolithography etching process. Compared with the existing multiple photolithography etching processes, the number of photolithography etching times can be significantly reduced, the process flow can be compressed, and the product quality rate can be improved.

[0045] In another aspect, the present application further provides a method for preparing a semiconductor device, the method comprising:

[0046] A first groove, a second groove, and a third groove are formed in the base, wherein the groove width of the first groove and the groove width of the third groove are both smaller than the groove width of the second groove, and the groove width of the first groove is larger than the groove width of the third groove, and the groove width is a dimension perpendicular to the length direction of the groove;

[0047] A first electrode, a capacitor dielectric layer, and a second electrode are sequentially formed in the first groove, the second groove, and the third groove;

[0048] Etching the first electrode, the capacitor dielectric layer, and the second electrode above the first groove and the third groove so that the second electrode in the first groove is exposed and the first electrode in the third groove is exposed;

[0049] The circuit layer is prepared so that the first conductive through hole in the circuit layer penetrates to the second electrode in the first groove, and the second conductive through hole in the circuit layer penetrates to the first electrode in the third groove.

[0050] In the preparation method of the present application, when opening the grooves, some of the grooves are narrow grooves and some are wide grooves. After depositing the electrodes and capacitor dielectric layers in the grooves of different widths, the electrodes in the narrow grooves can be exposed through a single photolithography etching process, and the electrodes in the narrow grooves are electrically connected to the lead-out electrodes. Compared with the existing photolithography etching process of at least two times, the number of etching times can be reduced and the process flow can be simplified. In some deep trench capacitors, when more electrodes are included, a single photolithography etching process can still be used to expose multiple electrodes, and the simplified process flow is more effective.

[0051] In one possible implementation, the first groove, the second groove, and the third groove are formed in the substrate, including:

[0052] The second groove is opened between the first groove and the third groove, the first groove and the second groove are connected, and the second groove and the third groove are connected.

[0053] In one possible implementation, the first groove, the second groove, and the third groove are formed in the substrate, including:

[0054] A plurality of second grooves are provided, and a portion of the plurality of second grooves is arranged along a first direction parallel to the substrate surface to form a first array. Another portion of the plurality of second grooves is arranged along a second direction parallel to the substrate surface to form a second array. A first groove is provided between one of two adjacent second arrays and the first array, and a third groove is provided between the other of the two adjacent second arrays and the first array. The first direction is perpendicular to the second direction.

[0055] In the capacitor array produced using this method, narrow slots are placed between the wide slots arranged in the array. This fully utilizes the space between the wide slot arrays, improves space utilization, and increases the capacitor integration density.

[0056] In one possible implementation, the first groove, the second groove, and the third groove are formed in the substrate, including:

[0057] A plurality of second grooves are provided, and the plurality of second grooves are arranged along a first direction parallel to the surface of the substrate. A first groove and a second groove are provided, and the first groove and the third groove are arranged along the second direction parallel to the surface of the substrate. The first groove connects two adjacent second grooves, and the third groove connects two adjacent second grooves. The first direction is perpendicular to the second direction.

[0058] In this manufacturing method, narrow slots are placed in a wide slot array, and the wide slot arrays are isolated from each other. In this way, each wide slot array works independently, and the utilization yield of the capacitor can be improved.

[0059] In one possible implementation, the first groove, the second groove, and the third groove are formed in the substrate, including:

[0060] The groove depth of the first groove and the groove depth of the third groove are both smaller than the groove depth of the second groove, and the groove depth of the first groove is greater than the groove depth of the third groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIG1 is a schematic diagram of a structure of part of an electronic device provided in an embodiment of the present application;

[0062] FIG2 is a schematic structural diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0063] FIG3 is a top view of each groove in the semiconductor device shown in FIG2;

[0064] FIG4A is a top view of a substrate after multiple grooves are formed in the substrate according to an embodiment of the present application;

[0065] FIG4B is a schematic diagram of the structure cut along the AA direction of FIG4A ;

[0066] FIG5A is a top view of a plurality of grooves filled with electrodes and capacitor dielectric layers according to an embodiment of the present application;

[0067] FIG5B is a cross-sectional view of an embodiment of the present application after electrodes and capacitor dielectric layers are filled in multiple grooves;

[0068] FIG6 is a cross-sectional view after a photolithography process according to an embodiment of the present application;

[0069] FIG7A is a top view of a dielectric layer formed above a plurality of grooves according to an embodiment of the present application;

[0070] FIG7B is a cross-sectional view of a dielectric layer formed above a plurality of grooves according to an embodiment of the present application;

[0071] FIG8 is a cross-sectional view of a first metal layer formed on a dielectric layer according to an embodiment of the present application;

[0072] FIG9 is a cross-sectional view of a redistributed contact hole formed on a first metal layer according to an embodiment of the present application;

[0073] FIG10 is a schematic structural diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0074] 11A to 11I are schematic structural diagrams corresponding to the preparation of a semiconductor device including a deep trench capacitor in the related art;

[0075] FIG12 is a schematic structural diagram of a semiconductor device including a deep trench capacitor manufactured using the related art;

[0076] FIG13 is a schematic structural diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0077] FIG14 is a schematic structural diagram of a partial structure of a semiconductor device provided in an embodiment of the present application;

[0078] FIG15 is a top view of a substrate after multiple grooves are formed in the substrate according to an embodiment of the present application;

[0079] FIG16A is a cross-sectional view of a substrate after multiple grooves are formed in the substrate according to an embodiment of the present application;

[0080] FIG16B is a cross-sectional view of a structure after electrodes and capacitor dielectric layers are filled in multiple grooves according to an embodiment of the present application;

[0081] FIG16C is a cross-sectional view after a single photolithography process according to an embodiment of the present application;

[0082] FIG17 is a top view of a substrate after multiple grooves are formed in the substrate according to an embodiment of the present application;

[0083] FIG18 is a schematic structural diagram cut along the BB direction of FIG17;

[0084] FIG19A is a top view of a substrate after multiple grooves are formed in the substrate according to an embodiment of the present application;

[0085] FIG19B is a schematic diagram of the structure cut along the CC direction of FIG19A;

[0086] FIG20A is a top view of a plurality of grooves filled with electrodes and capacitor dielectric layers according to an embodiment of the present application;

[0087] FIG20B is a cross-sectional view of a structure after electrodes and capacitor dielectric layers are filled in multiple grooves according to an embodiment of the present application;

[0088] FIG21 is a cross-sectional view after a photolithography process according to an embodiment of the present application;

[0089] FIG22 is a cross-sectional view after forming a portion of the circuit layer according to an embodiment of the present application;

[0090] FIG23 is a flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] The present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, or may be a household appliance, an aircraft engine control system, an avionics system, an automotive system, a downhole oil exploration system, a military application, or the like. The present application does not impose any particular restrictions on the specific form of the electronic device.

[0092] As shown in FIG1 , the electronic device may include a circuit board 100, such as a printed circuit board (PCB), with a semiconductor device package structure disposed on the circuit board 100. The semiconductor device package structure may be electrically connected to the circuit board 100 via an electrical connection structure 500, thereby enabling signal interconnection between the semiconductor device package structure and other chips or other electronic modules on the circuit board 100.

[0093] In an alternative embodiment, the electrical connection structure 500 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

[0094] In some examples, as shown in FIG1 , a semiconductor device package structure includes multiple chips 400 , which are disposed on an interposer 300 , and interconnect signals between the multiple chips 400 via the interposer 300 . This type of packaging may be referred to as a 2.5D package.

[0095] The adapter board 300 is disposed on the substrate 200 , such as a packaging substrate. The substrate 200 is disposed on the circuit board 100 via the electrical connection structure 500 .

[0096] The chip 400 shown in FIG. 1 may be a single chip or a plurality of chips stacked three-dimensionally.

[0097] In some implementation structures, the chip 400 may include a memory, a system on chip (SOC), and may also include an analog chip, a digital chip, etc.

[0098] In the semiconductor device packaging process, by introducing deep trench capacitors into the adapter plate 300 shown in FIG1 , they can effectively serve as coupling capacitors for high-frequency signal straighteners and as decoupling capacitors for solving decoupling problems in bias circuits. For example, by placing deep trench capacitors in a silicon substrate, such capacitors can be referred to as silicon capacitors. Silicon capacitors are suitable for harsh environments, including aircraft engine control, avionics systems, automotive systems, downhole oil exploration systems, and military applications. Furthermore, silicon capacitors provide stable capacitance performance as a function of voltage and temperature, and are immune to capacitor aging. Furthermore, the reliability and capacitance of silicon capacitors do not degrade under DC bias conditions.

[0099] In deep trench capacitor structures, as capacitance density increases, the number of dielectric and electrode layers increases. For example, at least four dielectric layers and five electrode layers are required. This increases the number of photolithography, etching, and other related process steps, making the manufacturing process more complex. Furthermore, the increase in process steps reduces product yield and increases product cost.

[0100] The embodiments of the present application provide some deep trench capacitor structures and methods for manufacturing the deep trench capacitor structures. When using this method to prepare deep trench capacitors, the preparation process will not become increasingly complicated due to the increase in the number of capacitor dielectric layers and electrodes.

[0101] As shown in FIG2 , FIG2 is a process structure diagram of a deep trench capacitor provided in a semiconductor device according to an embodiment of the present application. The semiconductor device may be the interposer 300 shown in FIG1 , or the chip 400 shown in FIG1 , or other semiconductor devices with integrated passive devices.

[0102] The semiconductor device shown in Figure 2 includes a substrate 1, a circuit layer 2 disposed on substrate 1, and a capacitor disposed within the semiconductor device. The capacitor includes at least one capacitor dielectric layer and at least two electrode layers. For example, the capacitor shown in Figure 2 includes a first electrode 31, a second electrode 32, and a capacitor dielectric layer 4 located between the first electrode 31 and the second electrode 32.

[0103] For example, the capacitor structure shown in FIG2 of the present application can be provided in the adapter plate 300 shown in FIG1 . The adapter plate 300 can be a passive interposer or an active interposer. The substrate 1 of the adapter plate 300 can be made of silicon.

[0104] For another example, the capacitor structure shown in FIG. 2 of the present application example may be provided in the chip 400 shown in FIG. 1 , and the material of the substrate 1 of the chip 400 may include at least one of silicon, silicon carbide, sapphire, and the like.

[0105] The capacitor shown in FIG2 is a deep trench capacitor, that is, a trench is provided in the substrate 1 along the thickness direction of the substrate 1 (the Z direction shown in FIG2 ), and the capacitor is provided in the trench.

[0106] As shown in Figure 2, a first groove 51, a second groove 52, and a third groove 53 are formed in the substrate 1. The first groove 51, the second groove 52, and the third groove 53 are arranged in a direction parallel to the surface of the substrate 1. For example, the first groove 51, the second groove 52, and the third groove 53 are arranged in the X direction parallel to the surface of the substrate 1.

[0107] 2 , the second groove 52 is located between the first groove 51 and the third groove 53. In other examples, the third groove 53 may be located between the first groove 51 and the second groove 52, or the first groove 51 may be located between the second groove 52 and the third groove 53.

[0108] In the present embodiment, adjacent two grooves of the first groove 51, the second groove 52, and the third groove 53 are connected. For example, in FIG2 , the second groove 52 is located between the first groove 51 and the third groove 53. The first groove 51 is adjacent to the second groove 52, and the first groove 51 and the second groove 52 are connected. The second groove 52 is adjacent to the third groove 53, and the second groove 52 and the third groove 53 are connected.

[0109] See Figure 2. In the example of this application, the grooves arranged in the substrate 1 have a depth dimension along the thickness direction of the substrate 1. For example, any one of the first groove 51, the second groove 52 or the third groove 53 extends along the thickness direction of the substrate 1, and any one of the grooves has a dimension in the thickness direction of the substrate 1.

[0110] In the example of this application, as shown in FIG2 , the first groove 51 and the second groove 52 are connected, which can be understood as: the sides of the first groove 51 and the second groove 52 that are close to each other are connected; the second groove 52 and the third groove 53 are connected, which can also be understood as: the sides of the second groove 52 and the third groove 53 that are close to each other are connected. For example, as shown in FIG2 , the first groove 51, the second groove 52, and the third groove 53 are arranged along the X direction, and in the X direction, the first groove 51, the second groove 52, and the third groove 53 are connected.

[0111] The groove widths of the first groove 51, the second groove 52 and the third groove 53 may be different. For example, as shown in Figure 3, Figure 3 is an example of a top view of the grooves in Figure 2, wherein the groove width d2 of the second groove 52 is greater than the groove width d1 of the first groove 51, the groove width d2 of the second groove 52 is greater than the groove width d3 of the third groove 53, and the groove width d1 of the first groove 51 is greater than the groove width d3 of the third groove 53.

[0112] As shown in Figure 3 , in the example of this application, the grooves can be strip-shaped grooves, and the groove width can be understood as the dimension perpendicular to the groove length. For example, if the first groove 51, the second groove 52, and the third groove 53 all extend along the X direction parallel to the surface of the substrate 1, then the groove width of the first groove 51, the groove width of the second groove 52, and the groove width of the third groove 53 are all dimensions along the Y direction.

[0113] As shown in Figure 2, the first and second grooves 51 and 52 include stacked first and second electrodes 31 and 32, and a capacitor dielectric layer 4 located between the first and second electrodes 31 and 32. The first electrode 31 is closer to the inner wall of the groove than the second electrode 32. This can be understood as follows: first, the first electrode 31 is formed in the groove, the capacitor dielectric layer 4 is formed on the first electrode 31, and then the second electrode 32 is formed on the capacitor dielectric layer 4. The first electrode 31, the capacitor dielectric layer 4, and the second electrode 32 are stacked in sequence from the outside to the inside, away from the inner wall of the groove.

[0114] The third groove 53 includes the first electrode 31 .

[0115] The circuit layer 2 includes a first conductive through-hole 9A and a second conductive through-hole 9B; the first conductive through-hole 9A passes through to the second electrode 32 in the first groove 51 and is electrically connected to the second electrode 32; the second conductive through-hole 9B passes through to the first electrode 31 in the third groove 53 and is electrically connected to the first electrode 31 in the third groove 53.

[0116] Continuing with FIG2 , the first groove 51 and the second groove 52 are connected, and the second groove 52 and the third groove 53 are connected. In an optional manufacturing process, the first electrode 31 in the first groove 51, the first electrode 31 in the second groove 52, and the first electrode 31 in the third groove 53 are connected as one body, and the second electrode 32 in the first groove 51 and the second electrode 32 in the second groove 52 are connected as one body. The connection as one body in this example can be understood as using the same material and using the same process to manufacture them all at once.

[0117] As shown in FIG2 , in the second slot 52 with a larger slot width, no conductive through-hole is provided to lead out the second electrode. Since the second electrode 32 in the first slot 51 and the second electrode 32 in the second slot 52 are connected as one body, the second electrode 32 in the second slot 52 can be led out using the conductive through-hole extending into the first slot 51 .

[0118] As shown in FIG2 , the second groove 52 with a larger groove width includes multiple electrodes and a capacitor dielectric layer of the capacitor. The capacitor in the second groove 52 is a capacitor that can contribute to capacitance density.

[0119] Compared to the second groove 52, since the groove width of the third groove 53 is smaller, when the first electrode 31 is formed in the second groove 52 and the third groove 53, the thickness of the first electrode 31 in the third groove 53 is greater than the thickness of the first electrode 31 in the second groove 52. For example, as shown in FIG2, the first electrode 31 in the third groove 53 is almost filled to the groove opening. The thickness in this example refers to the dimension along the groove width. After the capacitor dielectric layer 4 and the second electrode 32 are further formed in the first groove 51, the second groove 52, and the third groove 53, a single photolithography process can be used to expose the thicker first electrode 31 in the third groove 53 and the second electrode 32 in the first groove 51. Then, the circuit layer is formed. The second electrode 32 in the first groove 51 is electrically connected to the extraction electrode (e.g., VDD) in the circuit layer through a conductive via, and the first electrode 31 in the third groove 53 is electrically connected to the extraction electrode (e.g., VSS) in the circuit layer through a conductive via.

[0120] That is, the present application utilizes the electrodes arranged in the grooves with smaller groove widths to electrically connect with the lead-out electrodes, and realizes the input and output of signals through the grooves with smaller groove widths. In addition, it also contributes a small amount of capacitance density, such as the capacitor arranged in the first groove.

[0121] The following describes how this application simplifies the capacitor manufacturing process through the process flow and corresponding structural drawings.

[0122] 4A to 8 exemplarily show the structure of a capacitor array prepared in an adapter plate, where the exemplary capacitor includes three electrodes and two capacitor dielectric layers.

[0123] As shown in Figures 4A and 4B, Figure 4A is a top view when a groove is opened in the base of the adapter plate, and Figure 4B is a cross-sectional view along the AA direction. In order to make the structure after cutting clearer, Figure 4B only shows one second groove 61 of the first array Y2 in Figure 4A, and does not show the remaining four second grooves 61 in the first array Y2.

[0124] As shown in FIG4A , a plurality of slots are arranged in an array within the base 1 of the adapter plate. For example, the adapter plate includes a plurality of second slots 61 arranged along a first direction (e.g., the X direction in FIG4A ), each of which extends along a second direction (e.g., the Y direction in FIG4A ); and a plurality of fourth slots 62 arranged along the second direction (e.g., the Y direction in FIG4A ), each of which extends along the first direction (e.g., the X direction in FIG4A ). In some examples, the first direction X and the second direction Y are perpendicular and parallel to the surface of the base 1 .

[0125] The plurality of second grooves 61 arranged along the first direction X are collectively referred to as the first array, and the plurality of fourth grooves 62 arranged along the second direction Y are collectively referred to as the second array. Multiple first arrays and multiple second arrays are provided within the substrate 1, and the multiple first arrays and multiple second arrays are arranged alternately in one direction. For example, in FIG4A , the multiple first arrays and multiple second arrays are arranged alternately in both the first direction X and the second direction Y.

[0126] As shown in FIG4A , each second slot 61 in the first array and each fourth slot 62 in the second array serve as functional slots for accommodating capacitors and contributing to capacitance density.

[0127] As shown in Figure 4A , slots are provided between adjacent first and second arrays. In the example shown in Figure 4A , a fifth slot 63A is provided between the first array Y1 and the second array E1, a first slot 63B is provided between the second array E1 and the first array Y2, and a third slot 63C is provided between the first array Y2 and the second array E2.

[0128] Referring to FIG4A , the second and fourth trenches 61 and 62, which contribute to capacitance density, have relatively large widths, while the fifth trench 63A, first trench 63B, and third trench 63C, which are disposed between the second and fourth trenches 61 and 62, have relatively small widths. For example, along the arrangement direction of the fifth trench 63A, first trench 63B, and third trench 63C, the widths of the fifth trench 63A, first trench 63B, and third trench 63C gradually decrease. Alternatively, in other examples, the width of the first trench 63B is greater than the widths of the fifth and third trenches 63A and 63C, and the width of the fifth trench 63A is greater than the width of the third trench 63C.

[0129] It can be understood that in the example shown in Figure 4A, narrow slots are provided at both ends of the wide slot array, and the slot widths of the narrow slots at both ends can be different. In the example of Figure 4A, the slot width of the wide slots in the first array is the dimension along the X direction, the slot width of the wide slots in the second array is the dimension along the Y direction, and the slot width of the narrow slots in both the first and second arrays is the dimension along the Y direction.

[0130] 5A and 5B , which are structural diagrams after capacitors are arranged in the plurality of slots opened as described above.

[0131] The first electrode 31 , the first capacitor dielectric layer 41 , the second electrode 32 , the second capacitor dielectric layer 42 and the third electrode 33 are formed in the grooves opened in FIG. 4A and FIG. 4B .

[0132] As shown in Figure 5B, the second groove 61 and the fourth groove 62, as well as the fifth groove 63A, the first groove 63B, and the third groove 63C are respectively filled with the first electrode 31, the first capacitor dielectric layer 41, the second electrode 32, the second capacitor dielectric layer 42, and the third electrode 33. The first electrode 31, the first capacitor dielectric layer 41, the second electrode 32, the second capacitor dielectric layer 42, and the third electrode 33 are stacked in sequence in a direction away from the inner wall of the groove.

[0133] The thickness of the first electrode 31 in the third groove 63C is greater than the thickness of the first electrode 31 in the remaining grooves. The thickness of the first electrode 31 in the fifth groove 63A, the fourth groove 62, the first groove 63B, and the second groove 61 are equal.

[0134] In some examples, the first electrode 31 in the third trench 63C is filled to the trench opening of the third trench 63C.

[0135] The thickness of the second electrode 32 in the first groove 63B is greater than that in the remaining grooves. The thickness of the second electrode 31 in the fifth groove 63A, the fourth groove 62, the second groove 61 and the third groove 63C is equal.

[0136] In some examples, the second electrode 32 in the first trench 63B is filled to the trench opening of the first trench 63B.

[0137] In this example, the thickness dimension refers to the dimension along the slot width direction. For example, the thickness dimension of the first electrode 31 in the third slot 63C is the dimension along the Y direction shown in FIG4A , the thickness dimension of the first electrode 31 in the second slot 61 in the first array Y2 is the dimension along the X direction shown in FIG4A , and the thickness dimension of the first electrode 31 in the fourth slot 62 in the second array E1 is the dimension along the Y direction shown in FIG4A .

[0138] When preparing electrodes and capacitor dielectric layers in each groove, low-process processing technology can be compatible to produce the structure shown in Figure 5B in grooves of different widths.

[0139] As shown in Figure 6 , the electrodes and capacitor dielectric layer on the trenches connected between the second trench 61 and the fourth trench 62 are etched. For example, as shown in Figure 6 , the film layers on the fifth trench 63A, the first trench 63B, and the third trench 63C are etched to expose the third electrode 33 in the fifth trench 63A, the second electrode 32 in the first trench 63B, and the first electrode 31 in the third trench 63C.

[0140] As shown in Figures 7A and 7B , a dielectric layer 7 is formed, and then holes penetrating the dielectric layer 7 are formed in the dielectric layer 7. For example, in Figure 7B , a hole 8A is formed penetrating to the third electrode 33 in the fifth groove 63A, a hole 8B is formed penetrating to the second electrode 32 in the first groove 63B, and a hole 8C is formed penetrating to the first electrode 31 in the third groove 63C.

[0141] As shown in FIG8 , a first metal layer is formed on the dielectric layer 7 . When preparing the first metal layer, conductive material is filled into the holes 8A, 8B, and 8C shown in FIG7B to form conductive through-holes 9A, 9B, and 9C having electrical connection functions.

[0142] Conductive via 9A is electrically connected to the lead-out electrode (lead-out electrode VSS as shown in FIG8 ) through the circuit layer, conductive via 9B is electrically connected to the lead-out electrode (lead-out electrode VDD as shown in FIG8 ) through the circuit layer, and conductive via 9C is electrically connected to the lead-out electrode (lead-out electrode VSS as shown in FIG8 ) through the circuit layer.

[0143] As shown in FIG9 , a redistribution contact hole (RV) is formed on the first metal layer.

[0144] As shown in FIG10 , a second metal layer is formed on the redistribution contact hole, and the second metal layer can be used to electrically connect to the lead-out electrode.

[0145] As shown in Figures 4A to 10, the preparation method of the deep trench capacitor includes trenches of different widths when trenches are opened in the substrate. The wide trenches serve as functional trenches for accommodating capacitors; the narrow trenches serve as electrode lead-out trenches. As shown in Figure 10, the conductive through-holes electrically connecting the lead-out electrodes and the capacitor electrodes can pass through to the electrodes in the narrow trenches. The narrow trenches also serve as electrical signal bridges between the wide trench arrays, and the narrow trenches can also contribute a small amount of capacitance density.

[0146] Returning to FIG. 4A , in this example, narrow slots are positioned between two adjacent wide slot arrays. For example, fifth slot 63A is positioned between first array Y1 and second array E1, first slot 63B is positioned between second array E1 and first array Y2, and third slot 63C is positioned between first array Y2 and second array E2. The lengths of fifth slot 63A, first slot 63B, and third slot 63C can be smaller than the lengths of second slot 61 and fourth slot 62.

[0147] In this way, the space between the wide groove arrays can be fully utilized, the space utilization rate can be improved, more wide groove arrays can be integrated on the unit area of ​​the substrate, and the capacitance density can be improved.

[0148] In some examples, as shown in FIG. 4B , the groove depth of the second groove 61 and the groove depth of the fourth groove 62 may be equal.

[0149] In some possible structures, the groove depth of the fifth groove 63A, the groove depth of the first groove 63B, and the groove depth of the third groove 63C are all smaller than the groove depth of the second groove 61. For example, along the direction from the fifth groove 63A to the third groove 63C, the groove depth of the fifth groove 63A, the groove depth of the first groove 63B, and the groove depth of the third groove 63C gradually decrease.

[0150] As shown in FIG. 4B , the wide grooves in the wide groove array may be connected to the narrow grooves.

[0151] 11A to 11I show corresponding process structure diagrams for preparing a capacitor including three electrodes and two capacitor dielectric layers in the related art.

[0152] As shown in FIG11A , a plurality of grooves 61 are opened in the substrate 1 . These grooves 61 are all functional grooves, and are filled with the first electrode 31 , the first capacitor dielectric layer 41 , the second electrode 32 , the second capacitor dielectric layer 42 and the third electrode 33 of the capacitor.

[0153] After the first electrode 31, the first capacitor dielectric layer 41, the second electrode 32, the second capacitor dielectric layer 42 and the third electrode 33 are prepared, the stacked first electrode 31, the first capacitor dielectric layer 41, the second electrode 32, the second capacitor dielectric layer 42 and the third electrode 33 will also be formed above the groove.

[0154] Silicon oxide 10 and photoresist 11 are formed over the film structure above the trench.

[0155] As shown in FIG11B , the silicon oxide 10 and the photoresist 11 in FIG11A are etched using exposure and development techniques, and the silicon oxide 10 and the photoresist 11 located above the plurality of grooves are retained.

[0156] As shown in FIG. 11C , the third electrode 33 is retained and the second capacitor dielectric layer 42 is exposed.

[0157] The process steps shown in FIG. 11A to FIG. 11C may retain the third electrode 33 located above the groove.

[0158] As shown in FIG11D , a photoresist 11 is formed on the structure obtained in FIG11C .

[0159] As shown in FIG. 11E , the silicon oxide 10 and the photoresist 11 in FIG. 11D are etched using exposure and development techniques, leaving the silicon oxide 10 and the photoresist 11 located above the plurality of grooves.

[0160] As shown in FIG11F , the second capacitor dielectric layer 42 and the second electrode 32 are retained, and the first capacitor dielectric layer 41 is exposed.

[0161] The process steps shown in FIG. 11D to FIG. 11F may retain the second electrode 32 located above the groove.

[0162] As shown in FIG11G , a photoresist 11 is formed on the structure obtained in FIG11F .

[0163] As shown in FIG11H , the silicon oxide 10 and the photoresist 11 in FIG11G are etched using exposure and development techniques, and the silicon oxide 10 and the photoresist 11 located above the plurality of grooves are retained.

[0164] As shown in FIG11I , the second capacitor dielectric layer 42 , the second electrode 32 , the first capacitor dielectric layer 41 and the first electrode 31 are retained.

[0165] The process steps shown in FIG. 11G to FIG. 11I may retain the first electrode 31 located above the groove.

[0166] Figure 12 illustrates the structure of a deep trench capacitor fabricated using the method shown in Figures 11A through 11I. A circuit layer disposed on the deep trench capacitor can be used to lead out first electrode 31, second electrode 32, and third electrode 33, and electrically connect them to corresponding lead-out electrodes. For example, first electrode 31 and third electrode 33 are electrically connected to lead-out electrode VSS, and second electrode 32 is electrically connected to lead-out electrode VDD. In the method shown in Figures 11A through 11I, each electrode layer is fabricated using distributed photolithography.

[0167] Compare the related art shown in Figures 11A to 11I with the examples shown in Figures 4A to 10 of this application. As shown in Figure 6, before the circuit layer is formed, only one photolithography and etching process is required to expose and separate the first electrode 31, the second electrode 32, and the third electrode 33. However, in the technology of Figures 11A to 11I, three photolithography and etching processes are required before the circuit layer is formed to expose and separate the three electrodes. Therefore, this application uses grooves of different widths, with wide grooves as functional grooves and narrow grooves as electrode lead-out grooves, to reduce the number of photolithography and etching times, simplify the process flow, and improve the product quality rate.

[0168] For example, when fabricating a capacitor with five electrode layers, using the related techniques shown in Figures 11A to 11I above requires five photolithography steps to expose the electrodes. However, the present invention only requires one photolithography step to expose the electrodes in the narrow grooves. When fabricating more electrode layers, such as ten or even more electrodes, a single photolithography step is also required to expose the electrodes in the narrow grooves. This significantly reduces the number of photolithography steps compared to the conventional method of ten steps.

[0169] Compare the deep trench capacitor shown in FIG12 made by the prior art and the deep trench capacitor of the present application shown in FIG13. In the structure shown in FIG12, the three electrodes located above the groove are stepped. This structure has high requirements on the overlay accuracy of the photolithography process, especially when preparing deep trench capacitors with more layers of electrodes, which poses a higher challenge to the overlay accuracy of the photolithography process. However, as shown in FIG13, since all the electrodes in the narrow groove can be exposed through a single photolithography etching process, the conductive through-holes in the circuit layer can extend into the narrow groove. In this way, compared with FIG12, the overlay accuracy of the photolithography process can be reduced, and higher requirements will not be placed on the preparation equipment. It is compatible with low-process processing technology, and the device cost can be further reduced. In addition, the present application can also reduce the coverage requirements between film layers and reduce process requirements.

[0170] 12 and 13 , the present application reduces the requirements for etching morphology and etching selectivity of the etching process, thereby improving product quality and further reducing device costs.

[0171] The capacitor in the above example includes three electrodes and two capacitor dielectric layers. The following also exemplifies a deep trench capacitor structure including more electrodes and capacitor dielectric layers.

[0172] As shown in Figures 14 and 15, the deep trench capacitor includes a first electrode 31, a second electrode 32, a third electrode 33, a fourth electrode 34 and a fifth electrode 35, and a first capacitor dielectric layer 41, a second capacitor dielectric layer 42, a third capacitor dielectric layer 43 and a fourth capacitor dielectric layer 44.

[0173] The first capacitor dielectric layer 41 is located between the first electrode 31 and the second electrode 32, the second capacitor dielectric layer 42 is located between the second electrode 32 and the third electrode 33, the third capacitor dielectric layer 43 is located between the third electrode 33 and the fourth electrode 34, and the fourth capacitor dielectric layer 44 is located between the fourth electrode 34 and the fifth electrode 35.

[0174] The example shown in Figure 14 can be understood as: along the direction away from the inner wall of the groove, the first electrode 31, the first capacitor dielectric layer 41, the second electrode 32, the second capacitor dielectric layer 42, the third electrode 33, the third capacitor dielectric layer 43, the fourth electrode 34, the fourth capacitor dielectric layer 44 and the fifth electrode 35 are stacked in sequence.

[0175] As shown in Figure 15, the capacitor of the example of the present application includes five electrodes, and the five electrodes need to be led out separately. In some examples, narrow slots can be set between two adjacent wide slot arrays, such as the first slot 63B, the third slot 63C, the fifth slot 63A, the seventh slot 63D and the ninth slot 63E with narrower slot widths shown in Figures 14 and 15.

[0176] In some structures, the widths of the ninth groove 63E, the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C may gradually decrease from the ninth groove 63E to the third groove 63C.

[0177] As shown in Figure 14, the conductive through-hole 9A in the circuit layer can pass through to the fifth electrode 35 in the ninth slot 63E and be electrically connected to the fifth electrode 35; the conductive through-hole 9B in the circuit layer can pass through to the fourth electrode 34 in the seventh slot 63D and be electrically connected to the fourth electrode 34; the conductive through-hole 9C in the circuit layer can pass through to the third electrode 33 in the fifth slot 63A and be electrically connected to the third electrode 33; the conductive through-hole 9D in the circuit layer can pass through to the second electrode 32 in the first slot 63B and be electrically connected to the second electrode 32; the conductive through-hole 9E in the circuit layer can pass through to the first electrode 31 in the third slot 63C and be electrically connected to the first electrode 31.

[0178] The capacitors in the second slot 61A, the fourth slot 61B, the sixth slot 61C, and the eighth slot 61D serve as functional capacitors, primarily contributing to capacitance density. In addition, the narrow slots also contain capacitors, which can also contribute to capacitance density.

[0179] The deep trench capacitor shown in FIG14 can also be exposed through a single photolithography and etching process to expose the electrodes in the narrow trenches.

[0180] For example, as shown in Figure 16A, a plurality of grooves are opened in the substrate 1, and these grooves include a second groove 61A, a fourth groove 61B, a sixth groove 61C and an eighth groove 61D arranged in an array, and the second groove 61A, the fourth groove 61B, the sixth groove 61C and the eighth groove 61D are wide grooves; narrow grooves are opened between two adjacent wide groove arrays, for example, the ninth groove 63E, the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C are opened as narrow grooves.

[0181] As shown in FIG16B , the first electrode 31 , the first capacitor dielectric layer 41 , the second electrode 32 , the second capacitor dielectric layer 42 , the third electrode 33 , the third capacitor dielectric layer 43 , the fourth electrode 34 , the fourth capacitor dielectric layer 44 and the fifth electrode 35 are deposited in sequence.

[0182] As shown in FIG16C , the film layers on the ninth groove 63E, the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C are etched to expose the fifth electrode 35 in the ninth groove 63E, the fourth electrode 34 in the seventh groove 63D, the third electrode 33 in the fifth groove 63A, the second electrode 32 in the first groove 63B, and the first electrode 31 in the third groove 63C.

[0183] Based on FIG16C , the present application sets a narrow groove, and can expose the electrode in the narrow groove through a single photolithography etching process, thereby reducing the number of photolithography etching times.

[0184] In the above example, narrow slots are placed between wide slot arrays to fully utilize the space between the wide slot arrays. In the following examples, some other arrangements of narrow slots are also given.

[0185] As shown in Figure 17, Figure 17 shows a top view of a substrate having grooves. A plurality of grooves are arranged in an array within the substrate 1. For example, the plurality of grooves 62 are arranged along a first direction (the X direction in Figure 17), each extending along a second direction (the Y direction in Figure 17); and the plurality of grooves 61 are arranged along a second direction (the Y direction in Figure 17), each extending along the first direction (the X direction in Figure 17). In some examples, the first direction (X) and the second direction (Y) are perpendicular and parallel to the surface of the substrate 1.

[0186] The plurality of second grooves 61 arranged along the second direction Y are collectively referred to as a first array, and the plurality of second grooves 62 arranged along the first direction X are collectively referred to as a second array. Multiple first arrays and multiple second arrays are provided within the substrate 1, and the multiple first arrays and multiple second arrays are arranged alternately in one direction. For example, in FIG17 , the multiple first arrays and multiple second arrays are arranged alternately in the first direction X.

[0187] As shown in FIG17 , each second slot 61 in the first array and each second slot 62 in the second array serve as functional slots for accommodating capacitors and contributing to capacitance density.

[0188] Continuing with Figure 17 , narrow slots are arranged within the wide slot array, connecting two adjacent wide slots. In Figure 17 , the narrow slots include the seventh slot 63D, the fifth slot 63A, the first slot 63B, and the third slot 63C. The narrow slots extend perpendicularly to the wide slots. For example, the second slot 61 extends in the X direction, while the seventh slot 63D, the fifth slot 63A, the first slot 63B, and the third slot 63C all extend in the Y direction.

[0189] In the example of FIG17 , the wide slot arrays are separated from each other by a substrate. For example, there is no connecting slot between the first array Y1 and the second array E1 , but they are separated by a substrate.

[0190] In some examples, as shown in FIG17 , the widths of the seventh slot 63D, the fifth slot 63A, the first slot 63B, and the third slot 63C gradually decrease from the seventh slot 63D toward the third slot 63C. For example, the seventh slot 63D can accommodate four electrodes, the fifth slot 63A can accommodate three electrodes, the first slot 63B can accommodate two electrodes, and the third slot 63C can accommodate one electrode.

[0191] As shown in Figure 18, Figure 18 is a process structure diagram cut along the BB direction of Figure 17. In this example, the capacitor includes four electrodes and three capacitor dielectric layers. The conductive via 9A in the circuit layer can extend into the seventh groove 63D to electrically connect to the fourth electrode 34, the conductive via 9B in the circuit layer can extend into the fifth groove 63A to electrically connect to the third electrode 33, the conductive via 9C in the circuit layer can extend into the first groove 63B to electrically connect to the second electrode 32, and the conductive via 9D in the circuit layer can extend into the third groove 63C to electrically connect to the first electrode 31.

[0192] As shown in FIG17 and FIG18 , when narrow grooves are arranged in a wide groove array, the electrodes in the narrow grooves can also be exposed through a single photolithography and etching process. The following describes the process that can be implemented with reference to the accompanying drawings.

[0193] As shown in Figure 19A, multiple grooves are formed in the substrate 1. The multiple grooves are arranged in an array. In each array, not only wide grooves but also narrow grooves are included. For example, as shown in Figure 19B, which is a process structure diagram cut along the CC direction of Figure 19A, in the first array Y1 shown in Figure 19A, along the extension direction of the wide second groove 61, the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C, which are narrow grooves, are spaced apart. These narrow grooves are connected to the wide grooves.

[0194] In some examples, the widths of every two narrow grooves are different. For example, the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C may gradually decrease.

[0195] As shown in FIG20A and FIG20B , a first electrode, a first capacitor dielectric layer, a second electrode, a second capacitor dielectric layer, a third electrode, a third capacitor dielectric layer and a fourth electrode are sequentially formed in the plurality of grooves shown in FIG19A .

[0196] Since the multiple grooves shown in Figure 20A include narrow grooves of different widths, the thickness dimensions of different electrodes are different in different narrow grooves. For example, as shown in Figure 20B, in the third groove 63C, the thickness dimension of the first electrode 31 is the largest, in the first groove 63B, the thickness dimension of the second electrode 32 is the largest, and in the fifth groove 63A, the thickness dimension of the third electrode 33 is the largest.

[0197] As shown in Figure 21, the electrodes and capacitor dielectric layer on the narrow grooves are etched. For example, the film layers on the seventh groove 63D, the fifth groove 63A, the first groove 63B, and the third groove 63C are etched to expose the fourth electrode 34 in the seventh groove 63D, the third electrode 33 in the fifth groove 63A, the second electrode 32 in the first groove 63B, and the first electrode 31 in the third groove 63C.

[0198] As shown in Figure 22, a circuit layer is prepared so that the conductive through hole 9A of the circuit layer passes through to the fourth electrode 34 in the seventh groove 63D and is electrically connected to the fourth electrode 34, the conductive through hole 9B passes through to the third electrode 33 in the fifth groove 63A and is electrically connected to the third electrode 33, the conductive through hole 9C passes through to the second electrode 32 in the first groove 63B and is electrically connected to the second electrode 32, and the conductive through hole 9D passes through to the first electrode 31 in the third groove 63C and is electrically connected to the first electrode 31.

[0199] Based on the above different examples, by opening grooves of different widths in the substrate and setting the narrow groove between two adjacent wide groove arrays, or setting the narrow groove within the wide groove array, the electrode in the narrow groove can be exposed through a single photolithography etching process, and the electrode in the narrow groove can be electrically connected to the lead-out electrode in the circuit layer.

[0200] Based on the above different examples, this application provides a process flow of a method for preparing a semiconductor device including a deep trench capacitor, as shown in FIG23 , including:

[0201] S1: A first groove, a second groove and a third groove are opened in the base, the groove width of the first groove and the groove width of the third groove are both smaller than the groove width of the second groove, the groove width of the first groove is larger than the groove width of the third groove, and the groove width is the dimension perpendicular to the length direction of the groove.

[0202] That is, when etching grooves in the substrate, grooves of different widths can be etched. For example, the first and third grooves are narrower than the second groove. The wide groove is used to accommodate the capacitor, and the narrow groove is used to lead out the electrode.

[0203] In some examples, the first groove, the second groove and the third groove are arranged sequentially in one direction, the second groove is located between the first groove and the third groove, the first groove and the second groove are connected, and the second groove and the third groove are connected.

[0204] In this example, there may be multiple second grooves, and the multiple second grooves are arranged in an array. For example, the multiple second grooves are arranged along the X direction parallel to the substrate surface to form a first array, and the multiple second grooves are arranged along the Y direction parallel to the substrate surface to form a second array.

[0205] In some implementations, narrow slots, such as the first slot and the third slot, may be opened between the first array and the second array.

[0206] In some other possible implementations, the narrow slots may be arranged in the first array or the second array of wide slots.

[0207] S2: forming a first electrode, a capacitor dielectric layer, and a second electrode in the first groove, the second groove, and the third groove in sequence.

[0208] Since the widths of the first, second and third grooves prepared in step S1 are inconsistent, after the electrodes and capacitor dielectric layers are prepared, the thickness of the film in different grooves is different. For example, the thickness of the first electrode is larger in the third groove with a smaller width.

[0209] S3: etching the first electrode, the capacitor dielectric layer, and the second electrode above the first trench and the third trench, so that the second electrode in the first trench is exposed and the first electrode in the third trench is exposed.

[0210] After step S2 is performed, since the thickness of the electrodes in the first groove and the third groove are different, the second electrode in the first groove and the first electrode in the third groove can be exposed through one photolithography process.

[0211] S4: preparing a circuit layer so that the first conductive through hole in the circuit layer penetrates to the second electrode in the first groove, and the second conductive through hole in the circuit layer penetrates to the first electrode in the third groove.

[0212] The conductive through-holes in this example may penetrate into the slots and be electrically connected to corresponding electrodes.

[0213] When deep trench capacitors are prepared using the preparation method provided in this application, the preparation process flow will not be excessively increased due to the increase in the number of electrode layers and capacitor dielectric layers of the capacitor. In this way, the product processing cycle can be shortened, the manufacturing cost can be reduced, and it is compatible with the process processing technology, and the device cost is further reduced.

[0214] Based on semiconductor processing technology, the groove opening, thin film filling, and circuit layer layout provided in this application can all be achieved using processes such as photolithography, diffusion process, chemical vapor deposition (CVD), physical vapor deposition (PVD), and chemical mechanical polishing.

[0215] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0216] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a substrate and a circuit layer arranged on the substrate, wherein the semiconductor device further comprises a capacitor, and the capacitor comprises a first electrode, a second electrode and a first capacitor dielectric layer; The substrate has a first groove, a second groove, and a third groove, wherein the first groove, the second groove, and the third groove are arranged in a direction parallel to the surface of the substrate, and two adjacent grooves of the first groove, the second groove, and the third groove are connected; The groove width of the first groove and the groove width of the third groove are both smaller than the groove width of the second groove, and the groove width of the first groove is larger than the groove width of the third groove. The groove width is the dimension perpendicular to the longitudinal direction of the groove; The first groove and the second groove include the first electrode and the second electrode, and the first capacitor dielectric layer located between the first electrode and the second electrode; the first electrode is closer to the inner wall of the groove than the second electrode; The third tank includes the first electrode; The circuit layer includes a first conductive through-hole and a second conductive through-hole. The first conductive through-hole passes through to the second electrode in the first groove, and the second conductive through-hole passes through to the first electrode in the third groove.

2. The semiconductor device according to claim 1, wherein The length of the first slot and the length of the third slot are both smaller than the length of the second slot.

3. The semiconductor device according to claim 1 or 2, wherein: The groove depth of the first groove and the groove depth of the third groove are both smaller than the groove depth of the second groove, and the groove depth of the first groove is greater than the groove depth of the third groove.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The thickness of the first electrode in the third groove is greater than the thickness of the first electrode in the second groove; The thickness of the first electrode in the second groove is equal to the thickness of the first electrode in the first groove; The thickness is the dimension along the groove width direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The second groove is located between the first groove and the third groove, and the first groove is communicated with the second groove, and the second groove is communicated with the third groove.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The second electrode in the second groove is connected to the second electrode in the first groove as a whole, and the first conductive through hole is connected to the second electrode as a whole.

7. The semiconductor device according to any one of claims 1 to 6, wherein: There are a plurality of second grooves, which are arranged along a first direction parallel to the surface of the substrate, and the second grooves extend along a second direction parallel to the surface of the substrate, and the first direction is perpendicular to the second direction; The first groove is located at one end of the second groove, and the third groove is located at the other end of the second groove.

8. The semiconductor device according to claim 7, wherein: A plurality of second grooves are arranged along the second direction; A plurality of the second grooves arranged along the first direction form a first array, and a plurality of the second grooves arranged along the second direction form a second array; The first array is arranged between two adjacent second arrays; The first groove is arranged between one of two adjacent second arrays and the first array, and the third groove is arranged between the other of two adjacent second arrays and the first array.

9. The semiconductor device according to any one of claims 1 to 6, wherein: There are a plurality of second grooves, the plurality of second grooves are arranged along a first direction parallel to the surface of the substrate, the second grooves extend along a second direction parallel to the surface of the substrate, the first grooves and the third grooves are arranged along the second direction, the first grooves and the third grooves both extend along the first direction, and the first direction is perpendicular to the second direction; The first groove communicates with two adjacent second grooves, and the third groove communicates with two adjacent second grooves.

10. The semiconductor device according to claim 9, wherein A plurality of second grooves are arranged along the second direction; A plurality of the second grooves arranged along the first direction form a first array, and a plurality of the second grooves arranged along the second direction form a second array; The first array and the second array are separated by the substrate.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The capacitor further includes a third electrode and a second capacitor dielectric layer; The base further includes a fourth groove and a fifth groove, wherein the groove width of the fifth groove and the groove width of the first groove are both smaller than the groove width of the fourth groove, and the groove width of the fifth groove is larger than the groove width of the first groove; The fifth groove, the fourth groove, and the second groove include the stacked first electrode, the second electrode, and the third electrode, and the first capacitor dielectric layer located between the first electrode and the second electrode, and the second capacitor dielectric layer located between the second electrode and the third electrode, wherein the first electrode is closer to the inner wall of the groove than the second electrode; The circuit layer further includes a third conductive through-hole, and the third conductive through-hole passes through to the third electrode in the fifth groove.

12. The semiconductor device according to claim 11, wherein The fifth groove, the fourth groove, the first groove, the second groove, and the third groove are arranged in sequence along a direction parallel to the surface of the substrate, and every two adjacent grooves among the fifth groove, the fourth groove, the first groove, the second groove, and the third groove are connected.

13. The semiconductor device according to claim 11 or 12, characterized in that The groove width of the second groove is equal to the groove width of the fourth groove.

14. The semiconductor device according to any one of claims 11 to 13, wherein: From the direction from the fifth groove to the third groove, the groove depth of the fifth groove, the groove depth of the first groove and the groove depth of the third groove decrease in sequence.

15. The semiconductor device according to any one of claims 11 to 14, characterized in that The thickness of the first electrode in the third groove is greater than the thickness of the first electrode in the first groove and the fifth groove; The thickness of the second electrode in the first groove is greater than the thickness of the second electrode in the fifth groove; the thickness is the dimension along the groove width direction.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that The semiconductor device is a transfer board, or the semiconductor device is a chip.

17. A semiconductor device packaging structure, characterized in that: include: The semiconductor device according to any one of claims 1 to 16; A substrate is provided on which the semiconductor device is arranged.

18. The semiconductor device packaging structure according to claim 17, wherein: The semiconductor device is a transfer board; The semiconductor device packaging structure further includes a first chip and a second chip; The first chip and the second chip are arranged on the transfer board.

19. An electronic device, characterized in that: include: Circuit board; The semiconductor device packaging structure according to claim 17 or 18; The semiconductor device packaging structure is arranged on the circuit board.

20. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: A first groove, a second groove, and a third groove are formed in the base, wherein the groove width of the first groove and the groove width of the third groove are both smaller than the groove width of the second groove, and the groove width of the first groove is larger than the groove width of the third groove, and the groove width is a dimension perpendicular to the length direction of the groove; Sequentially forming a first electrode, a capacitor dielectric layer, and a second electrode in the first groove, the second groove, and the third groove; Etching the first electrode, the capacitor dielectric layer, and the second electrode located above the first groove and the third groove, so that the second electrode in the first groove is exposed and the first electrode in the third groove is exposed; A circuit layer is prepared so that a first conductive through hole in the circuit layer passes through to the second electrode in the first groove, and a second conductive through hole in the circuit layer passes through to the first electrode in the third groove.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The first groove, the second groove and the third groove are formed in the substrate, comprising: The second groove is opened between the first groove and the third groove, the first groove is connected to the second groove, and the second groove is connected to the third groove.

22. The method for preparing a semiconductor device according to claim 20 or 21, wherein: The first groove, the second groove and the third groove are formed in the substrate, comprising: A plurality of second grooves are provided, and a portion of the plurality of second grooves is arranged along a first direction parallel to the surface of the substrate to form a first array. Another portion of the plurality of second grooves is arranged along a second direction parallel to the surface of the substrate to form a second array. The first groove is provided between one of two adjacent second arrays and the first array, and the third groove is provided between the other of two adjacent second arrays and the first array. The first direction is perpendicular to the second direction.

23. The method for preparing a semiconductor device according to claim 20 or 21, wherein: The first groove, the second groove and the third groove are formed in the substrate, comprising: A plurality of second grooves are formed, and the plurality of second grooves are arranged along a first direction parallel to the surface of the substrate. and the second groove, the first groove and the third groove are arranged along a second direction parallel to the surface of the substrate, the first groove connects two adjacent second grooves, the third groove connects two adjacent second grooves, and the first direction is perpendicular to the second direction.

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