Multiplexer module and manufacturing method therefor

Abstract

The present invention provides a multiplexer module and a manufacturing method therefor. The manufacturing method comprises: providing an intermediate plastic encapsulation structure, wherein the intermediate plastic encapsulation structure comprises a plurality of filter chips, a plastic encapsulation layer wrapping back faces and side walls of the filter chips, retaining walls located on two sides of the front face of each of the filter chips, and an isolation layer covering the retaining walls and defining cavities with the retaining walls and the front faces of the filter chips; forming at least one rewiring layer, wherein the rewiring layer is electrically connected to the front faces of the filter chips; and forming bonding pads, wherein the bonding pads are electrically connected to the rewiring layer. The present invention combines WLP filter manufacturing and fan-out encapsulation to realize a multiplexer module, such that the manufacturing complexity of the multiplexer module can be effectively reduced and the filter wafer breakage rate is lowered; and at least one rewiring layer provides higher cavity strength so that cavity collapse during a secondary plastic encapsulation process can be resisted. In addition, the multiplexer module which is thus manufactured and has a smaller three-dimensional size can be used in a wider range of application fields.

Description

Multiplexer module and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a multiplexer module and a manufacturing method thereof. Background Art

[0002] With the development of communication technology, filters and multiplexers are becoming increasingly important in the communication field.

[0003] The multiplexer module is composed of multiple acoustic filters of different frequency bands. During the design process, it is difficult to make the thickness of the IDT (Interdigital Transducer) of the frequency band filters uniform, making it impossible to implement the multiplexer on the same wafer. At the same time, in order to ensure the normal operation of the filters in each frequency band, it is necessary to build a cavity on the surface of the IDT structure of the filter. Therefore, traditional multiplexers are usually implemented by welding and plastic-sealing multiple WLP (Wafer Level Packaging) filters with built cavities on the substrate, or first bonding or welding the filter bare chip with bumps to the substrate, and then a layer of film is sealed on the entire module to form a cavity, and finally the packaging is completed by plastic sealing.

[0004] The main disadvantages of the multiplexer modules formed by the above two methods are: 1. The package size is relatively thick, which does not meet the requirements of miniaturization of RF modules, especially the secondary packaging is extremely difficult in the more integrated PAMiD module; 2. The filter wafer is relatively thin and is very easy to break during bump production or WLP packaging, resulting in yield loss; 3. It is extremely sensitive to molding pressure during the plastic packaging process, and it is easy to cause cavity collapse or plastic packaging material to be poured in, resulting in device failure. Summary of the Invention

[0005] The purpose of the present invention is to provide a multiplexer module and a manufacturing method thereof, which adopts WLP filter manufacturing combined with fan-out packaging to effectively reduce the manufacturing complexity of the multiplexer module and reduce the filter wafer breakage rate.

[0006] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a multiplexer module is provided, comprising the following steps:

[0007] Providing an intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips;

[0008] forming at least one redistribution layer on the intermediate plastic package structure, wherein the redistribution layer is electrically connected to the front surface of the filter chip; and

[0009] A pad is formed on the redistribution layer, and the pad is electrically connected to the redistribution layer.

[0010] Optionally, an IDT and electrodes on both sides of the IDT are formed on the front of the filter chip; the IDT is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrodes, and the redistribution layer is electrically connected to the electrodes.

[0011] Optionally, the method of providing the intermediate plastic packaging structure includes:

[0012] Make filter wafers and cut them into individual filter chips;

[0013] Providing a carrier board, and mounting a plurality of filter chips face-down on the carrier board;

[0014] forming a plastic encapsulation layer on the carrier, wherein the plastic encapsulation layer covers the back surface, side walls and a portion of the carrier of the filter chip;

[0015] Removing the carrier board to expose the front surface of the filter chip;

[0016] forming retaining walls on both sides of the front surface of the filter chip; and

[0017] An isolation layer is formed on the retaining wall, and the isolation layer, the retaining wall and the front surface of the filter chip constitute a cavity.

[0018] Optionally, the method of providing the intermediate plastic packaging structure includes:

[0019] Manufacturing a filter wafer, forming a retaining wall on the filter wafer, and dividing the filter wafer into individual filter chips;

[0020] Providing a carrier board, and mounting a plurality of filter chips face-down on the carrier board;

[0021] forming a plastic encapsulation layer on the carrier, the plastic encapsulation layer covering the back surface and side wall of the filter chip, the side wall of the retaining wall away from the IDT, and a portion of the carrier;

[0022] removing the carrier board to expose the front surface of the filter chip; and

[0023] An isolation layer is formed on the retaining wall on the front side of the filter chip, and the isolation layer, the retaining wall and the front side of the filter chip constitute a cavity.

[0024] Optionally, the method of providing the intermediate plastic packaging structure includes:

[0025] Manufacturing a filter wafer, forming a retaining wall on the filter wafer, and dividing the filter wafer into individual filter chips;

[0026] providing a carrier plate, and forming an isolation layer corresponding to the retaining wall on the carrier plate;

[0027] Mounting a plurality of filter chips face-down on the carrier, wherein the isolation layer, the retaining wall and the front face of the filter chips form a cavity;

[0028] forming a plastic encapsulation layer on the carrier, the plastic encapsulation layer covering the back surface and side wall of the filter chip, the side wall of the retaining wall away from the IDT, the side wall of the isolation layer away from the IDT, and a portion of the carrier; and

[0029] The carrier board is removed to expose the front surface of the filter chip.

[0030] Optionally, after mounting the plurality of filter chips face down on the carrier, and before forming the plastic encapsulation layer, the method further includes: forming a shielding layer, wherein the shielding layer at least covers the back surface, side walls and a portion of the carrier surface of the filter chips;

[0031] After removing the carrier board, the method further includes: removing a portion of the shielding layer to expose a portion of the surface of the plastic packaging layer.

[0032] Optionally, after forming the pad, the method further includes forming a bump on the pad.

[0033] To solve the above technical problems, according to a second aspect of the present invention, a multiplexer module is provided, comprising:

[0034] an intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips;

[0035] at least one redistribution layer located on the intermediate plastic package structure, the redistribution layer being electrically connected to the front surface of the filter chip; and

[0036] A pad is located on the redistribution layer, and is electrically connected to the redistribution layer.

[0037] Optionally, an IDT and electrodes on both sides of the IDT are formed on the front of the filter chip; the IDT is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrodes, and the redistribution layer is electrically connected to the electrodes.

[0038] Optionally, the thickness of the retaining wall is greater than the sum of the thickness of the interdigital transducer and the thickness of the electrode.

[0039] Optionally, the cross-sectional area of ​​the opening of the retaining wall on a side close to the filter chip is smaller than or equal to the cross-sectional area on a side away from the filter chip.

[0040] Optionally, a cross-sectional area of ​​the opening of the isolation layer on a side close to the filter chip is smaller than or equal to a cross-sectional area on a side away from the filter chip.

[0041] Optionally, a cross-sectional area of ​​the opening of the isolation layer on a side close to the filter chip is greater than or equal to a cross-sectional area of ​​the opening of the retaining wall at a corresponding position on a side away from the filter chip.

[0042] Optionally, the multiplexer module further includes a shielding layer, and the shielding layer at least covers the back surface and side walls of the filter chip.

[0043] In summary, in the multiplexer module and its manufacturing method provided by the present invention, an intermediate plastic packaging structure is first provided, the intermediate plastic packaging structure includes a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chip, retaining walls located on both sides of the front of the filter chip, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chip; then at least one redistribution layer is formed, the redistribution layer is electrically connected to the front of the filter chip; then a solder pad is formed, the solder pad is electrically connected to the redistribution layer. The present invention combines WLP filter production and fan-out packaging to realize a multiplexer module, which can effectively reduce the complexity of multiplexer module production and reduce the filter wafer breakage rate. At least one redistribution layer provides higher cavity strength to resist cavity collapse during the secondary plastic packaging process. At the same time, the smaller three-dimensional size produced in this way can achieve a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a flow chart of a method for manufacturing a multiplexer module according to an embodiment of the present invention.

[0045] 2 to 11 are schematic structural diagrams of the steps of the method for manufacturing a multiplexer module provided in the first embodiment of the present invention.

[0046] 12 to 20 are schematic structural diagrams of the steps of a method for manufacturing a multiplexer module provided in the second embodiment of the present invention.

[0047] 21 to 25 are schematic structural diagrams of the steps of the method for manufacturing a multiplexer module provided in the third embodiment of the present invention.

[0048] 26 to 32 are schematic structural diagrams of the steps of the method for manufacturing a multiplexer module provided in the fourth embodiment of the present invention.

[0049] 33 to 36 are schematic structural diagrams of the steps of the method for manufacturing a multiplexer module provided in the fifth embodiment of the present invention.

[0050] 37 to 39 are schematic structural diagrams of the steps of the method for manufacturing a multiplexer module provided in the sixth embodiment of the present invention.

[0051] Explanation of the accompanying drawings: 1-temporary bonding structure; 11-carrier; 12-bonding layer; 2-filter chip; 21-filter substrate; 22-interdigital transducer; 23-electrode; 24-retaining wall; 25-cavity; 3-shielding layer; 4-plastic sealing layer; 5-isolation layer; 6-rewiring layer; 61-metal circuit layer; 62-dielectric layer; 7-solder pad; 8-bump; 9-solder mask layer; 10-filter wafer. DETAILED DESCRIPTION

[0052] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0053] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0054] FIG1 is a flow chart of a method for manufacturing a multiplexer module according to an embodiment of the present invention. As shown in FIG1 , the method for manufacturing a multiplexer module includes the following steps:

[0055] S1: Providing an intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips;

[0056] S2: forming at least one redistribution layer on the intermediate plastic package structure, wherein the redistribution layer is electrically connected to the front surface of the filter chip; and

[0057] S3: forming a pad on the redistribution layer, wherein the pad is electrically connected to the redistribution layer.

[0058] This invention combines WLP filter fabrication with fan-out packaging to create a multiplexer module, effectively reducing manufacturing complexity and filter wafer breakage. The at least one redistribution layer provides increased cavity strength, resisting cavity collapse during secondary plastic packaging. Furthermore, the resulting smaller three-dimensional dimensions enable a wider range of applications.

[0059] The following describes in detail the method for manufacturing the multiplexer module of the present invention through specific embodiments.

[0060] Example 1

[0061] 2 to 11 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module according to the first embodiment of the present invention. Next, the method for manufacturing a multiplexer module according to the embodiment of the present invention will be described in detail in conjunction with FIG1 and FIG2 to 11.

[0062] In step S1, please refer to Figure 8 and provide an intermediate plastic packaging structure, which includes multiple filter chips 2, a plastic packaging layer 4 covering the back and side walls of the filter chip 2, retaining walls 24 located on both sides of the front of the filter chip 2, and an isolation layer 5 covering the retaining walls 24 and forming a cavity 25 with the retaining walls 24 and the front of the filter chip 2.

[0063] Exemplarily, the intermediate molding structure may be formed through the following sub-steps S11 to S16.

[0064] 2 and 3 , a filter wafer 10 is fabricated and divided into individual filter chips 2 . FIG2 is a top view of the entire filter wafer 10 , and FIG3 is a cross-sectional view of a single filter chip 2 .

[0065] In this embodiment, filter chips are manufactured on a wafer to form a filter wafer 10, as shown in FIG2 , and a plurality of filter chips are regularly arranged on the wafer. The filter wafer 10 is then divided to form a plurality of single filter chips 2. Referring to FIG3 , the filter chip 2 includes a filter substrate 21, an interdigital transducer 22 formed on the front of the filter substrate 21, and electrodes 23 located on both sides of the interdigital transducer 22. The side on which the interdigital transducer 22 and the electrode 23 are formed serves as the front of the filter chip 2, and the other side opposite to the front serves as the back of the filter chip 2. The front of the filter chip 2 is the same surface as the front of the filter substrate 21.

[0066] Exemplarily, the material of the filter substrate 21 includes, but is not limited to, lithium niobate, lithium tantalate, silicon, or a multilayer material having a piezoelectric material layer. The IDT 22 is composed of a single-layer film or a multilayer film of a metal material such as titanium (Ti), aluminum (Al), or aluminum copper (AlCu). The surface of the IDT 22 can be covered with a silicon oxide or silicon nitride passivation layer to protect the IDT 22. The electrode 23 is composed of a single-layer film or a multilayer film of a metal material such as Ti, Al, or AlCu. The surface of the electrode 23 can also be covered with a silicon oxide or silicon nitride passivation layer, and the passivation layer has an opening to expose a portion of the electrode 23.

[0067] Execute sub-step S12 , referring to FIG. 4 , provide a carrier board 11 , and mount a plurality of filter chips 2 on the carrier board 11 with their front sides facing downward.

[0068] The carrier 11 can be a hard carrier, such as a silicon wafer, a glass plate or a metal panel. When the carrier 11 is a hard carrier, the supporting effect is better. The surface of the carrier 11 can be provided with a bonding layer 12, and the bonding layer 12 can be a debondable adhesive layer, which can be attached to the carrier 11 and can stick to the chip or device placed on it. After the plastic sealing is completed, the carrier 11 can also be easily peeled off and removed. Of course, the bonding layer 12 can also be other material layers well known in the art. The carrier 11 and the bonding layer 12 together constitute a temporary bonding structure 1.

[0069] Multiple filter chips 2 are mounted face down on the temporary bonding structure 1. The IDT 22 and electrodes 23 on the front of the filter chip 2 can be embedded in the bonding layer 12, and the front of the filter chip 2 can be attached to the surface of the bonding layer 12.

[0070] Execute sub-step S13 , referring to FIG. 5 , to form a plastic encapsulation layer 4 on the carrier 11 , wherein the plastic encapsulation layer 4 covers the back surface, side walls, and a portion of the carrier 11 of the filter chip 2 .

[0071] For example, the plastic encapsulation layer 4 can be formed by transfer film, compression film, lamination, etc. The plastic encapsulation layer 4 is a thermosetting resin material containing inorganic fillers.

[0072] Execute sub-step S14 , referring to FIG. 5 and FIG. 6 , to remove the carrier board 11 to expose the front surface of the filter chip 2 .

[0073] Execute sub-step S15 , referring to FIG. 7 , to form retaining walls 24 on both sides of the front surface of the filter chip 2 .

[0074] For example, a barrier wall material layer is first formed on the front surface of the filter chip 2, covering the IDT 22, the electrodes 23, and the filter substrate 21. The barrier wall material layer is then patterned, leaving the barrier wall material layer on both sides of the filter chip 2 to form barrier walls 24. The barrier walls 24 can be made of, but are not limited to, a dry film material or photoresist having exposure properties.

[0075] The retaining wall 24 is located on both sides of the front of the filter chip 2, exposing the interdigital transducer 22 on the front of the filter chip 2, and the retaining wall 24 has an opening to expose at least part of the electrode 23. In one embodiment of the present invention, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 is smaller than the cross-sectional area on the side away from the filter chip 2, that is, in the direction perpendicular to the filter substrate 21, the opening has a structure that is wide at the top and narrow at the bottom to facilitate the formation of the subsequent redistribution layer. In another embodiment of the present invention, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 may also be equal to the cross-sectional area on the side away from the filter chip 2.

[0076] In one embodiment of the present invention, the thickness of the retaining wall 24 is greater than the sum of the thickness of the IDT 22 and the thickness of the electrode 23 , so as to ensure the height of the cavity formed subsequently.

[0077] Execute sub-step S16 , referring to FIG. 8 , to form an isolation layer 5 on the retaining wall 24 . The isolation layer 5 , the retaining wall 24 , and the front surface of the filter chip 2 constitute a cavity 25 .

[0078] The isolation layer 5 , the retaining wall 24 , and the filter substrate 21 form a cavity 25 , and the IDT 22 is located in the cavity 25 .

[0079] In this embodiment, the isolation layer 5 may be made of a dry film material or photoresist with exposure characteristics, or thinned glass or silicon material with specific area openings. The thickness of the isolation layer 5 is not less than 3 μm.

[0080] The isolation layer 5 has an opening corresponding to the opening of the retaining wall 24 to expose a portion of the electrode 23. In one embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is smaller than the cross-sectional area on the side away from the filter chip 2, that is, the opening of the isolation layer 5 has a structure that is wide at the top and narrow at the bottom to facilitate the subsequent formation of the redistribution layer. In another embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 can also be equal to the cross-sectional area on the side away from the filter chip 2.

[0081] In one embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall 24 at the corresponding position on the side away from the filter chip 2, so as to completely expose the electrode 23 exposed by the retaining wall 24.

[0082] In step S2 , as shown in FIG. 9 , at least one redistribution layer 6 is formed on the intermediate plastic package structure. The redistribution layer 6 is electrically connected to the front surface of the filter chip 2 .

[0083] The redistribution layer 6 may include a plurality of metal circuit layers 61 and a dielectric layer 62 isolating the plurality of metal circuit layers 61. The metal circuit layer 61 covers the opening of the isolation layer 5 and the electrode 23 exposed by the opening of the retaining wall 24, thereby being electrically connected to the electrode 23. The material of the metal circuit layer 61 may be a metal such as copper or aluminum, and a titanium / copper (Ti / Cu) or titanium tungsten / copper (TiW / Cu) seed layer may be provided at the bottom of the metal such as copper or aluminum, and the metal circuit layer 61 may be formed by electroplating and etching. In addition to connecting the electrodes 23 of each filter chip 2 for signal extraction and grounding, the metal circuit layer 61 also includes a matching circuit pattern to ensure the electrical performance of the module. The dielectric layer 62 may be a dry film material or photoresist with exposure characteristics, but is not limited thereto.

[0084] In this embodiment, multiple layers of redistribution layers 6 can be formed, and the metal wiring layers 61 in the multiple layers of redistribution layers 6 are electrically connected. FIG9 shows only two layers of redistribution layers 6, but the present invention is not limited thereto. The thickness of each metal wiring layer 61 in the multiple layers of redistribution layers 6 can be the same or different, and the thickness of each dielectric layer 62 in the multiple layers of redistribution layers 6 can be the same or different.

[0085] In step S3 , as shown in FIG. 10 , a pad 7 is formed on the redistribution layer 6 , and the pad 7 is electrically connected to the redistribution layer 6 .

[0086] The material of the pad 7 includes but is not limited to copper, and the surface of the pad 7 can be treated to prevent oxidation. The pad 7 can be formed by electroplating and etching, and the pad 7 contacts the metal circuit layer 61 in the redistribution layer 6 to achieve electrical connection.

[0087] In one embodiment of the present invention, a bump 8 may be formed on the pad 7. The bump 8 may be a copper pillar or a solder ball.

[0088] In one embodiment of the present invention, please refer to Figure 11. In order to prevent short circuit during welding, a solder resist layer 9 can also be formed on the redistribution layer 6. The solder resist layer 9 is a material that is not wettable with tin or copper. The solder resist layer 9 has an opening at the pad 7 or the bump 8 to expose the pad 7 or the bump 8.

[0089] It can then be cut into individual modules and packaged.

[0090] The multiplexer module manufacturing method provided in this embodiment combines WLP filter fabrication with fan-out packaging to achieve a multiplexer module. This effectively reduces the complexity of multiplexer module manufacturing and lowers the filter wafer breakage rate. The at least one redistribution layer provides increased cavity strength to resist cavity collapse during the secondary plastic packaging process. Furthermore, the resulting smaller three-dimensional dimensions enable a wider range of applications.

[0091] Example 2

[0092] Compared with implementation one, the difference of this embodiment is that: after mounting multiple filter chips 2 with their front sides facing down on the carrier 11, before forming the plastic packaging layer 4, it also includes: forming a shielding layer 3, and the shielding layer 3 covers the back and side walls of the filter chip 2 to increase electromagnetic shielding.

[0093] Figures 12 to 20 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module according to a second embodiment of the present invention. Referring to Figure 12 , after mounting multiple filter chips 2 face-down on the carrier 11, a shielding layer 3 is formed. The shielding layer 3 covers the back and sidewalls of the filter chips 2, as well as the carrier 11 between adjacent filter chips 2 (specifically, the bonding layer 12 in this embodiment).

[0094] The shielding layer 3 is made of a metal material, such as a single metal layer or a multi-layer metal composite layer such as copper or nickel. The shielding layer 3 can be formed by electroplating or sputtering. The thickness of the shielding layer 3 can be greater than or equal to 1 μm, but is not limited thereto.

[0095] Then, referring to FIG. 13 , a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0096] Next, the carrier board 11 is removed to expose the front surface of the filter chip 2. Figure 14 is a schematic diagram of the structure after the carrier board 11 is removed, and Figure 15 is a cross-sectional view of Figure 14 taken along line AB. Referring to Figures 14 and 15 , the shielding layer 3 surrounds the back surface and sidewalls of the filter chip 2 and covers the plastic encapsulation layer 4 between adjacent filter chips 2.

[0097] In one embodiment of the present invention, after removing the carrier board 11, a portion of the shielding layer 3 may also be removed to expose a portion of the plastic encapsulation layer 4. Figure 16 is a schematic diagram of the structure after partially removing the shielding layer, and Figure 17 is a cross-sectional view taken along line AB of Figure 16 . Referring to Figures 16 and 17 , removing a portion of the shielding layer 3 to expose the plastic encapsulation layer 4 facilitates improving the bonding strength between the subsequently formed redistribution layer and the intermediate plastic encapsulation structure, thereby increasing module reliability.

[0098] Next, please refer to Figures 18 and 19, where retaining walls 24 are formed on both sides of the front of the filter chip 2, and an isolation layer 5 is formed on the retaining walls 24. The isolation layer 5, the retaining walls 24 and the front of the filter chip 2 constitute a cavity 25, thereby forming an intermediate plastic packaging structure.

[0099] Then, referring to FIG. 20 , at least one redistribution layer 6 is formed on the intermediate plastic package structure. The metal wiring layer 61 in the redistribution layer 6 is electrically connected to the electrode 23, and a dielectric layer 62 is used to isolate the metal wiring layer 61. Subsequently, a solder pad 7 is formed on the redistribution layer 6, and the solder pad 7 is electrically connected to the redistribution layer 6. Bumps 8 may also be formed on the solder pads 7, and a solder resist layer 9 is formed on the redistribution layer 6 to expose the solder pads 7 and the bumps 8.

[0100] Example 3

[0101] Compared with the first embodiment, the present embodiment is different in that the method of forming the intermediate plastic packaging structure is different.

[0102] Figures 21 to 25 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module provided in Example 3 of the present invention. First, a filter wafer is manufactured, a retaining wall is formed on the filter wafer, and the filter wafer is divided into individual filter chips 2 to form a structure as shown in Figure 21. The filter chip 2 includes a filter substrate 21, an interdigital transducer 22 formed on the front of the filter substrate 21, and electrodes 23 located on both sides of the interdigital transducer 22. Retaining walls 24 are formed on both sides of the front of the filter substrate 21, and the retaining walls 24 cover part of the electrodes 23, and the retaining walls 24 have openings to expose part of the electrodes 23.

[0103] Referring to FIG. 22 , a carrier board 11 is provided, and a plurality of filter chips 2 are mounted face-down on the carrier board 11. A bonding layer 12 is also formed on the carrier board 11, and the carrier board 11 and the bonding layer 12 form a temporary bonding structure 1. The filter chips 2 are mounted face-down on the temporary bonding structure 1, with the retaining walls 24 in contact with or embedded in the bonding layer 12.

[0104] Next, referring to FIG. 23 , a plastic encapsulation layer 4 is formed on the carrier 11. The plastic encapsulation layer 4 covers the back surface and sidewalls of the filter chip 2 and the carrier 11 (specifically, the bonding layer 12). In this embodiment, the plastic encapsulation layer 4 also covers the sidewall of the retaining wall 24 away from the IDT 22.

[0105] Please refer to FIG. 24 , in which the carrier board 11 is removed to expose the front surface of the filter chip 2 .

[0106] Please refer to FIG. 25 . An isolation layer 5 is formed on the retaining wall 24 on the front surface of the filter chip 2 . The isolation layer 5 , the retaining wall 24 and the front surface of the filter chip 2 constitute a cavity 25 .

[0107] In this embodiment, retaining walls 24 are first formed on the filter wafer, and then the filter wafer is divided into individual filter chips 2. This embodiment can simultaneously form retaining walls 24 on the filter wafer. Compared with the first embodiment, which first divides the filter wafer into individual filter chips 2 and then forms retaining walls 24 on each filter chip 2, this saves process steps and reduces process costs.

[0108] Example 4

[0109] Compared with the third embodiment, the difference of this embodiment is that: after the multiple filter chips 2 are mounted face down on the carrier 11, before the plastic packaging layer 4 is formed, it also includes: forming a shielding layer 3, and the shielding layer 3 at least covers the back and side walls of the filter chip 2 to increase electromagnetic shielding.

[0110] Figures 26 to 32 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module according to a fourth embodiment of the present invention. Referring to Figure 26 , after mounting the plurality of filter chips 2 face-down on the carrier 11, a shielding layer 3 is formed. The shielding layer 3 covers the back and side walls of the filter chips 2, the sidewall of the retaining wall 24 away from the IDT 22, and the carrier 11 (specifically, the bonding layer 12 in this embodiment) between adjacent filter chips 2.

[0111] The shielding layer 3 is made of metal material, such as a single metal layer or a multi-layer metal composite layer such as copper or nickel. The shielding layer 3 can be formed by electroplating or sputtering. The thickness of the shielding layer 3 is greater than or equal to 1 μm, but is not limited thereto.

[0112] Then, referring to FIG. 27 , a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0113] Next, the carrier board 11 is removed to expose the front surface of the filter chip 2. Figure 28 is a schematic diagram of the structure after the carrier board 11 is removed, and Figure 29 is a cross-sectional view taken along line AB of Figure 28 . Referring to Figures 28 and 29 , after the carrier board 11 is removed, the shielding layer 3 surrounds the back surface and sidewalls of the filter chip 2 and covers the plastic encapsulation layer 4 between adjacent filter chips 2.

[0114] In one embodiment of the present invention, after removing the carrier board 11, a portion of the shielding layer 3 may also be removed to expose a portion of the plastic encapsulation layer 4. Figure 30 is a schematic diagram of the structure after the shielding layer is partially removed, and Figure 31 is a cross-sectional view of Figure 30 taken along line AB. Referring to Figures 30 and 31, removing a portion of the shielding layer 3 to expose the plastic encapsulation layer 4 facilitates improving the bonding strength between the subsequently formed redistribution layer and the intermediate plastic encapsulation structure, thereby increasing module reliability.

[0115] Next, referring to FIG. 32 , an isolation layer 5 is formed on the retaining wall 24 . The isolation layer 5 , the retaining wall 24 and the front surface of the filter chip 2 constitute a cavity 25 , thereby forming an intermediate plastic packaging structure.

[0116] Example 5

[0117] Compared with the first embodiment, the present embodiment is different in that the method of forming the intermediate plastic packaging structure is different.

[0118] Figures 33 to 36 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module provided in Example 5 of the present invention. Similar to Example 3, a filter wafer is first manufactured, a retaining wall is formed on the filter wafer, and the filter wafer is divided into individual filter chips 2 to form a structure as shown in Figure 21. The filter chip 2 includes a filter substrate 21, an interdigital transducer 22 formed on the front of the filter substrate 21, and electrodes 23 located on both sides of the interdigital transducer 22. Retaining walls 24 are formed on both sides of the front of the filter substrate 21, and the retaining walls 24 cover a portion of the electrodes 23, and the retaining walls 24 have openings to expose a portion of the electrodes 23.

[0119] Referring to FIG. 33 , a carrier board 11 is provided, and an isolation layer 5 is formed on the carrier board 11 corresponding to the retaining wall 24. This step can be performed simultaneously with the previous step. A bonding layer 12 is also formed on the carrier board 11. The carrier board 11 and the bonding layer 12 form a temporary bonding structure 1, and the isolation layer 5 is formed on the bonding layer 12.

[0120] Please refer to FIG. 34 , where a plurality of the filter chips 2 are mounted on the carrier 11 with their front sides facing downward, and the isolation layer 5 , the retaining wall 24 and the filter substrate 21 form a cavity 25 .

[0121] Next, referring to FIG. 35 , a plastic encapsulation layer 4 is formed on the carrier 11. The plastic encapsulation layer 4 covers the back surface and sidewalls of the filter chip 2 and the carrier 11 (specifically, the bonding layer 12). In this embodiment, the plastic encapsulation layer 4 also covers the sidewall of the retaining wall 24 away from the IDT 22 and the sidewall of the isolation layer 5 away from the IDT 22.

[0122] Please refer to FIG. 36 , where the carrier board 11 is removed to expose the front surface of the filter chip 2 , ultimately forming an intermediate plastic package structure.

[0123] In this embodiment, retaining walls 24 are first formed on the filter wafer, and then the filter wafer is divided into individual filter chips 2, and an isolation layer 5 is simultaneously formed on the carrier 11. Compared with the third embodiment, the retaining walls 24 and the isolation layer 5 can be fabricated simultaneously, thereby saving process time.

[0124] Example 6

[0125] Compared with the fifth embodiment, the difference of this embodiment is that: after the multiple filter chips 2 are mounted face down on the carrier 11, before the plastic packaging layer 4 is formed, it also includes: forming a shielding layer 3, and the shielding layer 3 at least covers the back and side walls of the filter chip 2 to increase electromagnetic shielding.

[0126] Figures 37 to 39 are schematic diagrams of the various steps of the method for manufacturing a multiplexer module according to the sixth embodiment of the present invention. Referring to Figure 37 , after mounting a plurality of filter chips 2 face-down on the carrier 11, a shielding layer 3 is formed. The shielding layer 3 covers the back and side walls of the filter chips 2, the side walls of the retaining wall 24 away from the IDT 22, the side walls of the isolation layer 5 away from the IDT 22, and the carrier 11 (specifically, the bonding layer 12 in this embodiment) between adjacent filter chips 2.

[0127] Then, referring to FIG. 38 , a plastic encapsulation layer 4 is formed on the carrier board 11 , and the plastic encapsulation layer 4 covers the shielding layer 3 .

[0128] Next, the carrier board 11 is removed to expose the front surface of the filter chip 2, forming an intermediate plastic packaging structure as shown in FIG. 39 .

[0129] It should be noted that the embodiments in this specification are described in a progressive manner, and the manufacturing methods described later focus on the differences from the methods described previously, and the similarities and similarities between the embodiments can be referred to each other.

[0130] Correspondingly, the present invention further provides a multiplexer module, which can be manufactured using the manufacturing method of the multiplexer module described in any one of the above embodiments.

[0131] Referring to FIG. 11 , the multiplexer module manufactured by the manufacturing method of the multiplexer module described in Example 1 is used as an example for description. The multiplexer module includes:

[0132] An intermediate plastic packaging structure, comprising a plurality of filter chips 2, a plastic packaging layer 4 covering the back and side walls of the filter chips 2, retaining walls 24 located on both sides of the front of the filter chips 2, and an isolation layer 5 covering the retaining walls 24 and forming a cavity 25 with the retaining walls 24 and the front of the filter chips 2;

[0133] At least one redistribution layer 6 located on the intermediate plastic package structure, wherein the redistribution layer 6 is electrically connected to the front surface of the filter chip 2; and

[0134] The pad 7 is located on the redistribution layer 6 , and the pad 7 is electrically connected to the redistribution layer 6 .

[0135] In this embodiment, an IDT 22 and electrodes 23 located on both sides of the IDT 22 are formed on the front of the filter chip 2; the IDT 22 is located in the cavity 25, and the retaining wall 24 and the isolation layer 5 both have openings to expose at least part of the electrode 23, and the redistribution layer 6 is electrically connected to the electrode 23.

[0136] In one embodiment of the present invention, the thickness of the retaining wall 24 is greater than the sum of the thickness of the IDT 22 and the thickness of the electrode 23 , so as to ensure the height of the cavity 25 .

[0137] In one embodiment of the present invention, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 is smaller than the cross-sectional area on the side away from the filter chip 2, that is, the opening has a structure that is wider at the top and narrower at the bottom, to facilitate electrical connection between the redistribution layer 6 and the electrode 23. In another embodiment of the present invention, the cross-sectional area of ​​the opening of the retaining wall 24 on the side close to the filter chip 2 can also be equal to the cross-sectional area on the side away from the filter chip 2.

[0138] In one embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is smaller than the cross-sectional area on the side away from the filter chip 2. That is, the opening of the isolation layer 5 has a structure that is wider at the top and narrower at the bottom, so as to facilitate the electrical connection between the redistribution layer 6 and the electrode 23. In another embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 can also be equal to the cross-sectional area on the side away from the filter chip 2.

[0139] In one embodiment of the present invention, the cross-sectional area of ​​the opening of the isolation layer 5 on the side close to the filter chip 2 is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall 24 at the corresponding position on the side away from the filter chip 2, so as to completely expose the electrode 23 exposed by the retaining wall 24.

[0140] In one embodiment of the present invention, as shown in FIG20 , the multiplexer module further includes a shielding layer 3 that covers at least the back surface and sidewalls of the filter chip 2 to enhance electromagnetic shielding. In this embodiment, the shielding layer 3 may also expose a portion of the plastic encapsulation layer 4 to ensure adhesion between the intermediate plastic encapsulation structure and the redistribution layer 6, thereby enhancing module reliability.

[0141] In summary, in the multiplexer module and its manufacturing method provided by the present invention, an intermediate plastic packaging structure is first provided, the intermediate plastic packaging structure includes a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chip, retaining walls located on both sides of the front of the filter chip, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chip; then at least one redistribution layer is formed, the redistribution layer is electrically connected to the front of the filter chip; then a solder pad is formed, the solder pad is electrically connected to the redistribution layer. The present invention combines WLP filter production and fan-out packaging to realize a multiplexer module, which can effectively reduce the complexity of multiplexer module production and reduce the filter wafer breakage rate. At least one redistribution layer provides higher cavity strength to resist cavity collapse during the secondary plastic packaging process. At the same time, the smaller three-dimensional size produced in this way can achieve a wider range of applications.

[0142] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a multiplexer module, characterized in that: The following steps are involved: Providing an intermediate plastic packaging structure, the intermediate plastic packaging structure comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips; forming at least one redistribution layer on the intermediate plastic package structure, wherein the redistribution layer is electrically connected to the front surface of the filter chip; and A pad is formed on the redistribution layer, and the pad is electrically connected to the redistribution layer.

2. The method for manufacturing a multiplexer module according to claim 1, wherein: An interdigital transducer and electrodes on both sides of the interdigital transducer are formed on the front of the filter chip; the interdigital transducer is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrodes, and the redistribution layer is electrically connected to the electrodes.

3. The method for manufacturing a multiplexer module according to claim 2, wherein: The method for providing an intermediate plastic packaging structure includes: Make filter wafers and cut them into individual filter chips; Providing a carrier board, and mounting a plurality of filter chips face-down on the carrier board; forming a plastic encapsulation layer on the carrier, wherein the plastic encapsulation layer covers the back surface, side walls and a portion of the carrier of the filter chip; Removing the carrier board to expose the front surface of the filter chip; forming retaining walls on both sides of the front surface of the filter chip; and An isolation layer is formed on the retaining wall, and the isolation layer, the retaining wall and the front surface of the filter chip constitute a cavity.

4. The method for manufacturing a multiplexer module according to claim 2, wherein: The method for providing an intermediate plastic packaging structure includes: Manufacturing a filter wafer, forming a retaining wall on the filter wafer, and dividing the filter wafer into individual filter chips; Providing a carrier board, and mounting a plurality of filter chips face-down on the carrier board; forming a plastic encapsulation layer on the carrier, the plastic encapsulation layer covering the back surface and side wall of the filter chip, the side wall of the retaining wall away from the IDT, and a portion of the carrier; removing the carrier board to expose the front surface of the filter chip; and An isolation layer is formed on the retaining wall on the front side of the filter chip, and the isolation layer, the retaining wall and the front side of the filter chip constitute a cavity.

5. The method for manufacturing a multiplexer module according to claim 2, wherein: The method for providing an intermediate plastic packaging structure includes: Manufacturing a filter wafer, forming a retaining wall on the filter wafer, and dividing the filter wafer into individual filter chips; providing a carrier plate, and forming an isolation layer corresponding to the retaining wall on the carrier plate; Mounting a plurality of filter chips face-down on the carrier, wherein the isolation layer, the retaining wall and the front face of the filter chips form a cavity; forming a plastic encapsulation layer on the carrier, the plastic encapsulation layer covering the back surface and side wall of the filter chip, the side wall of the retaining wall away from the IDT, the side wall of the isolation layer away from the IDT, and a portion of the carrier; and The carrier board is removed to expose the front surface of the filter chip.

6. The method for manufacturing a multiplexer module according to claim 3, 4 or 5, wherein: After mounting the plurality of filter chips face-down on the carrier, and before forming the plastic encapsulation layer, the method further includes: forming a shielding layer, wherein the shielding layer at least covers the back surface, side walls and a portion of the carrier surface of the filter chips; After removing the carrier board, the method further includes: removing a portion of the shielding layer to expose a portion of the surface of the plastic packaging layer.

7. The method for manufacturing a multiplexer module according to claim 1, wherein: After forming the pad, the method further includes forming a bump on the pad.

8. A multiplexer module, characterized in that: include: An intermediate plastic packaging structure, comprising a plurality of filter chips, a plastic packaging layer covering the back and side walls of the filter chips, retaining walls located on both sides of the front of the filter chips, and an isolation layer covering the retaining walls and forming a cavity with the retaining walls and the front of the filter chips; At least one redistribution layer located on the intermediate plastic package structure, the redistribution layer being electrically connected to the front surface of the filter chip; as well as A pad is located on the redistribution layer, and is electrically connected to the redistribution layer.

9. The multiplexer module according to claim 8, wherein: An interdigital transducer and electrodes on both sides of the interdigital transducer are formed on the front of the filter chip; the interdigital transducer is located in the cavity, the retaining wall and the isolation layer both have openings to expose at least part of the electrodes, and the redistribution layer is electrically connected to the electrodes.

10. The multiplexer module according to claim 9, wherein: The thickness of the retaining wall is greater than the sum of the thickness of the interdigital transducer and the thickness of the electrode.

11. The multiplexer module according to claim 9, wherein: The cross-sectional area of ​​the opening of the retaining wall at a side close to the filter chip is smaller than or equal to the cross-sectional area at a side away from the filter chip.

12. The multiplexer module according to claim 11, wherein: The cross-sectional area of ​​the opening of the isolation layer at a side close to the filter chip is smaller than or equal to the cross-sectional area at a side away from the filter chip.

13. The multiplexer module according to claim 12, wherein: The cross-sectional area of ​​the opening of the isolation layer on the side close to the filter chip is greater than or equal to the cross-sectional area of ​​the opening of the retaining wall at the corresponding position on the side away from the filter chip.

14. The multiplexer module according to any one of claims 8 to 13, wherein: The multiplexer module further includes a shielding layer, which at least covers the back surface and side walls of the filter chip.

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