A frequency multiplier circuit for frequency multiplying a frequency input signal, as well as corresponding device and methods

Abstract

A frequency multiplier circuit, comprising a resonant tank tuneable to a harmonic of a differential mode, DM, injection voltage, said resonant tank comprising an inductance and a voltage controlled capacitance for tuning said resonant tank, an injection locking circuit arranged for receiving said DM injection voltage, said injection locking circuit comprising a transistor for providing said harmonic of said DM injection voltage to said resonant tank, a tuning circuit, comprising an amplifier, said amplifier being configured to receive a tuning voltage at a first input and a voltage at a centre tap of said resonant tank at a second input, wherein the frequency multiplier circuit comprises a feedback path from the output of the amplifier to the centre tap of the resonant tank.

Description

[0001] A frequency multiplier circuit for frequency multiplying a frequency input signal, as well as corresponding device and methods

[0002] Technical field

[0003] The present disclosure generally relates to the field of frequency multiplier circuits and, more specifically, to a frequency multiplier circuit with centre frequency tuning capability.

[0004] Background

[0005] In the context of wireless communication technologies, the push towards higher frequencies, specifically in the millimeter-wave and sub-terahertz ranges, is a characteristic of the anticipated 6G telecommunication standard. However, operating oscillators at these elevated frequencies may pose challenges, that may require innovative solutions. One technique employed in these scenarios is the use of frequency multipliers.

[0006] At these high frequencies, the conventional approach of directly generating the local oscillator, LO, frequency may face certain obstacles. Existing technologies find it increasingly difficult to handle the complications of oscillators operating in these domains. Frequency multipliers provide a workaround to this issue.

[0007] Instead of directly generating the LO frequency, a sub-harmonic oscillator is designed to operate at a fraction of the LO frequency. The output of this sub-harmonic oscillator is then fed into a frequency multiplication circuit, resulting in the desired LO frequency.

[0008] Directly generating the desired LO frequency, or using conventional frequency multiplication circuits, may pose several challenges.

[0009] Varactors and switched capacitors, commonly used in frequency tuning circuits, are known to exhibit increased losses at sub-terahertz, sub-THz, frequencies. These losses can result in reduced efficiency and performance of the tuning circuits.

[0010] Amplifiers operating at high frequencies often demand a significant amount of energy. This high energy requirement can pose challenges in terms of power consumption, potentially leading to inefficiencies and increased energy costs. Employing a dedicated LO frequency synthesizer for each front-end in a direct LO approach may be costly in terms of chip area and could be less flexible than a multiplier solution.

[0011] Summary

[0012] It is an object of the present disclosure to provide for a frequency multiplier circuit that is, at least, able to provide for an increased tuning range. Further objects include associated devices as well as associated methods.

[0013] In a first aspect of the present disclosure, there is provided a frequency multiplier circuit.

[0014] The frequency multiplier circuit comprises a resonant tank tuneable to a harmonic of a differential mode, DM, injection voltage, said resonant tank comprising an inductance and a voltage controlled capacitance for tuning said resonant tank.

[0015] The frequency multiplier circuit further comprises an injection locking circuit arranged for receiving said DM injection voltage, said injection locking circuit comprising a transistor for providing said harmonic of said DM injection voltage to said resonant tank.

[0016] The frequency multiplier circuit further comprises a tuning circuit, comprising an amplifier, said amplifier being configured to receive a tuning voltage at a first input and a voltage at a centre tap of said resonant tank at a second input, wherein the frequency multiplier circuit comprises a feedback path from the output of the amplifier to the centre tap of the resonant tank.

[0017] The inventors have found that it may be beneficial to include a tuning circuit in combination with the feedback path. This allows to tune the DC voltage of the resonant tank. This is further explained here below following an example of the present disclosure.

[0018] In an example, the voltage controlled capacitances, as mentioned above, are comprised by the parasitic capacitance of transistors present in the resonant tank. These parasitic capacitances are, for example the gate-drain capacitance and the gate-source capacitance.

[0019] The feedback path, as mentioned above, will steer the voltage at the centre tap of the resonant tank to the tuning voltage applied to the amplifier. This voltage will influence the parasitic capacitance of the transistors present in the resonant tank. The tuning voltage will thus control the voltage controlled capacitance of the resonant tank such that the oscillating frequency of the resonant tank can be tuned.

[0020] A resonant tank, in the context of electronic circuits, is a combination of inductor(s) and capacitor(s) arranged in a way that creates a resonant circuit. This resonant circuit has a natural or resonant frequency at which it exhibits maximum energy storage and transfer. The term "tank" is used because this circuit can store and release energy in a manner analogous to a tank storing and dispensing liquid.

[0021] In a frequency multiplier circuit, the resonant tank is used to generate a periodic waveform, such as a sinusoidal signal. Specifically, the Radio Frequency, RF, carrier may be generated. The combination of the inductor and capacitor allows energy to oscillate between them, creating the desired waveform. This resonant frequency is determined by the values of the inductor and capacitor.

[0022] The present disclosure allows for a voltage controlled capacitance for tuning the resonant tank, i.e. for tuning the resonant tank in the frequency domain. The voltage used for controlling the capacitance is the DC voltage at the centre tap of the resonant tank. The tuning circuit, in combination with the feedback path, is arranged to steer the voltage at the centre tap of the resonant tank to a tuning voltage that is applied to the amplifier of the tuning circuit. This, thus, allows for the frequency tuning of the frequency multiplier circuit.

[0023] The injection locking circuit is arranged to receive a Differential Mode, DM, injection voltage. The injection voltage may be a signal that is originating from an oscillator operating at a sub-harmonic of the desired frequency.

[0024] The transistor, comprised by the injection locking circuit, will generate the harmonics of the DM injection voltage. So, the sub-harmonic, i.e. the fundamental, frequency originating from an oscillator is injected into the transistor which, due to the non-linear behaviour of the transistor, injects signal energy at the harmonics of the fundamental frequency as well. The fundamental frequency, i.e. the sub-harmonic frequency originating from the oscillator, as well as its harmonic frequencies are thus generated and provided to the resonant tank. The resonant tank is, for example, tuned to the 3rdor 5thharmonic frequency. For example, if the resonant tank is tuned to the 3rdharmonic, then a frequency multiplication of three is realized. If the resonant tank is tuned to the 5thharmonic, then a frequency multiplication of five is realized.

[0025] It is noted that the frequency multiplication is not limited to three or five. In the present disclosure, the resonant tank is tuned to one output frequency, which may be any harmonic frequency corresponding to the fundamental frequency originating from the oscillator.

[0026] The introduction of the harmonic signal from the transistor into the resonant tank thus initiates a resonance effect, contributing to the generation of a multiplied frequency. This frequency multiplication is an aspect of the overall operation of the circuit, allowing it to produce an output signal with a frequency that is a multiple of the original input signal.

[0027] Transistors, specifically Field-Effect Transistors, FETs, or Bipolar Junction Transistors, BJTs, are employed due to their ability to amplify and manipulate electrical signals effectively. These transistors function by nonlinearly amplifying the input signal, resulting in the creation of harmonics. Nonlinear devices, such as transistors, generate harmonics due to the distortion introduced during signal amplification. The resonant tank is then “tuned” to a specific harmonic content of the input signal.

[0028] In an example, the feedback path further comprises: a transistor, wherein said output of said amplifier is connected to a control terminal of said transistor, and wherein an output of said transistor is connected to said injection locking circuit.

[0029] In a further example, the resonant tank comprises: two series connected inductors for providing said inductance, wherein said centre tap is in between said two in series connected inductors.

[0030] The two series connected inductors may be implemented in semiconductor material. The inductors may be separated, and mirrored, to one another with a centre tap in between those inductors. Another option is that a single inductor is implemented, wherein the single inductor has a centre tap.

[0031] For two inductors connected in series, the point in between them is referred to as the center point or center tap. This center point is taken as a reference point in the circuit. The present disclosure defines that the voltage at this point is steered towards the tuning voltage applied to the amplifier. Similarly, in the case of a single inductor with a center tap, it means that the inductor has a winding with a midpoint connection. This center tap may also serve as the reference point in the circuit.

[0032] In another example, the resonant tank further comprises: at least one fixed capacitance such that said resonant tank is tuned to said harmonic of said DM injection voltage using said inductance, said voltage controlled capacitance and said fixed capacitance.

[0033] As mentioned above, the resonant tank has a voltage controlled capacitance for controlling I tuning the resonant frequency of the resonant tank. This voltage controlled capacitance may be the parasitic capacitances of the transistors present in the resonant tank, for example the Field Effect Transistors, FETs, present in the resonant tank.

[0034] The behaviour of FETs is strongly by the voltage applied to their gate terminals, particularly in relation to the parasitic capacitances associated with FETs. FETs may exhibit three parasitic capacitances, i.e. the gate-source capacitance Cgs, the gate-drain capacitance Cgd and the drain source capacitance Cds, which may all arise from the physical structure of the transistor. When a voltage is applied to the gate, it creates an electric field that modifies the distribution of charge within the transistor.

[0035] The gate voltage affects the width of the depletion region between the semiconductor material and the gate terminal. This modulation in the depletion region, in turn, influences the values of the parasitic capacitances. Specifically, the Cgs and Cgd are voltage-dependent, meaning their magnitudes change with variations in the gate voltage. This voltage-controlled capacitance may be of importance in resonant tanks where the FET operates at high frequencies.

[0036] The gate voltage(s) is / are steered towards the tuning voltage using the amplifier in combination with the feedback path.

[0037] In addition to the above, at least one fixed capacitance may be provided in the resonant tank.

[0038] As mentioned above, in FET-based resonant tank circuits, the parasitic capacitances inherent to FETs, like Cgs and Cgd, can function as a voltage-controlled capacitance. This feature may become significant in high-frequency applications, where the resonant behaviour of the resonant tank circuit is of importance. However, to fine-tune and stabilize this resonant behaviour, an additional fixed capacitance can be introduced in the resonant tank.

[0039] The inclusion of a fixed capacitance may serve several purposes. Firstly, it may allow precise tuning of the resonant frequency by choosing the value of the fixed capacitance to complement the voltage-controlled capacitance from the FET's parasitic capacitances. This ensures that the resonant frequency can be adjusted as needed. Secondly, the fixed capacitance may contribute to the stability of the circuit, compensating for variations in the FET's parasitic capacitances due to factors like manufacturing tolerances or temperature changes. This stability promotes consistent performance. The Combination of the voltage-controlled capacitance and the fixed capacitance may further improve the Q factor of the resonant tank, providing a sharper and more well-defined resonance.

[0040] In a further example, the injection locking circuit comprises: two injection locking transistors arranged for receiving said DM injection voltage at gates of said respective two injection locking transistors, wherein an output of a first of said two injection locking transistors is connected to a first end of said resonant tank and wherein an output of a second of said two injection locking transistors is connected to a second end, opposite to said first end, of said resonant tank.

[0041] The above mentioned transistors may, for example, be FETs or BJTs.

[0042] In a further example, the resonant tank comprises: two Field Effect Transistors, FETs, wherein sources of said two transistors are connected to one another, wherein a gate of a first of said two FETs is connected to a drain of a second of said two FETs, and wherein a gate of said second of said two FETs is connected to a drain of said first of said to FETs, and wherein said drain of said first of said two FETs is connected to a first end of said inductance, and wherein said drain of said second of said two FETs is connected to a second end of said inductance.

[0043] As an alternative, the resonant tank comprises: two bipolar junction transistors, BJTs, wherein emitter terminals of the two BJTs are connected to one another, where a base terminal of a first of the two BJTs is connected to a collector terminal of a second of the two BJTs, and wherein a base terminal of said second of said two BJTs is connected to a collector terminal of said first of said two BJTs, and wherein said collector terminal of said first of said two BJTs is connected to a first end of said inductance,

[0044] And wherein said collector terminal of said second of said two BJTs is connected to a second end of said inductance.

[0045] In a second aspect of the present disclosure, there is provided a signal generator comprising a frequency multiplier circuit in accordance with any of the previous examples and comprising a control circuit for controlling said tuning voltage, said control circuit comprising: a mixer arranged for mixing said differential mode, DM, injection voltage with an output of said resonant tank; a control mechanism arranged for detecting power in an output of said mixer, and for controlling said tuning voltage based on said detected power.

[0046] It is noted that the advantages as explained with reference to the first aspect of the present disclosure, being the frequency multiplier circuit, are also applicable to the second aspect of the present disclosure, being the signal generator.

[0047] The underlying idea is to tune the resonant frequency of the tank to be a multiple of the frequency of the injected DM voltage. The resonant frequency of the resonant tank is, for example, three times or fives times the frequency of the injected DM voltage.

[0048] The mixer mixes one or both of the differential mode, DM, injection voltage with an output of the resonant tank. The output of the mixer contains a mix of frequencies, including the sums and differences of the original frequencies. In the situation above, wherein an injected DM voltage has a frequency approximately one- third of the frequency output of the frequency multiplier circuit, the output will include components at the sum and difference frequencies of the two input signals, as well as the original frequencies themselves.

[0049] If the resonant tank is tuned perfectly, then that would mean that there is no, or almost no, power detectable around DC. If there is power detected around DC, then that would mean that the resonant tank is not tuned fully correct to the resonant frequency. The control mechanism may control the tuning voltage based on the detected power, for example the detected power around DC.

[0050] In an example, the control mechanism further comprises: a low pass filter arranged for filtering said output of said mixer before said detection of said power.

[0051] In a further example, the mixer comprises: an XOR-gate, wherein a first input of said XOR gate is connected to one of two inputs used for said differential mode, DM, injection voltage, and wherein a second input of said XOR gate is connected to one of two outputs of said resonant tank.

[0052] If both the inputs of the XOR gate detect power then the output of the XOR gate is zero. If only one of the inputs of the XOR gate detects power then the output of the XOR gate is one.

[0053] In a third aspect of the present disclosure, there is provided a phase- locked loop comprising a signal generator in accordance with any of the previous examples and / or a frequency multiplier circuit in accordance with any of the previous examples.

[0054] In a fourth aspect, there is provided an electronic apparatus comprising a signal generator in accordance with any of the previous examples and / or a frequency multiplier circuit in accordance with any of the previous examples.

[0055] The electronic apparatus may, for example, be a communication apparatus.

[0056] In a further example, the communication apparatus is a User Equipment, UE, for a cellular communications system or a radio base station for a cellular communications system, like a gNodeB or an eNodeB.

[0057] In another aspect of the present disclosure, there is provided a method of operating a frequency multiplier circuit in accordance with any of the previous example, wherein said method comprises the steps of: receiving, by said injecting locking circuit, said DM injection voltage and providing, by said injecting locking circuit, said harmonic of said DM injection voltage to said resonant tank; receiving, by said amplifier, a tuning voltage at a first input and a voltage at a centre tap of said resonant tank at a second input; wherein the frequency multiplier circuit comprises a feedback path from the output of the amplifier to the centre tap of the resonant tank.

[0058] In a further example, the feedback path further comprises a transistor, and wherein said method further comprises the step of: receiving, by said transistor, said output of said amplifier.

[0059] In a further example, the resonant tank comprises two series connected inductors for providing said inductance, wherein said centre tap is in between said two in series connected inductors.

[0060] In yet another example of the present disclosure, there is provided a method of operating a signal generator in accordance with any of the previous examples, wherein said method comprises the steps of: mixing, by said mixer, said differential mode, DM, injection voltage with said output of said resonant tank; detecting, by said control mechanism, said power in said output of said mixer, and controlling, by said control mechanism, said tuning voltage based on said detected power.

[0061] In a further example, the control mechanism further comprises a low pass filter, and wherein said method further comprises the step of: filtering, by said low pass filter, said output of said mixer before said detection of said power.

[0062] In yet another example, the mixer comprises an XOR-gate, and wherein a first input of said XOR gate is connected to one of two inputs used for said differential mode, DM, injection voltage, and wherein a second input of said XOR gate is connected to one of two outputs of said resonant tank.

[0063] In the appended figures, similar components and / or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label. The above and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter.

[0064] Brief description of the drawings

[0065] Figure 1 discloses an adaptive Antenna System, AAS, arrangement with an Local Oscillator synthesizer that also includes phase shifting functionality locally for each frond-end;

[0066] Figure 2 discloses an AAS arrangement with a central frequency feeding multiple phase shifters and each then drives a multiply by M circuit to feed the frondend;

[0067] Figure 3 discloses an implementation of a frequency multiplier circuit in accordance with the present disclosure;

[0068] Figure 4 discloses an example of a signal generator in accordance with the present disclosure;

[0069] Figure 5 discloses a flow chart in accordance with the present disclosure;

[0070] Figure 6 discloses an example of an electronic apparatus in accordance with the present disclosure;

[0071] Figure 7a and 7b disclose the tuning range corresponding to the 3rdharmonic and the 5thharmonic of the injected fundamental frequency.

[0072] Detailed description

[0073] It is noted that in the description of the figures, same reference numerals refer to the same or similar components performing a same or essentially similar function.

[0074] A more detailed description is made with reference to particular examples, some of which are illustrated in the appended drawings, such that the manner in which the features of the present disclosure may be understood in more detail. It is noted that the drawings only illustrate typical examples and are therefore not to be considered to limit the scope of the subject matter of the claims. The drawings are incorporated for facilitating an understanding of the disclosure and are thus not necessarily drawn to scale. Advantages of the subject matter as claimed will become apparent to those skilled in the art upon reading the description in conjunction with the accompanying drawings.

[0075] The ensuing description above and below provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.

[0076] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." As used herein, the terms "connected," "coupled," or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word "or," in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0077] Figure 1 discloses an adaptive Antenna System, AAS, arrangement with an Local Oscillator synthesizer that also includes phase shifting functionality locally for each frond-end.

[0078] In antenna array systems the Local Oscillator path is often chosen to add phase control functionality. An example of an implementation is shown in figure 1 , where each front-end has a local Phased Locked Loop, PLL, system with phase shifting capability and a frequency multiplier afterwards. This solution may be expensive in terms of chip area as each local PLL would fill a large footprint. An attractive solution would be then to have one central PLL generating a continuous wave for all the front-ends. This is shown in figure 2.

[0079] The phase control functionality is implemented by adding a phase shifter before or after the frequency multiplier. Figure 2 shows a phase shifter connected to the output of the PLL. To compensate for the phase shifter loss, buffers and amplifiers are usually inserted to boost signal levels. A benefit of phase shifting before multiplication is that since the signal is multiplied in frequency then applying the shift at lower frequency reduces the overall tuning range by a factor of M, where M is the frequency multiplication ratio.

[0080] The present disclosure is directed to a frequency multiplying circuit that is able to multiply a frequency input signal by, for example 3 or 5, depending on if the input signal frequency is the third or fifth subharmonic. A specific implementation is shown in figure 3.

[0081] This is achieved by injecting a nonlinear signal that contains the fundamental frequency as well as harmonic frequencies into resonant tank tuned to a specific output frequency.

[0082] An injection locking circuit is provided for receiving a Differential Mode, DM, injection voltage. In this particular scenario, the injection locking circuit is comprised by the devices M4 and M5. Thus, the injection is performed using differential signals through devices M4 and M5. The devices may be biased such that amplitudes are higher for the high order harmonics, which may be desired. The output of the injecting devices is current that is directly injected into the resonant tank.

[0083] The resonant tank is often comprised of an inductor in parallel I series with a tunable capacitor, i.e. varactor, or a switch capacitor bank. Operating at high frequency, for example above 100 GHz, may make use of such capacitors difficult. This is because the Q-factors of the varactors and switches are very low, resulting in low output amplitude. High power consumption is then required to sustain oscillation at the output frequency.

[0084] A resonant tank is provided, which tuneable to a harmonic of the differential mode, DM, injection voltage, wherein the resonant tank comprising an inductance and a voltage controlled capacitance for tuning said resonant tank. In the example shown in figure 3, the resonant tank comprises the inductors LT1 and LT2 as well as (amongst other) gate-drain capacitances of the Field Effect Transistors, FETs, M2 and M3.

[0085] A tuning circuit is provided for tuning the resonance frequency of the resonant tank. The tuning circuit comprises the amplifier shown as an Operational Amplifier, OPAMP. The amplifier is configured to receive a tuning voltage VtUne at a first input and a voltage at a centre tap of said resonant tank at a second input. The centre tap of the resonant tank is identified in between the inductors LT1 and LT2.

[0086] The frequency multiplier circuit further comprises a feedback path from the output of the amplifier to the centre tap of the resonant tank. In this particular case, the feedback includes the FET M6 as well as the FETs M4 and M5 and the inductors LT1 and LT2.

[0087] Here, the output of the amplifier is connected to the control terminal of the FET M6, i.e. the gate terminal of the FET M6. The output of the FET M6 is connected to the injection locking circuit, i.e. to the FETs M4 and M5.

[0088] In the example shown in figure 3, varactors may be avoided by applying this feedback path that measures the center tap voltage of the resonator inductor LT 1 , LT2, i.e. multiplier common mode VCM. The voltage is compared to a predefined tuning voltage, i.e. VtUne, and the output is fed to the gate of M6 forcing the differential DC voltage to become close to VtUne.

[0089] Changing that voltage also changes the voltage-controlled capacitances in the active devices, mainly the ones of the Field Effect Transistors, FETs M2, M3, M4 and M5. Those capacitances include the gate-drain capacitance Cgd and the gatesource capacitance, Cgs. This results in changing the operating frequency of the oscillator without the need of varactors.

[0090] A benefit of using a feedback part is that no resistive elements are required in the signal path. Excessive resistance in that path would result in AM-FM conversion which directly increases the phase noise level.

[0091] Figure 4 discloses an example of a signal generator in accordance with the present disclosure.

[0092] It is desirable to be able to detect if the frequency multiplier circuit is locked to the injected signal. Then it is possible to improve locking range and account for different process corners. To demonstrate the possibility for lock detection using a simple mixer function, the frequency multiplier circuit (the multiplier core) inputs and outputs are connected to an XOR gate. The XOR gate is visualized as a mixer.

[0093] The low pass filtered XOR-mixer output may include a frequency component corresponding to the frequency difference between the injected signal and the multiplier sub-harmonic. The output of the mixer is connected to a Low Pass Filter, LPF, for filtering the signal. Using an RF power detector, PowDet, and comparing it to a threshold level, it can be judged whether an RF signal is present or not at the mixer output - and thereby also if the frequency multiplier circuit is locked or not.

[0094] The comparison with the threshold level is visualized as the comparator block. The output of the comparator block is provided to a Finite State Machine, FSM. The tuning voltage, Vtune, is then generated by a Digital to Analog converter, D / A, which converts the digital output of the FSM to an analogue tuning voltage Vtune.

[0095] As the lock range for the frequency multiplier circuit is large, there is a lower limit to the mixer output frequency meaning that the search for frequency components is simplified. Still the proposed solution for an algorithm includes an extensive search making sure that the selected tuning voltage results in centering of the tuning range.

[0096] To avoid the ambiguity of detecting no change when the multiplier does not start, i.e. it does not generate an output signal, another power detector can be used to detect the power, and its output is then monitored to detect change in its output voltage. In that case then the locking algorithm can start.

[0097] As an alternative to the above described startup algorithm, the mixer output could also be digitized using an A / D converter and the frequency content could be identified in digital domain using a correlator. The benefit of this would be a larger knowledge of the actual frequency deviation in case of an unlocked multiplier.

[0098] Figure 5 discloses a flow chart in accordance with the present disclosure.

[0099] First, the phased array system may be set up including a central PLL driving remote frequency multiplier circuits. An initial tuning voltage may be applied to the frequency multiplier circuit. The in- and outputs of the frequency multiplier circuit may be mixed. Radio Frequency, RF, power may then be detected in output of the frequency multiplier circuit. If RF power is detected then that would indicate that the frequency multiplier circuit is not tuned, i.e. out of range. If no RF power is detected then that would indicate that the frequency multiplier circuit is tuned, i.e. in range. This process may be performed for the whole tuning range, such that the tuning voltage is adjusted each time. The tuning voltage is applied at the centre of the lock range.

[0100] Figure 6 discloses an example of an electronic apparatus in accordance with the present disclosure.

[0101] The electronic apparatus 42 comprises an input terminal 44, an input device 43, an output terminal 46 and an output device 45.

[0102] The electronic apparatus may further comprise a processor 47 connected to a memory 48.

[0103] On top of the above, the electronic apparatus may comprise a frequency multiplier circuit and / or a signal generator 49 in accordance with any of the examples provided above.

[0104] The electronic apparatus may be a communication apparatus such as a User Equipment, UE, or a base station like an eNodeB or a gNodeB.

[0105] Simulations have been made on an implementation of the circuit in fig. 3 in a 22 nm technology. The MOS devices and passive components include parasitic models making the results close to a laid-out circuit. A 5 fF capacitor load was also added to the output to account for an output buffer. Figure 7a and 7b disclose the tuning range corresponding to the 3rdharmonic and the 5thharmonic of the injected fundamental frequency. The same operating conditions were kept for both fig. 7a and fig. 7b. The circuit output frequency is centered around 127GHz. The tuning range is here defined as when the circuit produces an amplitude of at least 100 mV peak.

[0106] The horizontal axis 103, 303, shows the frequency in GHz and the vertical axis 102, 302, shows the amplitude in mV at the 3rd(fig. 7a) and 5th(fig. 7b) harmonic, respectively.

[0107] These figures show the frequency tuning range 101 , 301 when injecting differential signals at one third of the output frequency (fig. 7a) and at one fifth of the output frequency (fig. 7b). When injecting at one third of the output frequency at different tuning voltages the frequency range becomes, for example, 112.5 GHz to 142.5 GHz with a tuning range of 23%. When applying one fifth of the output frequency the tuning range becomes, for example, 117.5 GHz to 137.5 GHz reducing to around 16 % due to the reduced injection efficiency.

[0108] It should be noted that the above-mentioned examples illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative examples without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A frequency multiplier circuit, comprising: a resonant tank (LT 1 , LT2, M2, M3) tuneable to a harmonic of a differential mode, DM, injection voltage, said resonant tank (LT1 , LT2, M2, M3) comprising an inductance and a voltage controlled capacitance for tuning said resonant tank (LT1 , LT2, M2, M3); an injection locking circuit (M4, M5) arranged for receiving said DM injection voltage, said injection locking circuit (M4, M5) comprising a transistor for providing said harmonic of said DM injection voltage to said resonant tank (LT 1 , LT2, M2, M3); a tuning circuit, comprising an amplifier, said amplifier being configured to receive a tuning voltage at a first input and a voltage at a centre tap of said resonant tank (LT 1 , LT2, M2, M3) at a second input, wherein the frequency multiplier circuit comprises a feedback path (M6) from the output of the amplifier to the centre tap of the resonant tank (LT 1 , LT2, M2, M3).

2. A frequency multiplier circuit in accordance with claim 1 , wherein said feedback path further comprises: a transistor (M6), wherein said output of said amplifier is connected to a control terminal of said transistor, and wherein an output of said transistor is connected to said injection locking circuit (M4, M5).

3. A frequency multiplier circuit in accordance with any of the previous claims, wherein said resonant tank (LT1 , LT2, M2, M3) comprises: two series connected inductors for providing said inductance, wherein said centre tap is in between said two in series connected inductors.

4. A frequency multiplier circuit in accordance with any of the previous claims, wherein said resonant tank (LT1 , LT2, M2, M3) further comprises:at least one fixed capacitance such that said resonant tank (LT 1 , LT2, M2, M3) is tuned to said harmonic of said DM injection voltage using said inductance, said voltage controlled capacitance and said fixed capacitance.

5. A frequency multiplier circuit in accordance with any of the previous claims, wherein said injection locking circuit (M4, M5) comprises: two injection locking transistors arranged for receiving said DM injection voltage at gates of said respective two injection locking transistors, wherein an output of a first of said two injection locking transistors is connected to a first end of said resonant tank (LT 1 , LT2, M2, M3) and wherein an output of a second of said two injection locking transistors is connected to a second end, opposite to said first end, of said resonant tank (LT 1 , LT2, M2, M3).

6. A frequency multiplier circuit in accordance with any of the previous claims, wherein said resonant tank (LT1 , LT2, M2, M3) comprises: two Field Effect Transistors, FETs, (M2, M3) wherein drains of said two transistors are connected to one another, wherein a gate of a first of said two FETs is connected to a source of a second of said two FETs, and wherein a gate of said second of said two FETs is connected to a source of said first of said to FETs, and wherein said source of said first of said two FETs is connected to a first end of said inductance, and wherein said source of said second of said two FETs is connected to a second end of said inductance.

7. A frequency multiplier circuit in accordance with any of the claims 1 - 5, wherein said resonant tank (LT1 , LT2, M2, M3) comprises: two bipolar junction transistors, BJTs, wherein emitter terminals of the two BJTs are connected to one another, where a base terminal of a first of the two BJTs is connected to a collector terminal of a second of the two BJTs, and wherein a base terminal of said second of said two BJTs is connected to a collector terminal of said first of said two BJTs, and wherein said collector terminal of said first of said two BJTs is connected to a first end of said inductance,and wherein said collector terminal of said second of said two BJTs is connected to a second end of said inductance.

8. A signal generator comprising a frequency multiplier circuit in accordance with any of the previous claims and comprising a control circuit for controlling said tuning voltage, said control circuit comprising: a mixer arranged for mixing said differential mode, DM, injection voltage with an output of said resonant tank (LT 1 , LT2, M2, M3); a control mechanism arranged for detecting power in an output of said mixer, and for controlling said tuning voltage based on said detected power.

9. A signal generator in accordance with claim 8, wherein said control mechanism further comprises: a low pass filter (LPF) arranged for filtering said output of said mixer before said detection of said power.

10. A signal generator in accordance with any of the claims 8 - 9, wherein said mixer comprises: an XOR-gate, wherein a first input of said XOR gate is connected to one of two inputs used for said differential mode, DM, injection voltage, and wherein a second input of said XOR gate is connected to one of two outputs of said resonant tank (LT1 , LT2, M2, M3).

11. A phase-locked loop comprising a signal generator in accordance with any of the claims 8 - 10 and / or a frequency multiplier circuit in accordance with any of the claims 1 - 7.

12. An electronic apparatus comprising a signal generator in accordance with any of the claims 8 - 10 and / or a frequency multiplier circuit in accordance with any of the claims 1 - 7.

13. An electronic apparatus in accordance with claim 12, wherein the electronic apparatus is a communication apparatus.

14. An electronic apparatus in accordance with claim 13, wherein the communication apparatus is a User Equipment, UE, for a cellular communications system.

15. An electronic apparatus in accordance with claim 12, wherein the communication apparatus is a radio base station for a cellular communications system.

16. A method of operating a frequency multiplier circuit in accordance with any of the claims 1 — 7, wherein said method comprises the steps of: receiving, by said injecting locking circuit, said DM injection voltage and providing, by said injecting locking circuit, said harmonic of said DM injection voltage to said resonant tank (LT1 , LT2, M2, M3); receiving, by said amplifier of said tuning circuit, a tuning voltage at a first input and a voltage at a centre tap of said resonant tank (LT 1 , LT2, M2, M3) at a second input, wherein the frequency multiplier circuit comprises a feedback path from the output of the amplifier to the centre tap of the resonant tank (LT 1 , LT2, M2, M3).

17. A method in accordance with claim 16, wherein said feedback path further comprises a transistor, and wherein said method further comprises the step of: receiving, by said transistor, said output of said amplifier.

18. A method in accordance with any of the claims 16 - 17, wherein said resonant tank (LT1 , LT2, M2, M3) comprises two in series connected inductors for providing said inductance, wherein said centre tap is in between said two in series connected inductors.

19. A method of operating a signal generator in accordance with any of the claims 8 - 11 , wherein said method comprises the steps of: mixing, by said mixer, said differential mode, DM, injection voltage with said output of said resonant tank (LT 1 , LT2, M2, M3);detecting, by said control mechanism, said power in said output of said mixer, and controlling, by said control mechanism, said tuning voltage based on said detected power.

20. A method in accordance with claim 19, wherein said control mechanism further comprises a low pass filter, and wherein said method further comprises the step of: filtering, by said low pass filter, said output of said mixer before said detection of said power.

21. A method in accordance with any of the claims 19 - 20, wherein said mixer comprises an XOR-gate, and wherein a first input of said XOR gate is connected to one of two inputs used for said differential mode, DM, injection voltage, and wherein a second input of said XOR gate is connected to one of two outputs of said resonant tank (LT1 , LT2, M2, M3).

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