A transistor stress state model and its applications

Abstract

A, preferably computer-implemented, method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.

Description

[0001] Description

[0002] Title of the Invention

[0003] A Transistor Stress State Model and its Applications

[0004] Technical Field

[0005] The present disclosure relates to the design, manufacturing and / or test of integrated circuits. More particular the present disclosure relates to a, preferably computer-implemented, method of determining latent defects in an integrated circuit, an augmented library cell, a computer program and an apparatus or system.

[0006] Background Art

[0007] Testing is a very important step in the fabrication of integrated circuits. The manufacturing process in the nanometer era is very susceptible to flaws and an early screening of integrated circuits is mandatory to prevent defective integrated circuits in the field. Among the general detection of flawed integrated circuits, the detection of latent defects is of immense importance.

[0008] Latent defects are introduced in the manufacturing process and usually caused by wear-out mechanisms like Negative Bias Temperature Instability, NBTI, Hot-Carrier Injection, HCI, or Time-Dependent Dielectric Breakdown, TDDB. These defects are not detectable during the initial tests of an integrated circuit. As a result, integrated circuits, ICs, containing latent defects pass the tests and are used for further processing and shipped to customers. However, latent defects are a main reason for early life failures. The shipped ICs are highly likely to fail in the field causing customer returns and / or increased costs or even safety and / or security risks when used.

[0009] A method to detect latent defects already early in the testing phase is the stress test. Here, the ICs are conducted to a higher stress level to accelerate the wear-out effects, i.e. , make the latent defects permanent and thus observable and / or detectable in the following test steps. The induced stress is especially known to accelerate various gate oxide defects. As a result, the ICs are more likely to fail already during the testing phase and not in the field afterwards. The reduction of the so-called infant mortality is an important part on the road to achieve zero defective parts per billion.

[0010] In general, the stress can be induced by two different means: temperature and elevated supply voltage. Both means cause an increase of the electrical activity or field inside the IC accelerating the wear-out effects. One important part of the stress test is the application of certain patterns or stimuli to the IC or cell causing the activity on the die. These patterns or stimuli have a fundamental significance on the stress test since they create the activity which in turn induces the stress on the transistors of the cell or the IC, as the case may be.

[0011] S. Natarajan, A. Sathaye, C. Oak, N. Chaplot and S. Banerjee, "DEFCON: Defect Acceleration through Content Optimization," 2022 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2022, pp. 298-304, doi: 10.1109 / ITC50671.2022.00038 describes that during manufacturing of integrated circuits, it is imperative for cost and quality that defects that occur on the die are screened early in the test process, preferably before packaging. As part of screening, stress steps are performed to accelerate latent defects so that they become observable and are detected by subsequent test steps. Traditionally, the levers for applying stress have been increased supply voltage and temperature while concurrently running a sliver of content that had been created to "test" defects. S. Natarajan et al. describe a methodology to generate content specifically targeting stress at latent defects by maximizing electrical activity. It is their goal to efficiently accelerate all classes of latent defects.

[0012] Summary

[0013] It is an object of the present disclosure to determine latent defects, for example in order to make them permanent, and thus to improve the detection of latent defects, e.g., early in the testing phase and / or preferably using one or more stress tests.

[0014] According to a first aspect, the object is achieved by a, preferably computer-implemented, method. The method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.

[0015] According to a second aspect, the object is achieved by an augmented library cell comprising a description of the connectivity of the elements of a library cell, e.g., in the form a netlist and / or a hardware description language, and a stress target of the library cell, wherein the stress target is obtained by and / or is indicative of one or more stress states of at least one transistor of the library cell. According to a third aspect, the object is achieved by a computer-program, preferably stored on a non-transitory medium, comprising program code that when executed performs the method steps according to the first aspect.

[0016] According to a fourth aspect, the object is achieved by an apparatus or system comprising a memory configured to store computer-executable instructions; and a computing system, such as a processor, which in response to execution of the computer-executable instructions, is configured to perform the method steps according to the first aspect.

[0017] Further advantageous aspects are provided herein, inter alia in the dependent claims, the drawings, and the detailed description.

[0018] The aspects disclosed herein provide an effective, universal solution for generating effective stress test patterns and / or stimuli, and / or allow to measure the quality of existing patterns. In particular, the quality of the generated stress test patterns may be determined and / or improved. This results in lower PPM levels for the produced ICs to customers due to a reduction of early life failures. By way of highly optimized stress test patterns or a set of test patterns the test costs can be significantly reduced. A further main advantage is the flexibility. The relevant data may be generated once per library cell and can be reused for different IC designs, e.g. comprising one or more instances of the library cell.

[0019] Independent of the grammatical term usage, individuals with male, female or other gender identities are included within the term.

[0020] Brief Description of the Drawings

[0021] Fig. 1 shows an illustration of an integrated circuit.

[0022] Fig. 2 illustrates testing of an integrated circuit.

[0023] Fig. 3 illustrates an exemplary library cell.

[0024] Fig. 4 illustrates a transistor with and without a latent defect.

[0025] Fig. 5 illustrates an NMOS and a PMOS transistor, respectively, with short circuits.

[0026] Fig. 6 illustrates a state model of a transistor.

[0027] Fig. 7 illustrates stress states of an NMOS and a PMOS transistor, respectively.

[0028] Fig. 8 illustrates additional stress states of a PMOS and a NMOS transistor, respectively.

[0029] Fig. 9 illustrates cycles between stress states of a transistor for detecting open defects. Fig. 10 illustrates exemplary method steps, and the relevant input and output data for determining latent defects with a focus on generation of stress relevant data and / or identification of stress states, e.g., a stress view.

[0030] Fig. 11 illustrates exemplary method steps, and the relevant input and output data for determining latent defects with a focus on stress test applications, e.g., based on a stress view.

[0031] Fig. 12 illustrates an exemplary insertion of a test pattern into a scan chain.

[0032] Fig. 13 to Fig 26 show exemplary method steps according to different aspects.

[0033] Detailed Description

[0034] Figure 1 shows an illustration of an integrated circuit, IC, also referred to as chip or microchip. On an IC, elements such as transistors, resistors, capacitors, and / or inductors, are interconnected, e.g. via a wiring. Nowadays, each manufactured chip is subjected to one or more tests, e.g. one or more manufacturing tests and / or stress tests, ensuring the overall quality. Therein, latent defects are a major concern. These latent defects can often not be detected during a manufacturing test and are a major reason for early life failures. In order to determine or detect any latent defects, e.g. to make the latent defect permanent, stress tests are used.

[0035] As shown in Figure 2, the IC, also referred to as Circuit Under Test, CUT, in Figure 2, may be tested. Once a stimulus and / or test patterns are generated, the expected response of the integrated circuit for each pattern is obtained in pre-silicon. Herein, a test pattern or pattern refers to the inputs of the integrated circuit, whereas a stimulus is referred to herein as the inputs for (an instance of) a library cell. The expected responses along with the patterns or stimulus are then stored, e.g., in the memory of Automatic Test Equipment, ATE. In post-silicon, the manufactured chip is tested in a so-called manufacturing test, for example using the ATE which loads the pattern or stimulus and compares it with the expected response for pass or fail status.

[0036] However, latent defects might not be detected because the relevant transistor states or stress states haven’t been determined or identified beforehand. To prevent this, a test step referred to as stress test may be performed before the manufacturing test. The goal of the stress test is to determine latent defects by stressing them, in order for the one or more latent defects to become real defects or actual defects, and thus to be detected in the following manufacturing test. Hence, a stress test may be performed to cause one or more latent defects to become real defects. The provoked one or more defects can then be detected during the subsequent manufacturing test.

[0037] There is thus a need to generate an efficient stress test stressing, preferably all, transistors of a (instance of a) cell and / or IC with improved and preferably maximum coverage. Today, there is no automated workflow available solving this problem. Currently, a stress test may be performed with a stress test set, e.g., comprising one or more patterns, which however is not generated for the specific need(s) of the stress test, e.g. for the specific cell, instance, and / or IC. In particular, toggle tests are used since they promise a certain degree of stress. However, these stress tests have the shortcoming that they are generated without any view inside of the cell and therefore lack quality. It is thus proposed herein to adapt the stress test to the one or more specific cells or cell instances in an IC. Recent works, cf. , e.g., US 2020 / 0302028 A1 , use analog simulations to measure the current inside a cell to identify stress test scenarios on selected locations inside cells but his approach is not able to target all stress scenarios and is not able to provide a maximum or at least optimized coverage of the stress test.

[0038] Hence, new aspects for determining one or more latent defects are proposed herein. A transistor stress state model may be used to that end. Furthermore, a switch-level simulation may be used to determine all stress scenarios inside a cell, i.e. the one or more stress targets. The scenarios may be transformed into a stress view of the cell, which may be stored in the library cell. Alternatively, the stress view may be associated with the library cell. The stress view allows, e.g., based on a, e.g., switch-level and / or analog, simulation of one or more stress test patterns of a test set, to calculate the stress test coverage of the respective stress test pattern. Coverage gaps may be eliminated by the usage of a shift and / or capture cycle approach, as proposed herein. The aspects and embodiments proposed herein achieve a stress test of higher quality and / or coverage than known solutions. Furthermore, aspects and embodiments provide a coverage metric and the ability to close coverage gaps, e.g., during the generation, of stress test patterns and / or stimuli. A main advantage is achieved by the use of the transistor stress state model, the creation of a stress test view based on the transistor stress state model, and / or the use of shift cycle(s) for automatic test pattern generation, ATPG, or in an automatic test pattern generator. The stress view refers to information and / or data identifying stress states (or cycles between such stress states) of the one or more transistors in a library cell.

[0039] Fig. 3 illustrates an exemplary library cell. A library cell is also referred to as a standard cell, or simply as cell. A layout model or view of an exemplary library cell is shown in Figure 3. One or more library cells may form a cell library, i.e., comprising the one or more library cells. A library cell may be understood as a group of elements such as one or more transistors and / or interconnect structures that provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) and / or a storage function (flipflop or latch). A cell's boolean logic function is referred to as its logical view, i.e. , the functional behavior of the cell is captured in the form of a truth table or Boolean algebra equation (for combinational logic), or a state transition table (for sequential logic). A library cell is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches, and / or buffers. These cells may be realized as fixed-height, variablewidth full-custom cells. These library cells are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. A library cell may also comprise the following one or more components: a layout of the cell, a SPICE model of the cell, a Verilog model or VHDL-VITAL model, parasitic extraction models and / or one or more design rule checks. In any case, a library cell may thus comprise one or more, e.g., of the mentioned, elements, e.g., in the form a netlist and / or hardware description language.

[0040] The initial design of a standard cell is developed at the transistor level, in the form of a transistor netlist or schematic view. The netlist is a nodal description of transistors, of their connections to each other, and of their terminals (ports) to the external environment. A schematic view may be generated with a number of different Computer Aided Design, CAD, or Electronic Design Automation, EDA, programs that provide a Graphical User Interface, GUI, for this netlist generation process. Designers use additional CAD programs such as SPICE to simulate the electronic behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and then calculating the cell’s or circuit's time domain (analog) response. The simulations verify whether the netlist implements the desired function and / or predict other pertinent parameters, such as power consumption and / or signal propagation delay.

[0041] Since the logical and / or netlist views are only useful for abstract (algebraic) simulation, and not device fabrication, the physical representation of the standard cell must be designed too. Also called the layout view, this is the lowest level of design abstraction in common design practice.

[0042] Now, when a cell is used in an IC or a design of an IC, IC design, it may be referred to as instance. The IC design, and thus the instances, are synthesized, e.g., by a logic synthesis tool, into a netlist. The netlist is the cell representation of the design, at the logical view level. It comprises instances of the standard-cell libraries’ gates and the connectivity between the gates. Furthermore, it should be understood that the implementation of a cell on an integrated circuit, e.g., made of a semiconductor material, may also be referred to as an instance. Hence, once the front-end process, i.e., the formation of transistors in the semiconductor material, such as silicon, has been completed, the integrated circuit is subjected to a variety of tests, e.g., said mentioned manufacturing test and / or stress test, to determine if it functions properly.

[0043] An example of a transistor is illustrated in Figure 4. The transistor as-designed is shown on the left-hand side. On the right-hand side a potentially faulty transistor, i.e. having a latent defect, is depicted. This transistor possesses a latent defect on the gate oxide which is able to break when stress is applied. However, the stress is not evenly distributed across the die of the integrated circuit but depends on the applied signals, i.e. pattern(s) or stimulus / stimuli, depending on whether reference is made to the inputs of the IC or the cell(s) therein. If the wrong set of (stress test) patterns or (stress test) stimuli is applied to the integrated circuit or the circuit(s) of a cell, there is a risk of stress coverage holes, i.e., some parts of the IC, instance or cell are not stressed and therefore leaving one or more latent defects unexposed. Herein a transistor stress state model, TSSM, and a methodology to create a stress view for one or more library cells, as well as an application flow to assess and / or improve the quality of the stress test and / or the manufacturing test is proposed. In particular, this may comprise a shift and / or capture cycle test approach.

[0044] The transistor stress state model, and e.g. the stress view, allows to measure the quality of the applied stress test stimuli and / or stress test patterns, as the case may be. This is achieved by using a cell-aware stress definition based on the transistor states inside a cell. A cell, or for example all cells of a cell library, is analyzed, and for example for each cell or instance thereof, one or more, or all, stress scenarios are listed, e.g., as stress states, and stored in the cell and / or the library - or are associated with the cell or library. Furthermore, the transistor stress state model allows extraction of the missing stress scenarios, e.g., in an existing stress test pattern, and / or to create stress test stimuli or patterns to close the coverage gap resulting in a reliable stress test.

[0045] As mentioned, stress can be induced by two different means: temperature and elevated supply voltage. Burn-in testing is very costly since costly equipment, e.g., heat chamber, is needed as well as a large amount of test time. Therefore, stress testing with elevated voltage is widely used to screen out latent defects. This is typically referred to as High Voltage Stress Testing, HVST. The use of HVST is known to significantly reduce the amount of burn-in. During HVST patterns or stimuli are applied at higher-than-normal voltage for a short period of time. The duration of the stress is related to defects and / or process technology, but a short duration is usually sufficient. On the other hand, built-in circuitry to monitor and / or control effects, e.g., high voltage generation, and screen out defects may be used. However, this goes along with additional hardware overhead. Still further, thermal activation energy may be calculated and a confidence value for stress test can be modelled.

[0046] The selection of the stress test (patterns) which are to be applied is very important since these stress tests are responsible for each transistor having a high voltage across its oxide. Iddq or toggle tests are widely used as patterns or stimuli since they are able to provide switching activity on signal lines. An optimal toggle test set is able to switch the polarity of each signal line, i.e. , a gate’s output and the gate’s inputs. This model is inaccurate since toggling of the cell inputs does not guarantee stress on each transistor inside the cell. Furthermore, stress on a transistor can be defined as elevated voltage on the gate terminal and low voltage on the drain and source terminal for NMOS. For PMOS, it is the opposite. Stress tests are then generated using (pseudo) stuck-at faults. However, this stress model misses some important stress scenarios like the negative-bias temperature instability, NBTI, effect. Using the test set of a Pseudo-Stuck-at Fault, PSF, model for the minimized two-level sum of product, SOP, circuit representation of the cell’s function provides full coverage for the leakage fault model. A leakage fault models a short between pairs of transistor terminals, i.e., gate, source, drain and bulk. This may be extended to stress tests. Therein, the same fault model, i.e., the PSF model, may serve also as a basis for the stimuli generation. However, this fault model has an inherent flaw when it comes to stress test in the state-of-the-art IC design. The development process transitioned from using simple gates to using complex cells with various corners for different power and delay behavior. The simplified PSF model is only able to provide full coverage for cells in its minimized form. The reason lies in specific assumptions made for the underlying leakage fault mode.

[0047] A transistor is strongly sensitized on (off) when its gate is driven to its on (off) value and its source (drain) is assuming the strong value. Furthermore, this is only valid when a change on its gate inverts the cell’s output. The latter condition is especially important for the usage of the PSF model since the PSF model always assumes a fault on a cell’s output. Without this restriction, no full coverage can be guaranteed. Hence, a cell-aware modelling for stress test was proposed. Hitherto, a defect inside the cell was extracted, simulated, and mapped onto a set of stimuli on the cell’s inputs. These cell stimuli were then used to generate one or more test patterns, e.g., by an ATPG tool, cf. US20100229061A1. This in part allowed to cope with the increase of cell complexity.

[0048] Analogously to the general use of cell-aware testing there is a need of a cell-aware solution for stress testing. Hitherto, an analog simulation of the cell may be performed to determine or measure the power, e.g. the current, on the one or more inner nodes of one or more cells and extract stimuli producing high stress on certain inner nodes. These stimuli are given to an ATPG tool to produce one or more stress test patterns. However, this method can only be used with a limited number of pre-defined measurement points and does not specify a coverage. Furthermore, it was shown that manufacturing tests generated for detecting defects are ineffective in accelerating latent defects, i.e. for stress testing. However, latent defects are a major reason for early-life failures. In particular, MOS transistors are prone to latent defects due to pinholes in the gate oxide. There is thus still a need for a structured method to address each and all potential latent defect in an IC (design).

[0049] Turning to Figure 5 transistor terminals with shorts are shown. Latent defects may be determined and / or activated, i.e. made permanent, by inducing stress on the MOS transistor to accelerate aging. The main aging effects are Hot Carrier Injection, HCI, for NMOS and Negative Bias Temperature Instability, NBTI, for PMOS as well as Time-Dependent Dielectric Breakdown, TDDB. HCI occurs when electrons or holes gain enough energy to overcome the barrier between the conducting channel and the gate through the oxide. This effect grows larger when the electric field increases. In order to stress the transistor with respect to HCI, an elevated bias has to be applied across the gate along the gate-source and the gate-drain path. NBTI is caused by a constant electric field which degrades the dielectric. This in turn causes a degradation in the threshold voltage leading to a failing device due to lower switching speed. In order to induce NBTI stress on the transistor, the gate must be negatively biased with respect to source and drain, i.e. the PMOS transistor’s gate has to be logic 0 while source and drain are grounded. The TDDB effect modifies the dielectric film of transistors and creates a conducting path between the gate oxide and the gate terminal. This, in turn, causes higher power consumption and the impairs the voltage level. Typically, TDDB is caused by constant voltage stress on the gate.

[0050] The specific physical defect is not important for the stress test, but the way stress is induced on the transistor. A latent defect may be modelled as a short between all transistor terminals, i.e., gate, drain, source as well as an open on the source and drain terminal. The bulk terminal is not modelled here since it is not relevant for stress test generation. Figure 4 shows an NMOS transistor on the left-hand side and a PMOS transistor on the right-hand side. Both MOS transistors have potential latent short locations indicated by VGS, VGD and VDS. There is a difference in how stress is induced to latent short defects and latent open defects. For latent short defects, it is sufficient to increase the electric field across the gate using an elevated bias. This is not enough for latent open defects. Here, the stress is induced by current flow caused by switching. This difference has also an effect on the stress stimuli generation. For latent short defects, a one cycle stimuli can be used while open defects need two cycles to make sure that switching occurs.

[0051] Now turning to Figure 6, transistor states of a transistor t are shown. That is, the transistor model may comprise transistor states wherein one or more of the transistor states are stress states. The transistor states may be the switching states of the transistor and / or may be given by a high or low voltage signal applied to each of the one or more transistor connections. The stress states may correspond to a stress model of the transistor, or to put it differently, the transistor may be modelled by one or more stress states. A fault model for a stress test, e.g., the PSF model, may not be accurate enough to cope with a cell-aware test approach. A transistor stress state model, TSSM, is thus proposed to identify stress scenarios or stress states for one or more, or preferably each, transistor inside a cell. The TSSM allows assessing the stress induced to a cell by an input stimulus, e.g., with respect to the coverage of the stimulus. Stress on the transistor is induced by specific transistor states, i.e. , elevated voltage across terminal shorts and current through opens. Therefore, it is proposed to formalize the effect of a stimulus for the one or more transistors of a cell.

[0052] Independently from the type of the transistor, i.e., PMOS or NMOS, a transistor may be modelled as a tuple t of its connections, i.e., gate (g), drain (d) and source (s): t = {g,d,s}. When applying a stimulus to the inputs of a cell, each connection inside a cell assumes a certain voltage value. For the low voltage value the notation (0) and for the high voltage value the notation (1) is used. Values outside the low / high voltage ranges can be defined as unknown (X). However, unknown values are not valid for any tests, therefore these are not considered in the proposed model. Furthermore, two different scenarios are distinguished with respect to the value on the transistor’s gate. A transistor is OFF when its gate value is 1 for PMOS and when its gate value is 0 for NMOS. A transistor is ON when its gate value is 0 for PMOS and when its gate value is 1 for NMOS. No current flows when a transistor is OFF. With respect to this definition, the transistor states are given in the table of Figure 6. Therefore, a single cycle transistor state St for transistor t consists of one transistor state St = {TRoffOO, TRoffOl , TRofflO, TRoffl 1 , TRonOO, TRonOI , TRonlO, TRonl 1}. The two-cycle transistor state St2 is modelled as the transition between two single cycle states St2 = St -> St. As an example, when a transistor t assumes the state TRoffOl , the transistor blocks while there is high voltage on the source terminal and low voltage on the drain terminal. When the transistor is modelled in two cycles and it assumes the state TRofflO -> TRonlO, the gate terminal switches from OFF to ON and the conducting channel is formed. Turning to Figure 7, the stress scenarios or stress states may be specified based on the transistor states. The way stress is induced on the transistor can vary for different technologies. The transistor state model, as e.g. shown in Figure 6, is a general model and technology independent. The following stress scenarios or stress states are based on the current state-of- the-art but can be replaced by other scenarios if needed when other technologies are used. In order to stress the latent short defects, there has to be an elevated bias across the defect location. This is achieved by having opposite values on the shorted terminals. Here, it has to be distinguished between PMOS and NMOS transistors since the gate value is different. The transistor states shown in Figure 7 stress the potential latent short defects VGS, VGD as well as VDS.

[0053] Additionally, as shown in Figure 8, the stress states may include TRonOO for PMOS transistor’s NBTI stress test and TRoffl 1 for NMOS transistor’s PBTI stress test. Here, the gate is negatively biased, e.g., with elevated temperature. Since the effect of PBTI for NMOS transistors is less relevant for aging, it is often not considered and could also be left out.

[0054] Furthermore, and as shown in Figure 9, in order to stress the latent open defects, a current has to flow through the transistor. This happens when either the source or drain assumes the 1 value and the gate switches von OFF to ON. Additionally, when the gate is ON and either the source or drain switches from 0 to 1 when the other terminal is 0. The two cycle stress tests shown in Figure 9 are needed to target the gate, drain and source opens.

[0055] The set of all transistor states inducing stress on the transistor t is referred to the stress states or the state stress set of t. Each transistor, e.g., of a library cell, should be brought into a stress state during an effective stress test.

[0056] Now turning to Figure 10, a stress test, preferably based on the transistor stress state model, TSSM, is described.

[0057] In general, the design flow for ICs is typically based on the use of a, e.g., technologydependent, cell library comprising one or more library cells. Therein, one or more (latent) defects may be mapped onto the boundaries, i.e. inputs, of each cell during a process which may be performed for one or more cells, e.g., each cell, in a cell library, for example, to avoid the use of an analog simulation during the stress test (generation) flow. In cell-aware stress testing, analog cell simulation and / or defect simulation may be used to identify stress test patterns and / or stimuli detecting the (latent) defects inside the cell. These cell-aware stress tests may be stored in the library cell as well and / or may be used for test generation and / or simulation.

[0058] Now, a stress test generation and / or simulation is proposed using one or more stress targets. Therein, the stress target may be given as the one or more stress states of the one or more transistors in the one or more library cells. This allows for creating a transistor stress view for one or more library cells. The proposed application flow may be (conceptually) divided into two steps, as shown in Figure 10: In Step 1 (comprising substeps F1, F2) the stress relevant data, e.g., said stress target, is generated. The Step 1 requires input data D1 , and P1 and / or P2, as the case may be, to execute the necessary calculations. In particular, the input data D1 may include a spice view or other description, e.g. of the layout, of the one or more library cells, for example of an IC (design). At the end of Step 1 , a stress view D2 is created. In Step 2, indicated by substep F3, the stress view D2 generated by Step 1 is used to execute one or more stress test applications. The stress vie wis equivalent to and / or may comprise the stress target. The stress target may comprise the stress states, and for example additional data as described herein.

[0059] At first, a layout extraction step may be performed, which reads the layout data D1 of the individual library cell and / or creates a transistor netlist, e.g., a SPICE list, for example in a detailed standard parasitic format (DSPF), in particular including parasitic elements like resistors and capacitors which for example is stored in a file format of input and / or layout data D1. The one or more cells, e.g., each cell, for example of a cell library, may then be simulated. To that end, a switch-level simulation may be performed in step F1, with input combinations P1 and / or P2, wherein P1 comprises (all possible) single cycle inputs, and P2 comprises (all possible) two cycle inputs as will be described in further detail below. Thereupon the one or more stress states and / or the input stimulus for reaching said stress states may be obtained as a result of step F1. Hence, the stimulus at the input of a cell for reaching a certain transistor state, preferably the one or more stress states of the one or more, preferably all, i.e. each, transistors of the cell, may be determined.

[0060] Thereupon, an analog fault simulation may be performed in a step F2. The analog fault simulation may comprise the extraction of one or more stress states, e.g., obtained as a result of step F1. The aim of the analog simulation then is to determine, or measure, the current (values) through one or more, or preferably each, transistor of a cell, or one or more cells of an IC (design) as the case may be. The resulting data D2, e.g., comprising the current (values) of a transistor in the stress states, may be stored, e.g., together with the stress target, i.e. the stress states and the associated input. The resulting data D2 may be stored as the cell-dependent data D2, e.g., in a file format. The analog simulation may take the input combinations of (all possible) single cycle inputs P1 and / or (all possible) two cycle inputs P2 as input, e.g., in addition to the stress states obtained by step F1. The analog simulation of step F2 may also be based on the inputs for reaching the stress states as determined by step F1 , e.g., the analog simulation may be based on the stimulus for reaching the stress states of the one or more transistors of the one or more cells (instead of all possible input combinations P1 and / or P2).

[0061] The data generation flow (Step 1) for one or more library cells is outlined below and may comprise one or more of the following steps:

[0062] / / Data generation stage

[0063] M = empty set;

[0064] For each c e set of library cells

[0065] P1 = determine single cycle input combinations(c) Determine transistor stress states (c, P1) Analog simulation (c, P1)

[0066] Optionally{

[0067] P2 = determine two cycle input combinations(c)

[0068] Determine transistor stress switching activity (c, P2)

[0069] Analog simulation (c, P2)

[0070] }

[0071] M += c

[0072] End c is applicable

[0073] End

[0074] Optionally{

[0075] / / Data collection stage

[0076] For each c e M

[0077] Add transistor stress state data (c)

[0078] Add transistor stress switching data (c)

[0079] Add cell current data (c)

[0080] End

[0081] } As mentioned, the analog simulation may be performed optionally, e.g. in addition to the determination of the stress states of the one or more transistors of a cell, for example in order to determine relevant data, such as one or more current values, for performing the stress test and / or one or more stress test applications.

[0082] Now turning in more detail to substep F1 , i.e., the switch-level simulation, for determining and / or generating of the transistor stress state data, e.g., said one or more stress states and / or (input) stimuli for reaching said stress states, in a cell-aware stress test. The switch-level simulation or modeling provides a level of abstraction describing the interconnection of transmission gates of IC and / or cell circuit elements, such as transistors. One or more of the transistor states may form the stress states of a stress target or stress test for a (single) transistor. The flexibility of the proposed approach allows to modify the stress test according to the used technology and / or use only a subset of these transistor states, e.g., the stress states, if needed.

[0083] The set of one or more, or preferably all, stress states for one or more, preferably all, transistors in a cell c may be referred to the stress target or stress target set of a cell c. More specifically, a stress target of a cell is a tuple (t, st, V) of the transistor t, the transistor state st, e.g., a stress state, as well as a set of input stimuli of the cell V leading to the transistor state st.

[0084] The transistor t and the stress states st may be known by definition or custom setup, or may be identified as described herein. In general the stress states may form a (true) subset of the transistor states. In the step F1 , the stimuli set V has to be generated to form the stress target(s). Each cell in the library may need to be simulated, e.g., with (all possible) input combinations P1 and / or P2. The number of simulations depends on the number of cell inputs. For a cell with n inputs, 2nstimuli have to be simulated for single cycle, i.e. P1 , as well as 22nstimuli for two cycles, i.e. P2. Furthermore, the switch-level simulation may need to be able to identify the voltage value on each transistor terminal to determine the transistor. For each stimuli, the transistor state of each transistor may be recorded, i.e. the values on the transistor terminals, e.g., given by the input stimuli, have to be mapped to a specific transistor state. Thus, the stress states of the one or more, or preferably all transistors, e.g. in a cell, may be associated with the input stimuli leading to the stress states, or vice versa the input stimuli leading to the respective transistor stress state(s) may be identified and may then be associated with said stress state(s).

[0085] Given a stimuli V and a (complete) set of transistors T = {t1 ,... ,tm} of the cell, the switch-level simulation results in a set of transistor states Sv = {st 1 , ... ,stm}. Those transistor states which corresponds to transistor stress states st are extracted and a stress target is created by inserting, linking or associating the stimuli set V to the corresponding stress target. This information may be stored in the respective cell, and / or in the library at each cell as data D2 or may be associated with each cell, e.g. by linking the stimuli set V to the respective cell.

[0086] Now turning in more detail to substep F2, i.e. , the analog simulation. An analog simulation is also performed for stimuli P1 and / or P2, e.g., in addition to the switch-level simulation. Alternatively, the analog simulation may (only) be performed for the stimuli set V leading to the stress states of the transistors of the one or more cells. The aim of the analog simulation is to determine or measure the current through one or more, or preferably each, transistor of a cell, preferably for the stress states of the transistors. The resulting data, e.g. indicating the current through the transistor in each of its states, or preferably (only) in its stress states, may be stored together with the stress target (data) as data D2. This data D2 may then be used to weight the relevance of input stimuli for the one or more stress targets, e.g., an input stimuli with a higher current through transistor t can be prioritized with respect to an input stimuli for the same transistor t with a lower current.

[0087] Step 1 may be executed, e.g., once, on cell library level, i.e. for (each one of) the one or more cells in a cell library. Step 2 may be executed at IC design level, e.g., comprising instances of one or more library cell in an IC or IC design.

[0088] In the second step “Step 2”, indicated by F3, the data and / or stress view, D2, generated by Step 1 may be used to execute different applications with respect to the stress test. Thus, now turning in more detail to the second step F3, i.e., one or more stress-test applications. After the stress relevant data D2 has been generated in sub-steps F1 and / or F2, this data D2 may be used in Step 2, i.e., in one or more sub-steps F3a, F3b, F3c, F3d. As shown in Figure 11, a fault model for a stress target fault may be generated in a step F3a. Therein, the data D2 is used to create further data for the different applications. The different stress target fault models can be used to perform different stress-test variants. The stress target fault model may then be applied for fault grading (existing) stress test patterns D3 in a step F3b. Based on the stress target fault grading, (existing) stress test patterns can be sorted according to their relevance in a step F3c. Furthermore, a stress test pattern generation can be performed in a step F3d. Each of the steps F3a, F3b, F3c, F3d are described in more detail in the following. The stress target fault may refer to a fault to be targeted by a stress test. Said (stress target) fault may be a latent defect that is targeted by a stress target, e.g. comprising the stress states of one or more transistors of a library cell. Hence, it may be necessary to model such a stress target fault in order to create and / or configure one or more stress tests or stress test applications.

[0089] Regarding the stress target fault model generation F3a: Since the overall goal is to apply a stress test to a complete IC design, the data D2 may need to be elevated from cell level to IC circuit level. During the IC design, instances of the same and / or different cells are placed upon a die. These instances may inherit the library data and consequently also the (generated) stress targets in the library cell and / or associated to the library cell. It may thus be desired to create a (overall) stress target or (overall) stress target list. This is done by creating stress target faults based on, e.g. each, stress target. Given an instance i of an IC (design) based on a cell c, the stress targets of a cell c are transferred or assigned to an instance i, and a stress target fault may be created for each stress target for the instance, or, e.g., each, instance. Each such stress target fault f = (i, C) may comprise a stress target fault location, e.g., given by the instance i, as well as a set of one or more conditions C = c1 , ... ,cn. A condition c is an assignment at the instance’s inputs which is derived directly from the input stimuli, e.g., stimuli set V, of the stress target. As an example, the stress target (t, TRoffOO, (0,0), (1 ,1)) of the instance i may be considered. The transistor stress state TRoffOO at transistor t is caused by the assignment of (0,0) and (1,1) at the instance’s inputs. For this stress target the stress target fault f t Roffoo = (i, (0,0), (1,1)) is created. In contrast to regular faults for stress test generation, these stress target faults do not need observation. It is sufficient to justify one condition, i.e. given for example by an input stimuli. The set of generated stress target faults for the one or more, preferably all, instances may form an (overall) stress target fault or (overall) stress target fault list. A stress target fault may thus be deemed as detected, e.g., by a stress test or stress test pattern, when or if a condition c at the inputs of an instance of a cell is fulfilled.

[0090] Regarding the fault grading F3b: The stress target fault model, or (overall) stress target fault (list), can be applied to fault grade (existing) stress test patterns D3. The IC (design) may need to be switch-level, gate-level and / or logic-level simulated with a set of one or more stress test patterns D3.

[0091] In a logic-level simulation cell and / or IC circuit elements may be modeled as simple switches or gates connected by wires the propagation delay of which is typically zero. Logic-level simulators provide the ability to simulate larger designs than circuit-level simulators can, at the expense of detail. Logic-level simulators may simulate at the device level or at the gate level. In a switch-level simulators circuits are modelled as a collection of transistors and wires, and must be provided with connectivity information. This information consists of a list of transistors and wires, which provide the equivalent of a schematic of the design. Transistors are modeled as simple switches and wires are modeled as idealized, zero-delay conductors. Usually a simple delay model is incorporated into the transistor model; for example, unit-delay in switching. Other delay information such as transistor delays derived in a previous circuit simulation, may be incorporated if available. Processing is a matter of solving simplified equations based on approximate circuit theory. Rudimentary timing information, within the limits of the simplified model, is available for the nodes being monitored. In spite of the approximations involved, the timing information may be sufficient to determine overall system parameters such as worst-case delays and maximum clock rates.

[0092] In a gate-level simulation the same logic values as switch-level simulators may be used, but circuit elements are modeled at the gate rather than the transistor level. Gate-level simulators can be used to simulate still larger designs in terms of logic values.

[0093] Since a stress test is typically based on a scan test, the logic-level, gate-level and / or switchlevel simulation may need to include shift cycles as well as the capture cycles. The goal of this simulation is to check which stress target faults are detected, i.e., which transistor stress states are targeted, by which one or more stress test patterns D3. However, it may not be sufficient to check whether a stress target fault was detected, but one or more of the following data may be obtained for an (efficient) fault grading: how often a stress target fault was detected, how many cycles in sequence was a stress target fault detected, and / or an (estimated) current during detection, i.e. a current at the point in time or period of time the condition(s) at the input(s) of an instance were present.

[0094] The fault simulation, e.g., for the fault grading, is outlined below and may comprise one or more of the following steps:

[0095] / / Shift and Capture cycle fault simulation tests = test patterns (D3) detection counter = init counter for all stress target faults(O) max sequence = init max for all stress target faults(O) max current = init max for all stress target faults (0) For each t e tests cycles = shift cycles(t) + capture cycles(t) state = initial state For each c e cycles state = simulate(c, state) update counters(state) update max sequence(state) update max current(state) End

[0096] End

[0097] After each simulated cycle, the detected stress target faults may be determined for each instance and / or the counters have to be updated. Detailed information about the induced stress on each transistor can be calculated. A coverage value can also be calculated. The coverage value of the stress test describes the percentage of stress target faults which are detected at least once by the stress test patterns with respect to the total number of stress target faults.

[0098] Regarding the pattern sorting F3c: The pattern sorting method or application F3c allows to sort the stress test patterns according to the stress target fault model F3a and a, e.g., user configurable, sort key. The aim of the pattern sorting (method) is to have those patterns with the highest impact first. For the stress test application, it is very important to apply a small stress test set to reduce the stress test costs. The sorting method is therefore useful to truncate the stress test pattern set and keep only the most important patterns. For example, one or more of the following sorting methods may be used: A first sort key could be the total number of detections and / or a second sort key could based on the maximum estimated current. Another sort key could be the average maximum sequence of cycles for all detected faults with a second key of the total number of detections. Here, as before, the detection of a stress target fault refers to the presence of input stimuli at an instance of cell, e.g. in an IC (design).

[0099] Regarding the stress test pattern generation F3d: The stress test pattern generation step or application F3d provides the functionality of generating stress test patterns according to the stress target fault model F3a. A main difference compared to other test generation approaches is that no observation is required. This allows for a stress test (pattern) generation and / or testing methodology in the capture cycles and / or in the shift cycles. The consideration of shift cycles is very important to obtain a small test set. The number of shift cycles is much higher than the number of capture cycles. Therefore, a shift cycle stress test pattern generation or ATPG is proposed. There are many well-known test generation approaches for the capture cycle but not for the shift cycles. The shift cycle pattern generation and / or testing as proposed herein is outlined in the steps below: / / Shift cycle ATPG

[0100] T = {init empty test}

[0101] S = set of scan chains

[0102] For each f e list of stress target faults scan enable = 0 state = combinational ATPG (f) / / no observation e = essentials bits(state.f) scan enable = 1

[0103] For each t . T if justify in scan chains (S,e,t) != CONFLICT update test (S,e,t) GOTO next fault f

[0104] END

[0105] END

[0106] If test was not inserted

[0107] T = T + new test(e)

[0108] END

[0109] END

[0110] At first, a stress target fault may need to be justified using combinational ATPG, preferably without fault propagation. Here, the IC may be in functional mode (scan enable = 0). The conditions of the stress target fault, i.e. the instance’s input assignment, may be justified and / or a scan cell assignment may need to be found which leads to the target conditions. The bits for reaching the conditions have to be extracted. Next these bits need to be justified in the scan chains, i.e., each scan cell assignment has to arrive in the same shift cycle (scan enable = 1). When the correct position and cycle is found, the stress test pattern may be updated. In order to obtain a compact stress test set, the generated bits for the next stress target fault(s) are inserted into existing tests first. Only if this is not possible, i.e. (CONFLICT), a new test is created. A further improvement may comprise the justification in the scan chains into the combinational ATPG, e.g., such that backtracking can be used.

[0111] The described transistor stress state model or view generation for library cells, as described herein, provides an effective, universal solution for generating effective stress test patterns and / or allows to measure the quality of (existing) stress test patterns. The main advantage is the improved quality of the (generated) stress test patterns. For an IC manufacturer, this clearly results into lower PPM levels for the delivered ICs to customers due to a reduction of early life failures. Furthermore, the described ATPG algorithm guaranties that a highly optimized set of stress test patterns can be generated, such that the test costs can be significantly reduced. A further main advantage is the flexibility of this solution. The test patterns, and / or the data may be generated once per library and / or may be reused for different ICs, or IC designs and / or different configurations. Depending on the needs, the translation of the stored data into the specific transistor state model can be controlled for the specific application.

[0112] Thus, a transistor state-oriented library view may be provided, which is for example created from, e.g., the spice view, of the library cell. Furthermore, other inputs in addition to the spice view may be used as well. Thus, a spice view of a library cell may be used to assist in the creation of the transistor state stress view. An library view may be created from the transistor state stress view. The transistor state stress view may be obtained as an output of a switchlevel simulation, or may be created manually. The transistor state stress view may comprise the information about the stress scenarios that occur when an exhaustive set of input stimuli or input stimuli sequences are applied to the cell. Thus, the library view may be derived from the spice view of the library cells. The library view and / or the stress view may be used for generating the stress test patterns and / or calculating coverage figures. The library view and / or the stress view may be used to control the data to be used for stress test pattern generation and / or fault simulation. The stress test pattern algorithm may make use of shift cycles, e.g., in order to optimize the stress test pattern generation.

[0113] In Figure 12 an exemplary insertion of a stress test pattern into a scan chain is shown. In particular, a scan test may be a mandatory part of the IC design process that helps to reduce the complexity of testing, e.g., sequential circuits. The basic concept of a scan test is to connect memory elements like flipflops or latches forming chains, so that shifting through scan chains allows to control and observe the states of the IC or IC design. Since scan vectors are based on regular and uniform structures, basic knowledge about scan designs, scan test modes and targeted fault models helps to interpret scan vectors. It is thus proposed to make use of the shift cycles for stress testing and in particular for stress target fault detection.

[0114] In order to enable a scan test for an IC (design), a test logic may be inserted, this is called “scan insertion”. Hitherto, a scan insertion may comprise the steps of replacing plain memory cells like flipflops or latches by scan cells and connecting these together forming one or more chains. Scan cells can be operated in two modes, the functional mode used during normal operation and the scan mode that allows shifting through the scan chains. Figure 12 shows an exemplary IC that implements a 4 bit counter with just three inputs: a clock input “clock”, an input “incrmnt” to increment the counters value and a reset signal “reset” to set the counter back to “0”. The outputs “count” allow to read the counters value. Finally, output “overflow” is a flag which is set if the counter exceeds its counting range. In addition a scan insertion, with scan cells forming a chain with input “scanjn” and output “scan_out” is shown. The input “scan_en” has been added in order to control the mode of the scan cells. In general, a scan test comprises: Shifting into scan chains to directly set the state of the IC, and applying one or more clock cycles of normal operation. Optionally the outputs are checked for correct values, and finally the resulting state is shifted out via scan chains and compared to the expected state to check for the correct behavior of the IC. To that end, a scan pattern, e.g. for said 4 bit counter, may be provided. When data is shifted into the scan chain, i.e. , the scan chain is loaded in scan mode, the required time may depend on the size of the longest scan chain and / or the underlying frequency, called “shift frequency” or “scan frequency”. Typically, scan chains comprise hundreds or thousands of scan cells and the shift frequency is lower than frequencies used for functional test. The shift cycles for loading the scan chain may correspond to the number of scan cells in the IC design. After the scan load sequence and optionally additional wait cycles, one or more clock cycles are applied in functional mode to launch certain events in the IC in order to capture IC’s response. These cycles are called “launch cycles” and / or “capture cycles”, and might run with a different frequency compared to the normal operation of the device. Finally, the captured response is shifted out of the scan chains and compared to expected values; this is also called “chain unload”. The whole sequence of chain load, launch / capture cycles and chain unload may be referred to as a scan pattern. Usually, a scan test may comprising hundreds or thousands of scan patterns. While the response data of a scan pattern is shifted out of a scan chain, the scan chain can be simultaneously loaded with the scan input data of the following pattern.

[0115] The software that generates test vectors, or stimuli, or patterns, as the case may be, for the scan test is called “Automatic Test Pattern Generation”, ATPG, software. As input an ATPG tool may require IC design data of the device under test, DUT, i.e. a logical gate level description in a hardware description language, and setup files defining scan specific settings: input sequences to configure scan mode for the device, fault models, projected coverage, and maximum pattern size and so on. The ATPG tool may check if the IC design is capable to perform the scan test according to the settings, and then it may generate (scan) test patterns, performs fault grading to determine the test / fault coverage and dumps scan patterns. The most common formats are the Standard Tester Interface Language (STIL) format and the Waveform Generation Language (WGL) format. As designs become larger, including hundreds of thousands or even millions of scan cells, the size of plain scan test patterns, the memory required to store these patterns and the scan test time increases as well. These test patterns may serve for detecting easy-to-detect or hard-to-detect faults, or in particular activated latent defects of the IC. Hence, one or more ICs may be subject of a stress test where the one or more stress test patterns are applied to inputs or terminals of the IC.

[0116] Fig. 13 shows exemplary method steps according to an aspect. In a first step S1, one or more latent defects in an integrated circuit may be determined, e.g., based on a stress target of a library cell. Therein, the step of determining may comprise the execution of a stress test based on a stress test pattern applied to the integrated circuit. The step of determining may comprise targeting of one or more latent defects by applying a stress test pattern to the one or more inputs of the integrated circuit. Therein the stress test pattern may be generated based on the stress target. Thus, instead or in addition to the library cell, the instance of the library cell may comprise or may be associated with the stress target. A latent defect may be (deemed) determined or detected if an input stimulus is applied to the (instance of the) library cell leading to a stress state of the one or more transistors of the (instance of the) library cell. Step S1 may comprise a step S2, wherein the stress target of a library cell serves for determining or detecting latent defects in (an instance of) the library cell. Step S1 may additionally or alternatively comprise that the stress target comprises a plurality of stress states, preferably all of the stress states, of the one or more, most preferably each one of the, transistors of the library cell in a step S3. Futhermore, the integrated circuit may comprise plurality of instances of the same and / or different library cells. The stress target may thus be an overall stress target comprising the stress targets of each (instance of the) library cell, and thus preferably the stress states of each transistor of each (instance of the) library cell. In general, the stress target may comprise a plurality of, and preferably all, stress states of (an instance of) a library cell, or a plurality of library cells, as the case may be.

[0117] It should be noted that, a stress test pattern for stress testing an integrated circuit may be generated based on a stress target, wherein the integrated circuit, e.g., given by an IC design, may comprise at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell. This stress test pattern may serve for determining one or more latent defects in an integrated circuit. The stress test pattern may then be applied in a stress test to the integrated circuit in order to determine the one or more latent defects. As described herein, the stress test pattern may be generated by identifying the input stimulus at a cell’s or instance’s inputs leading to the one or more stress states, and by then generating an input pattern, i.e. stress test pattern, for the IC leading to the input stimulus at the cell’s or instance’s inputs when the input pattern is applied to the inputs of the IC.

[0118] As shown in Figure 14 according to another aspect, a stress test pattern for stress testing the integrated circuit may be determined or generated based on the stress target of the one ormore library cells in a step S4. As the case may be, the stress target may serve for the generation of stress test patterns (de novo), or may serve for adapting existing stress test patterns, e.g. inserting essential bits into an existing stress test pattern, or may serve for determining one or more stress test patterns among a plurality of (existing) stress test patterns. In a step S5, the coverage of at least one (existing) stress test pattern (set) may be determined, e.g., measured, based on the stress target of the one or more library cells. In a step S6, a stress test of the integrated circuit may be performed using at least one stress test pattern, e.g., satisfying the stress target, for determining or detecting one or more latent defects of the integrated circuit.

[0119] It should be noted that thus for (the purpose of) determining a latent defect, different uses of a stress target are possible. As described herein, a stress target may be used for one or more or a plurality of different stress test applications, such as fault generation, fault grading, pattern sorting, and / or pattern generation or pattern adaptation. Hence, for determining one or more latent defects in an integrated circuit a stress target may be used. That is, determining one or more latent defects in an integrated circuit may be based on a stress target.

[0120] According to an aspect as shown in Figure 15, the stress target of a library cell, or an instance thereof, may be determined by mapping the stress states of at least one transistor of the library cell to one or more inputs, or input signals, of the library cell in a step S7. This may be based on a switch-level, gate-level and / or logic-level simulation of the library cell. The input (signals) or input combination(s), also referred to condition, e.g. in case of an instance, or input stimuli leading to one or more stress states may be stored as part of the stress target in the library cell and / or be associated, e.g. by a link, with the library cell. The term input may refer to the input signals and / or input signal values. The term input may also refer to the terminals of the terminals of the cell or instance. The term primary input may refer to the input of the integrated circuit.

[0121] According to an aspect as shown in Figure 16, one or more stress states of a transistor in a library cell may be determined. In a step S9, a stimulus, to be applied to the terminals of the (instance of the) library cell, for stressing the one or more transistors of the library cell, preferably each transistor in the library cell, may be determined based on the one or more stress states. In a step S10, the stimulus may be stored in the library cell or associated with the library cell, e.g. stored on the same or a different (non-transitory) storage medium.

[0122] According to an aspect as shown in Figure 17, a state model of one or more of a plurality of transistors comprised in a library cell may be obtained in a step S12. In a step S12 the stress states within the state model of a transistor in the library cell may be determined. In a step S13, the stress states and the library cell may be stored, e.g., in a standard-cell library. Alternatively, the stress states and / or the library cell may be associated with a standard-cell library. For example, an identifier or other association or linking mechanism may be used in order to have stress states, the library cell and / or the standard-cell library associated. These steps may be performed for one or more cells of a cell library.

[0123] According to an aspect as shown in Figure 18, an analog simulation of the library cell, preferably each one of a set of library cells in a cell library, may be performed in a step S14. In a step S15, the stimulus for producing said one or more stress states of the transistors of the library cell may be determined or used, e.g. for performing the analog simulation. The stimulus may be obtained, e.g., beforehand, as described herein for example by a switch-level, gatelevel, or logic-level simulation of the library cell. Instead, all possible (single cycle and / or two ycle) input (signal) combination at the inputs of the cell may be used. It should be noted that herein the terms stimulus and stimuli are more or less used interchangeably, since for example a stimulus may refer to the set of stimuli, or stimuli as a whole, e.g. as applied subsequently to the same or different inputs, or to different inputs in parallel.

[0124] According to an aspect as shown in Figure 19, an analog simulation of the library cell using the stress states may be performed in a step S16. In a step S17, the results of the analog simulation may be stored in the library cell and / or associating the results with the library cell. Said results may preferably comprise the current values of the one or more transistors in their respective stress states, i.e. for detecting or triggering the one or more latent defects - since in order to stress the latent (open) defects, current has to flow through the transistor.

[0125] According to an aspect as shown in Figure 20, the one or more stimuli may be weighed. That is, a weight, or score, e.g., a number may be assigned, to a stimulus, thereby indicating a priority of the stimulus. In a subsequent step S19, the one or more stimuli (possessing a weight, or score) may be sorted according to the respective weight. As mentioned before, an input stimulus with a higher current through transistor t can be prioritized with respect to an input stimulus for the same transistor with a lower current. Similarly, on the IC (design) level, the one or more stress test patterns may be weighed and / or sorted, e.g., in accordance with a fault grading or coverage of the test pattern(s). The weighing and / or sorting may be performed based, again, on the current through a transistor, e.g., in its one or more stress states, or on the number of detections, i.e. how often a latent defect or stress target fault was detected, i.e. how often the respective input signal leading to a stress state of the transistor was applied to the input(s) of the (instance of a) cell or the IC (design).

[0126] According to an aspect as shown in Figure 21, in a step S20 at least one stress test stimulus of the at least one library cell may be determined. In a step S21 , a stress test pattern for the integrated circuit may be determined or generated, e.g. based on the stress test stimulus or the stress states. The stress test pattern may thus be determined based on a logic simulation of the integrated circuit in order to determine which test patterns target the transistor stress states or lead to the stress test stimulus at the cell or instance thereof. The stress test pattern determined may be applied to the integrated circuit in a step S22. The stress test stimulus may serve for identifying or detecting the one or more latent defects in a cell, i.e. for stress testing the cell or the instance thereof, as the case may be. The same applies to the stress test pattern which at the IC (design) level serves for identifying or detecting the one or more latent defects in a cell, or an instance thereof. Herein the term stimulus is also used as an abbreviation for term the stress test stimulus.

[0127] According to an aspect as shown in Figure 22, stress states for invoking, provoking, triggering or activating a latent defect in a transistor in form of one or more transistor states may be identified in a step S23. In a step S24, each transistor of the one or more library cells or the respective instance thereof, e.g. on the IC or the IC design level, may be brought into each one of its one or more stress states during a stress test, e.g. by a stress test pattern or a stress test stimulus, respectively.

[0128] According to an aspect as shown in Figure 23, the stress states for each one of a plurality of library cells in a standard-cell library may be determined in a step S25. In a step S26, the stress states of each one of the plurality of library cells may be stored in standard cell library, or may be associated thereto as the case may be. In a step S27, the stress test patterns may be generated based on (stress test) stimulus created from the stress states of the one or more, e.g., each one of the plurality of .library cells. Alternatively, the stress test patterns may be generated based on the stress states of the one or more, e.g., each one of the plurality of, library cells. In a step S28, the one or more, e.g., each, transistors of the one or more library cells or respective instances may be brought into each one of its one or more stress states during a stress test.

[0129] According to an aspect as shown in Figure 24, an integrated circuit (design) comprising a plurality of (instances of) library cells may be obtained in a step S29. In a step S30, one or more stress target faults of the integrated circuit corresponding to the one or more stress targets of the library cell maybe created. Thus, the actual stress test and / or the generation of the stress test patterns may be carried out at the IC design level, whereas for example, the switch-level, gate-level, or logic level simulation(s) and / or the analog simulation(s) of the one or more, preferably each, cell is performed on the cell library level.

[0130] According to an aspect as shown in Figure 25, a logic-level simulation of the integrated circuit based on one or more stress test patterns for fault grading a plurality of stress test patterns of the integrated circuit may be performed in a step S31. In a step S32, the results, e.g., the number of stress target faults detected, of the logic-level simulation may be stored. In a step S33, a coverage value of the one or more stress test patterns, which indicates the number of stress target faults detected by the one or more stress test patterns may be determined. In a step S34, a stress test pattern set from the available stress test patterns may be determined.

[0131] According to an aspect as shown in Figure 26, one or more shift cycles for loading a scan chain may be used for determining stress target faults, e.g., during the loading of the scan chain, in a step S35. Thus, the shift cycles may be used for stress testing the integrated circuit, e.g., in order to determine a latent defect in the integrated circuit. In a step S36, one or more stress test patterns for creating the stress target fault(s) of the integrated circuit may be generated, e.g. comprising the stress target fault conditions, e.g. causing the input stimulus leading to the stress target and / or stress states of the transistor(s), e.g., in the one or more cell instances and / or for detecting one or more latent defects. Thus, one or more stress test patterns for stress testing and / or creating the stress target faults of the integrated circuit during one or more shift and / or capture cycles may be generated, which for example make use of the shift cycles for loading a scan chain. That is, the stress test, and / or detection of the latent defect or stress target fault may be executed during one or more shift cycles or detection cycles of the integrated circuit. That is the shift cycle(s) are used for stress testing the integrated circuit and thus for determining or detecting one or more latent defects. To that and, stress test patterns may be generated or adapted. This may be achieved by determining the necessary input (signals) leading to the stress states in the cell or instance thereof on the IC. Thus, existing stress test patterns may be improved by optimizing the shift cycles. Thus, the IC may be stress tested during the shift cycles or so-called detection cycles.

Claims

Patent claims1. A, preferably computer-implemented, method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.

2. The method according to the preceding claim, further comprising: determining a stress test pattern for stress testing the integrated circuit based on the stress target of the library cell.

3. The method according to any one of the preceding claims, further comprising: determining, e.g., measuring, the stress coverage of at least one stress test pattern based on the stress target of the library cell.

4. The method according to any one of the preceding claims, further comprising: performing a stress test of the integrated circuit using at least one stress test pattern, e.g., satisfying the stress target, for determining one or more latent defects of the integrated circuit.

5. The method according to any one of the preceding claims, further comprising: determining the stress target of a library cell by mapping the stress states of at least one transistor of the library cell to one or more inputs and / or input signals of the library cell.

6. The method according to any one of the preceding claims, wherein the stress target of a library cell serves for determining one or more latent defects in the library cell and / or an instance of the library cell, and / or wherein the stress target comprises a plurality of stress states, preferably all of the stress states, most preferably of each one, of the one or more transistors of the library cell.

7. The method according to any one of the preceding claims, wherein the stress test pattern, which is applied to the inputs of the integrated circuit, is configured to determine one or more latent defects in the one or more instances of the library cell in the integrated circuit.

8. The method according to any one of the preceding claims, wherein a stress target of a library cell is determined comprising the following steps: determining one or more stress states of the one or more transistors in the library cell, determining a stress test stimulus, to be applied to the terminals of the (instance of the) library cell, for stressing the one or more transistors of the library cell, preferably each transistor in the library cell, based on the one or more stress states, storing the stress test stimulus in the library cell and / or associating the stress test stimulus to the library cell.

9. The method according to the preceding claim, further comprising: obtaining a state model of one or more of a plurality of transistors of a library cell, wherein preferably one or more instances of a plurality of library cells are comprised in the integrated circuit, and / or determining the stress states within the state model of the transistor in the library cell and / or storing the stress states and / or the library cell in a standard-cell library, wherein the stress states indicate the inputs and / or input signals and / or input signal values at the terminals of the transistor.

10. The method according to any one of the preceding claims, further comprising: performing an analog simulation of the library cell, e.g., to determine one or more electric characteristics, such as voltage and / or current, of one or more transistors of the library cell, and / or determining stress test stimulus leading to the one or more stress states of the transistors of the library cell.

11. The method according to any one of the preceding claims, further comprising: performing an analog simulation of the library cell, preferably for each one of a plurality of library cells, based on the stress states, and preferably storing the results, e.g., the electrical characteristics, such as the current and / or voltage values, of each transistor for each stress state, of the analog simulation in the library cell and / or associating the results with the library cell.

12. The method according to any one of the preceding claims, further comprising: weighing the stress test stimulus, e.g., based on the electrical characteristics, wherein for example, a stress test stimulus with a higher current through a transistor is to be prioritized with respect to a stress test stimulus for the same transistor with a lower current.

13. The method according to the preceding claim, further comprising: sorting the stress test stimuli according to the respective weight.

14. The method according to any one of the preceding claims, further comprising: determining a stress test pattern for the integrated circuit, i.e. , to be applied to the primary inputs, e.g., for filling one or more scan cells, of the integrated circuit, based on the at least one stress test stimulus and / or stress states of the at least one library cell.

15. The method according to any one of the preceding claims, further comprising: identifying stress states for determining a latent defect in a transistor in form of one or more transistor states, e.g., in particular a transition between different transistor states, in the state model of the one or more transistors.

16. The method according to any one of the preceding claims, further comprising: bringing each transistor of the one or more instances of the one or more library cells into, preferably each one of its, one or more stress states during a stress test of the integrated circuit.

17. The method according to any one of the preceding claims, further comprising: determining the stress states for each one of a plurality of library cells in a standard-cell library, and / or storing the stress states of each one of the plurality of library cells in the standard cell library.

18. The method according to any one of the preceding claims, further comprising: generating stress test patterns based on the stress test stimulus created from the stress states of each one of the plurality of library cells.

19. The method according to the preceding claim, further comprising: determining one or more stress target faults of the integrated circuit corresponding to the one or more stress targets of the library cell.

20. The method according to any one of the preceding claims, further comprising: performing a logic-level simulation of the integrated circuit based on one or more stress test patterns for fault grading a plurality of stress test patterns of the integrated circuit, preferably storing the results, e.g., the number of faults detected, of the logic-level simulation, most preferably determining a coverage value of the one or more stress test patterns, which indicates the number of stress target faults detected by the one or more stress test patterns,in particular determining a stress test pattern set from the available test patterns, e.g., by truncating the stress test patterns based on a threshold coverage value and / or a maximum number of stress test patterns.

21. The method according to any one of the preceding claims, further comprising: using shift cycles, e.g., for loading a scan chain, for stress testing an integrated circuit in order to determine one or more stress target faults, e.g., during the loading of the scan chain.

22. The method according to any one of the preceding claims, further comprising: generating one or more stress test patterns for stress testing and / or determining one or more stress target faults of the integrated circuit during one or more shift and / or capture cycles.

23. A, preferably computer-implemented, method for detecting one or more latent defects in an integrated circuit, e.g., during a stress test, the method comprising: generating a stress test pattern for detecting one or more latent defects in the integrated circuit based on a stress target of a library cell or an instance of the library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, and wherein the stress target of the library cell is indicative of one or more stress states of one or more transistors, preferably each transistor, of the library cell.

24. An augmented library cell, preferably stored on a non-transitory medium, comprising a description of the connectivity of the elements of a library cell, e.g., in the form a netlist or hardware description language, and a stress target of the library cell, wherein the stress target is obtained by and / or is indicative of one or more stress states of one or more transistors, preferably each transistor, of the library cell.

25. A computer-program, preferably stored on a non-transitory medium, comprising program code that when executed performs the method steps of any one of the preceding claims 1-23.

26. An apparatus or system comprising a memory configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to perform the method steps of any one of the preceding claims 1-23.

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