Doherty amplifier

Abstract

A Doherty amplifier (100) comprising a carrier amplifier (160) and a peak amplifier (170) comprises: a distributor (180) that distributes an input signal to the carrier amplifier (160) and the peak amplifier (170); a detection circuit (110) that is connected to the output, on the peak amplifier (170) side, of the distributor (180) and detects the power inputted to the peak amplifier (170); and an active bias circuit (120) that adjusts the gate bias of the carrier amplifier (160) or the peak amplifier (170) according to an output signal from the detection circuit (110).

Description

Doherty Amplifier

[0001] The present disclosure relates to power amplifiers, and more particularly to Doherty amplifiers.

[0002] Mobile phone base stations for fifth-generation mobile communication systems (5G) and other applications require power amplifiers that are capable of high-output and highly linear operation. Furthermore, because the power-added efficiency of a power amplifier has a significant impact on the power consumption of a base station, highly efficient operation is also highly desired.

[0003] Currently, the mainstream Doherty amplifiers use gallium nitride (GaN) high electron mobility transistors (HEMTs) capable of high voltage and high current density operation or silicon lateral diffused MOSFETs (LDMOSs) as power amplification transistors. Because Doherty amplifiers can increase efficiency during back-off operation, they are capable of high-efficiency operation even in mobile phone base stations such as 5G, which have a large difference between average output power and peak output power (Peak-To-Average Power Ratio: PAPR). However, there is generally a trade-off between the power-added efficiency, saturated output power, and linearity characteristics of Doherty amplifiers.

[0004] To improve the trade-off of the Doherty amplifier characteristics, Patent Document 1 describes an adaptive bias circuit that detects the input signal level of the Doherty amplifier and adjusts the bias voltage of the amplifying element of the peak amplifier circuit.

[0005] Japanese Patent Application Laid-Open No. 2008-125044

[0006] However, in the technology disclosed in Patent Document 1, it is necessary to split a part of the input signal before the splitter in order to detect the input signal level, which reduces the input signal level to be amplified by the Doherty amplifier, thereby reducing the power gain of the Doherty amplifier and the power-added efficiency.

[0007] Therefore, an object of the present disclosure is to solve the above problems and provide a Doherty amplifier that improves the trade-off between power-added efficiency, saturated output power, and linearity.

[0008] In order to achieve the above object, a Doherty amplifier according to one embodiment of the present disclosure is a Doherty amplifier including a carrier amplifier and a peak amplifier, and includes: a divider that distributes an input signal to the carrier amplifier and the peak amplifier; a detection circuit that is connected to the peak amplifier side output of the divider and detects the power input to the peak amplifier; and an active bias circuit that adjusts the gate bias of the carrier amplifier or the peak amplifier according to the output signal of the detection circuit.

[0009] The Doherty amplifier according to the present disclosure can improve the trade-off between power-added efficiency, saturated output power, and linearity.

[0010] FIG. 1 is a circuit diagram showing an example of a configuration of a Doherty amplifier according to a first embodiment. FIG. 2 is a circuit diagram showing an example of a configuration of a detection circuit, an active bias circuit, and a peak amplifier according to the first embodiment. FIG. 3 is a circuit diagram showing an example of a configuration of a divider according to the first embodiment. FIG. 4 is a diagram showing an example of a characteristic of a peak amplifier input power relative to an input power of the Doherty amplifier according to the first embodiment. FIG. 5 is a diagram showing an example of a characteristic of a peak amplifier bias voltage relative to an output power of the Doherty amplifier according to the first embodiment. FIG. 6 is a diagram showing an example of a characteristic of a power gain relative to an output power of the Doherty amplifier according to the first embodiment. FIG. 7 is a circuit diagram showing an example of a configuration of a Doherty amplifier according to a second embodiment. FIG. 8 is a circuit diagram showing an example of a configuration of a Doherty amplifier according to a third embodiment. FIG. 9 is a circuit diagram showing an example of a configuration of a Doherty amplifier according to a fourth embodiment. FIG. 10 is a circuit diagram showing another example of a configuration of a Doherty amplifier according to the fourth embodiment. FIG. 11 is a circuit diagram showing an example of a configuration of a Doherty amplifier according to a fifth embodiment.

[0011] The Doherty amplifier of the present disclosure will be described below with reference to the drawings. However, detailed descriptions may be omitted. For example, detailed descriptions of well-known matters or redundant descriptions of substantially identical configurations may be omitted. Also, the drawings are not necessarily accurate representations. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art.

[0012] Note that the embodiments described below each represent a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement positions, and connection configurations shown in the following embodiments are merely examples and are intended to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims. Furthermore, in this specification, the term "connection" means an electrical connection, and includes not only a case where two circuit elements are directly connected, but also a case where two circuit elements are indirectly connected with another circuit element inserted between them.

[0013] First Embodiment A Doherty amplifier according to a first embodiment will be specifically described below with reference to FIGS.

[0014] FIG. 1 is a circuit diagram showing a configuration of a Doherty amplifier according to the first embodiment.

[0015] 1, Doherty amplifier 100 is a power amplifier device that amplifies an RF input signal input from a PIN terminal to an RF output signal output from a POUT terminal, and is used in, for example, base stations for mobile phones and satellite communications. Note that Doherty amplifier 100 is not limited to base stations, and may also be used in, for example, mobile phone terminals, radar transmitters, wireless power transmitters, microwave ovens, microwave heating devices, and the like.

[0016] The Doherty amplifier 100 is, for example, a GaN HEMT power amplifier module, and includes, as external input / output terminals, a PIN terminal and a POUT terminal for RF signal terminals, as well as a DC power supply terminal and a GND terminal (not shown). The Doherty amplifier 100 also includes, for example, a detection circuit 110, an active bias circuit 120, a driver amplifier 150, a carrier amplifier 160, a peak amplifier 170, a divider 180, a phase shifter 130, and quarter-wave transmission lines 141 and 142.

[0017] The PIN terminal is connected to the input of the driver amplifier 150 and is a terminal to which an RF input signal is input.

[0018] The POUT terminal is connected to the output of the quarter-wave transmission line 142 and is a terminal from which an RF output signal is output.

[0019] The DC power supply terminal is a terminal that supplies power necessary for operating circuit elements such as power amplification transistors inside the Doherty amplifier 100. The DC power supply terminal differs depending on the mounting form of the Doherty amplifier 100, but may be, for example, a lead pin, a leadless pin, a wire bonding pad, a solder ball pad, a connector terminal, or the like.

[0020] The GND terminal is a terminal for grounding the GND wiring or GND wiring layer that is the reference potential inside the Doherty amplifier 100 .

[0021] The driver amplifier 150 amplifies an RF input signal input from a PIN terminal and outputs the signal to the distributor 180. The driver amplifier 150 is composed of, for example, an input matching circuit, a power amplifier transistor, a bias circuit, and an output matching circuit, and the power amplifier transistor operates in class AB or class A. The power amplifier transistor is a GaN HEMT formed on a semiconductor substrate. The power gain of the driver amplifier 150 is set to, for example, 10 dB to 20 dB.

[0022] The divider 180 divides the RF signal amplified by the driver amplifier 150 into a path to the carrier amplifier 160 and a path to the peak amplifier 170. As the divider 180, for example, a Wilkinson divider is used.

[0023] Carrier amplifier 160 amplifies RF signal CAin distributed from distributor 180 and outputs it to quarter-wave transmission line 141. Carrier amplifier 160 is composed of, for example, an input matching circuit, a power amplification transistor, a bias circuit, an output matching circuit, and a harmonic processing circuit, and the power amplification transistor operates in class AB. The power amplification transistor is a GaN HEMT formed on a semiconductor substrate.

[0024] The quarter-wave transmission line 141 delays the phase of the output signal of the carrier amplifier 160 by, for example, 90 degrees. The quarter-wave transmission line 141 is also connected to the junction with the output of the peak amplifier 170 to convert impedance and realize cooperative operation of the carrier amplifier 160 and the peak amplifier 170. The quarter-wave transmission line 141 may be a simple transmission line, or may be configured with distributed constants or lumped constants.

[0025] The phase shifter 130 delays the phase of the RF signal distributed to the path from the distributor 180 to the peak amplifier 170 and outputs the delayed signal. The phase delay is set to, for example, 45 to 135 degrees.

[0026] The detection circuit 110 is connected to the output of the phase shifter 130 and the input of the peak amplifier 170, detects the power of the RF signal distributed to the path from the distributor 180 to the peak amplifier 170, and outputs a detection signal Pdet to the active bias circuit 120.

[0027] The active bias circuit 120 sets and adjusts the peak amplifier bias voltage VgPA of the peak amplifier 170 in response to the detection signal Pdet of the detection circuit 110 .

[0028] Peak amplifier 170 amplifies RF signal PAin input from distributor 180 via phase shifter 130 and detection circuit 110, combines it with the output signal of carrier amplifier 160 that has passed through quarter-wave transmission line 141, and outputs the combined signal to quarter-wave transmission line 142. Peak amplifier 170 is composed of, for example, an input matching circuit, a power amplification transistor, an output matching circuit, and a harmonic processing circuit, and the power amplification transistor operates while changing between class C and class AB in accordance with peak amplifier bias voltage VgPA of active bias circuit 120.

[0029] The quarter-wave transmission line 142 converts the RF signal, which is output and combined from the carrier amplifier 160 and the peak amplifier 170, to a reference impedance of 50Ω and outputs it to the POUT terminal. The quarter-wave transmission line 142 may be a simple transmission line, or may be configured with a distributed constant or a lumped constant.

[0030] Next, examples of the configurations of the detection circuit 110, the active bias circuit 120, and the peak amplifier 170 will be described.

[0031] FIG. 2 is a circuit diagram showing a configuration of the detection circuit 110, the active bias circuit 120, and the peak amplifier 170 according to the first embodiment.

[0032] The detection circuit 110 is composed of capacitors 111 and 112, a resistor 113, a diode 114, an inductor 115, and the like. The diode 114 is, for example, a Schottky barrier diode formed on a semiconductor substrate, and its anode is biased by applying a DC power supply voltage VDD via the resistor 113, while its cathode is grounded via the inductor 115. The bias current flowing through the diode 114 can be adjusted by the resistance value of the resistor 113, and the amount of change in the detection signal Pdet in response to changes in the input power of the RF signal can be adjusted by the inductance value of the inductor 115. For example, the DC power supply voltage VDD is set to 1 V to 5 V, the resistance value of the resistor 113 is set to 100 Ω to 10 kΩ, and the inductance value of the inductor 115 is set to 10 pH to 1000 pH. The anode voltage of the diode 114 is output to the active bias circuit 120 as the detection signal Pdet. The anode voltage and current of diode 114 change in response to the RF signal input to detection circuit 110, causing a change in detection signal Pdet. Specifically, the half-wave rectification of diode 114 causes detection signal Pdet to become a negative voltage that depends on the power of the RF signal. Furthermore, to prevent DC current from flowing from detection circuit 110 to phase shifter 130 and peak amplifier 170, capacitors 111 and 112 for DC blocking are connected to the input / output sections of detection circuit 110.

[0033] The active bias circuit 120 is composed of resistors 121, 122, 123, 124, 125, and 126 and a transistor 127. The transistor 127 is, for example, a P-type FET formed on a semiconductor substrate, with its source connected to GND. The gate of the transistor 127 receives a voltage obtained by dividing the detection signal Pdet by resistors 121 and 122. A resistor 123 is connected to the gate of the transistor 127, forming a low-pass filter together with the gate parasitic capacitance of the transistor 127, and a stable DC negative voltage is applied to the gate of the transistor 127. A capacitor may be added to the gate of the transistor 127 to further stabilize the gate voltage. A resistor 124 is connected to the drain of the transistor 127 to limit current. When transistor 127 is non-conductive, the peak amplifier bias voltage VgPA is generated by resistively dividing the DC power supply voltage VGG using resistors 125 and 126. However, when transistor 127 begins to conduct, the resistive division ratio changes, and the voltage increases. That is, the larger the negative voltage of the detection signal Pdet, the larger the drain current of transistor 127 and the higher the peak amplifier bias voltage VgPA. For example, the DC power supply voltage VGG is set to -1 V to -5 V, and the resistance values ​​of resistors 121, 122, 123, 124, 125, and 126 are set to 10 Ω to 100 kΩ. When transistor 127 is non-conductive, the peak amplifier bias voltage VgPA is set to, for example, -2 V to -5 V, and the increase in the peak amplifier bias voltage VgPA due to transistor 127 becoming conductive is set to, for example, 0.2 V to 4 V.

[0034] The peak amplifier 170 is composed of matching circuits 171 and 174, a power amplifier transistor 172, an inductor 173, and the like. The power amplifier transistor 172 is, for example, a GaN HEMT formed on a semiconductor substrate. The gate is biased by a peak amplifier bias voltage VgPA from the active bias circuit 120, and the drain is biased by applying a DC power supply voltage VCC via an inductor 173. The power amplifier transistor 172 amplifies the power of an RF signal PAin input via the matching circuit 171 and outputs the amplified signal via the matching circuit 174. The matching circuits 171 and 174 may be simple transmission lines or may be configured with distributed or lumped constants. The matching circuits 171 and 174 may also include a harmonic processing circuit.

[0035] Next, an example of the configuration of the distributor 180 will be described.

[0036] FIG. 3 is a circuit diagram showing one configuration of the distributor 180 according to the first embodiment.

[0037] Divider 180 is a Wilkinson divider and is composed of quarter-wave transmission lines 181 and 182, an isolation resistor 188, and the like. In the case of a Wilkinson divider that divides signals equally, the characteristic impedance of quarter-wave transmission lines 181 and 182 is, for example, 70.7 Ω, and the resistance value of isolation resistor 188 is 100 Ω. Divider 180 may also be a Wilkinson divider that divides signals unequal, and the characteristic impedances of quarter-wave transmission lines 181 and 182 may be different. Furthermore, quarter-wave transmission lines 181 and 182 may be simple transmission lines or may be configured with distributed or lumped constants. Furthermore, the resistance value of isolation resistor 188 may be set to 50 Ω to 200 Ω. Furthermore, divider 180 does not have to be a Wilkinson divider, and may be a dividing means such as a T-branch line formed by wiring on a substrate, a coupler, a balun, a branch, or a rat race.

[0038] The operation of the Doherty amplifier 100 of the first embodiment configured as described above will now be described. An RF input signal input from a PIN terminal is amplified by driver amplifier 150 and distributed by distributor 180 to a path to carrier amplifier 160 and a path to peak amplifier 170. The RF signal CAin distributed to the path to carrier amplifier 160 is amplified by carrier amplifier 160 and output to a junction with the output of peak amplifier 170 via quarter-wave transmission line 141. Meanwhile, the RF signal distributed to the path to peak amplifier 170 becomes RF signal PAin via phase shifter 130 and detection circuit 110, is amplified by peak amplifier 170, and is combined with the output from carrier amplifier 160. The combined RF signal output from carrier amplifier 160 and peak amplifier 170 is impedance-converted to a reference impedance of 50Ω via quarter-wave transmission line 142 and output to the POUT terminal. The power amplifier transistor 172 of the peak amplifier 170 operates in class C when the power of the RF signal input from the PIN terminal is low, and transitions to class AB when the power increases, due to the peak amplifier bias voltage VgPA adjusted by the active bias circuit 120. The operating class of the peak amplifier 170 changes depending on the power. This allows the Doherty amplifier 100 to reduce power consumption of the peak amplifier 170 through highly efficient class C operation when the power is low, and to increase the output power of the peak amplifier 170 through class AB operation with high power gain and saturated output power when the power is high, thereby enabling higher linearity and saturated output power compared to a Doherty amplifier equipped with a peak amplifier that continues class C operation at a typical constant bias voltage.

[0039] The operation of the detector circuit 110 and the active bias circuit 120 will now be described in detail.

[0040] When the RF signal distributed from the distributor 180 to the path to the peak amplifier 170 is input to the detection circuit 110, a portion of the RF signal is input to a diode 114 forward-biased by the DC power supply voltage VDD and becomes a half-wave rectified waveform. The amplitude of this half-wave rectified waveform is proportional to the power of the RF signal input to the detection circuit 110. Therefore, a signal with a half-wave rectified waveform that depends on the power of the RF signal is output from the detection circuit 110 as the detection signal Pdet. Note that, if the driver amplifier 150 is operating linearly, the power of the RF signal input to the detection circuit 110 is proportional to the power of the RF signal input from the PIN terminal. Therefore, the detection signal Pdet is a signal that depends on the power of the RF signal input to the Doherty amplifier 100.

[0041] The detection signal Pdet, which is a half-wave rectified waveform signal, is converted into a DC negative voltage by a low-pass filter formed by resistors 121, 122, and 123 of the active bias circuit 120 and the gate parasitic capacitance of the transistor 127. Alternatively, a low-pass filter may be provided within the detection circuit 110, which converts the RF signal into a DC voltage and then outputs the DC voltage to the active bias circuit 120 as the detection signal Pdet. When the power of the RF signal input from the PIN terminal is low, the absolute value of the DC negative voltage converted by the low-pass filter is low, and therefore the transistor 127 does not conduct. At this time, the DC power supply voltage VGG is divided by the resistor division ratio of resistors 125 and 126 to generate the peak amplifier bias voltage VgPA, and the peak amplifier 170 operates in class C. When the power of the RF signal input from the PIN terminal increases, the absolute value of the negative DC voltage converted by the low-pass filter increases and reaches the gate threshold voltage of the transistor 127, causing the transistor 127 to conduct, and the peak amplifier bias voltage VgPA increases (since the peak amplifier bias voltage VgPA is a negative voltage, its absolute value decreases). The amount of increase in the peak amplifier bias voltage VgPA can be adjusted by setting the bias current of the diode 114 and the resistance values ​​of the resistors 121 and 122, for example, so that the input power at which the peak amplifier 170 operates in Class AB can be set to a desired value. For example, by increasing the peak amplifier bias voltage VgPA at an input power at which the carrier amplifier 160 begins to saturate, the trade-off between the power-added efficiency, saturated output power, and linearity of the Doherty amplifier 100 can be improved.

[0042] 4 is a diagram showing an example of the characteristics of the peak amplifier input power of the Doherty amplifier 100 according to the first embodiment. More specifically, in FIG. 4, the horizontal axis represents the power (dBm) of the RF input signal input from the PIN terminal of the Doherty amplifier 100, and the vertical axis represents the power (dBm) of the RF signal PAin input to the peak amplifier 170. A dashed line 90a shows an example of the characteristics of the peak amplifier input power of a general Doherty amplifier that does not have the detection circuit 110 and the active bias circuit 120, and a solid line 90b shows an example of the characteristics of the peak amplifier input power of the Doherty amplifier 100 according to the first embodiment. In a general Doherty amplifier, when the power gain of the driver amplifier is 15 dB and the divider is an ideal, lossless divider that divides power at −3 dB to the path to the peak amplifier, the peak amplifier input power (dBm) is Doherty amplifier input power +12 (dBm), and is proportional to the Doherty amplifier input power. On the other hand, the peak amplifier input power of the Doherty amplifier 100 according to the first embodiment is lower than that of a general Doherty amplifier due to loss in the detector circuit 110. However, the loss in the detector circuit 110 is due to the half-wave rectification operation of the diode 114. As the peak amplifier input power increases, the loss in the detector circuit 110 decreases, approaching the peak amplifier input power characteristics of a general Doherty amplifier. For example, the loss in the detector circuit 110 is 5 dB or more when the input power of the Doherty amplifier 100 is low, but can be 0.5 dB or less at an input power corresponding to the saturated output power of the Doherty amplifier 100. Here, when the input power of the Doherty amplifier 100 is low, the peak amplifier 170 operates in Class C and has little effect on the amplification amount of the Doherty amplifier 100. Therefore, even if the loss in the detector circuit 110 is large, the effect on the characteristics of the Doherty amplifier 100 is small. On the other hand, when the input power of the Doherty amplifier 100 is high, particularly at an input power corresponding to the saturated output power, the peak amplifier 170 significantly affects the amplification amount and saturated output power of the Doherty amplifier 100, and therefore it is desirable to minimize the loss in the detection circuit 110.

[0043] 5 is a diagram showing an example of the characteristics of the peak amplifier bias voltage VgPA of the Doherty amplifier 100 according to the first embodiment. More specifically, in FIG. 5 , the horizontal axis represents the power (dBm) of the RF output signal output from the POUT terminal of the Doherty amplifier 100, and the vertical axis represents the peak amplifier bias voltage VgPA (V) output from the active bias circuit 120 to the peak amplifier 170. A dashed line 91 a shows an example of the characteristics of the peak amplifier bias voltage VgPA of a general Doherty amplifier that does not have the active bias circuit 120, and a solid line 91 b shows an example of the characteristics of the peak amplifier bias voltage VgPA of the Doherty amplifier 100 according to the first embodiment. In a general Doherty amplifier, by setting the peak amplifier bias voltage VgPA to a constant value of, for example, −3.6 V, the peak amplifier is biased to class C, and the peak amplifier does not operate when the input power is low, thereby improving the power-added efficiency of the Doherty amplifier. On the other hand, the peak amplifier bias voltage VgPA of the Doherty amplifier 100 according to the first embodiment is set by the detector circuit 110 and the active bias circuit 120 so as to rise to, for example, −3.2 V when the input power of the Doherty amplifier 100 is low and to −2.0 V at the input power corresponding to the saturated output power. When the input power of the Doherty amplifier 100 is low, the peak amplifier 170 is biased to class C, and the peak amplifier bias voltage VgPA is set taking into account a decrease in the peak amplifier input power due to losses in the detector circuit 110 so that the peak amplifier 170 begins to operate similarly to a general Doherty amplifier when the carrier amplifier 160 begins to reach power saturation. Furthermore, at the saturated output power, the power amplification transistor 172 of the peak amplifier 170 is biased to class AB, and is set so as to have a higher power gain and saturated output power during power amplification compared to class C.

[0044] FIG. 6 is a diagram illustrating an example of the power gain characteristics of the Doherty amplifier 100 according to the first embodiment. More specifically, in FIG. 6 , the horizontal axis represents the power (dBm) of the RF output signal output from the POUT terminal of the Doherty amplifier 100, and the vertical axis represents the power gain (dB) of the Doherty amplifier 100. A dashed line 92a indicates an example of the power gain characteristics of a general Doherty amplifier that does not include the detection circuit 110 and the active bias circuit 120, and a solid line 92b indicates an example of the power gain characteristics of the Doherty amplifier 100 according to the first embodiment. In a general Doherty amplifier, the power gain decreases in two stages depending on the output power. The first stage of power gain reduction occurs in a region where the carrier amplifier begins to saturate and cooperates with the peak amplifier. The amount of power gain reduction can be adjusted using the peak amplifier bias voltage VgPA or the like, but there is a trade-off between power-added efficiency and linearity. For example, the peak amplifier bias voltage VgPA or the like is adjusted so that the power gain reduction is 1.5 dB. The second-stage power gain reduction occurs when the Doherty amplifier reaches power saturation. The output power at which the sum of the power gain reductions in the first and second stages is 3 dB is defined as P3dB (dBm), which is sometimes used as a performance index of the Doherty amplifier. In the case of a typical Doherty amplifier shown by the dashed line 92a in FIG. 6 , P3dB is less than 49 dBm. Therefore, in a communication system having, for example, an average output power of 41 dBm and a PAPR of 8 dB, distortion increases, making correction difficult even with nonlinearity correction techniques such as digital pre-distortion (DPD). On the other hand, in the case of the Doherty amplifier 100 according to the first embodiment shown by the solid line 92b in FIG. 6 , the first-stage power gain reduction is equivalent to that of a typical Doherty amplifier. However, because the peak amplifier 170 is biased to class AB near the saturated output power, the second-stage power gain reduction occurs at a higher output power than that of a typical Doherty amplifier. In other words, the saturated output power is higher than that of a typical Doherty amplifier, and even in a communication system with an average output power of 41 dBm and a PAPR of 8 dB, the Doherty amplifier 100 can be used as a power amplifier by combining it with a nonlinearity correction technique such as DPD.Furthermore, by setting the peak amplifier bias voltage VgPA to start rising at the first stage of power gain reduction when the carrier amplifier 160 begins to saturate in power, the amount of power gain reduction in the first stage is reduced, resulting in a highly linear Doherty amplifier 100, making it easier to apply nonlinearity correction techniques such as DPD.

[0045] As described above, the Doherty amplifier 100 of the first embodiment detects the power of the RF signal distributed to the path from the divider 180 to the peak amplifier 170 using the detection circuit 110, and adjusts the peak amplifier bias voltage VgPA according to the power using the active bias circuit 120. This allows the Doherty amplifier 100 to reduce the power consumption of the peak amplifier 170 through highly efficient class C operation when the power is low, and to increase the output power of the peak amplifier 170 through class AB operation, which has high power gain and saturated output power, when the power is high. This allows for higher linearity and saturated output power compared to a Doherty amplifier equipped with a peak amplifier that continues class C operation at a typical constant bias voltage. Furthermore, although the detection circuit 110 generates losses due to detecting the input power, by detecting the RF signal distributed to the path from the divider 180 to the peak amplifier 170, the higher the input power to the peak amplifier 170, the smaller the loss in the detection circuit 110 becomes, and the lowering of the input signal level to be amplified by the Doherty amplifier 100 can be suppressed. Furthermore, when the input power is low and the loss in the detection circuit 110 is large, amplification by the peak amplifier 170 is not necessary and does not affect the amplification of the carrier amplifier 160, so the power gain of the Doherty amplifier 100 does not decrease, and the power-added efficiency of the Doherty amplifier 100 does not decrease.

[0046] In this embodiment, the active bias circuit 120 increases the peak amplifier bias voltage VgPA when the input power exceeds a predetermined threshold so that the amplifier operates in class C when the input power is low and in class AB when the input power is high. However, the peak amplifier bias voltage VgPA may be increased monotonically in proportion to the input power. Also, the Doherty amplifier 100 may be provided with a clamp circuit that sets an upper limit on the peak amplifier bias voltage VgPA.

[0047] In this embodiment, the Doherty amplifier 100 includes the driver amplifier 150, but the Doherty amplifier 100 may not include the driver amplifier 150 at the input section.

[0048] In this embodiment, the power amplification transistors of the driver amplifier 150, carrier amplifier 160, and peak amplifier 170 are GaN HEMTs formed on a semiconductor substrate, but all or some of the power amplification transistors may be silicon LDMOS. In the case of normally-off transistors, the peak amplifier bias voltage VgPA may be set to be a positive voltage. Also, all or some of the power amplification transistors may be current-controlled transistors. In that case, the peak amplifier bias voltage VgPA may be bias-applied to the base of the current-controlled transistor of the peak amplifier 170 via a voltage-current conversion circuit or the like.

[0049] In this embodiment, the diode 114 in the detection circuit 110 is a Schottky barrier diode formed on a semiconductor substrate, but a rectifier diode or the base-emitter diode characteristics of a transistor may also be utilized. The diode 114 may also be formed on the same semiconductor substrate as the power amplification transistor 172 in the peak amplifier 170. The diode 114 may also be formed on the same semiconductor substrate as the power amplification transistor in the driver amplifier 150 or the power amplification transistor in the carrier amplifier 160. The detection circuit 110 does not need to use a diode, and may simply be a circuit that changes voltage in accordance with the power of an RF signal.

[0050] In this embodiment, the transistor 127 in the active bias circuit 120 is a P-type FET formed on a semiconductor substrate, but an N-type FET or other transistors may be used to form a circuit that increases the peak amplifier bias voltage VgPA. Furthermore, the transistor 127 may be formed on the same semiconductor substrate as the diode 114, the power amplifier transistor 172, the power amplifier transistor in the driver amplifier 150, or the power amplifier transistor in the carrier amplifier 160.

[0051] In this embodiment, the active bias circuit 120 has a circuit configuration that adjusts the peak amplifier bias voltage VgPA in accordance with only the input power, but it may also include correction elements such as transistors that correct temperature characteristics and manufacturing variations, and adjust the peak amplifier bias voltage VgPA in a composite manner.

[0052] In this embodiment, only capacitors 111 and 112 for DC blocking are connected to the input and output sections of detection circuit 110, but matching circuits may be connected to each of them. Also, detection circuit 110 is connected in series between phase shifter 130 and peak amplifier 170, but it may also be connected in series between divider 180 and phase shifter 130. Also, detection circuit 110 may be connected in parallel via capacitor 111 between the connection point of phase shifter 130 and peak amplifier 170 or between the connection point of divider 180 and phase shifter 130 and GND. In this case, capacitor 112 is not necessary.

[0053] In this embodiment, an example has been described in which the divider 180 is a typical Wilkinson divider that divides equally, but it may divide unequally, and the resistance value of the isolation resistor 188 does not have to be 100 Ω. For example, the divider 180 may be a Wilkinson divider that divides power to the carrier amplifier 160 and the peak amplifier 170 at a power division ratio of 1:K, and the resistance value Riso of the isolation resistor 188 may be set to satisfy the following equation (1) based on the reference impedance Zo.

[0054]

[0055] By setting the resistance value Riso of the isolation resistor 188 to a large value, the input impedance of the detection circuit 110 and the peak amplifier 170 changes depending on the input power, and when the input power is low and the peak amplifier 170 does not operate, the amount of power distributed to the path to the carrier amplifier 160 increases, thereby increasing the power gain of the Doherty amplifier 100. Note that because isolation between the path to the carrier amplifier 160 and the path to the peak amplifier 170 deteriorates, it is advisable to set the resistance value Riso of the isolation resistor 188 to a large value to the extent that abnormal oscillations and the like do not occur.

[0056] As described above, the Doherty amplifier 100 according to the first embodiment is a Doherty amplifier including a carrier amplifier 160 and a peak amplifier 170, and includes a divider 180 that distributes an input signal to the carrier amplifier 160 and the peak amplifier 170, a detection circuit 110 that is connected to the output of the divider 180 on the peak amplifier 170 side and detects the power input to the peak amplifier 170, and an active bias circuit 120 that adjusts the gate bias of the peak amplifier 170 in accordance with the output signal of the detection circuit 110.

[0057] This allows the linearity and saturated power of the Doherty amplifier 100 to be improved without reducing the power-added efficiency, thereby improving the trade-off between power-added efficiency, saturated output power, and linearity.

[0058] Here, the detection circuit 110 may include a diode 114 .

[0059] According to this, the higher the power input to the peak amplifier 170, the smaller the loss in the detection circuit 110 becomes, and the reduction in the input signal level to be amplified by the Doherty amplifier 100 can be suppressed.

[0060] Here, the peak amplifier 170 has a power amplification transistor 172 formed on a first semiconductor substrate, and the diode 114 may also be formed on the first semiconductor substrate.

[0061] This allows for rational formation of semiconductor elements that constitute the Doherty amplifier 100, making it possible to reduce the size and cost of the power amplifier module. In addition, temperature coupling between the diode 114 and the peak amplifier 170 enables temperature compensation.

[0062] Here, the active bias circuit 120 may adjust the peak amplifier bias voltage VgPA of the peak amplifier 170 in accordance with the detection signal Pdet of the detection circuit 110 .

[0063] This allows class AB operation with high power gain and saturated output power when the power required for amplification by the peak amplifier 170 is high.

[0064] Here, the divider 180 is a Wilkinson divider that has an isolation resistor 188 and distributes power to the carrier amplifier 160 and the peak amplifier 170 at a power distribution ratio of 1:K, and the resistance value Riso of the isolation resistor 188 may satisfy the following equation (1) based on the reference impedance Zo.

[0065]

[0066] According to this, when the input power is low and the peak amplifier 170 does not operate, the amount of power distributed to the path to the carrier amplifier 160 increases, and the power gain of the Doherty amplifier 100 can be increased.

[0067] Second Embodiment Next, a Doherty amplifier according to a second embodiment will be described with reference to FIG.

[0068] In the second embodiment, a Doherty amplifier including an active bias circuit for adjusting the gate bias of a carrier amplifier will be described. Note that the description overlapping with the first embodiment will be omitted.

[0069] Fig. 7 is a circuit diagram showing one configuration of a Doherty amplifier according to the second embodiment. A Doherty amplifier 200 in Fig. 7 differs from the Doherty amplifier 100 according to the first embodiment in Fig. 1 in that it includes an active bias circuit 220 instead of the active bias circuit 120. The following description will focus on the differences.

[0070] 1, the active bias circuit 220 differs in that it outputs a carrier amplifier bias voltage VgCA instead of the peak amplifier bias voltage VgPA, and adjusts the gate bias voltage of the carrier amplifier 260 instead of the peak amplifier 170. Note that the peak amplifier 270 is applied with the peak amplifier bias voltage VgPA, which is a fixed voltage, in the same way as a general Doherty amplifier, and continues to operate in class C.

[0071] The operation of the Doherty amplifier 200 according to the second embodiment configured as described above will be described, focusing on the active bias circuit that is different from that of the first embodiment.

[0072] The Doherty amplifier 200 detects the power of the RF signal distributed to the path from the divider 180 to the peak amplifier 270 using the detection circuit 110, and adjusts the carrier amplifier bias voltage VgCA according to the power using the active bias circuit 220, thereby changing the gate bias state of the power amplification transistor of the carrier amplifier 260. For example, the active bias circuit 220 increases the carrier amplifier bias voltage VgCA as the input power increases, thereby enabling class AB operation with a small idle current when the input power is low and class AB operation with a large idle current when the input power is high, thereby improving the power-added efficiency when the input power is low without deteriorating the saturated output power or linearity of the Doherty amplifier 200.

[0073] As described above, the Doherty amplifier 200 according to the second embodiment can improve the trade-off between power added efficiency, saturated output power, and linearity.

[0074] In this embodiment, the active bias circuit 220 increases the carrier amplifier bias voltage VgCA when the input power is high so that class AB operation with a small idle current occurs when the input power is low and class AB operation with a large idle current occurs when the input power is high, but the active bias circuit 220 may also decrease the carrier amplifier bias voltage VgCA when the input power is high so that class AB operation with a large idle current occurs when the input power is low and class AB operation with a small idle current when the input power is high. If the carrier amplifier 260 operates in class AB mode with a constant idle current, resulting in poor linearity, the linearity and power added efficiency can be improved by decreasing the idle current when the input power is high.

[0075] In this embodiment, the peak amplifier 270 is applied with a fixed peak amplifier bias voltage VgPA so as to continue operating in class C, but as in embodiment 1, the peak amplifier bias voltage VgPA may also be adjusted by the active bias circuit 220 at the same time as the carrier amplifier bias voltage VgCA, and when the power that the peak amplifier 270 needs to amplify is high, it may be operated in class AB, which has a high power gain and saturated output power.

[0076] As described above, the active bias circuit 220 of the Doherty amplifier 200 according to the second embodiment adjusts the gate bias of the carrier amplifier 260 in accordance with the output signal of the detection circuit 110 .

[0077] This makes it possible to optimize the bias state of the carrier amplifier 260 in accordance with the input power, thereby improving the trade-off between power-added efficiency, saturated output power, and linearity.

[0078] Third Embodiment Next, a Doherty amplifier according to a third embodiment will be described with reference to FIG.

[0079] In the third embodiment, a Doherty amplifier including an active bias circuit for adjusting the gate bias of a driver amplifier will be described. Note that the description overlapping with the first embodiment will be omitted.

[0080] Fig. 8 is a circuit diagram showing one configuration of a Doherty amplifier according to the third embodiment. A Doherty amplifier 300 in Fig. 8 differs from the Doherty amplifier 100 according to the first embodiment in Fig. 1 in that it includes an active bias circuit 320 instead of the active bias circuit 120. The following description will focus on the differences.

[0081] 1, the active bias circuit 320 differs in that it outputs a driver amplifier bias voltage VgDr instead of the peak amplifier bias voltage VgPA, and adjusts the gate bias voltage of the driver amplifier 350 instead of the peak amplifier 170. Note that the peak amplifier 370 is applied with the peak amplifier bias voltage VgPA, which is a fixed voltage, in the same way as a general Doherty amplifier, and continues to operate in class C.

[0082] The operation of the Doherty amplifier 300 according to the third embodiment configured as above will be described, focusing on the active bias circuit that is different from that of the first embodiment.

[0083] The Doherty amplifier 300 detects the power of the RF signal distributed to the path from the divider 180 to the peak amplifier 370 using the detection circuit 110, and adjusts the driver amplifier bias voltage VgDr according to the power using the active bias circuit 320, thereby changing the gate bias state of the power amplifying transistor of the driver amplifier 350. For example, by increasing the driver amplifier bias voltage VgDr as the input power increases, it is possible to achieve class AB operation with a small idle current when the input power is low, and class AB operation with a large idle current when the input power is high, thereby improving the power-added efficiency when the input power is low, without deteriorating the saturated output power or linearity of the Doherty amplifier 300.

[0084] As described above, the Doherty amplifier 300 according to the third embodiment can improve the trade-off between power added efficiency, saturated output power, and linearity.

[0085] In this embodiment, the active bias circuit 320 increases the driver amplifier bias voltage VgDr when the input power is high so that the input power is low and the input power is high, but the active bias circuit 320 may decrease the driver amplifier bias voltage VgDr when the input power is high so that the input power is low and the input power is high, so that the input power is low and the input power is high, respectively. In cases where the driver amplifier 350 operates in class AB mode with a constant idle current, resulting in poor linearity due to gain expansion characteristics, the linearity and power added efficiency can be improved by decreasing the idle current when the input power is high.

[0086] In this embodiment, the peak amplifier 370 is applied with the peak amplifier bias voltage VgPA, which is a fixed voltage, and is configured to continue operating in class C, but as in embodiment 1, the peak amplifier bias voltage VgPA may also be adjusted simultaneously with the driver amplifier bias voltage VgDr by the active bias circuit 320, or when the power that the peak amplifier 370 needs to amplify is high, the peak amplifier 370 may be operated in class AB, which has a high power gain and saturated output power. Similarly, the carrier amplifier bias voltage VgCA of the carrier amplifier 160 may also be adjusted simultaneously with the driver amplifier bias voltage VgDr.

[0087] As described above, the Doherty amplifier 300 according to the third embodiment is a Doherty amplifier including the carrier amplifier 160 and the peak amplifier 370, and includes the driver amplifier 350 that amplifies an input signal, the divider 180 that distributes an output signal of the driver amplifier 350 to the carrier amplifier 160 and the peak amplifier 370, the detection circuit 110 that is connected to the output of the divider 180 on the peak amplifier 370 side and detects the power input to the peak amplifier 370, and the active bias circuit 320 that adjusts the gate bias of the driver amplifier 350 in accordance with the output signal of the detection circuit 110.

[0088] This makes it possible to optimize the bias state of the driver amplifier 350 in accordance with the input power, thereby improving the trade-off between power-added efficiency, saturated output power, and linearity.

[0089] Fourth Embodiment Next, a Doherty amplifier according to a fourth embodiment will be described with reference to FIG.

[0090] In the fourth embodiment, a carrier amplifier and a peak amplifier will be described as a Doherty amplifier, which is a multistage amplifier having a plurality of power amplification transistors. Note that the description overlapping with the first embodiment will be omitted.

[0091] Fig. 9 is a circuit diagram showing one configuration of a Doherty amplifier according to the fourth embodiment. The Doherty amplifier 400 in Fig. 9 differs from the Doherty amplifier 100 according to the first embodiment in Fig. 1 in that the driver amplifier is not connected before the distributor 480, and instead the carrier amplifier 460 and the peak amplifier 470 are each two-stage amplifiers. The following description will focus on these differences.

[0092] The carrier amplifier 460 is a two-stage amplifier including a carrier amplifier front stage 461 and a carrier amplifier rear stage 462, and has a power gain that is, for example, 15 dB higher than that of the carrier amplifier 160 in Fig. 1 . Similarly, the peak amplifier 470 is also a two-stage amplifier including a peak amplifier front stage 471 and a peak amplifier rear stage 472, and has a power gain that is, for example, 15 dB higher than that of the peak amplifier 170 in Fig. 1 . Therefore, the Doherty amplifier 400 can obtain a power gain equivalent to that of the Doherty amplifier 100 by providing the carrier amplifier 460 and the peak amplifier 470 with an amplification function equivalent to that of the driver amplifier 150 of the Doherty amplifier 100 in Fig. 1 .

[0093] The distributor 480 distributes the RF signal input from the PIN terminal to a path to the carrier amplifier 460 and a path to the peak amplifier 470 .

[0094] Carrier amplifier 460 amplifies RF signal CAin distributed from distributor 480 in carrier amplifier front stage 461 and carrier amplifier rear stage 462, and outputs the amplified signal to quarter-wave transmission line 141. The power amplification transistors in carrier amplifier front stage 461 and carrier amplifier rear stage 462 are gate biased so as to operate in class AB.

[0095] The quarter-wave transmission line 141 delays the phase of the output signal of the carrier amplifier 460 by, for example, 90 degrees. The quarter-wave transmission line 141 is also connected to the node with the output of the peak amplifier 470 to convert impedance and realize cooperative operation of the carrier amplifier 460 and the peak amplifier 470.

[0096] The phase shifter 430 delays the phase of the RF signal distributed to the path from the distributor 480 to the peak amplifier 470 and outputs the delayed signal. The phase delay is set to, for example, 45 to 135 degrees.

[0097] The detection circuit 410 is connected to the output of the phase shifter 430 and the input of the peak amplifier 470, detects the power of the RF signal distributed to the path from the distributor 480 to the peak amplifier 470, and outputs a detection signal Pdet to the active bias circuit 420.

[0098] The active bias circuit 420 sets and adjusts the peak amplifier bias voltage VgPA of the peak amplifier post-stage 472 of the peak amplifier 470 in response to the detection signal Pdet of the detection circuit 410 .

[0099] The peak amplifier 470 amplifies the RF signal PAin input from the distributor 480 via the phase shifter 430 and the detection circuit 410 in a peak amplifier front stage 471 and a peak amplifier rear stage 472, combines it with the output signal of the carrier amplifier 460 that has passed through the quarter-wave transmission line 141, and outputs the amplified signal to the quarter-wave transmission line 142. The power amplification transistor in the peak amplifier front stage 471 is gate biased so as to operate in class C. The power amplification transistor in the peak amplifier rear stage 472 is gate biased by a peak amplifier bias voltage VgPA from the active bias circuit 420, and operates while changing between class C and class AB depending on the input power.

[0100] The quarter-wave transmission line 142 converts the RF signal, which is the output combination from the carrier amplifier 460 and the peak amplifier 470, into a reference impedance of 50Ω and outputs the converted signal to the POUT terminal.

[0101] The operation of the Doherty amplifier 400 according to the fourth embodiment configured as above will be described, focusing on the differences from the first embodiment.

[0102] An RF input signal input from a PIN terminal is distributed by distributor 480 to a path to carrier amplifier 460 and a path to peak amplifier 470. RF signal CAin distributed to the path to carrier amplifier 460 is amplified by carrier amplifier 460 and output to a junction with the output of peak amplifier 470 via quarter-wave transmission line 141. Meanwhile, the RF signal distributed to the path to peak amplifier 470 becomes RF signal PAin via phase shifter 430 and detection circuit 410, is amplified by peak amplifier 470, and is combined with the output from carrier amplifier 460. The combined RF signal output from carrier amplifier 460 and peak amplifier 470 is impedance converted to a reference impedance of 50 Ω via quarter-wave transmission line 142 and output to a POUT terminal. The power amplifier transistor in the peak amplifier post-stage 472 of the peak amplifier 470 operates in class C when the power of the RF signal input from the PIN terminal is low, and transitions to class AB when the power increases, due to the peak amplifier bias voltage VgPA adjusted by the active bias circuit 420. The operating class of the peak amplifier post-stage 472 changes depending on the power. This allows the Doherty amplifier 400 to reduce power consumption of the peak amplifier 470 through highly efficient class C operation when the power is low, and to increase the output power of the peak amplifier 470 through class AB operation, which has high power gain and saturated output power, when the power is high. This allows for higher linearity and saturated output power compared to a Doherty amplifier equipped with a peak amplifier that continues class C operation with a typical peak amplifier bias voltage kept constant. Furthermore, the Doherty amplifier 400 can turn off the peak amplifier pre-stage 471 when the power is low and amplification by the peak amplifier 470 is not required. 1, even when the input power is low, the power is amplified by the driver amplifier 150 and then distributed to the path to the peak amplifier 170, and some power is wasted because the peak amplifier 170 does not amplify the power, but it is possible to prevent some of this power from being consumed by the Doherty amplifier 400. In other words, the power-added efficiency can be further improved compared to the Doherty amplifier 100 of FIG.

[0103] As described above, the Doherty amplifier 400 according to the fourth embodiment can improve the trade-off between power added efficiency, saturated output power, and linearity.

[0104] In this embodiment, the detector circuit 410 is connected to the output of the phase shifter 430 and the input of the peak amplifier 470. However, it may be connected to the path from the distributor 480 to the output of the peak amplifier 470. A different configuration example from this embodiment is shown in FIG. 10 . The Doherty amplifier 400a of FIG. 10 differs from the Doherty amplifier 400 of FIG. 9 in that the detector circuit 410a is connected to the output of the peak amplifier pre-stage 471a and the input of the peak amplifier post-stage 472a of the peak amplifier 470a. In this case, the RF signal input to the detector circuit 410a does not become large until the input power at which the peak amplifier pre-stage 471a begins amplifying. However, it is possible to adjust the peak amplifier bias voltage VgPA using the active bias circuit 420 when the input power is high. By locating the detector circuit 410a near the peak amplifier post-stage 472a, it becomes easier to form detector elements such as diodes in the detector circuit 410a on the same semiconductor substrate as the power amplification transistors in the peak amplifier post-stage 472a.

[0105] In this embodiment, the active bias circuit 420 is configured to output the peak amplifier bias voltage VgPA in order to adjust the gate bias of the peak amplifier subsequent stage 472 in accordance with the input, but the peak amplifier bias voltage VgPA may be used to adjust the gate bias of the peak amplifier subsequent stage 471. Furthermore, one or more of the gate biases of the carrier amplifier subsequent stage 461, the carrier amplifier subsequent stage 462, the peak amplifier subsequent stage 471, and the peak amplifier subsequent stage 472 may be adjusted simultaneously.

[0106] As described above, in the Doherty amplifier 400 according to the fourth embodiment, the carrier amplifier 460 and the peak amplifier 470 are each a multistage amplifier having a plurality of power amplification transistors.

[0107] This makes it possible to improve the trade-off between power added efficiency, saturated output power, and linearity of the Doherty amplifier 400 configured with the carrier amplifier 460 and peak amplifier 470 of a multistage amplifier.

[0108] Fifth Embodiment Next, a Doherty amplifier according to a fifth embodiment will be described with reference to FIG.

[0109] In the fifth embodiment, a peak amplifier will be described as a Doherty amplifier having a plurality of power amplification transistors to which different gate biases are applied. Note that descriptions overlapping with the first embodiment will be omitted.

[0110] Fig. 11 is a circuit diagram showing one configuration of a Doherty amplifier according to the fifth embodiment. The Doherty amplifier 500 in Fig. 11 differs from the Doherty amplifier 100 according to the first embodiment in Fig. 1 in that a peak amplifier 570 includes two amplifiers to which different gate bias voltages are applied from an active bias circuit 520. For example, the total device size of the two amplifiers in the peak amplifier 570 is the same as the device size of the peak amplifier 170 in Fig. 1. The following description will focus on the differences.

[0111] Divider 580 distributes the RF signal amplified by driver amplifier 150 to a path to carrier amplifier 560 and a path to peak amplifier 570. Because peak amplifier 570 is a two-input amplifier made up of first peak amplifier 571 and second peak amplifier 572, divider 580 is a three-way divider, and distributes power in a ratio of 2:1:1 to the path to carrier amplifier 560, the path to first peak amplifier 571, and the path to second peak amplifier 572, for example.

[0112] The carrier amplifier 560 amplifies the RF signal CAin distributed from the distributor 580 and outputs it to the quarter-wave transmission line 541 .

[0113] The quarter-wave transmission line 541 delays the phase of the output signal of the carrier amplifier 560 by, for example, 90 degrees. The quarter-wave transmission line 541 is also connected to the junction with the output of the first peak amplifier 571 to convert impedance and realize cooperative operation of the carrier amplifier 560 and the first peak amplifier 571. The quarter-wave transmission line 541 may be a simple transmission line, or may be configured with a distributed constant or a lumped constant.

[0114] Phase shifters 531 and 532 delay the phase of the RF signal distributed from distributor 580 to the path to first peak amplifier 571 and the path to second peak amplifier 572, and output the delayed signal. The phase delay is set to, for example, 45 to 135 degrees.

[0115] The detection circuit 510 is connected to the output of the phase shifter 532 and the input of the second peak amplifier 572, detects the power of the RF signal distributed to the path from the distributor 580 to the second peak amplifier 572, and outputs a detection signal Pdet to the active bias circuit 520.

[0116] The active bias circuit 520 sets and adjusts a first peak amplifier bias voltage VgPA1 of the first peak amplifier 571 and a second peak amplifier bias voltage VgPA2 of the second peak amplifier 572 in accordance with the detection signal Pdet from the detection circuit 510. The second peak amplifier bias voltage VgPA2 may be generated by level-shifting the first peak amplifier bias voltage VgPA1, or may be generated by a different circuit.

[0117] The first peak amplifier 571 amplifies the RF signal PA1in input from the distributor 580 via the phase shifter 531, combines it with the output signal of the carrier amplifier 560 via the quarter-wave transmission line 541, and outputs it to the quarter-wave transmission line 542. The power amplification transistor of the first peak amplifier 571 is gate-biased by the first peak amplifier bias voltage VgPA1 of the active bias circuit 520, and operates while changing between class C and class AB according to the input power.

[0118] The quarter-wave transmission line 542 delays, for example, by 90 degrees, the phase of the RF signal output and combined from the carrier amplifier 560 and the first peak amplifier 571. The quarter-wave transmission line 542 also converts impedance to achieve cooperative operation with the second peak amplifier 572. The quarter-wave transmission line 542 may be a simple transmission line, or may be configured with a distributed constant or a lumped constant.

[0119] The second peak amplifier 572 amplifies the RF signal PA2in input from the divider 580 via the phase shifter 532 and the detector circuit 510, combines it with the RF signal output from the quarter-wave transmission line 542, and outputs the resulting signal to the POUT terminal. The power amplification transistor of the second peak amplifier 572 is gate-biased by a second peak amplifier bias voltage VgPA2 from the active bias circuit 520, and operates while changing between class C and class AB depending on the input power. Note that the second peak amplifier 572 starts amplifying at a higher input power than the first peak amplifier 571, so that the second peak amplifier bias voltage VgPA2 is set lower than the first peak amplifier bias voltage VgPA1 when the input power is low (its absolute value is higher in the case of a negative voltage). At an input power corresponding to the saturated output power, the second peak amplifier bias voltage VgPA2 and the first peak amplifier bias voltage VgPA1 may be equal.

[0120] The operation of the Doherty amplifier 500 according to the fifth embodiment configured as above will be described, focusing on the differences from the first embodiment.

[0121] An RF input signal input from a PIN terminal is distributed by distributor 580 to a path to carrier amplifier 560, a path to first peak amplifier 571, and a path to second peak amplifier 572. RF signal CAin distributed to the path to carrier amplifier 560 is amplified by carrier amplifier 560 and output to a junction with the output of first peak amplifier 571 via quarter-wave transmission line 541. Meanwhile, the RF signal distributed to the path to first peak amplifier 571 becomes RF signal PA1in via phase shifter 531, is amplified by first peak amplifier 571, and is combined with the output from carrier amplifier 560. The combined RF signal output from carrier amplifier 560 and first peak amplifier 571 is impedance converted to a reference impedance of 50 Ω via quarter-wave transmission line 542 and output to a POUT terminal. Furthermore, the RF signal distributed to the path to the second peak amplifier 572 becomes an RF signal PA2in via the phase shifter 532 and the detection circuit 510, is amplified by the second peak amplifier 572, is combined with the RF signal output from the quarter-wave transmission line 542, and is output to the POUT terminal. The power amplification transistors of the first peak amplifier 571 and the second peak amplifier 572 operate in class C when the power of the RF signal input from the PIN terminal is low, and transition to class AB when the power increases, due to the first peak amplifier bias voltage VgPA1 and the second peak amplifier bias voltage VgPA2 adjusted by the active bias circuit 520. In the Doherty amplifier 500, when the input power is low, only the driver amplifier 150 and the carrier amplifier 560 perform amplification, but when the input power increases and the carrier amplifier 560 begins to reach power saturation, the first peak amplifier 571 begins amplification, and when the input power increases further, the second peak amplifier 572 also begins amplification, and the carrier amplifier 560, the first peak amplifier 571, and the second peak amplifier 572 operate in cooperation. The operating classes of the first peak amplifier 571 and the second peak amplifier 572 change depending on the power.As a result, the Doherty amplifier 500 can reduce the power consumption of the first peak amplifier 571 and the second peak amplifier 572 through highly efficient class C operation when the power is low, and can increase the output power of the first peak amplifier 571 and the second peak amplifier 572 through class AB operation, which has high power gain and saturated output power, when the power is high. This allows for higher linearity and saturated output power compared to a Doherty amplifier equipped with a peak amplifier that continues class C operation at a typical constant bias voltage. Furthermore, the Doherty amplifier 500 can turn off the second peak amplifier 572 when the power level requires amplification by the first peak amplifier 571 but not amplification by the second peak amplifier 572. This increases the power efficiency of the peak amplifier 570, and improves the power-added efficiency of the Doherty amplifier 500 compared to the Doherty amplifier 100 of FIG. 1 .

[0122] As described above, the Doherty amplifier 500 according to the fifth embodiment can improve the trade-off between power added efficiency, saturated output power, and linearity.

[0123] In this embodiment, the active bias circuit 520 is configured to adjust the gate bias of both the first peak amplifier 571 and the second peak amplifier 572, but it may adjust only one of them. For example, it is possible to adjust only the gate bias of the first peak amplifier 571 and apply a fixed peak amplifier bias voltage VgPA2 to the second peak amplifier 572, thereby continuing Class C operation. Furthermore, it is also possible to simultaneously adjust the gate bias of one or more of the driver amplifier 150, carrier amplifier 560, first peak amplifier 571, and second peak amplifier 572.

[0124] In this embodiment, the Doherty amplifier 500 is a 3-way Doherty amplifier distributed to a path to the carrier amplifier 560, a path to the 1st peak amplifier 571, and a path to the 2nd peak amplifier 572, but it may also be an N-way Doherty amplifier with more paths, and the gate bias of one or more peak amplifiers may be adjusted according to the input power.

[0125] As described above, the peak amplifier 570 of the Doherty amplifier 500 according to the fifth embodiment has a plurality of power amplification transistors to which different gate biases are applied.

[0126] This makes it possible to improve the trade-off between power-added efficiency, saturated output power, and linearity of the Doherty amplifier 500 including the peak amplifier 570 having a plurality of power amplifying transistors.

[0127] The accompanying drawings and detailed description have been provided as embodiments to illustrate the technology disclosed in this application.

[0128] Therefore, the components shown in the accompanying drawings and detailed description may include not only essential components for solving the problem, but also components that are not essential for solving the problem in order to illustrate the above technology. Therefore, the fact that these non-essential components are shown in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential.

[0129] Note that the technology in the present disclosure is not limited to these, and can be applied to embodiments with appropriate changes, substitutions, additions, omissions, etc. Furthermore, as long as they do not deviate from the spirit of the technology in the present disclosure, various modifications that a person skilled in the art could conceive of, and forms constructed by combining the components of multiple embodiments, are also included within the scope of the technology in the present disclosure.

[0130] The Doherty amplifier of the present disclosure includes an active bias circuit that adjusts the gate bias according to power, thereby improving the trade-off between power-added efficiency, saturated output power, and linearity.

[0131] The Doherty amplifier of the present disclosure can also be used in power amplification systems for base stations and terminals of mobile phones and satellite communications, radar transmitters, wireless power transmitters, microwave heating devices such as microwave ovens, and the like.

[0132] 100, 200, 300, 400, 400a, 500 Doherty amplifier 110, 410, 410a, 510 Detection circuit 111, 112 Capacitor 113, 121, 122, 123, 124, 125, 126 Resistor 114 Diode 115, 173 Inductor 127 Transistor 120, 220, 320, 420, 520 Active bias circuit 130, 430, 531, 532 Phase shifter 141, 142, 181, 182, 541, 542 1 / 4 wavelength transmission line 150, 350 Driver amplifier 160, 260, 460, 560 Carrier amplifier 170, 270, 370, 470, 470a, 570 Peak amplifier 171, 174 Matching circuit 172 Power amplification transistor 180, 480, 580 Distributor 188 Isolation resistor 461 Carrier amplifier front stage 462 Carrier amplifier rear stage 471, 471a Peak amplifier front stage 472, 472a Peak amplifier rear stage 571 1st peak amplifier 572 2nd peak amplifier

Claims

1. A Doherty amplifier having a carrier amplifier and a peak amplifier, comprising: a divider that distributes an input signal to the carrier amplifier and the peak amplifier; a detection circuit that is connected to the peak amplifier side output of the divider and detects the power input to the peak amplifier; and an active bias circuit that adjusts the gate bias of the carrier amplifier or the peak amplifier according to the output signal of the detection circuit.

2. The Doherty amplifier of claim 1, wherein the detector circuit comprises a diode.

3. The Doherty amplifier according to claim 2, wherein the peak amplifier has a power amplification transistor formed on a first semiconductor substrate, and the diode is formed on the first semiconductor substrate.

4. The Doherty amplifier according to claim 1, wherein the active bias circuit adjusts the gate bias of the peak amplifier in accordance with the output signal of the detection circuit.

5. The Doherty amplifier according to claim 1, wherein the active bias circuit adjusts the gate bias of the carrier amplifier in accordance with the output signal of the detection circuit.

6. A Doherty amplifier having a carrier amplifier and a peak amplifier, comprising: a driver amplifier that amplifies an input signal; a divider that distributes an output signal of the driver amplifier to the carrier amplifier and the peak amplifier; a detection circuit that is connected to the peak amplifier side output of the divider and detects the power input to the peak amplifier; and an active bias circuit that adjusts the gate bias of the driver amplifier in accordance with the output signal of the detection circuit.

7. The Doherty amplifier according to any one of claims 1 to 3 and 6, wherein the carrier amplifier and the peak amplifier are each multistage amplifiers having a plurality of power amplification transistors.

8. The Doherty amplifier according to any one of claims 1 to 3 and 6, wherein the peak amplifier has a plurality of power amplification transistors to which different gate biases are applied.

9. The Doherty amplifier according to any one of claims 1 to 3 and 6, wherein the divider is a Wilkinson divider that distributes power to the carrier amplifier and the peak amplifier at a power distribution ratio of 1:K, and has an isolation resistor, the resistance value Riso of the isolation resistor satisfying the following equation (1) based on a reference impedance Zo:

Images