Pixel circuit, driving method and display apparatus

Abstract

A pixel circuit, a driving method and a display apparatus. The pixel circuit comprises a driving circuit (10), a light-emitting element (E1), a first energy storage circuit (11), a second energy storage circuit (12), a first control circuit (13) and a second control circuit (14), wherein a first end of the first energy storage circuit (11) is electrically connected to a second node (N2), and a second end of the first energy storage circuit (11) is electrically connected to a third node (N3); a first end of the second energy storage circuit (12) is electrically connected to the third node (N3), and a second end of the second energy storage circuit (12) is electrically connected to a first node (N1); under the control of a first reset control signal, the first control circuit (13) provides to the third node (N3) a voltage signal provided by a reference voltage end (VB); and under the control of a first scanning signal, the second control circuit (14) controls the connection between the first node (N1) and the third node (N3). The pixel circuit can improve the threshold voltage compensation result, and can support the compensation for the threshold voltage of depletion-mode compensation transistors.

Description

Pixel circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0002] As the resolution and frequency of display devices increase, the solution of using data voltage to compensate for threshold voltage has encountered a driving bottleneck, and the demand for separate compensation circuits has greatly increased. Increasing the threshold voltage compensation time can improve the uniformity of the picture display. Since the LTPS (low-temperature polycrystalline silicon) process has high requirements for equipment precision, how to reduce costs has always been a difficult problem in the manufacturing process. Oxide thin-film transistors have their own low cost, high uniformity, and low leakage. Pixel circuits for oxides are urgently needed to be developed.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a light-emitting element, a first energy storage circuit, a second energy storage circuit, a first control circuit, and a second control circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element via the second node; the driving circuit is configured to drive the light-emitting element under the control of the potential of the first node;

[0006] The first end of the first energy storage circuit is electrically connected to the second node, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;

[0007] A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the first node, and the second energy storage circuit is used to store electrical energy;

[0008] The first control circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the third node respectively, and is configured to provide the voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal provided by the first reset control terminal;

[0009] The second control circuit is electrically connected to the first scanning end, the first node and the third node respectively, and is used to control the connection between the first node and the third node under the control of a first scanning signal provided by the first scanning end.

[0010] Optionally, in a refresh frame, the turn-on time of the first control circuit is greater than the turn-on time of the second control circuit; and when the second control circuit is turned on, the first control circuit is also turned on.

[0011] Optionally, in a refresh frame, the first control circuit is turned on at least twice.

[0012] Optionally, the pixel circuit further includes a node adjustment circuit;

[0013] A first terminal of the node adjustment circuit is electrically connected to the second node, a second terminal of the node adjustment circuit is electrically connected to a DC voltage terminal, and the node adjustment circuit is used to adjust the potential of the second node; or

[0014] A first end of the node adjustment circuit is electrically connected to the first node, a second end of the node adjustment circuit is electrically connected to a DC voltage end, and the node adjustment circuit is used to adjust the potential of the first node.

[0015] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit and a second light-emitting control circuit; the first terminal of the driving circuit is electrically connected to the power supply voltage terminal through the first light-emitting control circuit, and the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit;

[0016] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the communication between the power supply voltage terminal and the first terminal of the driving circuit under the control of a first light-emitting control signal provided by the first light-emitting control terminal;

[0017] The second light emitting control circuit is electrically connected to the second light emitting control terminal, the second node, and the first electrode of the light emitting element, respectively, and is configured to control the connection between the second node and the first electrode of the light emitting element under the control of a second light emitting control signal provided by the second light emitting control terminal;

[0018] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0019] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit;

[0020] The data writing circuit is electrically connected to the second scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the second scanning signal provided by the second scanning end.

[0021] Optionally, in a refresh frame, the start-up time of the data writing circuit does not overlap with the start-up time of the second control circuit; the start-up time of the data writing circuit at least partially overlaps with the start-up time of the first control circuit.

[0022] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes an initialization circuit;

[0023] The initialization circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0024] Optionally, in a refresh frame, when the initialization circuit is turned on, the first light-emitting control circuit is turned off.

[0025] Optionally, in a refresh frame, when the initialization circuit is turned on, the second control circuit is turned off.

[0026] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0027] The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0028] A gate of the second transistor is electrically connected to the first scanning end, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

[0029] Optionally, the driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0030] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the second node;

[0031] The first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node;

[0032] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first node.

[0033] Optionally, the node adjustment circuit includes a third capacitor;

[0034] The first end of the third capacitor is electrically connected to the second node, and the second end of the third capacitor is electrically connected to the DC voltage end; or,

[0035] The first terminal of the third capacitor is electrically connected to the first node, and the second terminal of the third capacitor is electrically connected to the DC voltage terminal. Optionally, the first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor;

[0036] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit;

[0037] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0038] Optionally, the data writing circuit includes a fifth transistor;

[0039] A gate of the fifth transistor is electrically connected to the second scanning end, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the first node.

[0040] Optionally, the initialization circuit includes a sixth transistor;

[0041] The gate of the sixth transistor is electrically connected to the second reset control terminal, the first electrode of the sixth transistor is electrically connected to the initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

[0042] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0043] The driving circuit drives the light emitting element under the control of the potential of the first node;

[0044] The first control circuit provides a voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal;

[0045] The second control circuit controls the connection between the first node and the third node under the control of the first scan signal;

[0046] The display cycle includes a refresh frame, the refresh frame includes a refresh period, and the refresh period includes a compensation phase; the driving method includes:

[0047] In the compensation phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the second control circuit controls the connection between the first node and the third node under the control of the first scan signal;

[0048] The pixel circuit further includes a data writing circuit; the refresh period further includes a writing phase arranged after the compensation phase; and the driving method further includes:

[0049] In the write phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the data write circuit writes the data voltage provided by the data line into the first node under the control of the second scan signal;

[0050] The pixel circuit further includes a first light emitting control circuit and a second light emitting control circuit; and the driving method further includes:

[0051] In the compensation stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;

[0052] At the beginning of the compensation phase, the driving circuit controls the connection between the first terminal of the driving circuit and the second node under the control of the potential of the first node, thereby charging the first energy storage circuit and the second energy storage circuit, until the potential of the second node becomes Vref1-Vth, and the driving circuit is turned off; Vth is the threshold voltage of the driving transistor in the driving circuit;

[0053] The refresh period also includes an initialization phase provided before the compensation phase; the driving method includes:

[0054] In the initialization phase, the first control circuit, under the control of the first reset control signal, provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node; the second control circuit, under the control of the first scan signal, controls the connection between the first node and the third node; and the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the second node and the first electrode of the light-emitting element;

[0055] The pixel circuit further includes an initialization circuit; and the driving method further includes:

[0056] In the initialization stage, the initialization circuit writes the initial voltage into the first electrode of the light-emitting element under the control of the second reset control signal;

[0057] The refresh period also includes a light emitting phase arranged after the writing phase; the driving method includes:

[0058] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0059] Optionally, the pixel circuit further includes a node adjustment circuit; the refresh time period further includes a stress application phase;

[0060] The driving method includes:

[0061] During the initialization phase, the compensation phase, the writing phase, and the light-emitting phase, the reference voltage terminal provides a first reference voltage;

[0062] During the stress application phase, the first control circuit provides a second reference voltage provided by a reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage.

[0063] Optionally, the stress application stage is set before the initialization stage; or, the stress application stage is set between the initialization stage and the compensation stage; or, the stress application stage is set between the compensation stage and the writing stage; or, the stress application stage is set between the writing stage and the light-emitting stage.

[0064] Optionally, the pixel circuit includes an initialization circuit; the refresh frame further includes at least one holding period set after the refresh period; the holding period includes a holding initialization phase, a holding stress application phase, and a holding light emission phase; the driving method includes:

[0065] In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage;

[0066] During the hold stress application phase, the first control circuit provides a second reference voltage provided by the reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage;

[0067] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0068] Optionally, the pixel circuit includes an initialization circuit; the display cycle further includes at least one hold frame provided after the refresh frame; the hold frame includes a hold initialization phase, a hold stress application phase, and a hold light emission phase; the driving method includes:

[0069] In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage;

[0070] During the hold stress application phase, the first control circuit provides a second reference voltage provided by the reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage;

[0071] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0072] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG2A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] FIG2B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG4A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG4B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG6A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG6B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG8A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG8B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] FIG10 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG9 ;

[0087] FIG11A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG9 ;

[0088] FIG11B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG9 ;

[0089] FIG12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG13 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12 ;

[0091] FIG14 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12 ;

[0092] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a driving circuit 10 , a light-emitting element E1 , a first energy storage circuit 11 , a second energy storage circuit 12 , a first control circuit 13 and a second control circuit 14 ;

[0094] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal VDD, and the second terminal of the driving circuit 10 is electrically connected to the light emitting element E1 through the second node N2;

[0095] The driving circuit 10 is used to drive the light emitting element E1 under the control of the potential of the first node N1;

[0096] A first end of the first energy storage circuit 11 is electrically connected to the second node N2, a second end of the first energy storage circuit 11 is electrically connected to the third node N3, and the first energy storage circuit 11 is used to store electrical energy;

[0097] A first end of the second energy storage circuit 12 is electrically connected to the third node N3, a second end of the second energy storage circuit 12 is electrically connected to the first node N1, and the second energy storage circuit 12 is used to store electrical energy;

[0098] The first control circuit 13 is electrically connected to the first reset control terminal R1, the reference voltage terminal VB and the third node N3 respectively, and is configured to provide a voltage signal provided by the reference voltage terminal VB to the third node N3 under the control of a first reset control signal provided by the first reset control terminal R1;

[0099] The second control circuit 14 is electrically connected to the first scan terminal GT1, the first node N1 and the third node N3 respectively, and is used to control the connection between the first node N1 and the third node N3 under the control of the first scan signal provided by the first scan terminal GT1.

[0100] The pixel circuit described in the embodiment of the present disclosure resets the gate and source of the driving transistor in the driving circuit, detects the threshold voltage at the source of the driving transistor, and separates the data voltage writing time from the threshold voltage compensation time, thereby improving the threshold voltage compensation result and supporting the compensation of the threshold voltage of the depletion-type compensation transistor; the pixel circuit described in the embodiment of the present disclosure writes a DC voltage signal to the connection node of the first energy storage circuit 11 and the second energy storage circuit 12 to perform a gate-source isolation design for the driving transistor, thereby improving the data voltage writing efficiency.

[0101] During specific implementation, the threshold voltage drift of the depletion-mode transistor may be relatively serious. At least one embodiment of the present disclosure can support compensation of the threshold voltage of the depletion-mode drive transistor.

[0102] In at least one embodiment of the present disclosure, in a refresh frame, the first control circuit is turned on for a longer time than the second control circuit; and when the second control circuit is turned on, the first control circuit is also turned on.

[0103] In a specific implementation, the turn-on time of the first control circuit is greater than the turn-on time of the second control circuit. When the second control circuit controls the connection between the first node N1 and the third node N3 under the control of the first scan signal provided by the first scan terminal GT1, the first control circuit 13, under the control of the first reset control signal provided by the first reset control terminal R1, provides the voltage signal provided by the reference voltage terminal VB to the third node N3, so as to provide the voltage signal provided by the reference voltage terminal VB to the first node N1, so as to reset the potential of the first node N1 and the potential of the third node N3.

[0104] In at least one embodiment of the present disclosure, in a refresh frame, the first control circuit is turned on at least twice.

[0105] In a specific implementation, in a refresh frame, the first control circuit provides the voltage signal provided by the reference voltage terminal VB to the third node N3 at least twice under the control of the first reset control signal provided by the first reset control terminal R1, so as to reset the potential of the third node N3 at least twice.

[0106] In at least one embodiment of the present disclosure, the first control circuit being turned on may refer to: the first control circuit providing the voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal provided by the first reset control terminal;

[0107] The second control circuit being turned on may mean that the second control circuit controls the first node and the third node to be connected under the control of the first scan signal provided by the first scan end.

[0108] In at least one embodiment of the present disclosure, the pixel circuit further includes a node adjustment circuit;

[0109] A first terminal of the node adjustment circuit is electrically connected to the second node, a second terminal of the node adjustment circuit is electrically connected to a DC voltage terminal, and the node adjustment circuit is used to adjust the potential of the second node; or

[0110] A first end of the node adjustment circuit is electrically connected to the first node, a second end of the node adjustment circuit is electrically connected to a DC voltage end, and the node adjustment circuit is used to adjust the potential of the first node.

[0111] In a specific implementation, the pixel circuit may further include a node adjustment circuit, a first end of the node adjustment circuit being electrically connected to the second node, a second end of the node adjustment circuit being electrically connected to the DC voltage end, and the node adjustment circuit being used to adjust the potential of the second node; the reference voltage end may provide a second reference voltage during the stress application phase, and provide a first reference voltage during a time period other than the stress application phase, so as to change the gate-source voltage of the driving transistor included in the driving circuit in combination with the node adjustment circuit during the stress application phase, so as to perform stress bias on the driving transistor, restore the threshold voltage offset of the driving transistor caused by hysteresis, and support stress reset between low-frequency frames or between PWM (pulse width modulation) pulses.

[0112] Optionally, the DC voltage terminal may be a power supply voltage terminal or an initial voltage terminal, but is not limited thereto.

[0113] In a specific implementation, the pixel circuit may further include a node adjustment circuit; a first end of the node adjustment circuit is electrically connected to the first node, a second end of the node adjustment circuit is electrically connected to the DC voltage end, and the node adjustment circuit is used to adjust the potential of the first node; the reference voltage end can provide a second reference voltage during the stress application stage, and provide a first reference voltage during a time period other than the stress application stage, so as to change the gate-source voltage of the driving transistor included in the driving circuit in combination with the node adjustment circuit during the stress application stage, so as to stress bias the driving transistor, restore the threshold voltage offset of the driving transistor caused by hysteresis, and support stress reset between low-frequency frames or PWM (pulse width modulation) pulses.

[0114] As shown in FIG2A , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a node adjustment circuit 21 ;

[0115] A first end of the node adjustment circuit 21 is electrically connected to the second node N2 , and a second end of the node adjustment circuit 21 is electrically connected to the DC voltage terminal VZ. The node adjustment circuit 21 is used to adjust the potential of the second node N2 .

[0116] As shown in FIG2B , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a node adjustment circuit 21 ;

[0117] A first end of the node adjustment circuit 21 is electrically connected to the first node N1 , and a second end of the node adjustment circuit 21 is electrically connected to the DC voltage terminal VZ. The node adjustment circuit 21 is used to adjust the potential of the first node N1 .

[0118] In at least one embodiment of the present disclosure, the DC voltage terminal VZ may be a power supply voltage terminal VDD or an initial voltage terminal, but is not limited thereto.

[0119] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit and a second light-emitting control circuit; the first terminal of the driving circuit is electrically connected to the power supply voltage terminal through the first light-emitting control circuit, and the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit;

[0120] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the communication between the power supply voltage terminal and the first terminal of the driving circuit under the control of a first light-emitting control signal provided by the first light-emitting control terminal;

[0121] The second light emitting control circuit is electrically connected to the second light emitting control terminal, the second node, and the first electrode of the light emitting element, respectively, and is configured to control the connection between the second node and the first electrode of the light emitting element under the control of a second light emitting control signal provided by the second light emitting control terminal;

[0122] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0123] In a specific implementation, the pixel circuit may include a first light-emitting control circuit and a second light-emitting control circuit; the first end of the driving circuit is electrically connected to the power supply voltage end through the first light-emitting control circuit, and the second node is electrically connected to the first pole of the light-emitting element through the second light-emitting control circuit; the first light-emitting control circuit controls the connection between the power supply voltage end and the first end of the driving circuit under the control of a first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0124] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 31 and a second light-emitting control circuit 32. The first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal VDD through the first light-emitting control circuit 31, and the second node N2 is electrically connected to the first electrode of the light-emitting element E1 through the second light-emitting control circuit 32.

[0125] The first light emitting control circuit 31 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the first terminal of the driving circuit 10, respectively, and is configured to control the communication between the power supply voltage terminal VDD and the first terminal of the driving circuit 10 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0126] The second light emitting control circuit 32 is electrically connected to the second light emitting control terminal EM2, the second node N2, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the second node N2 and the first electrode of the light emitting element E1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2;

[0127] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1.

[0128] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0129] As shown in FIG4A , based on at least one embodiment of the pixel circuit shown in FIG2A , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 31 and a second light-emitting control circuit 32. The first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal VDD through the first light-emitting control circuit 31, and the second node N2 is electrically connected to the first electrode of the light-emitting element E1 through the second light-emitting control circuit 32.

[0130] The first light emitting control circuit 31 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the first terminal of the driving circuit 10, respectively, and is configured to control the communication between the power supply voltage terminal VDD and the first terminal of the driving circuit 10 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0131] The second light emitting control circuit 32 is electrically connected to the second light emitting control terminal EM2, the second node N2, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the second node N2 and the first electrode of the light emitting element E1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2;

[0132] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1.

[0133] As shown in FIG4B , based on at least one embodiment of the pixel circuit shown in FIG2B , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 31 and a second light-emitting control circuit 32; the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal VDD through the first light-emitting control circuit 31, and the second node N2 is electrically connected to the first electrode of the light-emitting element E1 through the second light-emitting control circuit 32;

[0134] The first light emitting control circuit 31 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the first terminal of the driving circuit 10, respectively, and is configured to control the communication between the power supply voltage terminal VDD and the first terminal of the driving circuit 10 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0135] The second light emitting control circuit 32 is electrically connected to the second light emitting control terminal EM2, the second node N2, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the second node N2 and the first electrode of the light emitting element E1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2;

[0136] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1.

[0137] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit;

[0138] The data writing circuit is electrically connected to the second scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the second scanning signal provided by the second scanning end.

[0139] In a specific implementation, the pixel circuit may further include a data writing circuit; under the control of the second scanning signal, the data writing circuit writes the data voltage provided by the data line into the first node to perform data writing.

[0140] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, the data voltage provided by the data line can be written into the first node through the data writing circuit under the control of the second scanning signal, and the data writing time can be separated from the threshold voltage compensation time to improve the threshold voltage compensation effect.

[0141] In at least one embodiment of the present disclosure, in a refresh frame, the start time of the data write circuit does not overlap with the start time of the second control circuit; the start time of the data write circuit at least partially overlaps with the start time of the first control circuit.

[0142] In a specific implementation, in a refresh frame, when the data writing circuit writes the data voltage provided by the data line into the first node under the control of the second scanning signal to write data, the second control circuit controls the first node to be disconnected from the third node under the control of the first scanning signal;

[0143] In the refresh frame, when the data writing circuit writes the data voltage provided by the data line into at least a partial time period of the first node under the control of the second scanning signal, the second control circuit controls the connection between the first node and the third node under the control of the first scanning signal provided by the first scanning end.

[0144] In at least one embodiment of the present disclosure, turning on the data writing circuit may mean that the data writing circuit writes the data voltage provided by the data line into the first node under the control of the second scanning signal.

[0145] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 51 ;

[0146] The data writing circuit 51 is electrically connected to the second scanning terminal GT2, the data line DT and the first node N1 respectively, and is used to write the data voltage provided by the data line DT into the first node N1 under the control of the second scanning signal provided by the second scanning terminal GT2.

[0147] As shown in FIG6A , based on at least one embodiment of the pixel circuit shown in FIG4A , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 51 ;

[0148] The data writing circuit 51 is electrically connected to the second scanning terminal GT2, the data line DT and the first node N1 respectively, and is used to write the data voltage provided by the data line DT into the first node N1 under the control of the second scanning signal provided by the second scanning terminal GT2.

[0149] As shown in FIG6B , based on at least one embodiment of the pixel circuit shown in FIG4B , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 51 ;

[0150] The data writing circuit 51 is electrically connected to the second scanning terminal GT2, the data line DT and the first node N1 respectively, and is used to write the data voltage provided by the data line DT into the first node N1 under the control of the second scanning signal provided by the second scanning terminal GT2.

[0151] The pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit;

[0152] The initialization circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0153] In a specific implementation, the pixel circuit may further include an initialization circuit, which, under the control of a second reset control signal, writes the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0154] In at least one embodiment of the present disclosure, in a refresh frame, when the initialization circuit is turned on, the first light emitting control circuit is turned off.

[0155] In a specific implementation, in a refresh frame, when the initialization circuit writes the initial voltage provided by the initial voltage terminal into the first pole of the light-emitting element under the control of the second reset control signal, the first light-emitting control circuit controls the disconnection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal.

[0156] In at least one embodiment of the present disclosure, in a refresh frame, when the initialization circuit is turned on, the second control circuit is turned off.

[0157] In a specific implementation, in a refresh frame, when the initialization circuit writes the initial voltage provided by the initial voltage terminal into the first pole of the light-emitting element under the control of the second reset control signal, the second control circuit controls the disconnection between the first node and the third node under the control of the first scanning signal.

[0158] In at least one embodiment of the present disclosure, turning on the initialization circuit may refer to: the initialization circuit writing the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal;

[0159] The first light emitting control circuit being turned off may refer to: the first light emitting control circuit controlling the power supply voltage terminal and the first terminal of the driving circuit to be disconnected under the control of the first light emitting control signal;

[0160] The second control circuit being turned off may mean that the second control circuit controls the first node and the third node to be disconnected under the control of the first scan signal.

[0161] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit 71 ;

[0162] The initialization circuit 71 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0163] As shown in FIG8A , based on at least one embodiment of the pixel circuit shown in FIG6A , the pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit 71 ;

[0164] The initialization circuit 71 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0165] As shown in FIG8B , based on at least one embodiment of the pixel circuit shown in FIG6B , the pixel circuit according to at least one embodiment of the present disclosure further includes an initialization circuit 71 ;

[0166] The initialization circuit 71 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0167] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0168] The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0169] A gate of the second transistor is electrically connected to the first scanning end, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

[0170] Optionally, the driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0171] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the second node;

[0172] The first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node;

[0173] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first node.

[0174] Optionally, the node adjustment circuit includes a third capacitor;

[0175] The first end of the third capacitor is electrically connected to the second node, and the second end of the third capacitor is electrically connected to the DC voltage end; or,

[0176] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to a DC voltage terminal.

[0177] Optionally, the first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor;

[0178] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit;

[0179] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0180] Optionally, the data writing circuit includes a fifth transistor;

[0181] A gate of the fifth transistor is electrically connected to the second scanning end, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the first node.

[0182] Optionally, the initialization circuit includes a sixth transistor;

[0183] The gate of the sixth transistor is electrically connected to the second reset control terminal, the first electrode of the sixth transistor is electrically connected to the initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

[0184] As shown in FIG9 , based on at least one embodiment of the pixel circuit shown in FIG7 , the light emitting element is an organic light emitting diode O1;

[0185] The first control circuit includes a first transistor T1, and the second control circuit includes a second transistor T2;

[0186] The gate of the first transistor T1 is electrically connected to the first reset control terminal R1, the drain of the first transistor T1 is electrically connected to the reference voltage terminal VB, and the source of the first transistor T1 is electrically connected to the third node N3;

[0187] The gate of the second transistor T2 is electrically connected to the first scanning terminal GT1, the drain of the second transistor T2 is electrically connected to the first node N1, and the source of the second transistor T2 is electrically connected to the third node N3;

[0188] The driving circuit includes a driving transistor TD, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0189] The gate of the driving transistor TD is electrically connected to the first node N1;

[0190] A first end of the first capacitor C1 is electrically connected to the second node N2, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0191] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the first node N1;

[0192] The first light emitting control circuit includes a third transistor T3, and the second light emitting control circuit includes a fourth transistor T4;

[0193] The gate of the third transistor T3 is electrically connected to the first light emitting control terminal EM1, the drain of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the source of the third transistor T3 is electrically connected to the drain of the driving transistor TD;

[0194] The gate of the fourth transistor T4 is electrically connected to the second light emitting control terminal EM2, the drain of the fourth transistor T4 is electrically connected to the second node N2, the source of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS;

[0195] The data writing circuit includes a fifth transistor T5;

[0196] The gate of the fifth transistor T5 is electrically connected to the second scanning terminal GT2, the drain of the fifth transistor T5 is electrically connected to the data line DT, and the source of the fifth transistor T5 is electrically connected to the first node N1;

[0197] The initialization circuit includes a sixth transistor T6;

[0198] The gate of the sixth transistor T6 is electrically connected to the second reset control terminal R2, the drain of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the initial voltage terminal I1 is used to provide an initial voltage Vinit.

[0199] In at least one embodiment of the pixel circuit shown in FIG. 9 , all transistors are n-type transistors, and TD is a depletion-type transistor, but the present invention is not limited thereto.

[0200] In at least one embodiment of the pixel circuit shown in FIG. 9 , all transistors are oxide transistors, but the present invention is not limited thereto.

[0201] When at least one embodiment of the pixel circuit shown in FIG. 9 is in operation, VB may provide a first reference voltage Vref1 .

[0202] When at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure is in operation, by setting T1 and T2, when the potential of the first node N1 changes, the potential of the second node N2 is independent of the capacitance values ​​of C1 and C2, thereby improving the data voltage writing efficiency.

[0203] As shown in FIG10 , in operation of at least one embodiment of the pixel circuit shown in FIG9 of the present disclosure, a display cycle may include a refresh frame, wherein the refresh frame may include a refresh time period, and the refresh time period may include an initialization phase S1, a compensation phase S2, a writing phase S3, and a light emitting phase S4 that are sequentially arranged;

[0204] In the initialization phase S1, R1 provides a high voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a high voltage signal, EM2 provides a high voltage signal, EM1 provides a low voltage signal, T1 and T2 are turned on, T2 and T6 are turned on, the potential of N1 and the potential of N3 are Vref1, and the potential of N2 is Vinit, so that TD can be turned on when the compensation phase S2 begins;

[0205] In the compensation stage S2, R1 provides a high voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EM2 provides high and low voltage signals, EM1 provides a high voltage signal, T1 and T2 are turned on, T3 is turned on, and the potential of N1 and the potential of N3 are Vref1;

[0206] At the beginning of compensation phase S2, TD is turned on to charge the capacitor until the potential of N2 becomes Vref1-Vth, and TD is turned off. Vth is the threshold voltage of TD.

[0207] In the write phase S3, R1 provides a high voltage signal, GT1 provides a low voltage signal, GT2 provides a high voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a low voltage signal, T1 and T5 are turned on, DT provides a data voltage Vdata to N1, the potential of N2 is Vref1-Vth, and the potential of N3 is Vref1;

[0208] In the light-emitting stage S4, R1 provides a low voltage signal, R2 provides a low voltage signal, GT1 provides a low voltage signal, GT2 provides a low voltage signal, EM2 provides a high voltage signal, EM1 provides a high voltage signal, T3 and T4 are turned on, and TD drives O1 to emit light; the gate-source voltage Vgs of TD is equal to Vdata-Vref1+Vth, and Id is equal to 0.5K(Vdata-Vref1) 2 ; Wherein, K is the current coefficient of TD, and Id is the driving current generated by TD.

[0209] As shown in Figure 10, in the refresh frame,

[0210] The on-time of the first control circuit is greater than the on-time of the second control circuit, and when the second control circuit is turned on, the first control circuit is also turned on; that is, the on-time of T1 is greater than the on-time of T2, and when T2 starts, T1 is also turned on;

[0211] The start time of the data writing circuit does not overlap with the start time of the second control circuit; that is, the start time of T5 does not overlap with the start time of T1;

[0212] The start time of the data writing circuit and the start time of the first control circuit at least partially overlap; that is, the start time of T5 and the start time of T1 at least partially overlap;

[0213] When the initialization circuit is turned on, the first light emitting control circuit is turned off; that is, when T6 is turned on, T3 is turned off.

[0214] As shown in FIG11A , during operation of at least one embodiment of the pixel circuit shown in FIG9 of the present disclosure, a display cycle may include a refresh frame, wherein the refresh frame may include a refresh period, and the refresh period may include an initialization phase S1, a compensation phase S2, a writing phase S3, and a light emitting phase S4, which are sequentially arranged;

[0215] In the initialization phase S1, R1 and R2 provide a high voltage signal, GT1 provides a low voltage signal, GT2 provides a high voltage signal, EM2 provides a high voltage signal, EM1 provides a low voltage signal, T1 and T5 are turned on, T4 and T6 are turned on, DT provides a data voltage Vdata to the first node N1, the potential of the first node N1 is Vdata, the potential of the second node N2 is Vinit, and the potential of the third node N3 is Vref1, so that TD can be turned on when the compensation phase S2 begins;

[0216] In the compensation phase S2, R1 provides a high voltage signal, R2 provides a low voltage signal, GT1 and GT2 provide low voltage signals, EM2 provides a low voltage signal, EM1 provides a high voltage signal, T1 is turned on, and T3 is turned on;

[0217] At the beginning of compensation phase S2, TD is turned on to charge the capacitor until the potential of N2 becomes Vdata-Vth, and TD is turned off. Vth is the threshold voltage of TD.

[0218] In the write phase S3, R1 provides a high voltage signal, R2 provides a low voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, EM2 and EM1 provide low voltage signals, T1 and T2 are turned on, the potential of N1 is Vref1, the potential of N2 is Vdata-Vth, and the potential of N3 is Vref1;

[0219] In the light-emitting stage S4, R1, R2, GT1 and GT2 provide low voltage signals, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light; the gate-source voltage Vgs of TD is equal to Vref1-Vdata+Vth, and Id is 0.5K (Vref1-Vdata) 2 ; Wherein, K is the current coefficient of TD, and Id is the driving current generated by TD.

[0220] As shown in FIG11B , when at least one embodiment of the pixel circuit shown in FIG9 of the present disclosure is in operation, a display cycle may include a refresh frame, the refresh frame may include a refresh time period, and the refresh time period may include an initialization phase S1, a compensation phase S2, an interval phase Sj, a writing phase S3, and a light-emitting phase S4 that are sequentially arranged;

[0221] In the initialization phase S1, R1 provides a high voltage signal, GT1 provides a low voltage signal, GT2 provides a low voltage signal, R2 provides a high voltage signal, EM2 provides a high voltage signal, EM1 provides a low voltage signal, T1, T4 and T6 are turned on, VB provides a reference voltage Vref, I1 provides an initial voltage Vint, the potential of N3 is Vref, and the potential of N2 is Vint;

[0222] In the compensation phase S2, R1 provides a high voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a high voltage signal, T1, T2, and T3 are turned on, the potential of N1 is Vref, and the potential of N2 is Vref-Vth. This process can reduce the stress caused by the difference between the potentials of N1 and N2 in the initialization phase S1. Wherein, Vth is the threshold voltage of TD;

[0223] In the interval phase Sj, R1 provides a low voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EN2 provides a low voltage signal, EM1 provides a high voltage signal, T1 is turned off, T2 is turned on, and T3 is turned on;

[0224] In the write phase S3, R1 provides a high voltage signal, GT1 provides a low voltage signal, GT2 provides a high voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a low voltage signal, T1 and T5 are turned on, DT provides a data voltage Vdata to the first node N1, the potential of N1 is Vdata, the potential of N2 is Vref-Vth, and the potential of N3 is Vref;

[0225] In the light-emitting stage S4, R1 provides a low voltage signal, GT1 provides a low voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EM2 provides a high voltage signal, EM1 provides a high voltage signal, T3 and T4 are turned on, and TD drives O1 to emit light.

[0226] As shown in FIG11B , in the refresh frame,

[0227] The first control circuit is turned on twice, that is, T1 is turned on twice, the first time in the initialization phase S1 and the second time in the writing phase S3;

[0228] When the initialization circuit is turned on, the second control circuit is turned off, that is, when T6 is turned on, T2 is turned off.

[0229] In at least one embodiment of the pixel circuit shown in FIG9 of the present disclosure, when in operation, the refresh frame may include at least one holding period arranged after the refresh period; the holding period may include a holding initialization phase and a holding light emission phase arranged in sequence;

[0230] In the initialization stage, R2 provides a high voltage signal, T6 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0231] In the light-maintaining stage, EM1 and EM2 provide high voltage, T3 and T4 are turned on, and TD drives O1 to emit light.

[0232] In at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, when in operation, a display cycle may include at least one hold frame arranged after the refresh frame, and the hold frame may include a hold initialization phase and a hold light emission phase arranged in sequence;

[0233] In the initialization stage, R2 provides a high voltage signal, T6 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0234] In the light-maintaining stage, EM1 and EM2 provide high voltage, T3 and T4 are turned on, and TD drives O1 to emit light.

[0235] The difference between at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure is that:

[0236] At least one embodiment of the pixel circuit shown in FIG12 of the present disclosure further includes a node adjustment circuit;

[0237] The node adjustment circuit further includes a third capacitor C3;

[0238] A first end of C3 is electrically connected to the second node N2 , and a second end of C3 is electrically connected to the power supply voltage terminal VDD.

[0239] When at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure is in operation, the display cycle may include an initialization phase, a compensation phase, a writing phase, a light emitting phase, and a stress application phase;

[0240] In the initialization phase, the compensation phase, the writing phase and the light emitting phase, the reference voltage terminal VB provides a first reference voltage Vref1;

[0241] During the stress application phase, the reference voltage terminal VB provides a second reference voltage Vref2;

[0242] The first reference voltage Vref1 is different from the second reference voltage Vref2 .

[0243] In at least one embodiment of the pixel circuit shown in FIG12 of the present disclosure, by adopting the third capacitor C3, when the potential of N3 changes, the potential change amount of N1 and the potential change amount of N2 can be made different, so that the gate-source voltage of TD can be adjusted, so as to improve the hysteresis of TD during the stress application stage.

[0244] As shown in FIG13 , during operation, at least one embodiment of the pixel circuit shown in FIG12 of the present disclosure may include a refresh frame in a display cycle. The refresh frame may include a refresh period TS. The refresh period TS may include an initialization phase S1, a compensation phase S2, a writing phase S3, a stress application phase S0, and a light emitting phase S4, which are sequentially arranged.

[0245] In the initialization phase S1, R1 provides a high voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a high voltage signal, EM2 provides a high voltage signal, EM1 provides a low voltage signal, VB provides a first reference voltage Vref1, T1 is turned on, T2 is turned on, T4 is turned on, the potential of N3 and the potential of N1 are Vref1, the anode potential of O1 is Vinit, and the potential of N2 is Vinit, so that TD can be turned on when the compensation phase S2 begins; T6 is turned on, Vinit is written to the anode of O1 to clear the residual charge on the anode of O1;

[0246] In the compensation phase S2, R1 provides a high voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a high voltage signal, VB provides a first reference voltage Vref1, T1 is turned on, T2 is turned on, T3 is turned on, and the potential of N1 and the potential of N3 are Vref1;

[0247] At the beginning of compensation phase S2, TD is turned on to charge the capacitor until the potential of N2 becomes Vref1-Vth, and TD is turned off; Vth is the threshold voltage of TD;

[0248] In the write phase S3, R1 provides a high voltage signal, GT1 provides a low voltage signal, GT2 provides a high voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a low voltage signal, VB provides a first reference voltage Vref1, T1 is turned on, the potential of N3 is Vref1, T5 is turned on, DT provides a data voltage Vdata to the first node N1, the potential of N1 is Vdata, and the potential of N2 is Vref1-Vth;

[0249] In the stress application stage S0, R1 provides a high voltage signal, GT1 provides a low voltage signal, GT2 provides a low voltage signal, R2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a low voltage signal, VB provides a second reference voltage Vref2, T1 is turned on, and the potential of N3 is Vref2; at this time, the potential of N1 is Vdata+Vref2-Vref1, and the potential of N2 is Vref1-Vth+C1z×(Vref2-Vref1) / (C1z+C3z), which is used to change the gate-source voltage of TD, restore the threshold voltage of TD, and improve the hysteresis of TD; where C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0250] In the light-emitting stage S4, R1, GT1, GT2 and R2 provide low voltage signals, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light; the driving current Id is equal to 0.5K (Vdata-Vref1) 2 ; Wherein, K is the current coefficient of TD, and Id is the driving current generated by TD.

[0251] In a specific implementation, the stress application stage can be set between the writing stage and the light-emitting stage; or, the stress application stage can be set between the compensation stage and the writing stage; or, the stress application stage can be set between the initialization stage and the compensation stage; or, the stress application stage can be set before the initialization stage.

[0252] In at least one embodiment of the present disclosure, the second reference voltage Vref2 may be greater than the first reference voltage Vref1 ; or, the second reference voltage Vref2 may be less than the first reference voltage Vref1 .

[0253] As shown in FIG13 , the refresh frame further includes a holding period TK arranged after the refresh period TS;

[0254] The holding period TK may include a holding initialization phase SK1, a holding stress application phase SK2 and a holding light emitting phase SK3 which are arranged in sequence;

[0255] In the initialization phase SK1, R2 provides a high voltage signal, R1, GT1, GT2, EM1 and EM2 all provide low voltage signals, T6 is turned on, Vinit is written to the anode of O1 to clear the residual charge on the anode of O1; VB provides a first reference voltage Vref1;

[0256] In the stress application phase SK2, R1 provides a low voltage signal, R2, GT1, GT2, EM1 and EM2 all provide low voltage signals, T1 is turned on, and VB provides a second reference voltage Vref2 to the third node N3 to improve the hysteresis of TD;

[0257] In the light-maintaining stage SK3, R1, R2, GT1 and GT2 all provide low voltage signals, EM1 and EM2 both provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0258] In at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure, when in operation, a display cycle may include at least one hold frame provided after the refresh frame; the hold frame may include a hold initialization phase, a hold stress application phase, and a hold light emission phase provided in sequence;

[0259] In the initialization phase, R2 provides a high voltage signal, R1, GT1, GT2, EM1 and EM2 all provide low voltage signals, T6 is turned on, Vinit is written to the anode of O1, and the residual charge on the anode of O1 is cleared; VB provides a first reference voltage Vref1;

[0260] During the stress application phase, R1 provides a low voltage signal, R2, GT1, GT2, EM1, and EM2 all provide low voltage signals, T1 is turned on, and VB provides a second reference voltage Vref2 to the third node N3 to improve the hysteresis of TD.

[0261] In the stage of maintaining light emission, R1, R2, GT1 and GT2 all provide low voltage signals, EM1 and EM2 both provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0262] In a specific implementation, the maintenance stress application stage can be set between the maintenance initialization stage and the maintenance light emission stage; or, the maintenance stress application stage can be set before the maintenance initialization stage.

[0263] As shown in FIG14 , in operation, at least one embodiment of the pixel circuit shown in FIG12 of the present disclosure may include a refresh frame in a display cycle. The refresh frame may include a refresh period TS. The refresh period TS may include an initialization phase S1, a compensation phase S2, a writing phase S3, a stress application phase S0, and a light emitting phase S4, which are sequentially arranged.

[0264] In the initialization phase S1, R1 and R2 provide a high voltage signal, GT1 provides a low voltage signal, GT2 provides a high voltage signal, EM2 provides a high voltage signal, EM1 provides a low voltage signal, T1 is turned on, T6 is turned on, T5 is turned on, VB provides a first reference voltage Vref1 to the third node N3, DT provides a data voltage Vdata to the first node N1, the potential of N3 is Vref1, and the potential of N1 is Vdata; T4 is turned on, the potential of the anode of O1 is Vinit, so as to clear the anode of O1, and the potential of N2 is Vinit;

[0265] In the compensation phase S2, R1 provides a high voltage signal, R2 provides a low voltage signal, GT1 and GT2 both provide low voltage signals, EM2 provides a low voltage signal, EM1 provides a high voltage signal, T1 is turned on, VB provides the first reference voltage Vref1 to the third node N3, T3 is turned on,

[0266] At the beginning of compensation phase S2, TD is turned on to charge the capacitor until the potential of N2 becomes Vdata-Vth, and TD is turned off. Vth is the threshold voltage of TD.

[0267] In the write phase S3, R1 provides a high voltage signal, R2 provides a low voltage signal, GT1 provides a high voltage signal, GT2 provides a low voltage signal, EM2 provides a low voltage signal, EM1 provides a low voltage signal, T1 is turned on, T2 is turned on, and VB provides a first reference voltage Vref1 to the third node N3 and the first node N1;

[0268] In the stress application phase S0, R1 provides a high voltage signal, R2, GT1, GT2, EM2, and EM1 all provide low voltage signals, T1 is turned on, VB provides a second reference voltage Vref2 to the third node N3, the potential of N1 is Vref2, and the potential of N2 is Vdata-Vth+C1z×(Vref2-Vref1) / (C1z+C3z), changing the gate-source voltage Vgs of TD, restoring the threshold voltage of TD, and improving the hysteresis of TD; wherein C1z is the capacitance value of C1, and C3z is the capacitance value of C3;

[0269] In the light-emitting stage S4, R1, R2, GT1 and GT2 all provide low voltage signals, EM1 and EM2 both provide high voltage signals, T3 and T4 are both turned on, and TD drives O1 to emit light; the driving current Id is equal to 0.5K (Vref1-Vdata) 2 ; K is the current coefficient of TD, and Id is the driving current generated by TD.

[0270] As shown in FIG14 , the refresh frame may include a holding period TK set after the refresh period TS; the holding period TK may include a holding initialization phase SK1 , a holding stress application phase SK2 , and a holding light emitting phase SK3 set in sequence;

[0271] In the initialization phase SK1, R1 provides a low voltage signal, R2 provides a high voltage signal, GT1, GT2, EM1 and EM2 all provide low voltage signals, T6 is turned on, I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1; VB provides a first reference voltage Vref1;

[0272] In the stress application phase SK2, R1 provides a high voltage signal, R2, GT1, GT2, EM1 and EM2 all provide low voltage signals, T1 is turned on, and VB provides a second reference voltage Vref2 to the third node N3 to improve the hysteresis of TD;

[0273] In the light-maintaining stage SK3, R1, R2, GT1 and GT2 all provide low voltage signals, EM1 and EM2 both provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0274] In at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure, when in operation, a display cycle may include at least one hold frame provided after the refresh frame; the hold frame may include a hold initialization phase, a hold stress application phase, and a hold light emission phase provided in sequence;

[0275] During the initialization phase, R1 provides a low voltage signal, R2 provides a high voltage signal, GT1, GT2, EM1, and EM2 all provide low voltage signals, T6 is turned on, I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1; VB provides a first reference voltage Vref1;

[0276] During the stress application phase, R1 provides a high voltage signal, R2, GT1, GT2, EM1, and EM2 all provide low voltage signals, T1 is turned on, and VB provides a second reference voltage Vref2 to the third node N3 to improve the hysteresis of TD.

[0277] In the light-maintaining stage, R1, R2, GT1 and GT2 all provide low voltage signals, EM1 and EM2 both provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0278] In a specific implementation, the maintenance stress application stage can be set between the maintenance initialization stage and the maintenance light emission stage; or, the maintenance stress application stage can be set before the maintenance initialization stage.

[0279] The difference between at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure is that:

[0280] A first end of C3 is electrically connected to the first node N1.

[0281] When at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is in operation, the display cycle may include an initialization phase, a compensation phase, a writing phase, a light emitting phase, and a stress application phase;

[0282] In the initialization phase, the compensation phase, the writing phase and the light emitting phase, the reference voltage terminal VB provides a first reference voltage Vref1;

[0283] During the stress application phase, the reference voltage terminal VB provides a second reference voltage Vref2;

[0284] The first reference voltage Vref1 is different from the second reference voltage Vref2 .

[0285] In at least one embodiment of the pixel circuit shown in FIG15 of the present disclosure, by adopting the third capacitor C3, when the potential of N3 changes, the potential change amount of N1 and the potential change amount of N2 can be made different, so that the gate-source voltage of TD can be adjusted, so as to improve the hysteresis of TD during the stress application stage.

[0286] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0287] The driving circuit drives the light emitting element under the control of the potential of the first node;

[0288] The first control circuit provides the voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal;

[0289] The second control circuit controls the connection between the first node and the third node under the control of the first scan signal;

[0290] The display cycle may include a refresh frame, the refresh frame may include a refresh period, the refresh period may include a compensation phase; the driving method may include:

[0291] In the compensation phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the second control circuit controls the connection between the first node and the third node under the control of the first scan signal;

[0292] The pixel circuit further includes a data writing circuit; the refresh period further includes a writing phase arranged after the compensation phase; and the driving method further includes:

[0293] In the write phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the data write circuit writes the data voltage provided by the data line into the first node under the control of the second scan signal;

[0294] The pixel circuit further includes a first light emitting control circuit and a second light emitting control circuit; and the driving method further includes:

[0295] In the compensation stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal;

[0296] At the beginning of the compensation phase, the driving circuit controls the connection between the first terminal of the driving circuit and the second node under the control of the potential of the first node, thereby charging the first energy storage circuit and the second energy storage circuit, until the potential of the second node reaches Vref1-Vth, and the driving circuit is turned off; Vth is the threshold voltage of the driving transistor in the driving circuit;

[0297] The refresh period also includes an initialization phase provided before the compensation phase; the driving method includes:

[0298] In the initialization phase, the first control circuit, under the control of the first reset control signal, provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node; the second control circuit, under the control of the first scan signal, controls the connection between the first node and the third node; and the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the second node and the first electrode of the light-emitting element;

[0299] The pixel circuit further includes an initialization circuit; and the driving method further includes:

[0300] In the initialization stage, the initialization circuit writes the initial voltage into the first electrode of the light-emitting element under the control of the second reset control signal;

[0301] The refresh period also includes a light emitting phase arranged after the writing phase; the driving method includes:

[0302] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0303] In at least one embodiment of the present disclosure, the pixel circuit further includes a node adjustment circuit; the refresh period further includes a stress application phase;

[0304] The driving method includes:

[0305] In the initialization phase, the compensation phase, the writing phase and the light emitting phase, the reference voltage terminal provides a first reference voltage;

[0306] During the stress application phase, the first control circuit, under the control of the first reset control signal, provides the second reference voltage provided by the reference voltage terminal to the third node, so as to change the gate-source voltage of the driving transistor in the driving circuit and improve the hysteresis of the driving transistor; the first reference voltage is different from the second reference voltage.

[0307] In at least one embodiment of the present disclosure, the stress application stage is set before the initialization stage; or, the stress application stage is set between the initialization stage and the compensation stage; or, the stress application stage is set between the compensation stage and the writing stage; or, the stress application stage is set between the writing stage and the light-emitting stage.

[0308] In at least one embodiment of the present disclosure, the pixel circuit includes an initialization circuit; the refresh frame further includes at least one holding period set after the refresh period; the holding period includes a holding initialization phase, a holding stress application phase, and a holding light emission phase; and the driving method includes:

[0309] In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage;

[0310] During the hold stress application phase, the first control circuit, under control of the first reset control signal, provides a second reference voltage provided by a reference voltage terminal to the third node, so as to change a gate-source voltage of a driving transistor in the driving circuit and improve hysteresis of the driving transistor; the first reference voltage is different from the second reference voltage;

[0311] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0312] In at least one embodiment of the present disclosure, the pixel circuit includes an initialization circuit; the display cycle further includes at least one hold frame provided after the refresh frame; the hold frame includes a hold initialization phase, a hold stress application phase, and a hold light emission phase; and the driving method includes:

[0313] In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage;

[0314] During the hold stress application phase, the first control circuit, under control of the first reset control signal, provides a second reference voltage provided by a reference voltage terminal to the third node, so as to change a gate-source voltage of a driving transistor in the driving circuit and improve hysteresis of the driving transistor; the first reference voltage is different from the second reference voltage;

[0315] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

[0316] Optionally, the maintaining initialization stage, the maintaining stress application stage and the maintaining light-emitting stage are set successively; or, the maintaining stress application stage, the maintaining initialization stage and the maintaining light-emitting stage are set successively.

[0317] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0318] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a driving circuit, a light-emitting element, a first energy storage circuit, a second energy storage circuit, a first control circuit, and a second control circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the power supply voltage terminal, and the second terminal of the driving circuit is electrically connected to the light-emitting element via the second node; the driving circuit is configured to drive the light-emitting element under the control of the potential of the first node; The first end of the first energy storage circuit is electrically connected to the second node, the second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy; A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to the first node, and the second energy storage circuit is used to store electrical energy; The first control circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the third node respectively, and is configured to provide the voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal provided by the first reset control terminal; The second control circuit is electrically connected to the first scanning end, the first node and the third node respectively, and is used to control the connection between the first node and the third node under the control of a first scanning signal provided by the first scanning end.

2. The pixel circuit according to claim 1, wherein: In a refresh frame, the on-time of the first control circuit is greater than the on-time of the second control circuit; and when the second control circuit is turned on, the first control circuit is also turned on.

3. The pixel circuit according to claim 1, wherein: In a refresh frame, the first control circuit is turned on at least twice.

4. The pixel circuit according to claim 1, wherein: The pixel circuit further includes a node adjustment circuit; A first terminal of the node adjustment circuit is electrically connected to the second node, a second terminal of the node adjustment circuit is electrically connected to a DC voltage terminal, and the node adjustment circuit is used to adjust the potential of the second node; or, A first end of the node adjustment circuit is electrically connected to the first node, a second end of the node adjustment circuit is electrically connected to a DC voltage end, and the node adjustment circuit is used to adjust the potential of the first node.

5. The pixel circuit according to claim 1, wherein: The drive circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the first terminal of the drive circuit is electrically connected to the power supply voltage terminal through the first light-emitting control circuit, and the second node is electrically connected to the first electrode of the light-emitting element through the second light-emitting control circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the communication between the power supply voltage terminal and the first terminal of the driving circuit under the control of a first light-emitting control signal provided by the first light-emitting control terminal; The second light emitting control circuit is electrically connected to the second light emitting control terminal, the second node and the first electrode of the light emitting element respectively, and is used to control the second light emitting control element under the control of the second light emitting control signal provided by the second light emitting control terminal. The node is connected to the first electrode of the light emitting element; The second electrode of the light emitting element is electrically connected to the first voltage end.

6. The pixel circuit according to claim 1, wherein: Also included is a data writing circuit; The data writing circuit is electrically connected to the second scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the second scanning signal provided by the second scanning end.

7. The pixel circuit according to claim 6, wherein: In a refresh frame, the start time of the data writing circuit does not overlap with the start time of the second control circuit; the start time of the data writing circuit at least partially overlaps with the start time of the first control circuit.

8. The pixel circuit according to claim 5, wherein: Also included is an initialization circuit; The initialization circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

9. The pixel circuit according to claim 8, wherein: In a refresh frame, when the initialization circuit is turned on, the first light emitting control circuit is turned off.

10. The pixel circuit according to claim 8, wherein: In a refresh frame, when the initialization circuit is turned on, the second control circuit is turned off.

11. The pixel circuit according to claim 1, wherein: The first control circuit includes a first transistor, and the second control circuit includes a second transistor; The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the third node; A gate of the second transistor is electrically connected to the first scanning end, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node.

12. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the second node; The first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first node.

13. The pixel circuit according to claim 4, wherein: The node adjustment circuit includes a third capacitor; The first end of the third capacitor is electrically connected to the second node, and the second end of the third capacitor is electrically connected to the DC voltage end; or, A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to a DC voltage terminal.

14. The pixel circuit according to claim 5, wherein: The first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the first terminal of the driving circuit; The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

15. The pixel circuit according to claim 6, wherein: The data writing circuit includes a fifth transistor; A gate of the fifth transistor is electrically connected to the second scanning end, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the first node.

16. The pixel circuit according to claim 8, wherein: The initialization circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the second reset control terminal, the first electrode of the sixth transistor is electrically connected to the initial voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.

17. A driving method, applied to the pixel circuit according to any one of claims 1 to 11, the driving method comprising: The driving circuit drives the light emitting element under the control of the potential of the first node; The first control circuit provides a voltage signal provided by the reference voltage terminal to the third node under the control of the first reset control signal; The second control circuit controls the connection between the first node and the third node under the control of the first scan signal; The display cycle includes a refresh frame, the refresh frame includes a refresh period, and the refresh period includes a compensation phase; the driving method includes: In the compensation phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the second control circuit controls the connection between the first node and the third node under the control of the first scan signal; The pixel circuit further includes a data writing circuit; the refresh period further includes a writing phase arranged after the compensation phase; and the driving method further includes: In the write phase, the first control circuit provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node under the control of the first reset control signal; the data write circuit writes the data voltage provided by the data line into the first node under the control of the second scan signal; The pixel circuit further includes a first light emitting control circuit and a second light emitting control circuit; and the driving method further includes: In the compensation stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal; At the beginning of the compensation phase, the driving circuit controls the connection between the first terminal of the driving circuit and the second node under the control of the potential of the first node, thereby charging the first energy storage circuit and the second energy storage circuit, until the potential of the second node becomes Vref1-Vth, and the driving circuit is turned off; Vth is the threshold voltage of the driving transistor in the driving circuit; The refresh period also includes an initialization phase provided before the compensation phase; the driving method includes: In the initialization phase, the first control circuit, under the control of the first reset control signal, provides the first reference voltage Vref1 provided by the reference voltage terminal to the third node; the second control circuit, under the control of the first scan signal, controls the connection between the first node and the third node; and the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the second node and the first electrode of the light-emitting element; The pixel circuit further includes an initialization circuit; and the driving method further includes: In the initialization stage, the initialization circuit writes the initial voltage into the first electrode of the light-emitting element under the control of the second reset control signal; The refresh period also includes a light emitting phase arranged after the writing phase; the driving method includes: In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

18. The driving method according to claim 17, wherein: The pixel circuit further includes a node adjustment circuit; the refresh period further includes a stress application phase; The driving method includes: During the initialization phase, the compensation phase, the writing phase, and the light-emitting phase, the reference voltage terminal provides a first reference voltage; During the stress application phase, the first control circuit provides a second reference voltage provided by a reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage.

19. The driving method according to claim 18, wherein: The stress application stage is set before the initialization stage; or, the stress application stage is set between the initialization stage and the compensation stage; or, the stress application stage is set between the compensation stage and the writing stage; or, the stress application stage is set between the writing stage and the light-emitting stage.

20. The driving method according to claim 18, wherein: The pixel circuit includes an initialization circuit; the refresh frame also includes at least one holding period set after the refresh period; the holding period includes a holding initialization phase, a holding stress application phase, and a holding light emission phase; the driving method includes: In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage; During the hold stress application phase, the first control circuit provides a second reference voltage provided by the reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage; In the light-maintaining stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first electrode of the light-emitting element under the control of the second light-emitting control signal. The light emitting element is driven.

21. The driving method according to claim 18, wherein: The pixel circuit includes an initialization circuit; the display cycle also includes at least one hold frame set after the refresh frame; the hold frame includes a hold initialization phase, a hold stress application phase, and a hold light emission phase; the driving method includes: In the initialization holding phase, the initialization circuit writes the initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; the reference voltage terminal provides a first reference voltage; During the hold stress application phase, the first control circuit provides a second reference voltage provided by the reference voltage terminal to the third node under the control of the first reset control signal; the first reference voltage is different from the second reference voltage; In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting element under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element.

22. A display device comprising the pixel circuit according to any one of claims 1 to 17.

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