Shift register and driving method, and gate drive circuit and display apparatus

Abstract

A shift register and a driving method, and a gate drive circuit and a display apparatus. The shift register may comprise: an input sub-circuit and an output sub-circuit. The input sub-circuit is electrically connected to each of a first node, a clock signal end and an input signal group, and is configured to provide a signal to the first node under the control of signals from the clock signal end and the input signal group; and the output sub-circuit is electrically connected to each of the first node, a power supply signal group and an output signal group, and is configured to provide a signal to the output signal group under the control of signals from the first node and the power supply signal group, wherein the input signal group comprises at least one input signal end, the power supply signal group comprises at least one power supply signal end, and the output signal group comprises at least one output signal end.

Description

Shift register and driving method, gate driving circuit and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, display technology, and in particular to a shift register and driving method, a gate driving circuit, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] SUMMARY OF THE INVENTION

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: an input sub-circuit and an output sub-circuit;

[0006] The input sub-circuit is electrically connected to the first node, the clock signal terminal and the input signal group, respectively, and is configured to provide a signal to the first node under the control of the signals of the clock signal terminal and the input signal group;

[0007] The output sub-circuit is electrically connected to the first node, the power signal group and the output signal group, respectively, and is configured to provide a signal to the output signal group under the control of the signals of the first node and the power signal group;

[0008] The input signal group includes: at least one input signal terminal, the power signal group includes: at least one power signal terminal, and the output signal group includes: at least one output signal terminal;

[0009] The at least one input signal terminal includes: a first signal input terminal; the input sub-circuit is configured to provide a signal of the first signal input terminal to the first node under the control of a signal of the clock signal terminal;

[0010] The input subcircuit includes: a first transistor; a control electrode of the first transistor is electrically connected to the clock signal terminal, a first electrode of the first transistor is electrically connected to the first signal input terminal, and a second electrode of the first transistor is electrically connected to the first node.

[0011] In some possible implementations, the at least one input signal terminal further includes: a second signal input terminal and a first control signal terminal;

[0012] The input sub-circuit is further configured to provide a signal from the first signal input terminal or the second signal input terminal to the first node under the control of the signals from the clock signal terminal and the first control signal terminal.

[0013] In some possible implementations, the input subcircuit further includes: a second transistor and a third transistor, wherein the first electrode of the first transistor is electrically connected to the first signal input terminal via the second transistor;

[0014] The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;

[0015] The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the first signal input terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0016] The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second signal input terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0017] In some possible implementations, the first transistor is an N-type transistor, one of the second transistor and the third transistor is a P-type transistor, and the other is an N-type transistor.

[0018] In some possible implementations, the at least one input signal terminal further includes: a second signal input terminal, a first control signal terminal, and a second control signal terminal;

[0019] The input sub-circuit is further configured to provide a signal from the first signal input terminal or the second signal input terminal to the first node under the control of signals from the clock signal terminal, the first control signal terminal and the second control signal terminal.

[0020] In some possible implementations, the input subcircuit further includes: a second transistor and a third transistor, wherein the first electrode of the first transistor is electrically connected to the first signal input terminal via the second transistor;

[0021] The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;

[0022] The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the first signal input terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0023] The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the second signal input terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0024] In some possible implementations, the first transistor is an N-type transistor, and the second transistor and the third transistor are both N-type transistors or P-type transistors.

[0025] In some possible implementations, the voltage value of the signal at the first control signal terminal is constant, the voltage value of the signal at the second control signal terminal is constant, and the time when the signal at the first control signal terminal is a valid level signal does not overlap with the time when the signal at the second control signal terminal is a valid level signal.

[0026] In some possible implementations, the shift register is provided on a display substrate, and the display substrate includes: a first scanning mode and a second scanning mode;

[0027] In the first scanning mode, the signal at the first control signal end is a valid level signal, and the signal at the second control signal end is an invalid level signal. In the second scanning mode, the signal at the first control signal end is an invalid level signal, and the signal at the second control signal end is a valid level signal.

[0028] In some possible implementations, the at least one power signal terminal includes: a first power terminal and a second power terminal, and the at least one output signal terminal includes: a signal output terminal;

[0029] The output sub-circuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of a signal of the first node.

[0030] In some possible implementations, the output subcircuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor;

[0031] The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the signal output terminal;

[0032] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;

[0033] The control electrode of the sixth transistor is electrically connected to the second power supply terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the third node;

[0034] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the signal output terminal;

[0035] The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the signal output terminal.

[0036] In some possible implementations, the fourth transistor is an N-type transistor, and the fifth transistor and the sixth transistor are P-type transistors.

[0037] In some possible implementations, the first power supply terminal continuously provides a high-level signal, and the second power supply terminal continuously provides a low-level signal.

[0038] In some possible implementations, the at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal, and a fourth power terminal; and the at least one output signal terminal includes: a signal output terminal and a cascade output terminal;

[0039] The output subcircuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal and provide a signal of the first power supply terminal or the third power supply terminal to the cascade output terminal under the control of a signal of the first node.

[0040] In some possible implementations, the output sub-circuit includes: seventh to sixteenth transistors, a third capacitor, and a fourth capacitor;

[0041] The control electrode of the seventh transistor is electrically connected to the first power supply terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the fourth node;

[0042] a control electrode of the eighth transistor electrically connected to the fourth node, a first electrode of the eighth transistor electrically connected to the first power supply terminal, and a second electrode of the eighth transistor electrically connected to the cascade output terminal;

[0043] a control electrode of the ninth transistor electrically connected to the third node, a first electrode of the ninth transistor electrically connected to the cascade output terminal, and a second electrode of the ninth transistor electrically connected to the fifth node;

[0044] a control electrode of the tenth transistor electrically connected to the third node, a first electrode of the tenth transistor electrically connected to the fifth node, and a second electrode of the tenth transistor electrically connected to the fourth power supply terminal;

[0045] a control electrode of the eleventh transistor electrically connected to the fourth power supply terminal, a first electrode of the eleventh transistor electrically connected to the first node, and a second electrode of the eleventh transistor electrically connected to the third node;

[0046] A control electrode of the twelfth transistor is electrically connected to the cascade output terminal, a first electrode of the twelfth transistor is electrically connected to the fifth node, and a second electrode of the twelfth transistor is electrically connected to the third power supply terminal;

[0047] a control electrode of the thirteenth transistor electrically connected to the fourth node, a first electrode of the thirteenth transistor electrically connected to the first power supply terminal, and a second electrode of the thirteenth transistor electrically connected to the signal output terminal;

[0048] a control electrode of the fourteenth transistor electrically connected to the third node, a first electrode of the fourteenth transistor electrically connected to the signal output terminal, and a second electrode of the fourteenth transistor electrically connected to the sixth node;

[0049] a control electrode of the fifteenth transistor electrically connected to the third node, a first electrode of the fifteenth transistor electrically connected to the sixth node, and a second electrode of the fifteenth transistor electrically connected to the second power supply terminal;

[0050] A control electrode of the sixteenth transistor is connected to the signal output terminal, a first electrode of the sixteenth transistor is electrically connected to the sixth node, and a second electrode of the sixteenth transistor is electrically connected to the third power supply terminal;

[0051] The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the signal output terminal;

[0052] The fourth capacitor includes a first plate and a second plate. The first plate of the fourth capacitor is electrically connected to the third node, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal.

[0053] In some possible implementations, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the sixteenth transistor are N-type transistors, and the ninth to eleventh transistors, the fourteenth transistor, and the fifteenth transistor are P-type transistors.

[0054] In some possible implementations, the first power supply terminal and the third power supply terminal continuously provide high-level signals, and the second power supply terminal and the fourth power supply terminal continuously provide low-level signals;

[0055] The voltage value of the first power supply terminal is less than or equal to the voltage value of the third power supply terminal, and the voltage value of the fourth power supply terminal is greater than the voltage value of the second power supply terminal.

[0056] In some possible implementations, the at least one power signal terminal includes: a first power terminal, a second power terminal, and a third power terminal, and the at least one output signal terminal includes: a signal output terminal;

[0057] The output sub-circuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of a signal of the first node.

[0058] In some possible implementations, the output sub-circuit includes: a seventeenth transistor to a twenty-first transistor and a first capacitor;

[0059] The control electrode of the seventeenth transistor is electrically connected to the first node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the signal output terminal;

[0060] The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the fifth node;

[0061] a control electrode of the nineteenth transistor electrically connected to the third node, a first electrode of the nineteenth transistor electrically connected to the fifth node, and a second electrode of the nineteenth transistor electrically connected to the second power supply terminal;

[0062] The control electrode of the twentieth transistor is electrically connected to the second power supply terminal, the first electrode of the twentieth transistor is electrically connected to the first node, and the second electrode of the twentieth transistor is electrically connected to the third node;

[0063] A control electrode of the twenty-first transistor is electrically connected to the signal output terminal, a first electrode of the twenty-first transistor is electrically connected to the fifth node, and a second electrode of the twenty-first transistor is electrically connected to the third power supply terminal;

[0064] The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the signal output end.

[0065] In some possible implementations, the seventeenth transistor and the twenty-first transistor are N-type transistors, and the eighteenth to twentieth transistors are P-type transistors.

[0066] In some possible implementations, the first power supply terminal and the third power supply terminal continuously provide a high-level signal, and the second power supply terminal continuously provides a low-level signal;

[0067] The voltage value of the first power supply terminal is less than or equal to the voltage value of the third power supply terminal.

[0068] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, comprising: a plurality of cascaded shift registers as described in any one of the first aspects.

[0069] In some possible implementations, the at least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, and the at least one output signal terminal of the at least one stage shift register includes: a signal output terminal;

[0070] The signal output terminal of the i-th stage shift register is electrically connected to the first signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

[0071] In some possible implementations, at least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, and at least one output signal terminal of the at least one stage shift register includes: a signal output terminal and a cascade output terminal;

[0072] The cascade output terminal of the i-th stage shift register is electrically connected to the first signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

[0073] In some possible implementations, at least one input signal terminal of the at least one stage shift register includes: a first signal input terminal and a second signal input terminal, and at least one output signal terminal of the at least one stage shift register includes: a signal output terminal;

[0074] The signal output end of the i-th stage shift register is electrically connected to the first signal input end of the i+1-th stage shift register, and the signal output end of the i+1-th stage shift register is electrically connected to the second signal input end of the i-th stage shift register, 1≤i≤M-1, M is the total number of shift registers.

[0075] In some possible implementations, at least one input signal terminal of the at least one stage shift register includes: a first signal input terminal and a second signal input terminal, and at least one output signal terminal of the at least one stage shift register includes: a signal output terminal and a cascade output terminal;

[0076] The cascade output end of the i-th stage shift register is electrically connected to the first signal input end of the i+1-th stage shift register, and the cascade output end of the i+1-th stage shift register is electrically connected to the second signal input end of the i-th stage shift register, 1≤i≤M-1, M is the total number of shift registers.

[0077] In a third aspect, an embodiment of the present disclosure provides a display device, comprising: a gate driving circuit as described in any one of the second aspects.

[0078] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first high-level power line, and a first low-level power line;

[0079] At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal;

[0080] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, and the second power supply terminal is electrically connected to the first low-level power supply line; the first signal input terminal of the first shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of shift registers.

[0081] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high-level power line, and a first low-level power line;

[0082] At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal;

[0083] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, and the first control signal terminal is electrically connected to the first scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0084] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high-level power line, and a first low-level power line;

[0085] At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal;

[0086] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the first control signal terminal is electrically connected to the first scanning signal line, and the second control signal terminal is electrically connected to the second scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0087] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first high-level power line, a first low-level power line, a second high-level power line, and a second low-level power line;

[0088] At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal;

[0089] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, and the fourth power supply terminal is electrically connected to the second low-level power supply line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0090] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high-level power line, a first low-level power line, a second high-level power line, and a second low-level power line;

[0091] At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal;

[0092] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the fourth power supply terminal is electrically connected to the second low-level power supply line, and the first control signal terminal is electrically connected to the first scan signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0093] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high-level power line, a first low-level power line, a second high-level power line, and a second low-level power line;

[0094] At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal;

[0095] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the fourth power supply terminal is electrically connected to the second low-level power supply line, the first control signal terminal is electrically connected to the first scanning signal line, and the second control signal terminal is electrically connected to the second scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0096] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first high-level power line, a first low-level power line, and a second high-level power line;

[0097] At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal;

[0098] The first power supply terminal of at least one stage of the shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, and the third power supply terminal is electrically connected to the second high-level power supply line; the first signal input terminal of the first stage of the shift register in the gate drive circuit is electrically connected to the initial signal line, the clock signal terminal of the j-th stage of the shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage of the shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0099] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high-level power line, a first low-level power line, and a second high-level power line;

[0100] At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal;

[0101] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, and the first control signal terminal is electrically connected to the first scan signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0102] In some possible implementations, the system further includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high-level power line, a first low-level power line, and a second high-level power line;

[0103] At least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal;

[0104] The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the first control signal terminal is electrically connected to the first scanning signal line, and the second control signal terminal is electrically connected to the second scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0105] In a fourth aspect, an embodiment of the present disclosure provides a method for driving a shift register, configured to drive the shift register according to any one of the first aspects, the method comprising:

[0106] The input sub-circuit provides a signal to the first node under the control of the clock signal terminal and the signal of the input signal group;

[0107] The output sub-circuit provides a signal to the output signal group under the control of the signal of the first node and the power signal group.

[0108] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0109] Summary of the Figures

[0110] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0111] FIG1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0112] FIG2 is an equivalent circuit diagram of an input subcircuit provided by an exemplary embodiment;

[0113] FIG3A is an equivalent circuit diagram of an input subcircuit provided by an exemplary embodiment;

[0114] FIG3B is an equivalent circuit diagram of an input subcircuit provided by an exemplary embodiment;

[0115] FIG4A is an equivalent circuit diagram of an input subcircuit provided by an exemplary embodiment;

[0116] FIG4B is an equivalent circuit diagram of an input subcircuit provided by an exemplary embodiment;

[0117] FIG5 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment;

[0118] FIG6 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment;

[0119] FIG7 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment;

[0120] FIG8 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0121] FIG9 is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0122] FIG10A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0123] FIG10B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0124] FIG11A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0125] FIG11B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0126] FIG12A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0127] FIG12B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0128] FIG13A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0129] FIG13B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0130] FIG14 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0131] FIG15 is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0132] FIG16A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0133] FIG16B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0134] FIG17A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0135] FIG17B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0136] FIG18A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0137] FIG18B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0138] FIG19A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0139] FIG19B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0140] FIG20 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0141] FIG21 is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0142] FIG22A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0143] FIG22B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0144] FIG23A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0145] FIG23B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0146] FIG24A is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0147] FIG24B is an equivalent circuit diagram of a shift register provided by an exemplary embodiment;

[0148] FIG25A is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0149] FIG25B is an operation timing diagram of a shift register provided by an exemplary embodiment;

[0150] FIG26 is a structural circuit diagram of a gate driving circuit provided by an exemplary embodiment;

[0151] FIG27 is a structural circuit diagram of a gate driving circuit provided by an exemplary embodiment;

[0152] FIG28 is a structural circuit diagram of a gate driving circuit provided by an exemplary embodiment;

[0153] FIG29 is a structural circuit diagram of a gate driving circuit provided by an exemplary embodiment;

[0154] FIG30 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0155] FIG31 is a schematic diagram of a single pulse output provided by an embodiment of the present disclosure;

[0156] FIG32 is a schematic diagram of a pulse output according to an embodiment of the present disclosure;

[0157] FIG33 is a multi-stage output timing diagram provided by an embodiment of the present disclosure;

[0158] FIG34 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0159] FIG35 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0160] FIG36 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0161] FIG37 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0162] FIG38 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0163] FIG39 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0164] FIG40 is a structural circuit diagram of a display device provided by an exemplary embodiment;

[0165] FIG41 is a structural circuit diagram of a display device provided by an exemplary embodiment.

[0166] Details

[0167] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0168] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0169] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0170] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0171] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0172] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0173] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0174] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0175] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0176] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0177] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0178] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0179] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0180] OLED display substrates include pixel circuits, light-emitting elements, and gate drive circuits. The gate drive circuits provide gate signals to the pixel circuits, driving the light-emitting elements to emit light. However, the gate drive circuits have a relatively simple output method and are unable to meet display requirements.

[0181] FIG1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure. As shown in FIG1 , the shift register provided by an embodiment of the present disclosure may include: an input sub-circuit and an output sub-circuit.

[0182] The input sub-circuit is electrically connected to the first node N1 , the clock signal terminal CLK and the input signal group IN, and is configured to provide a signal to the first node N1 under the control of the signals of the clock signal terminal CLK and the input signal group IN.

[0183] The output sub-circuit is electrically connected to the first node N1, the power signal group Vn and the output signal group Sn, respectively, and is configured to provide a signal to the output signal group Sn under the control of the signals of the first node N1 and the power signal group Vn.

[0184] The input signal group may include at least one input signal terminal, the power signal group may include at least one power signal terminal, and the output signal group may include at least one output signal terminal.

[0185] In an exemplary embodiment, the signal at the clock signal terminal CLK may be a periodic pulse signal.

[0186] In the shift register provided by the embodiment of the present disclosure, the input sub-circuit can provide a signal to the first node under the control of the signal of the clock signal terminal and at least one input signal terminal, and the output sub-circuit can provide a signal to the output signal group under the control of the signal of the first node and at least one power signal terminal, thereby realizing the output of the shift register.

[0187] In an exemplary embodiment of the present disclosure, at least one input signal terminal may be an initial signal terminal, which may be connected to an external start signal. The pulse width of the start signal may determine the pulse width output by the shift register, thereby achieving adjustable output pulse width of the shift register.

[0188] In an exemplary embodiment of the present disclosure, the at least one input signal terminal may include: a first signal input terminal; and the input sub-circuit is configured to provide a signal of the first signal input terminal to the first node under the control of a signal of a clock signal terminal.

[0189] FIG2 is an equivalent circuit diagram of an input sub-circuit provided by an exemplary embodiment. As shown in FIG2 , in an exemplary embodiment, the input sub-circuit may include: a first transistor M1 .

[0190] In an exemplary embodiment, as shown in FIG2 , the control electrode of the first transistor is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor is electrically connected to the first signal input terminal IN1 , and the second electrode of the first transistor is electrically connected to the first node N1 .

[0191] An exemplary structure of the input sub-circuit is shown in Figure 2. Those skilled in the art will readily appreciate that the implementation of the input sub-circuit is not limited thereto.

[0192] In an example embodiment of the present disclosure, at least one input signal terminal may include: a first signal input terminal, a second signal input terminal and a first control signal terminal; the input subcircuit is configured to provide a signal of the first signal input terminal or the second signal input terminal to the first node under the control of a signal of the clock signal terminal and the first control signal terminal.

[0193] Figure 3A is an equivalent circuit diagram of an input subcircuit provided in accordance with an exemplary embodiment, and Figure 3B is an equivalent circuit diagram of an input subcircuit provided in accordance with an exemplary embodiment. As shown in Figures 3A and 3B , in one exemplary embodiment, the input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3. The first electrode of the first transistor M1 is electrically connected to the first signal input terminal IN1 via the second transistor M2.

[0194] In an exemplary embodiment, as shown in Figures 3A and 3B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the first control signal terminal CK1, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2.

[0195] In an exemplary embodiment, the first transistor M1 is an N-type transistor, and one of the second transistor M2 and the third transistor M3 is a P-type transistor, and the other is an N-type transistor.

[0196] In an exemplary embodiment, as shown in FIG3A , the second transistor M2 is a P-type transistor, and the third transistor M3 is an N-type transistor.

[0197] In an exemplary embodiment, as shown in FIG3B , the second transistor M2 is an N-type transistor, and the third transistor M3 is a P-type transistor.

[0198] 3A and 3B show an exemplary structure of the input sub-circuit. It will be readily understood by those skilled in the art that the implementation of the input sub-circuit is not limited thereto.

[0199] In an example embodiment of the present disclosure, at least one input signal terminal may include: a first signal input terminal, a second signal input terminal, a first control signal terminal, and a second control signal terminal; the input subcircuit is configured to provide a signal from the first signal input terminal or the second signal input terminal to the first node under the control of signals from the clock signal terminal, the first control signal terminal, and the second control signal terminal.

[0200] In an exemplary embodiment, the voltage value of the signal at the first control signal terminal is constant, the voltage value of the signal at the second control signal terminal is constant, and the time when the signal at the first control signal terminal is a valid level signal does not overlap with the time when the signal at the second control signal terminal is a valid level signal.

[0201] In an exemplary embodiment, the shift register is arranged on a display substrate, and the display substrate may include: a first scanning mode and a second scanning mode; in the first scanning mode, the signal at the first control signal end is a valid level signal, and the signal at the second control signal end is an invalid level signal; in the second scanning mode, the signal at the first control signal end is an invalid level signal, and the signal at the second control signal end is a valid level signal.

[0202] In an exemplary embodiment, the first scanning mode may be a forward scanning mode, and the second scanning mode may be a reverse scanning mode.

[0203] Figure 4A is an equivalent circuit diagram of an input subcircuit provided in an exemplary embodiment, and Figure 4B is an equivalent circuit diagram of an input subcircuit provided in an exemplary embodiment. As shown in Figures 4A and 4B, in an exemplary embodiment, the input subcircuit may include: a first transistor M1, a second transistor M2, and a third transistor M3. The first electrode of the first transistor M1 is electrically connected to the first signal input terminal IN1 through the second transistor M2.

[0204] In an exemplary embodiment, as shown in Figures 4A and 4B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the second control signal terminal CK2, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2.

[0205] In an exemplary embodiment, the second transistor M2 and the third transistor M3 are of the same transistor type.

[0206] In an exemplary embodiment, as shown in FIG4A , the first transistor M1 is an N-type transistor, and the second transistor M2 and the third transistor M3 are both N-type transistors.

[0207] In an exemplary embodiment, as shown in FIG4B , the first transistor M1 is an N-type transistor, and the second transistor M2 and the third transistor M3 are both P-type transistors.

[0208] An exemplary structure of the input sub-circuit is shown in Figures 4A and 4B. It will be readily understood by those skilled in the art that the implementation of the input sub-circuit is not limited thereto.

[0209] In an exemplary embodiment of the present disclosure, at least one power signal terminal may include: a first power terminal and a second power terminal, and at least one output signal terminal may include: a signal output terminal; the output subcircuit is configured to provide a signal of the first power terminal or the second power terminal to the signal output terminal under the control of a signal of a first node.

[0210] In an exemplary embodiment, the first power supply terminal continuously provides a high-level signal, and the second power supply terminal continuously provides a low-level signal.

[0211] FIG5 is an equivalent circuit diagram of an output subcircuit provided by an exemplary embodiment. As shown in FIG5 , in an exemplary embodiment, the output subcircuit may include: a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a first capacitor C1 , and a second capacitor C2 .

[0212] In an exemplary embodiment, as shown in FIG5 , a control electrode of the fourth transistor M4 is electrically connected to the first node N1, a first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1, and a second electrode of the fourth transistor M4 is electrically connected to the signal output terminal OUT; a control electrode of the fifth transistor M5 is electrically connected to the third node N3, a first electrode of the fifth transistor M5 is electrically connected to the second power supply terminal V2, and a second electrode of the fifth transistor M5 is electrically connected to the signal output terminal OUT; a control electrode of the sixth transistor M6 is electrically connected to the second power supply terminal VHL1, a first electrode of the sixth transistor M6 is electrically connected to the first node N1, and a second electrode of the sixth transistor M6 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the signal output terminal OUT.

[0213] In an exemplary embodiment, the fourth transistor M4 is an N-type transistor, and the fifth transistor M5 and the sixth transistor M6 are P-type transistors.

[0214] An exemplary structure of the output sub-circuit is shown in Figure 5. Those skilled in the art will readily appreciate that the implementation of the output sub-circuit is not limited thereto.

[0215] In an example embodiment of the present disclosure, at least one power signal terminal may include: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal, and at least one output signal terminal may include: a signal output terminal and a cascade output terminal; the output sub-circuit is configured to provide a signal of the first power terminal or the second power terminal to the signal output terminal, and provide a signal of the first power terminal or the third power terminal to the cascade output terminal under the control of a signal of the first node.

[0216] In an exemplary embodiment, the first power terminal and the third power terminal continuously provide high-level signals, and the second power terminal and the fourth power terminal continuously provide low-level signals.

[0217] In an exemplary embodiment, the voltage value of the first power terminal is less than or equal to the voltage value of the third power terminal, and the voltage value of the fourth power terminal is greater than the voltage value of the second power terminal.

[0218] FIG6 is an equivalent circuit diagram of an output subcircuit provided by an exemplary embodiment. As shown in FIG6 , in an exemplary embodiment, the output subcircuit may include: a seventh transistor M7 to a sixteenth transistor M16, a third capacitor C3 and a fourth capacitor C4.

[0219] In an exemplary embodiment, as shown in FIG6 , a control electrode of the seventh transistor M7 is electrically connected to the first power supply terminal V1, a first electrode of the seventh transistor M7 is electrically connected to the first node N1, and a second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; a control electrode of the eighth transistor M8 is electrically connected to the fourth node N4, a first electrode of the eighth transistor M8 is electrically connected to the first power supply terminal V1, and a second electrode of the eighth transistor M8 is electrically connected to the cascade output terminal CR; a control electrode of the ninth transistor M9 is electrically connected to the third node N3, a first electrode of the ninth transistor M9 is electrically connected to the cascade output terminal CR, and a second electrode of the ninth transistor M9 is electrically connected to the fifth node N5; a control electrode of the tenth transistor M10 is electrically connected to the third node N3, a first electrode of the tenth transistor M10 is electrically connected to the fifth node N5, and a second electrode of the tenth transistor M10 is electrically connected to the fourth power supply terminal V4; a control electrode of the eleventh transistor M11 is electrically connected to the fourth power supply terminal V4, A first electrode of the eleventh transistor M11 is electrically connected to the first node N1, and a second electrode of the eleventh transistor M11 is electrically connected to the third node N3; a control electrode of the twelfth transistor M12 is electrically connected to the cascade output terminal CR, a first electrode of the twelfth transistor M12 is electrically connected to the fifth node N5, and a second electrode of the twelfth transistor M12 is electrically connected to the third power supply terminal V3; a control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, a first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal V1, and a second electrode of the thirteenth transistor M13 is electrically connected to the signal output terminal OUT; a control electrode of the fourteenth transistor M14 is electrically connected to the third node N3, a first electrode of the fourteenth transistor M14 is electrically connected to the signal output terminal OUT, and a second electrode of the fourteenth transistor M14 is electrically connected to the sixth node N6; a fifteenth transistor M15 is electrically connected to the cascade output terminal CR, a first electrode of the twelfth transistor M12 is electrically connected to the fifth node N5, and a second electrode of the twelfth transistor M12 is electrically connected to the third power supply terminal V3; a control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, a first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal V1, and a second electrode of the thirteenth transistor M13 is electrically connected to the signal output terminal OUT; The control electrode of the fifteenth transistor M15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor M15 is electrically connected to the sixth node N6, and the second electrode of the fifteenth transistor M15 is electrically connected to the second power supply terminal V2; the control electrode of the sixteenth transistor M16 is connected to the signal output terminal OUT, the first electrode of the sixteenth transistor M16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor M16 is electrically connected to the third power supply terminal V3; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the fourth node N4, and the second plate C32 of the third capacitor is electrically connected to the signal output terminal OUT; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected to the third node N3, and the second plate C42 of the fourth capacitor is electrically connected to the cascade output terminal CR.

[0220] In an exemplary embodiment, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13 and the sixteenth transistor M16 are N-type transistors, and the ninth transistor M9 to the eleventh transistor M11, the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

[0221] An exemplary structure of the output sub-circuit is shown in Figure 6. Those skilled in the art will readily appreciate that the implementation of the output sub-circuit is not limited thereto.

[0222] In an example embodiment of the present disclosure, at least one power signal terminal may include: a first power terminal, a second power terminal and a third power terminal, and at least one output signal terminal may include: a signal output terminal; the output sub-circuit is configured to provide a signal of the first power terminal or the second power terminal to the signal output terminal under the control of a signal of a first node.

[0223] FIG7 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment. As shown in FIG7 , in an exemplary embodiment, the output sub-circuit may include: a seventeenth transistor M17 to a twenty-first transistor M21 and a first capacitor C1.

[0224] In an exemplary embodiment, as shown in FIG7 , the control electrode of the seventeenth transistor M17 is electrically connected to the first node N1, the first electrode of the seventeenth transistor M17 is electrically connected to the first power supply terminal V1, and the second electrode of the seventeenth transistor M17 is electrically connected to the signal output terminal OUT; the control electrode of the eighteenth transistor M18 is electrically connected to the third node N3, the first electrode of the eighteenth transistor M18 is electrically connected to the signal output terminal OUT, and the second electrode of the eighteenth transistor M18 is electrically connected to the fifth node N5; the control electrode of the nineteenth transistor M19 is electrically connected to the third node N3, the first electrode of the nineteenth transistor M19 is electrically connected to the fifth node N5, and the second electrode of the nineteenth transistor M19 is electrically connected to the second node N3. The source terminal V2 is electrically connected; the control electrode of the twentieth transistor M20 is electrically connected to the second power supply terminal V2, the first electrode of the twentieth transistor M20 is electrically connected to the first node N1, and the second electrode of the twentieth transistor M20 is electrically connected to the third node N3; the control electrode of the twenty-first transistor M21 is electrically connected to the signal output terminal OUT, the first electrode of the twenty-first transistor M21 is electrically connected to the fifth node N5, and the second electrode of the twenty-first transistor M21 is electrically connected to the third power supply terminal V3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT.

[0225] An exemplary structure of the output sub-circuit is shown in Figure 7. Those skilled in the art will readily appreciate that the implementation of the output sub-circuit is not limited thereto.

[0226] Figure 8 is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figure 8 , in one exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, and the output subcircuit may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0227] In an exemplary embodiment, as shown in FIG8 , the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the first signal input terminal IN1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the fourth transistor M4 is electrically connected to the first node N1, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor M4 is electrically connected to the signal output terminal OUT; the control electrode of the fifth transistor M5 is electrically connected to the third node N3, the first electrode of the fifth transistor M5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor M5 is electrically connected to the signal output terminal OUT. The control electrode of the sixth transistor M6 is electrically connected to the second power supply terminal V2, the first electrode of the sixth transistor M6 is electrically connected to the first node N1, and the second electrode of the sixth transistor M6 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the signal output terminal OUT.

[0228] In an exemplary embodiment, the first transistor M1 and the fourth transistor M4 are N-type transistors, and the fifth transistor M5 and the sixth transistor M6 are P-type transistors.

[0229] An exemplary structure of a shift register is shown in Figure 8. Those skilled in the art will readily appreciate that the implementation of the shift register is not limited thereto.

[0230] FIG9 is an operation timing diagram of a shift register provided by an exemplary embodiment. The exemplary embodiment of the present disclosure is described below through the operation process of the shift register illustrated in FIG8 .

[0231] In an exemplary embodiment, as shown in FIG9 , the operation process of the shift register may include:

[0232] Phase P1: The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low-level signal to a high-level signal), the first transistor M1 turns on, and the voltage at the first node N1 reaches the high-level signal at the first signal input terminal IN1. At this point, the fourth transistor M4 turns on, the fifth transistor M5 turns off, and the signal output terminal OUT outputs a high-level signal at the first power supply terminal V1.

[0233] Phase P2: The signal at the first signal input terminal IN1 transitions to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal), the first transistor M1 turns on, and the voltage at the first node N1 reaches the low-level signal of the first signal input terminal IN1. The voltage at the third node N3 also reaches the low-level signal of the first signal input terminal IN1. At this point, the fourth transistor M4 turns off, the fifth transistor M5 turns on, and the signal output terminal OUT outputs a low-level signal from the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2 and the isolation effect of the sixth transistor M6, the voltage at the third node N3 is lower than the voltage at the first node N1. The fifth transistor M5 turns on in the linear region, allowing the signal output terminal OUT to quickly pull down from a high-level signal to a low-level signal.

[0234] Phase P3: When the signal at the first signal input terminal IN1 transitions to a high-level signal again, and the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low-level signal to a high-level signal), phase P1 repeats. Due to the bootstrap effect of the first capacitor C1, the voltage at the first node N1 is raised, and the fourth transistor M4 remains in the linear region, allowing the signal output terminal OUT to quickly rise from a low-level signal to a high-level signal.

[0235] Figure 10A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 10B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 10A and 10B, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3, and the output subcircuit may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0236] In an exemplary embodiment, as shown in Figures 10A and 10B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the first control signal terminal CK1, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2; the control electrode of the fourth transistor M4 is electrically connected to the first node N1, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1. a control electrode of the fifth transistor M5 is electrically connected to the third node N3, a first electrode of the fifth transistor M5 is electrically connected to the second power supply terminal V2, and a second electrode of the fifth transistor M5 is electrically connected to the signal output terminal OUT; a control electrode of the sixth transistor M6 is electrically connected to the second power supply terminal V2, a first electrode of the sixth transistor M6 is electrically connected to the first node N1, and a second electrode of the sixth transistor M6 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the signal output terminal OUT.

[0237] In an exemplary embodiment, the first transistor M1 and the fourth transistor M4 are N-type transistors, and the fifth transistor M5 and the sixth transistor M6 are P-type transistors.

[0238] In an exemplary embodiment, as shown in FIG10A , the second transistor M2 is a P-type transistor, the third transistor M3 is an N-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant negative voltage, and during reverse scanning, the first control signal terminal CK1 is a constant positive voltage.

[0239] In an exemplary embodiment, as shown in FIG10B , the second transistor M2 is an N-type transistor, the third transistor M3 is a P-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant positive voltage, and during reverse scanning, the first control signal terminal CK1 is a constant negative voltage.

[0240] An exemplary structure of a shift register is shown in Figures 10A and 10B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0241] FIG11A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG11B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation process of the shift register illustrated in FIG10A . The operation process of the shift register illustrated in FIG10B is similar in principle to that of the shift register illustrated in FIG10A , and will not be further described herein.

[0242] In an exemplary embodiment, as shown in FIG11A , the operation process of the shift register may include:

[0243] Phase P11 is called the forward scan phase: During the forward scan, the first control signal terminal CK1 maintains a constant negative voltage, the second transistor M2 turns on, the third transistor M3 turns off, and the voltage at the second node N2 equals the signal at the first signal input terminal IN1. The signal at the first signal input terminal IN1 is a high-level signal. When the clock signal terminal CLK reaches a rising edge—that is, when the clock signal terminal CLK transitions from a low-level signal to a high-level signal—the first transistor M1 turns on, and the voltage at the first node N1 equals the high-level signal at the first signal input terminal IN1. At this point, the fourth transistor M4 turns on, the fifth transistor M5 turns off, and the signal output terminal OUT outputs a high-level signal from the first power supply terminal V1.

[0244] Phase P12: The signal at the first signal input terminal IN1 changes to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the first signal input terminal IN1, and the voltage at the third node N3 becomes the low-level signal of the first signal input terminal IN1. At this time, the fourth transistor M4 turns off, the fifth transistor M5 turns on, and the signal output terminal OUT outputs a low-level signal from the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2 and the isolation effect of the sixth transistor M6, the voltage at the third node N3 is lower than the voltage at the first node N1. The fifth transistor M5 turns on in the linear region, allowing the signal output terminal OUT to quickly pull down from a high-level signal to a low-level signal.

[0245] In an exemplary embodiment, as shown in FIG11B , the operation process of the shift register may include:

[0246] Phase P21 is called the reverse scan phase: During reverse scanning, the first control signal terminal CK1 is a constant positive voltage, the second transistor M2 is off, the third transistor M3 is on, and the voltage at the second node N2 is the signal at the second signal input terminal IN2. The signal at the second signal input terminal IN2 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the second signal input terminal IN2. At this time, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, and the signal output terminal OUT outputs a high-level signal from the first power supply terminal V1.

[0247] Phase P22: The signal at the second signal input terminal IN2 turns to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the second signal input terminal IN2, and the voltage at the third node N3 becomes the low-level signal of the second signal input terminal IN2. At this time, the fourth transistor M4 turns off, the fifth transistor M5 turns on, and the signal output terminal OUT outputs a low-level signal of the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2 and the isolation effect of the sixth transistor M6, the voltage at the third node N3 is lower than the voltage at the first node N1. The fifth transistor M5 turns on in the linear region, allowing the signal output terminal OUT to quickly pull down from a high-level signal to a low-level signal.

[0248] Figure 12A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 12B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 12A and 12B, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3, and the output subcircuit may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0249] In an exemplary embodiment, as shown in Figures 12A and 12B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the second control signal terminal CK2, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2; the control electrode of the fourth transistor M4 is electrically connected to the first node N1, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor M4 is electrically connected to the first power supply terminal V1. a control electrode of the fifth transistor M5 is electrically connected to the third node N3, a first electrode of the fifth transistor M5 is electrically connected to the second power supply terminal V2, and a second electrode of the fifth transistor M5 is electrically connected to the signal output terminal OUT; a control electrode of the sixth transistor M6 is electrically connected to the second power supply terminal V2, a first electrode of the sixth transistor M6 is electrically connected to the first node N1, and a second electrode of the sixth transistor M6 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the signal output terminal OUT.

[0250] In an exemplary embodiment, the first transistor M1 and the fourth transistor M4 are N-type transistors, and the fifth transistor M5 and the sixth transistor M6 are P-type transistors.

[0251] In an exemplary embodiment, as shown in FIG12A , the second transistor M2 and the third transistor M3 are both N-type transistors, the first control signal terminal CK1 is a constant positive voltage, and the second control signal terminal CK2 is a constant negative voltage.

[0252] In an exemplary embodiment, as shown in FIG12B , the second transistor M2 and the third transistor M3 are both P-type transistors, the first control signal terminal CK1 is a constant negative voltage, and the second control signal terminal CK2 is a constant positive voltage.

[0253] An exemplary structure of a shift register is shown in Figures 12A and 12B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0254] FIG13A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG13B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation process of the shift register illustrated in FIG12A . The operation process of the shift register illustrated in FIG12B is similar in principle to that of the shift register illustrated in FIG12A , and will not be further described herein.

[0255] In an exemplary embodiment, as shown in FIG13A , the operation process of the shift register may include:

[0256] Phase P11 is called the forward scan phase: During the forward scan, the first control signal terminal CK1 is a constant positive voltage, the second control signal terminal CK2 is a constant negative voltage, the second transistor M2 is turned on, the third transistor M3 is turned off, and the voltage at the second node N2 is the signal at the first signal input terminal IN1. The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the first signal input terminal IN1. At this time, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, and the signal output terminal OUT outputs a high-level signal from the first power supply terminal V1.

[0257] Phase P12: The signal at the first signal input terminal IN1 changes to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the first signal input terminal IN1, and the voltage at the third node N3 becomes the low-level signal of the first signal input terminal IN1. At this time, the fourth transistor M4 turns off, the fifth transistor M5 turns on, and the signal output terminal OUT outputs a low-level signal from the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2 and the isolation effect of the sixth transistor M6, the voltage at the third node N3 is lower than the voltage at the first node N1. The fifth transistor M5 turns on in the linear region, allowing the signal output terminal OUT to quickly pull down from a high-level signal to a low-level signal.

[0258] In an exemplary embodiment, as shown in FIG13B , the operation process of the shift register may include:

[0259] Phase P21 is called the reverse scan phase: During reverse scanning, the first control signal terminal CK1 is at a constant negative voltage, the second control signal terminal CK2 is at a constant positive voltage, the second transistor M2 is off, the third transistor M3 is on, and the voltage at the second node N2 is the signal at the second signal input terminal IN2. The signal at the second signal input terminal IN2 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the second signal input terminal IN2. At this time, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, and the signal output terminal OUT outputs a high-level signal from the first power supply terminal V1.

[0260] Phase P22: The signal at the second signal input terminal IN2 turns to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the second signal input terminal IN2, and the voltage at the third node N3 becomes the low-level signal of the second signal input terminal IN2. At this time, the fourth transistor M4 turns off, the fifth transistor M5 turns on, and the signal output terminal OUT outputs a low-level signal of the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2 and the isolation effect of the sixth transistor M6, the voltage at the third node N3 is lower than the voltage at the first node N1. The fifth transistor M5 turns on in the linear region, allowing the signal output terminal OUT to quickly pull down from a high-level signal to a low-level signal.

[0261] Figure 14 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in Figure 14, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, and the output subcircuit may include seventh to sixteenth transistors M7 to M16, a third capacitor C3, and a fourth capacitor C4.

[0262] In an exemplary embodiment, as shown in FIG14 , the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the first signal input terminal IN1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the seventh transistor M7 is electrically connected to the first power supply terminal V1, the first electrode of the seventh transistor M7 is electrically connected to the first node N1, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor M8 is electrically connected to the fourth node N4, the first electrode of the eighth transistor M8 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor M8 is electrically connected to the cascade output terminal CR; the control electrode of the ninth transistor M9 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor M9 is electrically connected to the cascade output terminal CR; The third node N3 is electrically connected, the first electrode of the ninth transistor M9 is electrically connected to the cascade output terminal CR, and the second electrode of the ninth transistor M9 is electrically connected to the fifth node N5; the control electrode of the tenth transistor M10 is electrically connected to the third node N3, the first electrode of the tenth transistor M10 is electrically connected to the fifth node N5, and the second electrode of the tenth transistor M10 is electrically connected to the fourth power supply terminal V4; the control electrode of the eleventh transistor M11 is electrically connected to the fourth power supply terminal V4, the first electrode of the eleventh transistor M11 is electrically connected to the first node N1, and the second electrode of the eleventh transistor M11 is electrically connected to the third node N3; the control electrode of the twelfth transistor M12 is electrically connected to the cascade output terminal CR, and the first electrode of the twelfth transistor M12 is electrically connected to the The fifth node N5 is electrically connected, the second electrode of the twelfth transistor M12 is electrically connected to the third power supply terminal V3; the control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, the first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor M13 is electrically connected to the signal output terminal OUT; the control electrode of the fourteenth transistor M14 is electrically connected to the third node N3, the first electrode of the fourteenth transistor M14 is electrically connected to the signal output terminal OUT, and the second electrode of the fourteenth transistor M14 is electrically connected to the sixth node N6; the control electrode of the fifteenth transistor M15 is electrically connected to the third node N3, the first electrode of the fifteenth transistor M15 is electrically connected to the sixth node N6, and the fifteenth transistor M15 is electrically connected to the sixth node N6. A second electrode of the transistor M15 is electrically connected to the second power supply terminal V2; a control electrode of the sixteenth transistor M16 is electrically connected to the signal output terminal OUT, a first electrode of the sixteenth transistor M16 is electrically connected to the sixth node N6, and a second electrode of the sixteenth transistor M16 is electrically connected to the third power supply terminal V3; a third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the fourth node N4, and the second plate C32 of the third capacitor is electrically connected to the signal output terminal OUT; a fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected to the third node N3, and the second plate C42 of the fourth capacitor is electrically connected to the cascade output terminal CR.

[0263] In an exemplary embodiment, the first transistor M1, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13 and the sixteenth transistor M16 are N-type transistors, and the ninth transistor M9 to the eleventh transistor M11, the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

[0264] An exemplary structure of a shift register is shown in Figure 14. Those skilled in the art will readily appreciate that the implementation of the shift register is not limited thereto.

[0265] FIG15 is a timing diagram of an operation of a shift register provided by an exemplary embodiment. The exemplary embodiment of the present disclosure is described below through the operation process of the shift register illustrated in FIG14 .

[0266] In an exemplary embodiment, as shown in FIG15 , the operation process of the shift register may include:

[0267] Phase P1: The signal at the first signal input terminal IN1 is high. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low level to a high level, the first transistor M1 turns on, and the voltage at the first node N1 reaches the high level of the signal at the first signal input terminal IN1. The seventh transistor M7 turns off, and the voltage at the fourth node N4 reaches the high level of the signal at the first signal input terminal IN1. At this time, the eighth transistor M8 turns on, and the thirteenth transistor M13 turns on. The signal output terminal OUT and the cascade output terminal CR output a high level signal from the first power supply terminal V1. At this time, the eighth transistor M8 acts as an isolation bootstrap. The twelfth transistor M12 turns on, and the sixteenth transistor M16 turns on. The voltages at the fifth node N5 and the sixth node N6 reach the high level of the signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2 and from the first power supply terminal V1 to the fourth power supply terminal V4.

[0268] Phase P2: The signal at the first signal input terminal IN1 changes to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 becomes the low-level signal at the first signal input terminal IN1. The seventh transistor M7 turns off, and the voltage at the fourth node N4 becomes the low-level signal at the first signal input terminal IN1. The eleventh transistor M11 turns off, and the voltage at the third node N3 becomes the low-level signal at the first signal input terminal IN1. At this time, the eighth transistor M8 turns off, the thirteenth transistor M13 turns off, the ninth transistor M9 and the tenth transistor M10 turn on, and the fourteenth transistor M14 and the fifteenth transistor M15 turn on. The output at the signal output terminal OUT changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the second power supply terminal V2. The output at the cascade output terminal CR changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the fourth power supply terminal V4. At this time, the eleventh transistor M11 plays a role of isolation and bootstrapping, and the twelfth transistor M12 and the sixteenth transistor M16 are turned off.

[0269] In the P2 stage, due to the bootstrap effect of the fourth capacitor C4 and the isolation effect of the eleventh transistor M11, the voltage of the third node N3 is lower than the voltage of the fourth node N4, and the ninth transistor M9 is turned on in the linear region, so that the cascade output terminal CR can be quickly pulled down from a high-level signal to a low-level signal.

[0270] Phase P3: When the signal at the first signal input terminal IN1 transitions to a high-level signal again, and when the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low-level signal to a high-level signal), phase P1 repeats. Due to the bootstrap effect of the third capacitor C3, the voltage at the fourth node N4 is raised, and the thirteenth transistor M13 operates in the linear region, allowing the signal output terminal OUT to quickly rise from a low-level signal to a high-level signal.

[0271] In an exemplary embodiment, the voltage value of the first power supply terminal V1 is less than or equal to the voltage value of the third power supply terminal V3, so that the voltage difference between the ninth transistor M9 and the fourteenth transistor M14 is small or zero. In this case, the high-voltage waveforms of the cascade output terminal CR and the signal output terminal OUT will not be attenuated due to leakage.

[0272] In an exemplary embodiment, the voltage value of the fourth power supply terminal V4 is greater than the voltage value of the second power supply terminal V2, so that the voltage between the gate and the source of the fourteenth transistor M14 and the fifteenth transistor M15 is greater than zero, thereby preventing leakage caused by a positive change in the threshold voltage of the fourteenth transistor M14 and the fifteenth transistor M15.

[0273] Figure 16A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 16B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 16A and 16B, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3, and the output subcircuit may include seventh to sixteenth transistors, a third capacitor, and a fourth capacitor.

[0274] In an exemplary embodiment, as shown in Figures 16A and 16B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the first control signal terminal CK1, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2; the control electrode of the seventh transistor M7 is electrically connected to the first power supply terminal V1, and the first electrode of the seventh transistor M7 is electrically connected to the first node N1 is electrically connected, a second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; a control electrode of the eighth transistor M8 is electrically connected to the fourth node N4, a first electrode of the eighth transistor M8 is electrically connected to the first power supply terminal V1, and a second electrode of the eighth transistor M8 is electrically connected to the cascade output terminal CR; a control electrode of the ninth transistor M9 is electrically connected to the third node N3, a first electrode of the ninth transistor M9 is electrically connected to the cascade output terminal CR, and a second electrode of the ninth transistor M9 is electrically connected to the fifth node N5; a control electrode of the tenth transistor M10 is electrically connected to the third node N3, a first electrode of the tenth transistor M10 is electrically connected to the fifth node N5, and a second electrode of the tenth transistor M10 is electrically connected to the fourth power supply terminal V4; a control electrode of the eleventh transistor M11 is electrically connected to the fourth power supply terminal V4, and a first electrode of the eleventh transistor M11 is electrically connected to the first node N1 The first electrode of the twelfth transistor M12 is electrically connected to the cascade output terminal CR, the first electrode of the twelfth transistor M12 is electrically connected to the fifth node N5, and the second electrode of the twelfth transistor M12 is electrically connected to the third power supply terminal V3; the control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, the first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor M13 is electrically connected to the signal output terminal OUT; the control electrode of the fourteenth transistor M14 is electrically connected to the third node N3. a first electrode of the fourteenth transistor M14 is electrically connected to the signal output terminal OUT, and a second electrode of the fourteenth transistor M14 is electrically connected to the sixth node N6; a control electrode of the fifteenth transistor M15 is electrically connected to the third node N3, a first electrode of the fifteenth transistor M15 is electrically connected to the sixth node N6, and a second electrode of the fifteenth transistor M15 is electrically connected to the second power supply terminal V2; a control electrode of the sixteenth transistor M16 is connected to the signal output terminal OUT, a first electrode of the sixteenth transistor M16 is electrically connected to the sixth node N6, and a second electrode of the sixteenth transistor M16 is electrically connected to the third power supply terminal V3;The third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the fourth node N4, and the second plate C32 of the third capacitor is electrically connected to the signal output terminal OUT. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the third node N3, and the second plate C42 of the fourth capacitor is electrically connected to the cascade output terminal CR.

[0275] In an exemplary embodiment, the first transistor M1, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13 and the sixteenth transistor M16 are N-type transistors, and the ninth transistor M9 to the eleventh transistor M11, the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

[0276] In an exemplary embodiment, as shown in FIG16A , the second transistor M2 is a P-type transistor, the third transistor M3 is an N-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant negative voltage, and during reverse scanning, the first control signal terminal CK1 is a constant positive voltage.

[0277] In an exemplary embodiment, as shown in FIG16B , the second transistor M2 is an N-type transistor, the third transistor M3 is a P-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant positive voltage, and during reverse scanning, the first control signal terminal CK1 is a constant negative voltage.

[0278] An exemplary structure of a shift register is shown in Figures 16A and 16B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0279] FIG17A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG17B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation process of the shift register illustrated in FIG16A . The operation process of the shift register illustrated in FIG16B is similar in principle to that of the shift register illustrated in FIG16A , and will not be further described herein.

[0280] In an exemplary embodiment, as shown in FIG17A , the operation process of the shift register may include:

[0281] Phase P11 is called the forward scan phase: During the forward scan, the first control signal terminal CK1 is a constant negative voltage, the second transistor M2 is turned on, the third transistor M3 is turned off, and the voltage at the second node N2 is the signal at the first signal input terminal IN1. The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the first signal input terminal IN1. The seventh transistor M7 is turned off, and the voltage at the fourth node N4 is the high-level signal at the first signal input terminal IN1. At this time, the eighth transistor M8 is turned on, and the thirteenth transistor M13 is turned on. The signal output terminal OUT and the cascade output terminal CR output a high-level signal at the first power supply terminal V1. At this time, the eighth transistor M8 acts as an isolation bootstrap. The twelfth transistor M12 is turned on, the sixteenth transistor M16 is turned on, and the voltages of the fifth node N5 and the sixth node N6 are the high level of the signal of the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2 and preventing leakage from the first power supply terminal V1 to the fourth power supply terminal V4.

[0282] Phase P12: The signal at the first signal input terminal IN1 changes to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 becomes the low-level signal at the first signal input terminal IN1. The seventh transistor M7 turns off, and the voltage at the fourth node N4 becomes the low-level signal at the first signal input terminal IN1. The eleventh transistor M11 turns off, and the voltage at the third node N3 becomes the low-level signal at the first signal input terminal IN1. At this point, the eighth transistor M8 turns off, the thirteenth transistor M13 turns off, the ninth transistor M9 and the tenth transistor M10 turn on, and the fourteenth transistor M14 and the fifteenth transistor M15 turn on. The output at the signal output terminal OUT changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the second power supply terminal V2. The output at the cascade output terminal CR changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the fourth power supply terminal V4. At this time, the eleventh transistor M11 plays a role of isolation and bootstrapping, and the twelfth transistor M12 and the sixteenth transistor M16 are turned off.

[0283] In an exemplary embodiment, as shown in FIG17B , the operation process of the shift register may include:

[0284] Phase P21 is called the reverse scan phase: During reverse scanning, the first control signal terminal CK1 is a constant positive voltage, the second transistor M2 is turned off, the third transistor M3 is turned on, and the voltage at the second node N2 is the signal at the second signal input terminal IN2. The signal at the second signal input terminal IN2 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the second signal input terminal IN2. The seventh transistor M7 is turned off, and the voltage at the fourth node N4 is the high-level signal at the second signal input terminal IN2. At this time, the eighth transistor M8 is turned on, and the thirteenth transistor M13 is turned on. The signal output terminal OUT and the cascade output terminal CR output a high-level signal at the first power supply terminal V1. At this time, the eighth transistor M8 acts as an isolation bootstrap. The twelfth transistor M12 is turned on, the sixteenth transistor M16 is turned on, and the voltages of the fifth node N5 and the sixth node N6 are the high level of the signal of the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2 and preventing leakage from the first power supply terminal V1 to the fourth power supply terminal V4.

[0285] Phase P22: The signal at the second signal input terminal IN2 turns low. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low level to a high level, the first transistor M1 turns on, and the voltage at the first node N1 becomes the low level of the signal at the second signal input terminal IN2. The seventh transistor M7 turns off, and the voltage at the fourth node N4 becomes the low level of the signal at the second signal input terminal IN2. The eleventh transistor M11 turns off, and the voltage at the third node N3 becomes the low level of the signal at the second signal input terminal IN2. At this point, the eighth transistor M8 turns off, the thirteenth transistor M13 turns off, the ninth transistor M9 and the tenth transistor M10 turn on, and the fourteenth transistor M14 and the fifteenth transistor M15 turn on. The output of the signal output terminal OUT transitions from a high level signal at the first power supply terminal V1 to a low level signal at the second power supply terminal V2. The output of the cascade output terminal CR transitions from a high level signal at the first power supply terminal V1 to a low level signal at the fourth power supply terminal V4. At this time, the eleventh transistor M11 plays a role of isolation and bootstrapping, and the twelfth transistor M12 and the sixteenth transistor M16 are turned off.

[0286] Figure 18A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 18B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 18A and 18B , in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include transistors M7 through M16, a third capacitor C3, and a fourth capacitor C4.

[0287] In an exemplary embodiment, as shown in Figures 18A and 18B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the second control signal terminal CK2, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2. The control electrode of the seventh transistor M7 is electrically connected to the first power supply terminal V1, the first electrode of the seventh transistor M7 is electrically connected to the first node N1, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the control electrode of the eighth transistor M8 is electrically connected to the fourth node N4, the first electrode of the eighth transistor M8 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor M8 is electrically connected to the cascade output terminal CR; the control electrode of the ninth transistor M9 is electrically connected to the third node N3, the first electrode of the ninth transistor M9 is electrically connected to the cascade output terminal CR, and the second electrode of the ninth transistor M9 is electrically connected to the fifth node N5; the control electrode of the tenth transistor M10 is electrically connected to the third node N3, the first electrode of the tenth transistor M10 is electrically connected to the The fifth node N5 is electrically connected, the second electrode of the tenth transistor M10 is electrically connected to the fourth power supply terminal V4; the control electrode of the eleventh transistor M11 is electrically connected to the fourth power supply terminal V4, the first electrode of the eleventh transistor M11 is electrically connected to the first node N1, and the second electrode of the eleventh transistor M11 is electrically connected to the third node N3; the control electrode of the twelfth transistor M12 is electrically connected to the cascade output terminal CR, the first electrode of the twelfth transistor M12 is electrically connected to the fifth node N5, and the second electrode of the twelfth transistor M12 is electrically connected to the third power supply terminal V3; the control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, the first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal V1, and the thirteenth transistor M1 a control electrode of a fourth transistor M14 electrically connected to the third node N3, a first electrode of the fourth transistor M14 electrically connected to the signal output terminal OUT, and a second electrode of the fourth transistor M14 electrically connected to the sixth node N6; a control electrode of a fifteenth transistor M15 electrically connected to the third node N3, a first electrode of the fifteenth transistor M15 electrically connected to the sixth node N6, and a second electrode of the fifteenth transistor M15 electrically connected to the second power supply terminal V2; a control electrode of a sixteenth transistor M16 electrically connected to the signal output terminal OUT, a first electrode of the sixteenth transistor M16 electrically connected to the sixth node N6, and a second electrode of the sixteenth transistor M16 electrically connected to the third power supply terminal V3;The third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the fourth node N4, and the second plate C32 of the third capacitor is electrically connected to the signal output terminal OUT. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the third node N3, and the second plate C42 of the fourth capacitor is electrically connected to the cascade output terminal CR.

[0288] In an exemplary embodiment, the first transistor M1, the seventh transistor M7, the eighth transistor M8, the twelfth transistor M12, the thirteenth transistor M13 and the sixteenth transistor M16 are N-type transistors, and the ninth transistor M9 to the eleventh transistor M11, the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

[0289] In an exemplary embodiment, as shown in FIG18A , the second transistor M2 and the third transistor M3 are both N-type transistors, the first control signal terminal CK1 is a constant positive voltage, and the second control signal terminal CK2 is a constant negative voltage.

[0290] In an exemplary embodiment, as shown in FIG18B , the second transistor M2 and the third transistor M3 are both P-type transistors, the first control signal terminal CK1 is a constant negative voltage, and the second control signal terminal CK2 is a constant positive voltage.

[0291] An exemplary structure of a shift register is shown in Figures 18A and 18B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0292] FIG19A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG19B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation of the shift register illustrated in FIG18A . The operation of the shift register illustrated in FIG18B is similar in principle to that of the shift register illustrated in FIG18A , and will not be further described herein.

[0293] In an exemplary embodiment, as shown in FIG19A , the operation process of the shift register may include:

[0294] Phase P11 is called the forward scan phase: During the forward scan, the first control signal terminal CK1 is a constant positive voltage, the second control signal terminal CK2 is a constant negative voltage, the second transistor M2 is turned on, the third transistor M3 is turned off, and the voltage at the second node N2 is the signal at the first signal input terminal IN1. The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the first signal input terminal IN1. The seventh transistor M7 is turned off, and the voltage at the fourth node N4 is the high-level signal at the first signal input terminal IN1. At this time, the eighth transistor M8 is turned on, and the thirteenth transistor M13 is turned on. The signal output terminal OUT and the cascade output terminal CR output a high-level signal at the first power supply terminal V1. At this time, the eighth transistor M8 acts as an isolation bootstrap. The twelfth transistor M12 is turned on, the sixteenth transistor M16 is turned on, and the voltages of the fifth node N5 and the sixth node N6 are the high level of the signal of the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2 and preventing leakage from the first power supply terminal V1 to the fourth power supply terminal V4.

[0295] Phase P12: The signal at the first signal input terminal IN1 changes to a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 becomes the low-level signal at the first signal input terminal IN1. The seventh transistor M7 turns off, and the voltage at the fourth node N4 becomes the low-level signal at the first signal input terminal IN1. The eleventh transistor M11 turns off, and the voltage at the third node N3 becomes the low-level signal at the first signal input terminal IN1. At this point, the eighth transistor M8 turns off, the thirteenth transistor M13 turns off, the ninth transistor M9 and the tenth transistor M10 turn on, and the fourteenth transistor M14 and the fifteenth transistor M15 turn on. The output at the signal output terminal OUT changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the second power supply terminal V2. The output at the cascade output terminal CR changes from a high-level signal at the first power supply terminal V1 to a low-level signal at the fourth power supply terminal V4. At this time, the eleventh transistor M11 plays a role of isolation and bootstrapping, and the twelfth transistor M12 and the sixteenth transistor M16 are turned off.

[0296] In an exemplary embodiment, as shown in FIG19B , the operation process of the shift register may include:

[0297] Phase P21 is called the reverse scan phase: During the reverse scan, the first control signal terminal CK1 is at a constant negative voltage, the second control signal terminal CK2 is at a constant positive voltage, the second transistor M2 is off, the third transistor M3 is on, and the voltage at the second node N2 is the signal at the second signal input terminal IN2. The signal at the second signal input terminal IN2 is a high-level signal. When the clock signal terminal CLK reaches a rising edge, that is, when the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 is turned on, and the voltage at the first node N1 is the high-level signal at the second signal input terminal IN2. The seventh transistor M7 is turned off, and the voltage at the fourth node N4 is the high-level signal at the second signal input terminal IN2. At this time, the eighth transistor M8 is turned on, and the thirteenth transistor M13 is turned on. The signal output terminal OUT and the cascade output terminal CR output a high-level signal at the first power supply terminal V1. At this time, the eighth transistor M8 acts as an isolation bootstrap. The twelfth transistor M12 is turned on, the sixteenth transistor M16 is turned on, and the voltages of the fifth node N5 and the sixth node N6 are the high level of the signal of the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2 and preventing leakage from the first power supply terminal V1 to the fourth power supply terminal V4.

[0298] Phase P22: The signal at the second signal input terminal IN2 turns low. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low level to a high level, the first transistor M1 turns on, and the voltage at the first node N1 becomes the low level of the signal at the second signal input terminal IN2. The seventh transistor M7 turns off, and the voltage at the fourth node N4 becomes the low level of the signal at the second signal input terminal IN2. The eleventh transistor M11 turns off, and the voltage at the third node N3 becomes the low level of the signal at the second signal input terminal IN2. At this point, the eighth transistor M8 turns off, the thirteenth transistor M13 turns off, the ninth transistor M9 and the tenth transistor M10 turn on, and the fourteenth transistor M14 and the fifteenth transistor M15 turn on. The output of the signal output terminal OUT transitions from a high level signal at the first power supply terminal V1 to a low level signal at the second power supply terminal V2. The output of the cascade output terminal CR transitions from a high level signal at the first power supply terminal V1 to a low level signal at the fourth power supply terminal V4. At this time, the eleventh transistor M11 plays a role of isolation and bootstrapping, and the twelfth transistor M12 and the sixteenth transistor M16 are turned off.

[0299] FIG20 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. As shown in FIG20 , in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, and the output subcircuit may include seventeenth to twenty-first transistors M17 to M21, and a first capacitor C1.

[0300] In an exemplary embodiment, as shown in FIG20 , the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the first signal input terminal IN1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the seventeenth transistor M17 is electrically connected to the first node N1, the first electrode of the seventeenth transistor M17 is electrically connected to the first power supply terminal V1, and the second electrode of the seventeenth transistor M17 is electrically connected to the signal output terminal OUT; the control electrode of the eighteenth transistor M18 is electrically connected to the third node N3, the first electrode of the eighteenth transistor M18 is electrically connected to the signal output terminal OUT, and the second electrode of the eighteenth transistor M18 is electrically connected to the fifth node N5; the control electrode of the nineteenth transistor M19 is electrically connected to the third node N3, and the nineteenth transistor M19 is electrically connected to the third node N4. A first electrode of the transistor M19 is electrically connected to the fifth node N5, and a second electrode of the nineteenth transistor M19 is electrically connected to the second power supply terminal V2; a control electrode of the twentieth transistor M20 is electrically connected to the second power supply terminal V2, a first electrode of the twentieth transistor M20 is electrically connected to the first node N1, and a second electrode of the twentieth transistor M20 is electrically connected to the third node N3; a control electrode of the twenty-first transistor M21 is electrically connected to the signal output terminal OUT, a first electrode of the twenty-first transistor M21 is electrically connected to the fifth node N5, and a second electrode of the twenty-first transistor M21 is electrically connected to the third power supply terminal V3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT.

[0301] In an exemplary embodiment, the first transistor M1 , the seventeenth transistor M17 , and the twenty-first transistor M21 are N-type transistors, and the eighteenth transistor M18 to the twentieth transistor M20 are P-type transistors.

[0302] An exemplary structure of a shift register is shown in Figure 20. Those skilled in the art will readily appreciate that the implementation of the shift register is not limited thereto.

[0303] FIG21 is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The exemplary embodiment of the present disclosure is described below using the operation process of the shift register illustrated in FIG20 .

[0304] In an exemplary embodiment, as shown in FIG21 , the operation process of the shift register may include:

[0305] Phase P1: The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 reaches the high-level signal at the first signal input terminal IN1. At this point, the seventeenth transistor M17 turns on, the eighteenth transistor M18, the nineteenth transistor M19, and the second transistor M20 turn off, and the signal output terminal OUT outputs a high-level signal at the first power supply terminal V1. At this point, the twentieth transistor M20 acts as an isolation bootstrap. The twenty-first transistor M21 turns on, and the voltage at the fifth node N5 reaches the high-level signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2.

[0306] Phase P2: The signal at the first signal input terminal IN1 becomes a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal), the first transistor M1 turns on, the voltage at the first node N1 reaches the low-level signal of the first signal input terminal IN1, and the voltage at the third node N3 reaches the low-level signal of the first signal input terminal IN1. At this point, the seventeenth transistor M17 turns off, the eighteenth transistor M18 and the nineteenth transistor M19 turn on, the signal output terminal OUT outputs the low-level signal of the second power supply terminal V2, and the twenty-first transistor M21 turns off.

[0307] In the P2 phase, due to the isolation and bootstrapping effect of the twentieth transistor M20, the voltage of the third node N3 is lower than the voltage of the first node N1, and the eighteenth transistor M18 is turned on in the linear region, so that the signal output terminal OUT can be quickly pulled down from a high-level signal to a low-level signal.

[0308] Phase P3: When the signal at the first signal input terminal IN1 turns to a high level signal again, when the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low level signal to a high level, phase P1 is repeated.

[0309] Figure 22A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 22B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 22A and 22B, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3, and the output subcircuit may include seventeenth to twenty-first transistors M17 to M21, and a first capacitor C1.

[0310] In an exemplary embodiment, as shown in Figures 22A and 22B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the first control signal terminal CK1, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2; the control electrode of the seventeenth transistor M17 is electrically connected to the first node N1, the first electrode of the seventeenth transistor M17 is electrically connected to the first power supply terminal V1, and the second electrode of the seventeenth transistor M17 is electrically connected to the signal output terminal OUT; the control electrode of the eighteenth transistor M18 is electrically connected to the third node N3, and the eighteenth transistor M19 is electrically connected to the third node N4. A first electrode of the transistor M18 is electrically connected to the signal output terminal OUT, and a second electrode of the eighteenth transistor M18 is electrically connected to the fifth node N5; a control electrode of the nineteenth transistor M19 is electrically connected to the third node N3, a first electrode of the nineteenth transistor M19 is electrically connected to the fifth node N5, and a second electrode of the nineteenth transistor M19 is electrically connected to the second power supply terminal V2; a control electrode of the twentieth transistor M20 is electrically connected to the second power supply terminal V2, a first electrode of the twentieth transistor M20 is electrically connected to the first node N1, and a second electrode of the twentieth transistor M20 is electrically connected to the third node N3; a control electrode of the twenty-first transistor M21 is electrically connected to the signal output terminal OUT, a first electrode of the twenty-first transistor M21 is electrically connected to the fifth node N5, and a second electrode of the twenty-first transistor M21 is electrically connected to the third power supply terminal V3; and a first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT.

[0311] In an exemplary embodiment, the first transistor M1 , the seventeenth transistor M17 , and the twenty-first transistor M21 are N-type transistors, and the eighteenth transistor M18 to the twentieth transistor M20 are P-type transistors.

[0312] In an exemplary embodiment, as shown in FIG22A , the second transistor M2 is a P-type transistor, the third transistor M3 is an N-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant negative voltage, and during reverse scanning, the first control signal terminal CK1 is a constant positive voltage.

[0313] In an exemplary embodiment, as shown in FIG22B , the second transistor M2 is an N-type transistor, the third transistor M3 is a P-type transistor, and during forward scanning, the first control signal terminal CK1 is a constant positive voltage, and during reverse scanning, the first control signal terminal CK1 is a constant negative voltage.

[0314] An exemplary structure of a shift register is shown in Figures 22A and 22B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0315] FIG23A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG23B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation of the shift register illustrated in FIG22A . The operation of the shift register illustrated in FIG22B is similar in principle to that of the shift register illustrated in FIG22A , and will not be further described herein.

[0316] In an exemplary embodiment, as shown in FIG23A , the operation process of the shift register may include:

[0317] Phase P11 is called the forward scan phase: During the forward scan, the first control signal terminal CK1 maintains a constant negative voltage, the second transistor M2 turns on, the third transistor M3 turns off, and the voltage at the second node N2 equals the signal at the first signal input terminal IN1. The signal at the first signal input terminal IN1 is high. When the clock signal terminal CLK reaches a rising edge, i.e., when the clock signal terminal CLK transitions from a low level to a high level, the first transistor M1 turns on, and the voltage at the first node N1 equals the high level of the signal at the first signal input terminal IN1. At this point, the seventeenth transistor M17 turns on, while the eighteenth transistor M18, the nineteenth transistor M19, and the second transistor M20 turn off. The signal output terminal OUT outputs a high level signal from the first power supply terminal V1. At this point, the twentieth transistor M20 acts as an isolation bootstrap. The twenty-first transistor M21 turns on, and the voltage at the fifth node N5 equals the high level of the signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2.

[0318] Phase P12: The signal at the first signal input terminal IN1 becomes a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal), the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the first signal input terminal IN1, and the voltage at the third node N3 also becomes the low-level signal of the first signal input terminal IN1. At this point, the seventeenth transistor M17 turns off, the eighteenth transistor M18 and the nineteenth transistor M19 turn on, the signal output terminal OUT outputs the low-level signal of the second power supply terminal V2, and the twenty-first transistor M21 turns off.

[0319] In an exemplary embodiment, as shown in FIG23B , the operation process of the shift register may include:

[0320] Phase P21 is called the reverse scan phase: During the reverse scan, the first control signal terminal CK1 maintains a constant positive voltage, the second transistor M2 is off, the third transistor M3 is on, and the voltage at the second node N2 is the signal at the second signal input terminal IN2. The signal at the second signal input terminal IN2 is high. When the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low level to a high level), the first transistor M1 turns on, and the voltage at the first node N1 reaches the high level of the signal at the second signal input terminal IN2. At this point, the seventeenth transistor M17 turns on, while the eighteenth transistor M18, the nineteenth transistor M19, and the second transistor M20 turn off. The signal output terminal OUT outputs a high level signal from the first power supply terminal V1. At this point, the twentieth transistor M20 acts as an isolation bootstrap. The twenty-first transistor M21 turns on, and the voltage at the fifth node N5 reaches the high level of the signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2.

[0321] Phase P22: The signal at the second signal input terminal IN2 turns low. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low level to a high level), the first transistor M1 turns on, the voltage at the first node N1 reaches the low level of the signal at the second signal input terminal IN2, and the voltage at the third node N3 reaches the low level of the signal at the second signal input terminal IN2. At this point, the seventeenth transistor M17 turns off, the eighteenth transistor M18 and the nineteenth transistor M19 turn on, the signal output terminal OUT outputs the low level of the second power supply terminal V2, and the twenty-first transistor M21 turns off.

[0322] Figure 24A is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment, and Figure 24B is an equivalent circuit diagram of a shift register provided in accordance with an exemplary embodiment. As shown in Figures 24A and 24B, in an exemplary embodiment, the shift register may include an input subcircuit and an output subcircuit. The input subcircuit may include a first transistor M1, a second transistor M2, and a third transistor M3, and the output subcircuit may include seventeenth to twenty-first transistors M17 to M21, and a first capacitor C1.

[0323] In an exemplary embodiment, as shown in Figures 24A and 24B, the control electrode of the first transistor M1 is electrically connected to the clock signal terminal CLK, the first electrode of the first transistor M1 is electrically connected to the second node N2, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the control electrode of the second transistor M2 is electrically connected to the first control signal terminal CK1, the first electrode of the second transistor M2 is electrically connected to the first signal input terminal IN1, and the second electrode of the second transistor M2 is electrically connected to the second node N2; the control electrode of the third transistor M3 is electrically connected to the second control signal terminal CK2, the first electrode of the third transistor M3 is electrically connected to the second signal input terminal IN2, and the second electrode of the third transistor M3 is electrically connected to the second node N2; the control electrode of the seventeenth transistor M17 is electrically connected to the first node N1, the first electrode of the seventeenth transistor M17 is electrically connected to the first power supply terminal V1, and the second electrode of the seventeenth transistor M17 is electrically connected to the signal output terminal OUT; the control electrode of the eighteenth transistor M18 is electrically connected to the third node N3, and the eighteenth transistor M19 is electrically connected to the third node N4. A first electrode of the transistor M18 is electrically connected to the signal output terminal OUT, and a second electrode of the eighteenth transistor M18 is electrically connected to the fifth node N5; a control electrode of the nineteenth transistor M19 is electrically connected to the third node N3, a first electrode of the nineteenth transistor M19 is electrically connected to the fifth node N5, and a second electrode of the nineteenth transistor M19 is electrically connected to the second power supply terminal V2; a control electrode of the twentieth transistor M20 is electrically connected to the second power supply terminal V2, a first electrode of the twentieth transistor M20 is electrically connected to the first node N1, and a second electrode of the twentieth transistor M20 is electrically connected to the third node N3; a control electrode of the twenty-first transistor M21 is electrically connected to the signal output terminal OUT, a first electrode of the twenty-first transistor M21 is electrically connected to the fifth node N5, and a second electrode of the twenty-first transistor M21 is electrically connected to the third power supply terminal V3; and a first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the first node N1, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT.

[0324] In an exemplary embodiment, the first transistor M1 , the seventeenth transistor M17 , and the twenty-first transistor M21 are N-type transistors, and the eighteenth transistor M18 to the twentieth transistor M20 are P-type transistors.

[0325] In an exemplary embodiment, as shown in FIG24A , the second transistor M2 and the third transistor M3 are both N-type transistors, the first control signal terminal CK1 is a constant positive voltage, and the second control signal terminal CK2 is a constant negative voltage.

[0326] In an exemplary embodiment, as shown in FIG24B , the second transistor M2 and the third transistor M3 are both P-type transistors, the first control signal terminal CK1 is a constant negative voltage, and the second control signal terminal CK2 is a constant positive voltage.

[0327] An exemplary structure of a shift register is shown in Figures 24A and 24B. It will be readily understood by those skilled in the art that the implementation of the shift register is not limited thereto.

[0328] FIG25A is a timing diagram of the operation of a shift register provided by an exemplary embodiment, and FIG25B is a timing diagram of the operation of a shift register provided by an exemplary embodiment. The following describes an exemplary embodiment of the present disclosure using the operation process of the shift register illustrated in FIG24A . The operation process of the shift register illustrated in FIG24B is similar in principle to that of the shift register illustrated in FIG24A , and will not be further described in detail in the present disclosure.

[0329] In an exemplary embodiment, as shown in FIG25A , the operation process of the shift register may include:

[0330] Phase P10 is called the forward scanning phase: during forward scanning, the first control signal terminal CK1 is a constant positive voltage, the second control signal terminal CK2 is a constant negative voltage, the second transistor M2 is turned on, the third transistor M3 is turned off, and the voltage of the second node N2 is the signal of the first signal input terminal IN1.

[0331] Phase P11: The signal at the first signal input terminal IN1 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK jumps from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 reaches the high-level signal at the first signal input terminal IN1. At this time, the seventeenth transistor M17 turns on, the eighteenth transistor M18, the nineteenth transistor M19, and the second transistor M20 turn off, and the signal output terminal OUT outputs a high-level signal at the first power supply terminal V1. At this time, the twentieth transistor M20 acts as an isolation bootstrap. The twenty-first transistor M21 turns on, and the voltage at the fifth node N5 reaches the high-level signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2.

[0332] Phase P12: The signal at the first signal input terminal IN1 becomes a low-level signal. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal), the first transistor M1 turns on, the voltage at the first node N1 becomes the low-level signal of the first signal input terminal IN1, and the voltage at the third node N3 also becomes the low-level signal of the first signal input terminal IN1. At this point, the seventeenth transistor M17 turns off, the eighteenth transistor M18 and the nineteenth transistor M19 turn on, the signal output terminal OUT outputs the low-level signal of the second power supply terminal V2, and the twenty-first transistor M21 turns off.

[0333] In an exemplary embodiment, as shown in FIG25B , the operation process of the shift register may include:

[0334] Phase P20 is called the reverse scanning phase: during reverse scanning, the first control signal terminal CK1 is a constant negative voltage, the second control signal terminal CK2 is a constant positive voltage, the second transistor M2 is turned off, the third transistor M3 is turned on, and the voltage of the second node N2 is the signal of the second signal input terminal IN2.

[0335] Phase P21: The signal at the second signal input terminal IN2 is a high-level signal. When the signal at the clock signal terminal CLK reaches a rising edge, that is, when the signal at the clock signal terminal CLK transitions from a low-level signal to a high-level signal, the first transistor M1 turns on, and the voltage at the first node N1 reaches the high-level signal at the second signal input terminal IN2. At this point, the seventeenth transistor M17 turns on, the eighteenth transistor M18, the nineteenth transistor M19, and the second transistor M20 turn off, and the signal output terminal OUT outputs a high-level signal at the first power supply terminal V1. At this point, the twentieth transistor M20 acts as an isolation bootstrap. The twenty-first transistor M21 turns on, and the voltage at the fifth node N5 reaches the high-level signal at the third power supply terminal V3, preventing leakage from the first power supply terminal V1 to the second power supply terminal V2.

[0336] Phase P22: The signal at the second signal input terminal IN2 turns low. When the signal at the clock signal terminal CLK reaches a rising edge (i.e., when the clock signal terminal CLK transitions from a low level to a high level), the first transistor M1 turns on, the voltage at the first node N1 reaches the low level of the signal at the second signal input terminal IN2, and the voltage at the third node N3 reaches the low level of the signal at the second signal input terminal IN2. At this point, the seventeenth transistor M17 turns off, the eighteenth transistor M18 and the nineteenth transistor M19 turn on, the signal output terminal OUT outputs the low level of the second power supply terminal V2, and the twenty-first transistor M21 turns off.

[0337] The present disclosure also provides a gate drive circuit including a plurality of cascaded shift registers. The shift registers are the shift registers provided in any of the above embodiments, and their implementation principles and effects are similar, which will not be described in detail here.

[0338] Figure 26 is a structural circuit diagram of a gate drive circuit provided by an exemplary embodiment. As shown in Figure 26, at least one input signal terminal of at least one stage of shift register includes: a first signal input terminal IN1, and at least one output signal terminal of at least one stage of shift register includes: a signal output terminal OUT.

[0339] In an exemplary embodiment, as shown in FIG26 , the signal output terminal OUT of the i-th stage shift register is electrically connected to the first signal input terminal IN1 of the i+1-th stage shift register, 1≤i≤M-1, where M is the total number of stages of the shift register.

[0340] Figure 27 is a structural circuit diagram of a gate drive circuit provided by an exemplary embodiment. As shown in Figure 27, at least one input signal terminal of at least one stage of shift register includes: a first signal input terminal IN1, and at least one output signal terminal of at least one stage of shift register includes: a signal output terminal OUT and a cascade output terminal CR.

[0341] In an exemplary embodiment, as shown in FIG27 , the cascade output terminal CR of the i-th stage shift register is electrically connected to the first signal input terminal IN1 of the i+1-th stage shift register, 1≤i≤M-1, where M is the total number of stages of the shift register.

[0342] Figure 28 is a structural circuit diagram of a gate drive circuit provided by an exemplary embodiment. As shown in Figure 28, at least one input signal terminal of at least one stage of shift register includes: a first signal input terminal IN1 and a second signal input terminal IN2, and at least one output signal terminal of at least one stage of shift register includes: a signal output terminal OUT.

[0343] In an exemplary embodiment, as shown in Figure 28, the signal output terminal OUT of the i-th stage shift register is electrically connected to the first signal input terminal IN1 of the i+1-th stage shift register, and the signal output terminal OUT of the i+1-th stage shift register is electrically connected to the second signal input terminal IN2 of the i-th stage shift register, 1≤i≤M-1, M is the total number of stages of the shift register.

[0344] Figure 29 is a structural circuit diagram of a gate drive circuit provided by an exemplary embodiment. As shown in Figure 29, at least one input signal terminal of at least one stage of shift register includes: a first signal input terminal IN1 and a second signal input terminal IN2, and at least one output signal terminal of at least one stage of shift register includes: a signal output terminal OUT and a cascade output terminal CR.

[0345] In an exemplary embodiment, as shown in Figure 29, the cascade output terminal CR of the i-th stage shift register is electrically connected to the first signal input terminal IN1 of the i+1-th stage shift register, and the cascade output terminal CR of the i+1-th stage shift register is electrically connected to the second signal input terminal IN2 of the i-th stage shift register, 1≤i≤M-1, M is the total number of stages of the shift register.

[0346] An embodiment of the present disclosure further provides a display device, including a gate driving circuit. The gate driving circuit is the gate driving circuit provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0347] In an exemplary embodiment, the device may further include: a pixel circuit and a gate line, wherein the pixel circuit is electrically connected to at least one gate line, and an output signal terminal of a shift register in the gate driving circuit is electrically connected to the gate line.

[0348] The gate drive circuit provided in the embodiments of the present disclosure is located in a display device, wherein the display device is further provided with a pixel circuit and a gate line. The gate drive circuit can drive the pixel circuit. The pixel circuit is electrically connected to at least one gate line, and the output signal terminal of the shift register in the gate drive circuit is electrically connected to the gate line.

[0349] Figure 30 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 30, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first high-level power line VGH1 and a first low-level power line VGL1; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, and at least one power signal terminal includes: a first power terminal V1 and a second power terminal V2.

[0350] In an exemplary embodiment, as shown in Figure 30, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power supply line VGH1, and the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1; the first signal input terminal IN1 of the first stage of the shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0351] The first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line. The signal of the initial signal line can be an externally supplied start signal. The pulse width of the start signal can determine the pulse width output by the shift register, thereby achieving adjustable output pulse width and realizing single pulse or multi-pulse output.

[0352] In an exemplary embodiment, FIG31 is a schematic diagram of a single pulse output provided by an embodiment of the present disclosure. As shown in FIG31 , a single pulse output can be achieved for each row.

[0353] In an exemplary embodiment, FIG32 is a schematic diagram of the degree pulse output provided by an embodiment of the present disclosure. As shown in FIG32 , multiple pulse outputs per row can be achieved.

[0354] In an exemplary embodiment, Figure 33 is a multi-stage output timing diagram provided by an embodiment of the present disclosure. The clock signal terminal CLK of the cascaded shift register is electrically connected to the clock signal line in odd and even rows. For example, the clock signal terminal CLK of the i-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the i+1-th stage shift register is electrically connected to the second clock signal line CLKB. The timing shown in Figure 33 can be output to realize the shifting function between rows.

[0355] Figure 34 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 34, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scanning signal line CN, a first high-level power line VGH1 and a first low-level power line VGL1; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, a second signal input terminal IN2 and a first control signal terminal CK1, and at least one power signal terminal includes: a first power terminal V1 and a second power terminal V2.

[0356] In an exemplary embodiment, as shown in Figure 34, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power supply line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1, and the first control signal terminal CK1 is electrically connected to the first scan signal line CN; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0357] Figure 35 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 35, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scan signal line CN, a second scan signal line CNB, a first high-level power line VGH1 and a first low-level power line VGL1; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, a second signal input terminal IN2, a first control signal terminal CK1 and a second control signal terminal CK2, and at least one power signal terminal includes: a first power terminal V1 and a second power terminal V2.

[0358] In an exemplary embodiment, as shown in Figure 35, the first power supply terminal V1 of at least one stage shift register is electrically connected to the first high-level power supply line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1, the first control signal terminal CK1 is electrically connected to the first scan signal line CN, and the second control signal terminal CK2 is electrically connected to the second scan signal line CNB; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0359] Figure 36 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 36, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first high-level power line VGH1, a first low-level power line VGL1, a second high-level power line VGH2 and a second low-level power line VGL2A; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2, a third power terminal V3 and a fourth power terminal V4.

[0360] In an exemplary embodiment, as shown in Figure 36, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power line VGL1, the third power supply terminal V3 is electrically connected to the second high-level power line VGH2, and the fourth power supply terminal V4 is electrically connected to the second low-level power line VGL2; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, and M is the total number of stages of the shift register.

[0361] Figure 37 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 37, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scan signal line CN, a first high-level power line VGH1, a first low-level power line VGL1, a second high-level power line VGH2 and a second low-level power line VGL2; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, a second signal input terminal IN2 and a first control signal terminal CK1, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2, a third power terminal V3 and a fourth power terminal V4.

[0362] In an exemplary embodiment, as shown in Figure 37, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power line VGL1, the third power supply terminal V3 is electrically connected to the second high-level power line VGH2, the fourth power supply terminal V4 is electrically connected to the second low-level power line VGL2, and the first control signal terminal CK1 is electrically connected to the first scan signal line CN; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0363] Figure 38 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 38, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scan signal line CN, a second scan signal line CNB, a first high-level power line VGH1, a first low-level power line VGL1, a second high-level power line VGH2, and a second low-level power line VGL2; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, a second signal input terminal IN2, a first control signal terminal CK1 and a second control signal terminal CK2, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2, a third power terminal V3 and a fourth power terminal V4.

[0364] In an exemplary embodiment, as shown in Figure 38, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power line VGL1, the third power supply terminal V3 is electrically connected to the second high-level power line VGH2, the fourth power supply terminal V4 is electrically connected to the second low-level power line VGL2, the first control signal terminal CK1 is electrically connected to the first scan signal line CN, and the second control signal terminal CK2 is electrically connected to the second scan signal line CNB; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0365] Figure 39 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 39, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CKKB, a first high-level power line VGH1, a first low-level power line VGL1 and a second high-level power line VGH2; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2 and a third power terminal V3.

[0366] In an exemplary embodiment, as shown in Figure 39, the first power supply terminal V1 of at least one stage shift register is electrically connected to the first high-level power supply line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1, and the third power supply terminal V3 is electrically connected to the second high-level power supply line VGH2; the first signal input terminal IN1 of the first stage shift register in the gate drive circuit is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0367] Figure 40 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 40, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scan signal line CN, a first high-level power line VGH1, a first low-level power line VGL1 and a second high-level power line VGH2; at least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal IN1, a second signal input terminal IN2 and a first control signal terminal CK1, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2 and a third power terminal V3.

[0368] In an exemplary embodiment, as shown in Figure 40, the first power supply terminal V1 of at least one stage shift register is electrically connected to the first high-level power supply line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1, the third power supply terminal V3 is electrically connected to the second high-level power supply line VGH2, and the first control signal terminal CK1 is electrically connected to the first scan signal line CN; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0369] Figure 41 is a structural circuit diagram of a display device provided by an exemplary embodiment. As shown in Figure 41, it may also include: an initial signal line, a first clock signal line CLKA, a second clock signal line CLKB, a first scan signal line CN, a second scan signal line CNB, a first high-level power line VGH1, a first low-level power line VGL1 and a second high-level power line VGH2; at least one input signal terminal of at least one level of shift register includes: a first signal input terminal IN1, a second signal input terminal IN2, a first control signal terminal CK1 and a second control signal terminal CK2, and at least one power signal terminal includes: a first power terminal V1, a second power terminal V2 and a third power terminal V3.

[0370] In an exemplary embodiment, as shown in Figure 41, the first power supply terminal V1 of at least one stage of the shift register is electrically connected to the first high-level power supply line VGH1, the second power supply terminal V2 is electrically connected to the first low-level power supply line VGL1, the third power supply terminal V3 is electrically connected to the second high-level power supply line VGH2, and the first control signal terminal CK1 is electrically connected to the first scan signal line CN; the first signal input terminal IN1 of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal CLK of the j-th stage shift register is electrically connected to the first clock signal line CLKA, and the clock signal terminal CLK of the j+1-th stage shift register is electrically connected to the second clock signal line CLKB, 1≤j≤M-1, M is the total number of stages of the shift register.

[0371] The present disclosure also provides a shift register driving method, which is configured to drive the shift register. The shift register driving method may include:

[0372] The input sub-circuit provides a signal to the first node under the control of the clock signal terminal and the signal of the input signal group;

[0373] The output sub-circuit provides a signal to the output signal group under the control of the signal of the first node and the power signal group.

[0374] The shift register is the shift register provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0375] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0376] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0377] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register comprising: an input subcircuit and an output subcircuit; The input sub-circuit is electrically connected to the first node, the clock signal terminal and the input signal group, respectively, and is configured to provide a signal to the first node under the control of the signals of the clock signal terminal and the input signal group; The output sub-circuit is electrically connected to the first node, the power signal group and the output signal group, respectively, and is configured to provide a signal to the output signal group under the control of the signals of the first node and the power signal group; The input signal group includes: at least one input signal terminal, the power signal group includes: at least one power signal terminal, and the output signal group includes: at least one output signal terminal; The at least one input signal terminal includes: a first signal input terminal; the input sub-circuit is configured to provide a signal of the first signal input terminal to the first node under the control of a signal of the clock signal terminal; The input subcircuit includes: a first transistor; a control electrode of the first transistor is electrically connected to the clock signal terminal, a first electrode of the first transistor is electrically connected to the first signal input terminal, and a second electrode of the first transistor is electrically connected to the first node.

2. The shift register according to claim 1, wherein: The at least one input signal terminal further comprises: a second signal input terminal and a first control signal terminal; The input sub-circuit is further configured to provide a signal from the first signal input terminal or the second signal input terminal to the first node under the control of the signals from the clock signal terminal and the first control signal terminal.

3. The shift register according to claim 2, wherein: The input sub-circuit further includes a second transistor and a third transistor, wherein the first electrode of the first transistor is electrically connected to the first signal input terminal through the second transistor; The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the first signal input terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second signal input terminal, and the second electrode of the third transistor is electrically connected to the second node.

4. The shift register according to claim 3, wherein: The first transistor is an N-type transistor, one of the second transistor and the third transistor is a P-type transistor, and the other is an N-type transistor.

5. The shift register according to claim 1, wherein: The at least one input signal terminal further comprises: a second signal input terminal, a first control signal terminal, and a second control signal terminal; The input sub-circuit is further configured to provide a signal from the first signal input terminal or the second signal input terminal to the first node under the control of signals from the clock signal terminal, the first control signal terminal and the second control signal terminal. The shift register according to claim 5 , wherein: The input sub-circuit further includes: a second transistor and a third transistor, wherein the first electrode of the first transistor is electrically connected to the first signal input terminal via the second transistor; The control electrode of the first transistor is electrically connected to the clock signal terminal, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the first signal input terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the second control signal terminal, the first electrode of the third transistor is electrically connected to the second signal input terminal, and the second electrode of the third transistor is electrically connected to the second node.

7. The shift register according to claim 6, wherein: The first transistor is an N-type transistor, and the second transistor and the third transistor are both N-type transistors or P-type transistors.

8. The shift register according to claim 5, wherein: The voltage value of the signal at the first control signal terminal is constant, the voltage value of the signal at the second control signal terminal is constant, and the time when the signal at the first control signal terminal is a valid level signal does not overlap with the time when the signal at the second control signal terminal is a valid level signal.

9. The shift register according to claim 8, wherein: The shift register is provided on a display substrate, and the display substrate includes: a first scanning mode and a second scanning mode; In the first scanning mode, the signal at the first control signal end is a valid level signal, and the signal at the second control signal end is an invalid level signal. In the second scanning mode, the signal at the first control signal end is an invalid level signal, and the signal at the second control signal end is a valid level signal.

10. The shift register according to claim 1, wherein: At least one power signal terminal includes: a first power terminal and a second power terminal, and at least one output signal terminal includes: a signal output terminal; The output sub-circuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of a signal of the first node.

11. The shift register according to claim 10, wherein: The output sub-circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor; The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the signal output terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal; The control electrode of the sixth transistor is electrically connected to the second power supply terminal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the third node; The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the signal output terminal; The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the signal output terminal.

12. The shift register according to claim 11, wherein: The fourth transistor is an N-type transistor, and the fifth and sixth transistors are P-type transistors.

13. The shift register according to claim 10, wherein: The first power supply terminal continuously provides a high level signal, and the second power supply terminal continuously provides a low level signal.

14. The shift register according to claim 1, wherein: At least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal; at least one output signal terminal includes: a signal output terminal and a cascade output terminal; The output subcircuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal and provide a signal of the first power supply terminal or the third power supply terminal to the cascade output terminal under the control of a signal of the first node.

15. The shift register according to claim 14, wherein: The output sub-circuit includes: a seventh transistor to a sixteenth transistor, a third capacitor and a fourth capacitor; The control electrode of the seventh transistor is electrically connected to the first power supply terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the fourth node; a control electrode of the eighth transistor electrically connected to the fourth node, a first electrode of the eighth transistor electrically connected to the first power supply terminal, and a second electrode of the eighth transistor electrically connected to the cascade output terminal; The control electrode of the ninth transistor is electrically connected to the third node, and the first electrode of the ninth transistor is electrically connected to the cascade output terminal. The second electrode of the ninth transistor is electrically connected to the fifth node; a control electrode of the tenth transistor electrically connected to the third node, a first electrode of the tenth transistor electrically connected to the fifth node, and a second electrode of the tenth transistor electrically connected to the fourth power supply terminal; a control electrode of the eleventh transistor electrically connected to the fourth power supply terminal, a first electrode of the eleventh transistor electrically connected to the first node, and a second electrode of the eleventh transistor electrically connected to the third node; A control electrode of the twelfth transistor is electrically connected to the cascade output terminal, a first electrode of the twelfth transistor is electrically connected to the fifth node, and a second electrode of the twelfth transistor is electrically connected to the third power supply terminal; a control electrode of the thirteenth transistor electrically connected to the fourth node, a first electrode of the thirteenth transistor electrically connected to the first power supply terminal, and a second electrode of the thirteenth transistor electrically connected to the signal output terminal; a control electrode of the fourteenth transistor electrically connected to the third node, a first electrode of the fourteenth transistor electrically connected to the signal output terminal, and a second electrode of the fourteenth transistor electrically connected to the sixth node; a control electrode of the fifteenth transistor electrically connected to the third node, a first electrode of the fifteenth transistor electrically connected to the sixth node, and a second electrode of the fifteenth transistor electrically connected to the second power supply terminal; A control electrode of the sixteenth transistor is connected to the signal output terminal, a first electrode of the sixteenth transistor is electrically connected to the sixth node, and a second electrode of the sixteenth transistor is electrically connected to the third power supply terminal; The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the signal output terminal; The fourth capacitor includes a first plate and a second plate. The first plate of the fourth capacitor is electrically connected to the third node, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal.

16. The shift register according to claim 15, wherein: The seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the sixteenth transistor are N-type transistors, and the ninth to eleventh transistors, the fourteenth transistor, and the fifteenth transistor are P-type transistors.

17. The shift register according to claim 14, wherein: The first power supply terminal and the third power supply terminal continuously provide high-level signals, and the second power supply terminal and the fourth power supply terminal continuously provide low-level signals; The voltage value of the first power supply terminal is less than or equal to the voltage value of the third power supply terminal, and the voltage value of the fourth power supply terminal is greater than the voltage value of the second power supply terminal.

18. The shift register according to claim 1, wherein: The at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal; the at least one output signal terminal includes: a signal output terminal; The output sub-circuit is configured to provide a signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of a signal of the first node.

19. The shift register according to claim 18, wherein: The output sub-circuit includes: a seventeenth transistor to a twenty-first transistor and a first capacitor; The control electrode of the seventeenth transistor is electrically connected to the first node, the first electrode of the seventeenth transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the signal output terminal; The control electrode of the eighteenth transistor is electrically connected to the third node, the first electrode of the eighteenth transistor is electrically connected to the signal output terminal, and the second electrode of the eighteenth transistor is electrically connected to the fifth node; a control electrode of the nineteenth transistor electrically connected to the third node, a first electrode of the nineteenth transistor electrically connected to the fifth node, and a second electrode of the nineteenth transistor electrically connected to the second power supply terminal; The control electrode of the twentieth transistor is electrically connected to the second power supply terminal, the first electrode of the twentieth transistor is electrically connected to the first node, and the second electrode of the twentieth transistor is electrically connected to the third node; A control electrode of the twenty-first transistor is electrically connected to the signal output terminal, a first electrode of the twenty-first transistor is electrically connected to the fifth node, and a second electrode of the twenty-first transistor is electrically connected to the third power supply terminal; The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the signal output end.

20. The shift register according to claim 19, wherein: The seventeenth transistor and the twenty-first transistor are N-type transistors, and the eighteenth transistor to the twentieth transistor are P-type transistors.

21. The shift register according to claim 18, wherein: The first power supply terminal and the third power supply terminal continuously provide a high level signal, and the second power supply terminal continuously provides a low level signal; The voltage value of the first power supply terminal is less than or equal to the voltage value of the third power supply terminal.

22. A gate drive circuit comprising: A plurality of cascaded shift registers according to any one of claims 1 to 21.

23. The gate driving circuit according to claim 22, wherein: The at least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, and the at least one output signal terminal of the at least one stage shift register includes: a signal output terminal; The signal output terminal of the i-th stage shift register is electrically connected to the first signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

24. The gate driving circuit according to claim 22, wherein: At least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, and at least one output signal terminal of the at least one stage shift register includes: a signal output terminal and a cascade output terminal; The cascade output terminal of the i-th stage shift register is electrically connected to the first signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

25. The gate driving circuit according to claim 22, wherein: At least one input signal terminal of the at least one stage shift register includes: a first signal input terminal and a second signal input terminal, and at least one output signal terminal of the at least one stage shift register includes: a signal output terminal; The signal output end of the i-th stage shift register is electrically connected to the first signal input end of the i+1-th stage shift register, and the signal output end of the i+1-th stage shift register is electrically connected to the second signal input end of the i-th stage shift register, 1≤i≤M-1, M is the total number of shift registers.

26. The gate driving circuit according to claim 22, wherein: At least one input signal terminal of the at least one stage shift register includes: a first signal input terminal and a second signal input terminal; at least one output signal terminal of the at least one stage shift register includes: a signal output terminal and a cascade output terminal; The cascade output end of the i-th stage shift register is electrically connected to the first signal input end of the i+1-th stage shift register, and the cascade output end of the i+1-th stage shift register is electrically connected to the second signal input end of the i-th stage shift register, 1≤i≤M-1, M is the total number of shift registers.

27. A display device comprising the gate driving circuit according to any one of claims 22 to 26.

28. The display device according to claim 27, wherein: Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first high level power line and a first low level power line; At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, and the second power supply terminal is electrically connected to the first low-level power supply line; the first signal input terminal of the first shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of shift registers.

29. The display device according to claim 27, wherein It also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high level power line and a first low level power line; At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, and the first control signal terminal is electrically connected to the first scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

30. The display device according to claim 27, wherein It also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high level power line and a first low level power line; At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal and a second power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the first control signal terminal is electrically connected to the first scanning signal line, and the second control signal terminal is electrically connected to the second scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

31. The display device according to claim 27, wherein Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first high level power line, a first low level power line, a second high level power line, and a second low level power line; At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, and the fourth power supply terminal is electrically connected to the second low-level power supply line; the first signal input terminal of the first shift register is electrically connected to the initial signal line, and the j-th shift register is electrically connected to the initial signal line. The clock signal end of the shift register is electrically connected to the first clock signal line, and the clock signal end of the j+1th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

32. The display device according to claim 27, wherein Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high level power line, a first low level power line, a second high level power line, and a second low level power line; At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the fourth power supply terminal is electrically connected to the second low-level power supply line, and the first control signal terminal is electrically connected to the first scan signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

33. The display device according to claim 27, wherein Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high level power line, a first low level power line, a second high level power line, and a second low level power line; At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal, a third power terminal and a fourth power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the fourth power supply terminal is electrically connected to the second low-level power supply line, the first control signal terminal is electrically connected to the first scanning signal line, and the second control signal terminal is electrically connected to the second scanning signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

34. The display device according to claim 27, wherein Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first high level power line, a first low level power line, and a second high level power line; At least one input signal terminal of at least one stage of the shift register in the gate drive circuit includes: a first signal input terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal; The first power supply terminal of at least one stage of the shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, and the third power supply terminal is electrically connected to the second high-level power supply line; the first signal input terminal of the first stage of the shift register in the gate drive circuit is electrically connected to the initial signal line, the clock signal terminal of the j-th stage of the shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage of the shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

35. The display device according to claim 27, wherein It also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a first high-level power line, a first low-level power line, and a second high-level power line; At least one input signal terminal of the shift register of at least one stage in the gate drive circuit includes: a first signal input terminal, a second signal input terminal and a first control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal; The first power supply terminal of at least one shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, and the first control signal terminal is electrically connected to the first scan signal line; the first signal input terminal of the first-stage shift register is electrically connected to the initial signal line, the clock signal terminal of the j-th stage shift register is electrically connected to the first clock signal line, and the clock signal terminal of the j+1-th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

36. The display device according to claim 27, wherein Also includes: an initial signal line, a first clock signal line, a second clock signal line, a first scan signal line, a second scan signal line, a first high level power line, a first low level power line, and a second high level power line; At least one input signal terminal of the at least one stage shift register includes: a first signal input terminal, a second signal input terminal, a first control signal terminal and a second control signal terminal, and at least one power signal terminal includes: a first power terminal, a second power terminal and a third power terminal; The first power supply terminal of at least one stage of the shift register is electrically connected to the first high-level power supply line, the second power supply terminal is electrically connected to the first low-level power supply line, the third power supply terminal is electrically connected to the second high-level power supply line, the first control signal terminal is electrically connected to the first scan signal line, and the second control signal terminal is electrically connected to the second scan signal line; the first signal input terminal of the first stage of the shift register is electrically connected to the initial signal line, and the clock signal terminal of the j-th stage of the shift register is electrically connected to the first clock signal line. The clock signal terminal of the j+1th stage shift register is electrically connected to the second clock signal line, 1≤j≤M-1, and M is the total number of stages of the shift register.

37. A method for driving a shift register, configured to drive the shift register according to any one of claims 1 to 21, the method comprising: The input sub-circuit provides a signal to the first node under the control of the clock signal terminal and the signal of the input signal group; The output sub-circuit provides a signal to the output signal group under the control of the signal of the first node and the power signal group.

Images