Display panel, display device, and tiled display device

Abstract

A display panel, a display device, and a tiled display device. The display panel comprises a substrate and a plurality of connection leads. The substrate comprises a first surface and a second surface arranged opposite to each other, and at least one side surface connecting the first surface and the second surface, wherein the at least one side surface is a selected side surface. Each connection lead among the plurality of connection leads extends from the first surface, through the selected side surface, to the second surface. The plurality of connection leads comprises a first connection lead and a second connection lead, wherein the first connection lead and the second connection lead are adjacent in a direction perpendicular to the surface of the substrate and are arranged in different layers. The display panel is used for displaying an image.

Description

Display panel, display device and spliced display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel, a display device and a spliced display device. BACKGROUND

[0002] Micro Light-emitting Diode (Micro LED) or Mini Light-emitting Diode (Mini LED) is widely concerned and researched as a pixel of a display panel. At present, due to the problem of huge transfer yield of Micro LED and Mini LED display panels, a large-size display device cannot be manufactured at one time, and a small-size display device is usually used to assemble a large-size spliced display device.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided, comprising a substrate and a plurality of connection leads.

[0005] The substrate comprises a first surface and a second surface arranged oppositely, and at least one side surface connecting the first surface and the second surface, the at least one side surface being a selected side surface.

[0006] Each of the plurality of connection leads extends from the first surface to the second surface through the selected side surface.

[0007] The plurality of connection leads comprises a first connection lead and a second connection lead, the first connection lead and the second connection lead being arranged adjacent to and in different layers in a direction perpendicular to the surface of the substrate.

[0008] In some embodiments, the orthographic projections of the first connection lead and the second connection lead on the substrate at least partially overlap.

[0009] In some embodiments, the line widths of the first connection lead and the second connection lead are different.

[0010] In some embodiments, the signals transmitted by the first connection lead and the second connection lead are different.

[0011] In some embodiments, one of the first connection lead and the second connection lead is in contact with the surface of the substrate.

[0012] In some embodiments, the display panel further comprises a plurality of front electrodes and a plurality of back electrodes.

[0013] A plurality of front electrodes are disposed on the first surface side of the substrate, the plurality of front electrodes including a first electrode and a second electrode, the first electrode and the second electrode being adjacently disposed.

[0014] A plurality of back electrodes are disposed on the second surface side of the substrate, the plurality of back electrodes including a third electrode and a fourth electrode, the third electrode and the fourth electrode being adjacently disposed.

[0015] The first connecting lead is configured to connect the first electrode and the third electrode, and the second connecting lead is configured to connect the second electrode and the fourth electrode.

[0016] The first electrode and the third electrode at least partially overlap in orthographic projection on the second surface, and the second electrode and the fourth electrode at least partially overlap in orthographic projection on the second surface.

[0017] In some embodiments, the first electrode and the second electrode are disposed in the same layer, and / or the third electrode and the fourth electrode are disposed in the same layer.

[0018] In some embodiments, one of the first connecting lead and the second connecting lead is directly connected to the front electrodes and the back electrodes, and the other is connected to the front electrodes and the back electrodes through a via.

[0019] In some embodiments, the first electrode and the second electrode are disposed in different layers, and the first electrode is closer to the first surface relative to the second electrode.

[0020] In some embodiments, the third electrode and the fourth electrode are disposed in different layers, and the third electrode is closer to the second surface relative to the fourth electrode.

[0021] In some embodiments, the first connecting lead is closer to the substrate relative to the second connecting lead.

[0022] In some embodiments, the orthographic projection of the first electrode on the first surface at least partially coincides with the orthographic projection of the second electrode on the first surface.

[0023] In some embodiments, the orthographic projection of the third electrode on the second surface at least partially coincides with the orthographic projection of the fourth electrode on the second surface.

[0024] In some embodiments, the display panel further includes a plurality of pixel units on the first surface. The plurality of pixel units includes two pixel units adjacent in the first direction and both close to the selected side, and the first electrode and the second electrode are disposed between the two pixel units.

[0025] In some embodiments, the display panel further comprises a plurality of pixel units on the first surface. The plurality of pixel units comprises two pixel units adjacent to each other in a first direction and each close to the selected side.

[0026] The first connecting lead and the second connecting lead are disposed between the two pixel units.

[0027] In some embodiments, the display panel further comprises a plurality of pixel units on the first surface. The plurality of pixel units comprises two pixel units adjacent to each other in a first direction and each close to the selected side.

[0028] In a second direction, the first electrode and the second electrode at least partially overlap with the two pixel units. The second direction is perpendicular to the first direction

[0029] In some embodiments, the display panel further comprises a first insulating layer. The first insulating layer is between the first connecting lead and the second connecting lead.

[0030] In some embodiments, the display panel further comprises at least one recessed region on at least the selected side of the substrate.

[0031] The one of the first connecting lead and the second connecting lead closer to the substrate has a footprint on the selected side within the recessed region.

[0032] In some embodiments, a ratio of a size of the recessed region along the first direction to a size of the first connecting lead along the first direction is 1-2.

[0033] In some embodiments, the display panel further comprises a protective layer. The protective layer covers at least the second connecting lead, and the front electrode and the back electrode connected to the second connecting lead.

[0034] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments and a circuit board. The circuit board is electrically connected to the display panel, and the circuit board is configured to drive the display panel to display an image.

[0035] In yet another aspect, a tiled display device is provided, comprising a plurality of display panels according to any one of the above embodiments and at least one circuit board.

[0036] The plurality of display panels are tiled, and each of the at least one circuit board is electrically connected to at least one of the display panels. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0038] FIG. 1 is a structural diagram of a tiled display device according to some embodiments;

[0039] FIG. 2 is a structural diagram of a display device according to some embodiments;

[0040] FIG. 3 is a sectional view of the display panel in FIG. 2 along section line B-B;

[0041] FIG. 4 is a structural diagram of a partial region of a display panel according to some embodiments;

[0042] FIG. 5A is another structural diagram of a partial region of a display panel according to some embodiments;

[0043] FIG. 5B is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0044] FIG. 6 is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0045] FIG. 7 is a structural diagram of a display panel according to some embodiments;

[0046] FIG. 8A is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0047] FIG. 8B is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0048] FIG. 9A is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0049] FIG. 9B is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0050] FIG. 9C is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0051] FIG. 9D is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0052] FIG. 10A is yet another structural diagram of a partial region of a display panel according to some embodiments;

[0053] FIG. 10B is yet another diagram of a local area of a display panel, according to some embodiments;

[0054] FIG. 10C is yet another diagram of a local area of a display panel, according to some embodiments;

[0055] FIG. 10D is yet another diagram of a local area of a display panel, according to some embodiments;

[0056] FIG. 11A is yet another diagram of a local area of a display panel, according to some embodiments;

[0057] FIG. 11B is yet another diagram of a local area of a display panel, according to some embodiments;

[0058] FIG. 12A is yet another diagram of a local area of a display panel, according to some embodiments;

[0059] FIG. 12B is yet another diagram of a local area of a display panel, according to some embodiments;

[0060] FIG. 13A is yet another diagram of a local area of a display panel, according to some embodiments;

[0061] FIG. 13B is yet another diagram of a local area of a display panel, according to some embodiments;

[0062] FIG. 13C is a cross-sectional view of the display panel in FIG. 12A along section line H-H;

[0063] FIG. 13D is another cross-sectional view of the display panel in FIG. 12A along section line H-H;

[0064] FIG. 13E is yet another cross-sectional view of the display panel in FIG. 12A along section line H-H;

[0065] FIG. 14A is yet another diagram of a local area of a display panel, according to some embodiments;

[0066] FIG. 14B is yet another diagram of a local area of a display panel, according to some embodiments;

[0067] FIG. 15A is yet another diagram of a local area of a display panel, according to some embodiments;

[0068] FIG. 15B is yet another diagram of a local area of a display panel, according to some embodiments;

[0069] FIG. 15C is yet another diagram of a local area of a display panel, according to some embodiments;

[0070] FIG. 16 is a cross-sectional view of the display panel in FIG. 15A along section line G-G;

[0071] FIG. 17 is another cross-sectional view of the display panel in FIG. 15A along section line G-G;

[0072] FIG. 18 is a cross-sectional view of a local area of a display panel according to some embodiments;

[0073] FIG. 19A is yet another structural view of a local area of a display panel according to some embodiments;

[0074] FIG. 19B is yet another structural view of a local area of a display panel according to some embodiments;

[0075] FIG. 20A is yet another structural view of a local area of a display panel according to some embodiments;

[0076] FIG. 20B is yet another structural view of a local area of a display panel according to some embodiments. DETAILED DESCRIPTION

[0077] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0078] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, and other forms thereof, are used herein in an open-ended way to mean including but not limited to. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” etc. are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0079] The terms "first", "second", etc. are used herein only to describe one ordinal number, and do not necessarily indicate or imply a relative importance or a specific order. Thus, a feature defined with "first", "second" may include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is two or more unless otherwise specified.

[0080] In describing some embodiments, "coupled" and "connected", and variations thereof, can be used. The term "connected" is used broadly and encompass both direct and indirect connections, such as fixed or detachable connections, or integrally formed; and can be direct connections or indirect connections through an intermediate media. The term "coupled" means, for example, that two or more elements are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more elements are in contact with each other, but not necessarily directly. The embodiments disclosed herein are not necessarily limited to the context.

[0081] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", both of which include the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0082] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0083] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "upon" or "in response to a determination" or "in response to a detection of", depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" is, optionally, interpreted as meaning "upon determining" or "in response to a determination" or "upon detecting [a stated condition or event]" or "in response to a detection of [a stated condition or event]", depending on the context.

[0084] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not explicitly described.

[0085] In addition, the use of "based on" means open and inclusive, as the process, step, calculation, or other action based on one or more recited conditions or values can be based on additional conditions or values not recited.

[0086] As used herein, "about," "approximately," or "around" includes the value recited and the average value within an acceptable range of deviation from that value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0087] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, for example, a difference between the two that is less than or equal to 5% of either.

[0088] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0089] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features can be shown in the drawings. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, manufacturing or processing tolerances, variations from manufacturing to manufacturing, variations in the manufacturing process, and / or variations in materials. Thus, the exemplary embodiments are not to be construed as limited to the specific illustrative examples that are described herein but are to be construed broadly.

[0090] For the convenience of the following description, an XYZ coordinate system is established. A third direction Z is a thickness direction of the tiled display device or the display device, an XY plane is perpendicular to the Z direction, a first direction X and a second direction Y are crossed. For example, the first direction X and the second direction Y are perpendicular to each other.

[0091] As shown in FIG. 1, some embodiments of the present disclosure provide a tiled display device 1000 including a plurality of display panels 10 tiled together and at least one circuit board (not shown in the figure). Each circuit board is electrically connected to at least one display panel 10 for controlling the display panel 10 to emit light and realize the display function of the display panel 10.

[0092] By tiling a plurality of display panels 10 to form a large-size tiled display device 1000, the product reliability can be improved, and the transportation cost and maintenance cost can be reduced.

[0093] Exemplarily, the number of circuit boards in the tiled display device 1000 can be one, and the plurality of display panels 10 are connected to the same circuit board.

[0094] The number of circuit boards can also be multiple, for example, each display panel 10 in the plurality of display panels 10 is connected to one circuit board, that is, the display panel 10 and the circuit board are connected one by one; for another example, the plurality of display panels 10 are divided into multiple groups, and each group of display panels 10 is connected to one circuit board, wherein the number of display panels 10 in each group of display panels 10 can be the same or different.

[0095] Exemplarily, the circuit board includes but is not limited to a PCB (Printed Circuit Board) and an FPC (Flexible Printed Circuit Board).

[0096] As shown in FIG. 2, some embodiments of the present disclosure also provide a display device 100, which can be a standalone display device or used to tile to form the above-mentioned tiled display device 1000.

[0097] Exemplarily, the display device 100 can be a television, a display, a notebook computer, a tablet computer, a mobile phone, a navigator, or any product or component having a display function. In FIG. 2, the display device 100 is exemplarily taken as a mobile phone.

[0098] Exemplarily, the display device 100 can be a Micro LED (Micro Light-emitting Diode) or a Mini LED (Mini Light-emitting Diode).

[0099] The display device 100 can also be an electroluminescent display device or a photoluminescent display device. In the case where the display device 100 is an electroluminescent display device, the electroluminescent display device can be an organic electroluminescent display device (OLED) or a quantum dot electroluminescent display device (QLED). In the case where the display device 100 is a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device.

[0100] Please continue to refer to FIG. 2, the display device 100 includes a display panel 10 and a circuit board (not shown in the figure). The circuit board is electrically connected with the display panel 10 and is configured to drive the display panel 10 to display an image.

[0101] The display panel 10 is described in detail as follows.

[0102] The display panel 10 can be a Micro LED display panel or a Mini LED display panel, or an OLED display panel.

[0103] For example, when the display panel 10 is a Micro LED display panel or a Mini LED display panel, the Micro LED display panel or the Mini LED display panel includes an array substrate and micro light emitting diodes or submillimeter light emitting diodes on the array substrate.

[0104] For another example, when the display panel 10 is an OLED display panel, the OLED display panel includes an array substrate and a pixel definition layer on the array substrate, and an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode are sequentially arranged in a pixel definition region of the pixel definition layer.

[0105] Some embodiments of the present disclosure are described illustratively below by taking the display panel 10 as a Micro LED display panel or a Mini LED display panel, but the embodiments of the present disclosure include but are not limited to this, and any other display panel can also be considered as long as the same technical idea is applied.

[0106] Exemplarily, the display panel 10 can have a rectangular structure, a circular structure, or other shapes with corners, and the present disclosure does not make any specific limitation on this.

[0107] It should be noted that the "rectangular structure" refers to the shape of the boundary of the display panel 10 as a whole, but is not limited to a standard rectangle. That is, the "rectangle" here not only includes the shape of a standard rectangle, but also includes shapes similar to a rectangle in consideration of process conditions. For example, the long side and the short side of the rectangle are curved at each intersection (i.e., at the corners), that is, the corners are smooth, so that the shape of the boundary of the display panel 10 in the plan view is a rounded rectangle.

[0108] The display panel 10 is taken as an example of a rectangular structure below to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure include but are not limited to this, and the shape of the display panel 10 can also consider any other shape.

[0109] In some embodiments, as shown in FIG. 3, which is a sectional view of the display panel 10 in FIG. 2 along the section line B-B. The display panel 10 has a display area AA for displaying an image, and a peripheral area AN located at least one side of the display area AA.

[0110] For example, the peripheral area AN is located at one side of the display area AA.

[0111] For another example, the peripheral area AN is located at opposite sides of the display area AA.

[0112] For another example, the peripheral area AN surrounds the display area AA.

[0113] It should be noted that the specific arrangement of the peripheral area AN is related to the specific design of the display panel 10, and can be designed according to actual needs, which is only illustrative and not limiting to the present disclosure.

[0114] In some embodiments, as shown in FIG. 3, the display area AA of the display panel 10 is provided with a plurality of pixel units P, and each pixel unit P includes at least three color sub-pixels 3. The sub-pixel 3 is the smallest pixel unit in the display area AA.

[0115] The "each pixel unit P includes at least three color sub-pixels 3" means that each pixel unit P can include three, four or more sub-pixels 3, and the plurality of sub-pixels 3 included in each pixel unit P can be a row, a column or a group of sub-pixels 3. A group of sub-pixels 3 can be a plurality of sub-pixels 3 adjacent to each other, arranged in a row, a column, an L shape, a rectangle or a diamond shape, etc. At the same time, the light emitting area of the plurality of sub-pixels 3 included in each pixel unit P can be the same or not exactly the same. The above is only illustrative and not limiting to the present disclosure, and can be adaptively designed according to actual needs.

[0116] In some examples, the plurality of sub-pixels 3 emit light rays of the same color, and the display panel 10 can further include a color film layer disposed on the light-emitting side of the plurality of sub-pixels 3.

[0117] For example, the plurality of sub-pixels 3 emit light rays of the same color, such as white light, red light, green light, or blue light, and in this case, the color light emitted by the sub-pixel 3 remains the same color after passing through the color film layer and is emitted, or is converted into light of another color and is emitted, so that the display panel 10 can realize multi-color light emission when the plurality of sub-pixels 3 emit light of the same color.

[0118] In other examples, the plurality of sub-pixels 3 emit light rays of different colors, for example, the plurality of sub-pixels 3 include red sub-pixels emitting red light rays, green sub-pixels emitting green light rays, and blue sub-pixels emitting blue light rays, so as to realize multi-color light emission of the display panel 10.

[0119] For example, the driving assembly can include a thin film transistor, and the light-emitting assembly can include a mini LED or a micro LED.

[0120] For example, the plurality of pixel units P are arranged in multiple rows and multiple columns, that is, the plurality of pixel units P are arranged in an array along the first direction X and the second direction Y.

[0121] In some embodiments, the peripheral area AN of the display panel 10 can be used to dispose peripheral circuits and signal lines of the display area AA.

[0122] In some embodiments, as shown in FIG. 3, the display panel 10 further includes a substrate 1. The substrate 1 includes a first surface 1a and a second surface 1b disposed opposite to each other, and at least one side surface 1c connecting the first surface 1a and the second surface 1b. The pixel unit P mentioned above is disposed on the first surface 1a of the substrate 1.

[0123] For example, the material of the substrate 1 includes but is not limited to glass, quartz, plastic, etc. The material of the substrate 1 can also be a flexible material. For example, the material of the substrate 1 includes but is not limited to FPC, PI base film (Polyimide Film), etc.

[0124] It should be noted that the material of the substrate 1 is related to the specific design of the display panel 10, and can be selected according to actual needs, which is only used as an example for illustration and does not limit the present disclosure.

[0125] For example, as shown in FIG. 3, the side surface 1c is perpendicular or substantially perpendicular to the first surface 1a and the second surface 1b.

[0126] In some embodiments, please refer to FIG. 3, the substrate 1 further comprises a first chamfer surface 1d and a second chamfer surface 1e. The first chamfer surface 1d connects the first surface 1a of the substrate 1 and the side surface 1c of the substrate 1, and the second chamfer surface 1e connects the second surface 1b of the substrate 1 and the side surface 1c of the substrate 1.

[0127] For example, the first chamfer surface 1d and the second chamfer surface 1e can be arc surfaces or be inclined surfaces. In FIG. 3, only the first chamfer surface 1d and the second chamfer surface 1e are taken as examples to be arc surfaces.

[0128] For example, when the first chamfer surface 1d of the substrate 1 is an arc surface, the first surface 1a can be relatively gently transitioned to the side surface 1c by the first chamfer surface 1d, or the side surface 1c can be relatively gently transitioned to the first surface 1a by the first chamfer surface 1d.

[0129] Similarly, when the second chamfer surface 1e of the substrate 1 is also an arc surface, the second surface 1b can be relatively gently transitioned to the side surface 1c by the second chamfer surface 1e, or the side surface 1c can be relatively gently transitioned to the second surface 1b by the second chamfer surface 1e.

[0130] For example, when the first chamfer surface 1d of the substrate 1 is an inclined surface, the included angle between the first chamfer surface 1d and the first surface 1a of the substrate 1 and the included angle between the first chamfer surface 1d and the side surface 1c of the substrate 1 are obtuse angles, the first surface 1a can be relatively gently transitioned to the side surface 1c by the first chamfer surface 1d, or the side surface 1c can be relatively gently transitioned to the first surface 1a by the first chamfer surface 1d.

[0131] Similarly, when the second chamfer surface 1e of the substrate 1 is also an inclined surface, the second surface 1b can be relatively gently transitioned to the side surface 1c by the second chamfer surface 1e, or the side surface 1c can be relatively gently transitioned to the second surface 1b by the second chamfer surface 1e.

[0132] Hereinafter, some embodiments of the present disclosure are illustratively described with the substrate 1 comprising the first surface 1a, the second surface 1b, the side surface 1c, the first chamfer surface 1d and the second chamfer surface 1e.

[0133] In some embodiments, please refer to FIG. 3 and FIG. 4, the display panel 10 further comprises a plurality of connection leads 2. The plurality of connection leads 2 are arranged at intervals along a first direction X. On the first surface 1a of the substrate 1, the first direction X is perpendicular to the extension direction (a second direction Y) of the connection leads 2.

[0134] Each of the plurality of connection leads 2 extends from the first surface 1a of the substrate 1, through the side surface 1c of the substrate 1, to the second surface 1b of the substrate 1. For ease of description, the side surface 1c where the connection lead 2 is located is collectively referred to as a selected side surface 1cc.

[0135] It should be noted that when the substrate 1 includes multiple side surfaces 1c, the present disclosure does not limit the structure of other side surfaces 1c (i.e. side surfaces 1c other than the selected side surface 1cc) among the multiple side surfaces 1c. Exemplarily, when the display panel 10 is of a rectangular structure, it has four side surfaces 1c. For example, the four side surfaces 1c of the substrate 1 can all be the selected side surface 1cc; for another example, as shown in FIG. 3, one side surface 1c among the four side surfaces 1c of the substrate 1 is the selected side surface 1cc, and the structure of the other three side surfaces 1c is not limited.

[0136] Please continue to refer to FIG. 3, it can be understood that when the substrate 1 has the first chamfer surface 1d and the second chamfer surface 1e, each of the plurality of connecting leads 2 extends from the first surface 1a of the substrate 1, passes through the first chamfer surface 1d of the substrate 1, the selected side surface 1cc of the substrate 1 and the second chamfer surface 1e of the substrate 1 in sequence, and extends to the second surface 1b of the substrate 1. When the plurality of connecting leads 2 pass through the first chamfer surface 1d, since the first surface 1a of the substrate 1 can be smoothly transitioned to the selected side surface 1cc from the first chamfer surface 1d, or the selected side surface 1cc can be smoothly transitioned to the first surface 1a from the first chamfer surface 1d, compared with the case that the first surface 1a and the selected side surface 1cc are directly connected (in this case, the included angle between the first surface 1a and the selected side surface 1cc is 90°), in the embodiment of the present disclosure, the stress on each of the plurality of connecting leads 2 at the corner of the first surface 1a and the selected side surface 1cc (i.e. the first chamfer surface 1d) is smaller, reducing the problem of disconnection caused by excessive stress concentration, so that the plurality of connecting leads 2 are not prone to breakage at the corner of the first surface 1a and the selected side surface 1cc (i.e. the first chamfer surface 1d), ensuring that the plurality of connecting leads 2 can stably connect the oppositely arranged first surface 1a and the second surface 1b of the substrate 1, and improving the stability of the display panel 10.

[0137] Similarly, when the plurality of connecting leads 2 pass through the second chamfer surface 1e, the stress on each of the plurality of connecting leads 2 at the corner of the second surface 1b and the selected side surface 1cc (i.e. the second chamfer surface 1e) is smaller, reducing the problem of disconnection caused by excessive stress concentration, so that the plurality of connecting leads 2 are not prone to breakage at the corner of the second surface 1b and the selected side surface 1cc (i.e. the second chamfer surface 1e), ensuring that the plurality of connecting leads 2 can effectively connect the oppositely arranged first surface 1a and the second surface 1b of the substrate 1, and further improving the reliability of the display panel 10.

[0138] In some embodiments, the connecting leads 2 can be prepared by a method of patterning after plating, or can be directly prepared by a printing process.

[0139] Exemplarily, the connection lead 2 is prepared by a printing process, specifically, conductive paste is disposed on the first surface la, the selected side face lcc and the second surface lb of the substrate 1 (when the substrate 1 comprises the first chamfered face ld and the second chamfered face le, conductive paste also needs to be disposed on the first chamfered face ld and the second chamfered face le of the substrate 1), and then the conductive paste is solidified by laser or heating to form the connection lead 2.

[0140] The printing process described above may, for example, include screen printing, pad printing, transfer printing and printing, etc.

[0141] When the printing process described above is a printing process, the printing process may be a stereoscopic printing process. Please continue to refer to FIG. 4, the stereoscopic printing process is to use a printing needle head T with a certain caliber to extrude the conductive paste in the needle tube to a specific position on the substrate 1 by using air pressure, and the conductive paste will form the connection lead 2 after solidification.

[0142] The conductive paste described above may, for example, be silver paste. The silver paste may include silver powder and resin. The silver powder melts at high temperature, so that the silver powder and the resin are connected with each other to achieve the conductive effect.

[0143] In some embodiments, please continue to refer to FIG. 3, the display panel 10 further comprises a plurality of front electrodes 4 and a plurality of back electrodes 5. The plurality of front electrodes 4 are located on the first surface la of the substrate 1, and the plurality of back electrodes 5 are located on the second surface lb of the substrate 1.

[0144] Exemplarily, as shown in FIG. 5A, which is a structural diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure, the plurality of front electrodes 4 are arranged at intervals along the first direction X. The plurality of front electrodes 4 can be disposed in the display area AA of the display panel 10, with the boundary of the first surface la of the substrate 1 close to the selected side face lcc as the first boundary laa, and at least one front electrode 4 is located between two adjacent pixel units P in the row of pixel units P closest to the first boundary laa, that is, the front electrode 4 and the pixel unit P intersect at least one straight line (for example, the straight line CC) parallel to the first boundary laa at the same time, which is beneficial to improve the area ratio of the display area AA on the first surface la of the substrate 1, that is, the front electrode 4 can not occupy the area of the peripheral area AN, which can reduce the area ratio of the peripheral area AN of the display panel 10 on the first surface la of the substrate 1, greatly narrow the frame, and improve the display effect of the display panel 10.

[0145] Alternatively, as shown in FIG. 5B, FIG. 5B is a structural diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure. The plurality of front electrodes 4 are arranged along the first direction X at intervals. The plurality of front electrodes 4 are located in the peripheral area AN of the display panel 10, and the front electrodes 4 are closer to the first boundary 1aa than the pixel units P. There is no straight line parallel to the first boundary 1aa that intersects both the front electrodes 4 and the pixel units P, so that although the area ratio of the peripheral area AN of the display panel 10 on the first surface 1a of the substrate 1 is increased, the front electrodes 4 can be arranged in a larger space, and accordingly, a larger number of front electrodes 4 can be arranged without changing the size of the front electrodes 4, thereby reducing the design difficulty.

[0146] The following is a schematic description of some embodiments of the present disclosure, taking the plurality of front electrodes 4 located in the display area AA of the display panel 10 as an example, but the embodiments of the present disclosure include but are not limited to this, for example, the plurality of front electrodes 4 can also be located in the peripheral area AN of the display panel 10.

[0147] Exemplarily, as shown in FIG. 6, FIG. 6 is a structural diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure. The plurality of back electrodes 5 are arranged along the first direction X at intervals.

[0148] In some embodiments, please continue to refer to FIG. 3, FIG. 5A and FIG. 6, one end of each of the plurality of connection leads 2 is connected to one front electrode 4 located on the first surface 1a of the substrate 1, and the other end is connected to one back electrode 5 located on the second surface 1b of the substrate 1, which can shift the binding area of the display panel 10 to the second surface 1b of the display panel 10, so that the area of the peripheral area AN of the display panel 10 is reduced, which is beneficial to improve the screen-to-body ratio of the display panel 10.

[0149] Further, the screen-to-body ratio of the display device 100 comprising the above-mentioned display panel 10 can also be improved, which is beneficial to realize narrow frame of the display device 100 and improve the display effect of the display device 100.

[0150] Further, when the tiled display device 1000 includes a plurality of display panels 10, for example, as shown in FIG. 1, the peripheral area AN of the display panel 10 is located on one side of the display area AA of the display panel 10, the plurality of display panels 10 are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. In the plurality of display panels 10 that are tiled, the peripheral area AN of the display panel 10 is arranged along the first direction X. In the plurality of display panels 10 arranged in a row along the first direction X, there is substantially no joint gap between the adjacent two display panels 10 along the first direction X. In the plurality of display panels 10 arranged in a column along the second direction Y, there is a joint gap between the adjacent two display panels 10. That is, in the plurality of display panels 10 arranged in a row along the first direction X, the size of the joint gap between the adjacent two display panels 10 is smaller than the size of the joint gap between the adjacent two display panels 10 arranged in a column along the second direction Y.

[0151] When viewing the tiled display device 1000, due to the small area of the peripheral area AN of the display panel 10, the size of the joint gap between the adjacent two display panels 10 arranged in a column along the second direction Y is also small, and the joint gap between the adjacent two display panels 10 is difficult to be discovered by the naked eye within the viewing distance, so that the display image of the tiled display device 1000 is more complete, and a better display effect can be presented.

[0152] With the continuous development of the display panel 10, users have higher and higher requirements for the refresh rate, brightness, and resolution (Pixels Per Inch, PPI) of the display panel 10. The improvement of the refresh rate, brightness, and resolution (Pixels Per Inch, PPI) of the display panel 10 requires more signals to be transmitted from the circuit board to the AA area of the display panel 10. More signal transmission can be achieved by increasing the number of connection leads 2.

[0153] Please continue to refer to FIG. 4. When the number of connection leads 2 is increased, more connection leads 2 can be arranged on the substrate 1 (specifically, the first surface la, the first chamfered surface ld, the selected side face lcc, the second chamfered surface le, and the second surface lb of the substrate 1) by reducing the line width K1 of each connection lead 2 and / or reducing the spacing d1 between the adjacent two connection leads 2, that is, the density of the connection leads 2 is increased.

[0154] It should be noted that the "line width of the connection lead 2" refers to the size of the connection lead 2 along the first direction X. The following description of the "line width of the connection lead 2" also follows this description.

[0155] The "distance between the two adjacent connection leads 2" refers to the distance between the two adjacent connection leads 2 in the first direction X. The following description of the "distance between the two adjacent connection leads 2" also uses this description.

[0156] When the line width K1 of the connection lead 2 is reduced, for example, the connection lead 2 is formed by a printing process, the accuracy requirement of the printing needle T is higher, which increases the difficulty of manufacturing the connection lead 2, and because the line width K1 of the connection lead 2 is small, there is a risk of disconnection in some areas of the connection lead 2, which reduces the reliability of the connection lead 2 and easily affects the normal display of the display panel 10.

[0157] When the distance d1 between the two adjacent connection leads 2 is reduced, the two adjacent connection leads 2 are easily short-circuited, which also affects the normal display of the display panel 10.

[0158] Based on this, in some embodiments, as shown in FIG. 7, FIG. 7 is a structural diagram of a display panel 10 according to some embodiments. The plurality of connection leads 2 includes a first connection lead 21 and a second connection lead 22, and the first connection lead 21 and the second connection lead 22 are adjacent and out of layer in the direction perpendicular to the surface of the substrate 1.

[0159] By making the first connection lead 21 and the second connection lead 22 adjacent and out of layer in the plurality of connection leads 2, that is, the plurality of connection leads 2 are not located in the same film layer, the arrangement mode of the plurality of connection leads 2 is changed from planar arrangement to three-dimensional arrangement. On the one hand, it can reduce the limitation of planar space on the arrangement of the plurality of connection leads 2, and the line width K1 of the connection lead 2 can be widened, which is beneficial to reduce the manufacturing difficulty of the connection lead 2 and improve the reliability of the connection lead 2, and ensure the normal display of the display panel 10.

[0160] On the other hand, it can also increase the distance d1 between the two adjacent first connection leads 21 and the two adjacent second connection leads 22, reduce the probability of short circuit between the two adjacent first connection leads 21 and the two adjacent second connection leads 22, and further ensure the normal display of the display panel 10.

[0161] It should be noted that, in order to facilitate the description of the first connection lead 21 and the second connection lead 22, the second connection lead 22 in FIG. 7 is transparently processed to expose the first connection lead 21 which is relatively closer to the substrate 1.

[0162] Exemplarily, since the first connection lead 21 and the second connection lead 22 are arranged in different layers, i.e., the first connection lead 21 and the second connection lead 22 are respectively located in different film layers, when the first connection lead 21 and the second connection lead 22 are formed, one of the first connection lead 21 and the second connection lead 22 can be formed first, and then the other of the first connection lead 21 and the second connection lead 22 can be formed.

[0163] For example, please continue to refer to FIG. 7, based on the first connection lead 21 being closer to the substrate 1 than the second connection lead 22, the first connection lead 21 can be formed first, and then the second connection lead 22 can be formed on the side of the first connection lead 21 away from the substrate 1.

[0164] Exemplarily, in addition to the film layer for arranging the first connection lead 21 and the film layer for arranging the second connection lead 22, other film layers for arranging the connection lead 2 can also be formed. The film layer for arranging the first connection lead 21, the film layer for arranging the second connection lead 22, and the other film layers for arranging the connection lead 2 can be arranged in a direction perpendicular to the surface of the substrate 1. The limitation of the planar space on the arrangement of the plurality of connection leads 2 can be further reduced, which is conducive to further reducing the preparation difficulty of the connection lead 2, improving the reliability of the connection lead 2, and ensuring the normal display of the display panel 10.

[0165] Exemplarily, the signals transmitted by the first connection lead 21 and the second connection lead 22 are different. For example, the signals transmitted by the first connection lead 21 and the second connection lead 22 can include Vdd signals, Vss signals, Data signals, Vinit signals, Reset signals, and the like.

[0166] Exemplarily, one of the first connection lead 21 and the second connection lead 22 is in contact with the surface of the substrate 1.

[0167] For example, please continue to refer to FIG. 7, based on the first connection lead 21 being closer to the substrate 1 than the second connection lead 22, the first connection lead 21 can be in contact with the surface of the substrate 1. Exemplarily, please continue to refer to FIG. 7, since the first connection lead 21 and the second connection lead 22 are adjacent in the direction perpendicular to the surface of the substrate 1 (for example, on the selected side 1cc of the substrate 1, the first connection lead 21 and the second connection lead 22 are adjacent along the second direction Y), the orthographic projections of the first connection lead 21 and the second connection lead 22 on the substrate 1 can at least partially overlap.

[0168] Please continue to refer to FIG. 7, taking the orthographic projections of the first connection lead 21 and the second connection lead 22 on the plane of the selected side 1cc of the substrate 1 as an example, for example, in the region FF, the orthographic projections of the first connection lead 21 and the second connection lead 22 on the plane of the selected side 1cc of the substrate 1 partially overlap.

[0169] For another example, in the region DD, the area of the orthogonal projection of the first connecting lead 21 on the substrate 1 is smaller than the area of the orthogonal projection of the second connecting lead 22 on the substrate 1, and the orthogonal projection of the first connecting lead 21 on the substrate 1 falls within the range of the orthogonal projection of the second connecting lead 22 on the substrate 1.

[0170] For another example, in the region EE, the area and shape of the orthogonal projection of the first connecting lead 21 on the substrate 1 are the same as the area and shape of the orthogonal projection of the second connecting lead 22 on the substrate 1, and the orthogonal projection of the first connecting lead 21 on the substrate 1 coincides with the orthogonal projection of the second connecting lead 22 on the selected side surface 1cc of the substrate 1.

[0171] Exemplarily, please continue to refer to FIG. 7, the line width of the first connecting lead 21 is K1, and the line width of the second connecting lead 22 is K1’. The line width K1 of the first connecting lead 21 and the line width K1’ of the second connecting lead 22 can be the same, for example, in the region EE, K1 is equal to K1’.

[0172] Alternatively, the line width K1 of the first connecting lead 21 and the line width K1’ of the second connecting lead 22 can also be different. The line width K1 of the first connecting lead 21 and the line width K1’ of the second connecting lead 22 can be set based on actual needs, as long as the reliability of the first connecting lead 21 and the second connecting lead 22 is ensured.

[0173] For example, the line width K1 of the first connecting lead 21 can be set according to the area of the orthogonal projection of the front surface electrode 4 connected with the first connecting lead 21 on the first surface 1a of the substrate 1, or the area of the orthogonal projection of the back surface electrode 5 connected with the first connecting lead 21 on the second surface 1b of the substrate 1, so that the line width K1 of the first connecting lead 21 is positively correlated with the area of the orthogonal projection of the front surface electrode 4 connected with the first connecting lead 21 on the first surface 1a of the substrate 1, or the area of the orthogonal projection of the back surface electrode 5 connected with the first connecting lead 21 on the second surface 1b of the substrate 1, that is, the larger the area of the orthogonal projection of the front surface electrode 4 connected with the first connecting lead 21 on the first surface 1a of the substrate 1, or the larger the area of the orthogonal projection of the back surface electrode 5 connected with the first connecting lead 21 on the second surface 1b of the substrate 1, the larger the line width K1 of the first connecting lead 21.

[0174] Similarly, the line width K1' of the second connection lead 22 can be set according to the area of the front surface electrode 4 connected with the second connection lead 22 in the first surface la of the substrate 1, or the area of the back surface electrode 5 connected with the second connection lead 22 in the second surface lb of the substrate 1, so that the area of the front surface electrode 4 connected with the second connection lead 22 in the first surface la of the substrate 1, or the area of the back surface electrode 5 connected with the second connection lead 22 in the second surface lb of the substrate 1, and the line width K1' of the second connection lead 22 are positively correlated, that is, the greater the area of the front surface electrode 4 connected with the second connection lead 22 in the first surface la of the substrate 1, or the greater the area of the back surface electrode 5 connected with the second connection lead 22 in the second surface lb of the substrate 1, the greater the line width K1' of the second connection lead 22.

[0175] For example, the line width K1 of the first connection lead 21 can be greater than the line width K1' of the second connection lead 22, or, as shown in FIG. 7, the line width K1 of the first connection lead 21 can also be less than the line width K1' of the second connection lead 22 in the region DD.

[0176] For example, as shown in FIGS. 9A, 9C, 10A and 10C, each of FIGS. 9A, 9C, 10A and 10C is a structural diagram of a partial region of a display panel 10 according to some embodiments of the present disclosure. Based on the embodiment shown in FIG. 5A, in which the plurality of front surface electrodes 4 are located within the display area AA of the display panel 10, the connection lead 2 (i.e., the first connection lead 21 and the second connection lead 22) connected with the plurality of front surface electrodes 4 can also be arranged between two adjacent pixel units P along the first direction X.

[0177] In some embodiments, as shown in FIGS. 8A, 8B, 9A, 9B, 9C, 9D, each of FIGS. 8A, 8B, 9B and 9D is a structural diagram of a partial region of a display panel 10 according to some embodiments of the present disclosure. The display panel 10 further comprises a first insulating layer 61. The first insulating layer 61 is located between the first connection lead 21 and the second connection lead 22. The first insulating layer 61 can insulate the first connection lead 21 and the second connection lead 22 from each other, so as to avoid short circuit between the first connection lead 21 and the second connection lead 22, and ensure normal display of the display panel 10.

[0178] For example, the material used to form the first insulating layer 61 can include thermosetting resin or UV resin, etc. The first insulating layer 61 can be formed by a printing process.

[0179] The material used to form the first insulating layer 61 can also include silicon nitride, silicon oxide or silicon oxynitride, etc. The first insulating layer 61 can also be formed by a chemical vapor deposition process.

[0180] For example, the first insulating layer 61 covers at least the first connecting lead 21, and the front electrode 4 and the back electrode 5 connected with the first connecting lead 21.

[0181] For example, as shown in FIGS. 8A and 8B, the first insulating layer 61 can cover only the first connecting lead 21, and the front electrode 4 and the back electrode 5 connected with the first connecting lead 21. On the basis of insulating, the material for forming the first insulating layer 61 can also be saved, which is conducive to reducing the manufacturing cost of the display panel 10.

[0182] It should be noted that the first insulating layer 61 includes a plurality of separated insulating blocks 61a, each of which corresponds to cover a first connecting lead 21, and the front electrode 4 and the back electrode 5 connected with the first connecting lead 21. In FIGS. 8A and 8B, the front projection of the insulating block 61a and the first connecting lead 21 is completely coincident, so the first connecting lead 21 is not shown.

[0183] For another example, as shown in FIGS. 9A and 9B, the first insulating layer 61 can also cover the selected side surface 1cc of the substrate 1. When the first insulating layer 61 covering the selected side surface 1cc is formed on the selected side surface 1cc of the substrate 1, the first insulating layer 61 located on the selected side surface 1cc can simultaneously cover the part of the first connecting lead 21 located on the selected side surface 1cc, without the need to separately form the first insulating layer 61 covering the part of the first connecting lead 21 located on the selected side surface 1cc in the area where the first connecting lead 21 is arranged, which is conducive to reducing the preparation difficulty of the first insulating layer 61 and improving the preparation efficiency of the first insulating layer 61.

[0184] For another example, as shown in FIGS. 9A and 9B, when the substrate 1 includes the first chamfer surface 1d and the second chamfer surface 1e, the first insulating layer 61 can also cover the first chamfer surface 1d and the second chamfer surface 1e. When the first insulating layer 61 covering the first chamfer surface 1d and the second chamfer surface 1e is formed on the first chamfer surface 1d and the second chamfer surface 1e of the substrate 1, the first insulating layer 61 located on the first chamfer surface 1d and the second chamfer surface 1e can simultaneously cover the part of the first connecting lead 21 located on the first chamfer surface 1d and the second chamfer surface 1e, without the need to separately form the first insulating layer 61 covering the part of the first connecting lead 21 located on the first chamfer surface 1d and the second chamfer surface 1e in the area where the first connecting lead 21 is arranged, which is conducive to reducing the preparation difficulty of the first insulating layer 61 and improving the preparation efficiency of the first insulating layer 61.

[0185] For example, as shown in FIG. 9B, the first insulating layer 61 can also cover the area between two adjacent back electrodes 5 along the first direction X on the second surface 1b of the substrate 1. When the first insulating layer 61 covering the back electrodes 5 and the area between two adjacent back electrodes 5 along the first direction X is formed on the second surface 1b of the substrate 1, the first insulating layer 61 covering the back electrodes 5 and the first insulating layer 61 covering the area between two adjacent back electrodes 5 along the first direction X can be formed synchronously without the need to separately form the first insulating layer 61 covering the portion of the first connecting lead 21 on the second surface 1b, which is conducive to further reducing the difficulty of manufacturing the first insulating layer 61 and further improving the manufacturing efficiency of the first insulating layer 61.

[0186] For another example, as shown in FIG. 9C, the first insulating layer 61 can also cover the front electrode 4 not connected with the first connecting lead 21 on the first surface 1a of the substrate 1, which is conducive to increasing the coverage area of the first insulating layer 61 and avoiding insufficient coverage of the first insulating layer 61 on the front electrode 4 connected with the first connecting lead 21, and is conducive to improving the insulation performance of the first insulating layer 61.

[0187] As shown in FIG. 9D, the first insulating layer 61 can also cover the back electrode 5 not connected with the first connecting lead 21 on the second surface 1b of the substrate 1, which is conducive to increasing the coverage area of the first insulating layer 61 and avoiding insufficient coverage of the first insulating layer 61 on the back electrode 5 connected with the first connecting lead 21, and is conducive to further improving the insulation performance of the first insulating layer 61.

[0188] It should be noted that, in order to facilitate the description of the first connecting lead 21 and the first insulating layer 61, the first insulating layer 61 is transparently processed in FIGS. 9A and 9B to expose the first connecting lead 21.

[0189] Hereinafter, some embodiments of the present disclosure are illustratively described by taking the first insulating layer 61 covering the selected side surface 1cc, the first chamfer surface 1d, the second chamfer surface 1e, the first connecting lead 21, and the front electrode 4 and the back electrode 5 connected with the first connecting lead 21 as an example.

[0190] It can be understood that, as shown in FIGS. 10A, 10B, 10C and 10D, FIGS. 10A, 10B, 10C and 10D are all a structural diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure. The second connecting lead 22 is located on the side of the first insulating layer 61 away from the first connecting lead 21, that is, the first connecting lead 21 and the second connecting lead 22 are located on opposite sides of the first insulating layer 61.

[0191] Exemplarily, please continue to refer to FIG. 10A and FIG. 10B, when the first insulating layer 61 does not cover the front surface electrode 4 and the back surface electrode 5 not connected with the first connecting lead 21, the first connecting lead 21 and the front surface electrode 4, and the back surface electrode 5 are directly connected.

[0192] The second connecting lead 22 is also directly connected with the front surface electrode 4 and the back surface electrode 5.

[0193] Alternatively, please continue to refer to FIG. 10C and FIG. 10D, when the first insulating layer 61 covers the front surface electrode 4 and the back surface electrode 5 not connected with the first connecting lead 21, the first connecting lead 21 and the front surface electrode 4, and the back surface electrode 5 are directly connected.

[0194] The second connecting lead 22 and the front surface electrode 4, and the back surface electrode 5 are connected through a via L, for example, penetrating the first insulating layer 61.

[0195] In some embodiments, as shown in FIG. 11A, FIG. 11B, FIG. 12A and FIG. 12B, which are structural diagrams of a partial area of the display panel 10 according to some embodiments of the present disclosure, the display panel 10 further comprises a protective layer 62. The protective layer 62 covers at least the second connecting lead 22, and the front surface electrode 4 and the back surface electrode 5 connected with the second connecting lead 22.

[0196] The protective layer 62 can not only play an insulating role to avoid short circuit between the second connecting lead 22, and the front surface electrode 4 and the back surface electrode 5 connected with the second connecting lead 22, and other lines in the display panel 10, but also protect the second connecting lead 22, and the front surface electrode 4 and the back surface electrode 5 connected with the second connecting lead 22, to avoid corrosion or oxidation of the second connecting lead 22, and the front surface electrode 4 and the back surface electrode 5 connected with the second connecting lead 22 due to surface exposure.

[0197] Exemplarily, as shown in FIG. 11A and FIG. 11B, the protective layer 62 can cover only the second connecting lead 22, and the front surface electrode 4 and the back surface electrode 5 connected with the second connecting lead 22. On the basis of playing an insulating role, the material for forming the protective layer 62 can also be saved, which is conducive to reducing the manufacturing cost of the display panel 10.

[0198] For example, as shown in FIGS. 12A and 12B, the protective layer 62 can also cover the selected side surface 1cc of the substrate 1. When the protective layer 62 covering the selected side surface 1cc is formed on the selected side surface 1cc of the substrate 1, the protective layer 62 on the selected side surface 1cc can simultaneously cover the portion of the second connecting lead 22 located on the selected side surface 1cc, without the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the selected side surface 1cc in the area where the second connecting lead 22 is arranged, which is conducive to reducing the difficulty of preparing the protective layer 62 and improving the preparation efficiency of the protective layer 62.

[0199] For example, as shown in FIGS. 12A and 12B, when the substrate 1 includes the first chamfered surface 1d and the second chamfered surface 1e, the protective layer 62 can also cover the first chamfered surface 1d and the second chamfered surface 1e. When the protective layer 62 covering the first chamfered surface 1d and the second chamfered surface 1e is formed on the first chamfered surface 1d and the second chamfered surface 1e of the substrate 1, the protective layer 62 on the first chamfered surface 1d and the second chamfered surface 1e can simultaneously cover the portion of the second connecting lead 22 located on the first chamfered surface 1d and the second chamfered surface 1e, without the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the first chamfered surface 1d and the second chamfered surface 1e in the area where the second connecting lead 22 is arranged, which is conducive to reducing the difficulty of preparing the protective layer 62 and improving the preparation efficiency of the protective layer 62.

[0200] For example, as shown in FIG. 12B, on the second surface 1b of the substrate 1, along the first direction X, the protective layer 62 can also cover the area between two adjacent back electrodes 5. When the protective layer 62 covering the back electrode 5 and the area between two adjacent back electrodes 5 along the first direction X is formed on the second surface 1b of the substrate 1, the protective layer 62 covering the back electrode 5 and the protective layer 62 covering the area between two adjacent back electrodes 5 along the first direction X can be formed synchronously, without the need to separately form the protective layer 62 covering the portion of the second connecting lead 22 located on the second surface 1b in the area where the second connecting lead 22 is arranged, which is conducive to further reducing the difficulty of preparing the protective layer 62 and further improving the preparation efficiency of the protective layer 62.

[0201] It should be noted that, in order to facilitate the description of the second connecting lead 22 and the protective layer 62, the protective layer 62 in FIGS. 12A and 12B is transparently treated to expose the second connecting lead 22.

[0202] For example, the material used to form the protective layer 62 can include a thermosetting resin or a UV resin, etc. The protective layer 62 can be formed by a printing process.

[0203] The material used to form the protective layer 62 can also include silicon nitride, silicon oxide, or silicon oxynitride, etc. The protective layer 62 can also be formed by a chemical vapor deposition process.

[0204] In the tiled display device 1000, the size of the joint gap (the gap between two adjacent display panels 10) is an important factor affecting the display effect of the tiled display device 1000. Since the first connecting lead 21, the first insulating layer 61, the second connecting lead 22 and the protective layer 62 are sequentially arranged on the selected side surface 1cc of the substrate 1 along the second direction Y, the first connecting lead 21, the first insulating layer 61, the second connecting lead 22 and the protective layer 62 form an occupation on the selected side surface 1cc of the substrate 1, which is not conducive to the narrowing of the frame of the display panel 10, thereby causing the joint gap to increase when the display panels 10 are tiled, and display abnormalities such as bright joints and the like are prone to occur in the joint gap area in the tiled display device 1000, affecting the display effect of the tiled display device 1000.

[0205] Based on this, as shown in FIGS. 13A and 13B, both FIGS. 13A and 13B are a structural diagram of a partial area of a display panel 10 according to some embodiments of the present disclosure. The display panel 10 further comprises at least one recessed area Q, which is located at least on the selected side surface 1cc of the substrate 1.

[0206] It should be noted that the above-mentioned recessed area Q refers to that a groove is opened at least on the selected side surface 1cc of the substrate 1 to form the recessed area Q, i.e., the recessed area Q is recessed towards the inside of the substrate 1.

[0207] Exemplarily, please continue to refer to FIG. 13A, the recessed area Q can be located only on the selected side surface 1cc of the substrate 1.

[0208] Alternatively, please continue to refer to FIG. 13B, the recessed area Q can also extend to the first chamfer surface 1d and the second chamfer surface 1e of the substrate 1 on the basis of being located on the selected side surface 1cc of the substrate 1.

[0209] Further alternatively, the recessed area Q can also extend to the first surface 1a and the second surface 1b of the substrate 1.

[0210] Please continue to refer to FIGS. 13A and 13B, one of the first connecting lead 21 and the second connecting lead 22 that is closer to the substrate 1 has a projection on the selected side surface 1cc of the substrate 1 located in the recessed area Q.

[0211] Exemplarily, as shown in FIGS. 13A and 13B, the first connecting lead 21 is closer to the substrate 1 than the second connecting lead 22, and the projection of the first connecting lead 21 on the selected side surface 1cc of the substrate 1 is located in the recessed area Q.

[0212] Hereinafter, some embodiments of the present disclosure will be illustratively described taking the first connecting lead 21 as an example, which is closer to the substrate 1 than the second connecting lead 22.

[0213] Exemplarily, please continue to refer to FIG. 13A, the display panel 10 can include a plurality of recessed regions Q, and a projection of the first connection lead 21 on the selected side surface 1cc of the substrate 1 is located in one recessed region Q.

[0214] Alternatively, please continue to refer to FIG. 13B, a plurality of (for example, three) first connection leads 21, and a projection of the first connection lead 21 on the selected side surface 1cc of the substrate 1 is located in one recessed region Q.

[0215] In some embodiments, please continue to refer to FIG. 13A and FIG. 13B, when a projection of the first connection lead 21 on the selected side surface 1cc of the substrate 1 is located in one recessed region Q, a ratio of the size K3 of the recessed region Q along the first direction X to the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X is 1-2.

[0216] Exemplarily, the ratio of the size K3 of the recessed region Q along the first direction X to the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X can be 1, 1.2, 1.3, 1.5, 1.6, 1.8 or 2.

[0217] It can be understood that when the ratio of the size K3 of the recessed region Q along the first direction X to the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X is greater than 1, the size K3 of the recessed region Q along the first direction X is greater than the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X, which facilitates the formation of the first connection lead 21 in the recessed region Q and reduces the probability that the projection of the first connection lead 21 on the selected side surface 1cc of the substrate 1 is located outside the recessed region Q due to misalignment between the first connection lead 21 and the recessed region Q.

[0218] When the ratio of the size K3 of the recessed region Q along the first direction X to the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X is 1, the size K3 of the recessed region Q along the first direction X is the same as the size (i.e., the line width of the first connection lead 21) K1 of the first connection lead 21 along the first direction X, and the size K3 of the recessed region Q along the first direction X is relatively small, which can reduce the cost of forming the recessed region Q and further reduce the production cost of the display panel 10.

[0219] As shown in FIG. 13C, FIG. 13D and FIG. 13E, FIG. 13C, FIG. 13D and FIG. 13E are all cross-sectional views of the display panel 10 in FIG. 12A along the cross-sectional line H-H. It should be noted that FIG. 13C, FIG. 13D and FIG. 13E are respectively cross-sectional views of the display panel 10 in FIG. 12A along the cross-sectional line H-H in the case that the depth (i.e., the size of the recessed region Q along the second direction Y) of the recessed region Q of the display panel 10 is different.

[0220] The depth of the recessed region Q (i.e. the dimension of the recessed region Q along the second direction Y) is S1, and since the orthogonal projection of the first connecting lead 21 on the selected side surface 1cc of the substrate 1 is located within the recessed region Q, at least part of the first connecting lead 21 is located within the recessed region Q.

[0221] When at least part of the first connecting lead 21 is located within the recessed region Q, the footprint of the first connecting lead 21, the first insulating layer 61, the second connecting lead 22 and the protective layer 62 on the selected side surface 1cc of the substrate 1 can be reduced, i.e. the distance S6 between the side of the protective layer 62 away from the selected side surface 1cc and the selected side surface 1cc is reduced, which is beneficial for narrowing the frame of the display panel 10, so as to reduce the distance of the joint seam when the display panel 10 is spliced, and make it more difficult for the naked eye to find the joint seam between two adjacent display panels 10 within the viewing distance when the spliced display device 1000 is actually viewed, so as to avoid display abnormality in the joint seam area of the spliced display device 1000, ensure normal display of the spliced display device 1000, and present better display effect.

[0222] As shown in FIGS. 13C, 13D and 13E, and in combination with FIG. 15B, which are all structural diagrams of a partial region of the display panel 10 according to some embodiments of the present disclosure, the minimum distance between the edge of the front electrode 4 of the plurality of front electrodes 4 closest to the selected side surface 1cc of the substrate 1 and the first boundary 1aa of the first surface 1a is d2. It can be understood that the depth of the recessed region Q (i.e. the dimension of the recessed region Q along the second direction Y) should be less than or equal to d2, so as to avoid exposing the part of the front electrode 4 close to the side surface of the substrate 1.

[0223] Exemplarily, the minimum distance between the edge of the front electrode 4 of the plurality of front electrodes 4 closest to the selected side surface 1cc of the substrate 1 and the first boundary 1aa of the first surface 1a can be d2.

[0224] For example, the minimum distance between the edge of the front electrode 4 of the plurality of front electrodes 4 closest to the selected side surface 1cc of the substrate 1 and the first boundary 1aa of the first surface 1a can be d2.

[0225] Please continue to refer to FIGS. 13C, 13D and 13E, the thickness of the first connecting lead 21 (i.e. the dimension of the first connecting lead 21 along the second direction Y) is S2, the thickness of the first insulating layer 61 (i.e. the dimension of the first insulating layer 61 along the second direction Y) is S3, the thickness of the second connecting lead 22 (i.e. the dimension of the second connecting lead 22 along the second direction Y) is S4, and the thickness of the protective layer 62 (i.e. the dimension of the protective layer 62 along the second direction Y) is S5.

[0226] Exemplarily, as shown in FIG. 13C, the depth (i.e., the size of the recessed region Q along the second direction Y) S1 of the recessed region Q can be less than the thickness (i.e., the size of the first connecting lead 21 along the second direction Y) S2 of the first connecting lead 21, and part of the first connecting lead 21 is located within the recessed region Q.

[0227] Alternatively, as shown in FIG. 13D, the depth (i.e., the size of the recessed region Q along the second direction Y) S1 of the recessed region Q can be equal to the thickness (i.e., the size of the first connecting lead 21 along the second direction Y) S2 of the first connecting lead 21, and the whole of the first connecting lead 21 is located within the recessed region Q. The distance S6 between the side of the protective layer 62 away from the selected side face 1cc and the selected side face 1cc can be further reduced, which is conducive to the narrowing of the frame of the display panel 10, so as to reduce the distance of the joint seam when the display panel 10 is spliced, avoid display abnormality in the joint seam area of the spliced display device 1000, and ensure normal display of the spliced display device 1000.

[0228] Further alternatively, as shown in FIG. 13E, the depth (i.e., the size of the recessed region Q along the second direction Y) S1 of the recessed region Q can be greater than the thickness (i.e., the size of the first connecting lead 21 along the second direction Y) S2 of the first connecting lead 21. For example, the depth (i.e., the size of the recessed region Q along the second direction Y) S1 of the recessed region Q is equal to the sum of the thickness (i.e., the size of the first connecting lead 21 along the second direction Y) S2 of the first connecting lead 21, the thickness (i.e., the size of the first insulating layer 61 along the second direction Y) S3 of the first insulating layer 61, and the thickness (i.e., the size of the second connecting lead 22 along the second direction Y) S4 of the second connecting lead 22, and the whole of the first connecting lead 21, the first insulating layer 61, and the second connecting lead 22 are located within the recessed region Q. The distance S6 between the side of the protective layer 62 away from the selected side face 1cc and the selected side face 1cc can be further reduced, which is conducive to the narrowing of the frame of the display panel 10, so as to reduce the distance of the joint seam when the display panel 10 is spliced, avoid display abnormality in the joint seam area of the spliced display device 1000, and ensure normal display of the spliced display device 1000.

[0229] When the number of the connecting leads 2 increases, the number of the front electrodes 4 and the back electrodes 5 connected with the connecting leads 2 also increases correspondingly. As shown in FIGS. 14A and 14B, both of FIGS. 14A and 14B are a structure diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure. The arrangement of a larger number of front electrodes 4 on the first surface 1a of the substrate 1 and the arrangement of a larger number of back electrodes 5 on the second surface 1b of the substrate 1 can be realized by reducing the size of the front electrodes 4 and the size of the back electrodes 5, i.e., increasing the density of the front electrodes 4 and the back electrodes 5.

[0230] It should be noted that the "size of the front electrode 4" refers to the area of the orthographic projection of the front electrode 4 on the first surface la of the substrate 1, and the "size of the back electrode 5" refers to the area of the orthographic projection of the back electrode 5 on the second surface lb of the substrate 1. The following description of the "size of the front electrode 4" and the "size of the back electrode 5" also follows this description.

[0231] When the size of the front electrode 4 is reduced, the overlap area between the connecting lead 2 and the front electrode 4 is also reduced, which is likely to cause the problem of poor overlap between the connecting lead 2 and the front electrode 4, affecting the conduction performance of the connecting lead 2 and the front electrode 4, and possibly causing the display panel 10 to fail to display normally.

[0232] Based on this, the following first describes an embodiment of the setting manner of the front electrode 4.

[0233] In some embodiments, as shown in FIGS. 15A, 15B and 15C, each of FIGS. 15A, 15B and 15C is a structural diagram of a partial area of a display panel 10 according to some embodiments of the present disclosure. The plurality of front electrodes 4 are arranged at intervals along the first direction X and the second direction Y, respectively. Compared with the plurality of front electrodes 4 arranged at intervals only along the first direction X, arranging the plurality of front electrodes 4 at intervals along the first direction X and the second direction Y, respectively, can reduce the restriction of the size K2 of the first surface la of the substrate 1 along the first direction X on the arrangement of the plurality of front electrodes 4, ensure the size of the front electrode 4, increase the overlap area between the connecting lead 2 and the front electrode 4, avoid the problem of poor overlap between the connecting lead 2 and the front electrode 4, and be conducive to improving the conduction performance of the connecting lead 2 and the front electrode 4, and ensuring the normal display of the display panel 10.

[0234] Exemplarily, please continue to refer to FIGS. 15A, 15B and 15C, the plurality of front electrodes 4 include a first electrode 41 and a second electrode 42, and the first electrode 41 and the second electrode 42 are arranged adjacent to each other. The first electrode 41 is arranged at intervals along the first direction X. The second electrode 42 is also arranged at intervals along the first direction X, and the first electrode 41 and the second electrode 42 are arranged alternately along the second direction Y.

[0235] It should be noted that in FIGS. 15A, 15B and 15C, one first electrode 41 and one second electrode 42 are taken as an example to schematically show that they are arranged alternately along the second direction Y, however, the arrangement manner of the first electrode 41 and the second electrode 42 in the present disclosure is not limited thereto, for example, a plurality of first electrodes 41 and a plurality of second electrodes 42 can also be arranged alternately along the second direction Y.

[0236] For example, as shown in FIG. 15A, the first electrode 41 and the second electrode 42 can be arranged in a staggered manner along the second direction Y, and the first electrode 41 and the second electrode 42 partially overlap in the second direction Y to form an overlapping region J2.

[0237] Alternatively, as shown in FIG. 15C, the first electrode 41 and the second electrode 42 can be arranged in an array manner along the second direction Y, and the size of the first electrode 41 and the size of the second electrode 42 are the same, the first electrode 41 and the second electrode 42 completely overlap in the second direction Y to form an overlapping region J1.

[0238] For example, as shown in FIG. 15A, the first electrode 41 and the second electrode 42 can be arranged in a staggered manner along the second direction Y, and the first electrode 41 and the second electrode 42 partially overlap in the second direction Y to form an overlapping region J2.

[0239] For example, as shown in FIG. 15A, the size of the first electrode 41 and the size of the second electrode 42 can be the same. Alternatively, as shown in FIG. 15B, the size of the first electrode 41 and the size of the second electrode 42 can also be different, and the size of the first electrode 41 and the size of the second electrode 42 can be designed based on actual needs.

[0240] For example, as shown in FIG. 15A, the first electrode 41 and the second electrode 42 can be arranged in a staggered manner along the second direction Y, and the first electrode 41 and the second electrode 42 partially overlap in the second direction Y to form an overlapping region J2.

[0241] For example, as shown in FIG. 15A, the first electrode 41 and the second electrode 42 can be arranged in a staggered manner along the second direction Y, and the first electrode 41 and the second electrode 42 partially overlap in the second direction Y to form an overlapping region J2.

[0242] For example, as shown in FIG. 15A, the first electrode 41 and the second electrode 42 can be arranged in a staggered manner along the second direction Y, and the first electrode 41 and the second electrode 42 partially overlap in the second direction Y to form an overlapping region J2.

[0243] For another example, as shown in FIG. 15B, the first electrodes 41 and the second electrodes 42 can be arranged in an array along the second direction Y, and the size of the first electrodes 41 and the size of the second electrodes 42 are different, the first electrodes 41 and the second electrodes 42 completely overlap in the second direction Y, and there is an overlapping region J3.

[0244] In some embodiments, the plurality of front electrodes 4 (the first electrodes 41 and the second electrodes 42) can be disposed in the conductive layer on the first surface la of the substrate 1.

[0245] As shown in FIGS. 16 and 17, both FIGS. 16 and 17 are a cross-sectional view of the display panel 10 in FIG. 15A along the cross-sectional line G-G. It should be noted that FIGS. 16 and 17 are cross-sectional views of the display panel 10 in FIG. 15A along the cross-sectional line G-G in the case of different arrangements of the front electrodes 4 and the back electrodes 5 of the display panel 10, respectively.

[0246] The first surface la of the substrate 1 includes a second insulating layer 83, a first conductive layer 81, a third insulating layer 84, a second conductive layer 82, and a fourth insulating layer 85 which are sequentially stacked. The first conductive layer 81 is closer to the first surface la of the substrate 1 than the second conductive layer 82.

[0247] For example, the first conductive layer 81 can be provided with a gate electrode of a thin film transistor in a driving component in a pixel unit P, and the second conductive layer 82 can be provided with a source / drain electrode of the thin film transistor.

[0248] For example, the first conductive layer 81 and the second conductive layer 82 can be deposited by a PVD (Physical Vapor Deposition) process using one or more of MO (molybdenum), Ti (titanium), Al (aluminum), Cu (copper), ITO (Indium Tin Oxide), and the like.

[0249] For example, the first conductive layer 81 or the second conductive layer 82 can be deposited by a PVD (Physical Vapor Deposition) process using MO / Al / MO (molybdenum / aluminum / molybdenum), MO / Cu / MO (molybdenum / copper / molybdenum), Ti / Cu / Ti (titanium / copper / titanium), or ITO / Cu (Indium Tin Oxide / copper), and the like. The second conductive layer 82 has a greater oxidation resistance than the first conductive layer 81.

[0250] In some embodiments, as shown in FIG. 17, the first electrodes 41 and the second electrodes 42 can be disposed in the same layer.

[0251] Exemplarily, the first electrode 41 and the second electrode 42 are both located in the first conductive layer 81.

[0252] In other embodiments, please continue to refer to FIG. 16, the first electrode 41 and the second electrode 42 can be arranged in different layers, and the first electrode 41 is closer to the first surface 1a of the substrate 1 than the second electrode 42.

[0253] By arranging the first electrode 41 and the second electrode 42 in different conductive layers (the first conductive layer 81 and the second conductive layer 82), the plurality of front electrodes 4 are not located in the same plane, and the arrangement mode of the plurality of front electrodes 4 (the first electrode 41 and the second electrode 42) is changed from planar arrangement to three-dimensional arrangement, that is, the plurality of front electrodes 4 can be arranged in the third direction Z in addition to the first direction X and the second direction Y, which can reduce the limitation of planar space on the arrangement of the front electrodes 4 (the first electrode 41 and the second electrode 42), ensure the size of the front electrodes 4, further increase the overlapping area of the connecting leads 2 and the front electrodes 4, avoid the problem of poor overlap between the connecting leads 2 and the front electrodes 4, and be beneficial to further improving the conduction performance of the connecting leads 2 and the front electrodes 4, and ensuring the normal display of the display panel 10.

[0254] Exemplarily, in addition to the conductive layer for arranging the first electrode 41 and the conductive layer for arranging the second electrode 42, other conductive layers for arranging the front electrodes 4 can also be formed. The conductive layer for arranging the first electrode 41, the conductive layer for arranging the second electrode 42, and the other conductive layers for arranging the front electrodes 4 can be arranged in the third direction Z. The limitation of planar space on the arrangement of the front electrodes 4 can be further reduced, the size of the front electrodes 4 can be ensured, the overlapping area of the connecting leads 2 and the front electrodes 4 can be further increased, the problem of poor overlap between the connecting leads 2 and the front electrodes 4 can be avoided, and the conduction performance of the connecting leads 2 and the front electrodes 4 can be further improved, which is beneficial to further improving the conduction performance of the connecting leads 2 and the front electrodes 4, and ensuring the normal display of the display panel 10.

[0255] Exemplarily, the first electrode 41 can be located in the first conductive layer 81, and the second electrode 42 can be located in the second conductive layer 82.

[0256] Exemplarily, please continue to refer to FIG. 16, the orthographic projection of the first electrode 41 on the first surface 1a of the substrate 1 does not overlap with the orthographic projection of the second electrode 42 on the first surface 1a of the substrate 1, that is, the orthographic projection of the first electrode 41 on the first surface 1a of the substrate 1 does not have an overlapping area with the orthographic projection of the second electrode 42 on the first surface 1a of the substrate 1.

[0257] Alternatively, as shown in FIG. 18, which is a cross-sectional view of a partial region of the display panel 10 according to some embodiments of the present disclosure. The orthogonal projection of the first electrode 41 on the first surface la of the substrate 1 partially overlaps with the orthogonal projection of the second electrode 42 on the first surface la of the substrate 1, i.e., the orthogonal projection of the first electrode 41 on the first surface la of the substrate 1 and the orthogonal projection of the second electrode 42 on the first surface la of the substrate 1 have an overlapping region J4.

[0258] In some embodiments, please refer to FIG. 16, FIG. 17 and FIG. 18, the display panel 10 further comprises a plurality of opening portions K for exposing the plurality of front electrodes 4 (the first electrode 41 and the second electrode 42).

[0259] Exemplarily, as shown in FIG. 17, the opening portion K can penetrate through the third insulating layer 84 and expose the first electrode 41 and the second electrode 42 located in the first conductive layer 81.

[0260] Alternatively, as shown in FIG. 16 and FIG. 18, the opening portion K can penetrate through the fourth insulating layer 85 and expose the second electrode 42 located in the second conductive layer 82. The opening portion K can also penetrate through the fourth insulating layer 85 and the third insulating layer 84 in sequence and expose the first electrode 41 located in the first conductive layer 81.

[0261] The following describes embodiments of the arrangement of the back electrodes 5.

[0262] In some embodiments, as shown in FIG. 19A and FIG. 19B, both of which are a structural diagram of a partial region of the display panel 10 according to some embodiments of the present disclosure. The plurality of back electrodes 5 are arranged along the first direction X and the second direction Y respectively. Compared with the plurality of back electrodes 5 arranged along the first direction X only, arranging the plurality of back electrodes 5 along the first direction X and the second direction Y respectively can reduce the limitation of the size K2 of the second surface lb of the substrate 1 along the first direction X on the arrangement of the plurality of back electrodes 5, ensure the size of the back electrode 5, increase the overlapping area of the connecting lead 2 and the back electrode 5, avoid the problem of poor overlap between the connecting lead 2 and the back electrode 5, and be conducive to improving the conduction performance of the connecting lead 2 and the back electrode 5, and ensuring the normal display of the display panel 10.

[0263] Exemplarily, please refer to FIG. 19A and FIG. 19B, the plurality of back electrodes 5 comprise a third electrode 51 and a fourth electrode 52, and the third electrode 51 and the fourth electrode 52 are arranged adjacently. The third electrode 51 is arranged along the first direction X. The fourth electrode 52 is also arranged along the first direction X, and the third electrode 51 and the fourth electrode 52 are arranged alternately along the second direction Y.

[0264] It is to be noted that in FIGS. 19A and 19B, one third electrode 51 and one fourth electrode 52 are alternately arranged along the second direction Y as an example, but the arrangement of the third electrode 51 and the fourth electrode 52 is not limited to this in the present disclosure, and for example, a plurality of third electrodes 51 and a plurality of fourth electrodes 52 can be alternately arranged along the second direction Y.

[0265] As an example, referring to FIGS. 19A and 19B, the third electrode 51 is closer to the selected side surface 1cc of the substrate 1 than the fourth electrode 52.

[0266] As an example, as shown in FIG. 19A, the third electrode 51 and the fourth electrode 52 can have the same size. Alternatively, as shown in FIG. 19B, the third electrode 51 and the fourth electrode 52 can have different sizes, and the sizes of the third electrode 51 and the fourth electrode 52 can be designed based on actual needs.

[0267] As an example, referring to FIGS. 19A and 19B, along the second direction Y, the third electrode 51 and the fourth electrode 52 at least partially overlap.

[0268] For example, as shown in FIG. 19A, along the second direction Y, the third electrode 51 and the fourth electrode 52 can be arranged in a staggered manner, and the third electrode 51 and the fourth electrode 52 partially overlap in the second direction Y to form an overlapping region J9.

[0269] For another example, as shown in FIG. 19A, along the second direction Y, the third electrode 51 and the fourth electrode 52 can be arranged in an array, and the third electrode 51 and the fourth electrode 52 have the same size, and the third electrode 51 and the fourth electrode 52 completely overlap in the second direction Y to form an overlapping region J8.

[0270] For another example, as shown in FIG. 19B, along the second direction Y, the third electrode 51 and the fourth electrode 52 can be arranged in an array, and the third electrode 51 and the fourth electrode 52 have different sizes, and the third electrode 51 and the fourth electrode 52 completely overlap in the second direction Y to form an overlapping region J10.

[0271] In some embodiments, the plurality of back electrodes 5 (the third electrode 51 and the fourth electrode 52) can be disposed in a conductive layer on the second surface 1b of the substrate 1.

[0272] As shown in FIG. 16, which is a cross-sectional view of the display panel 10 in FIG. 15A along the cross-sectional line G-G, the second surface 1b of the substrate 1 includes a third conductive layer 91, a fifth insulating layer 93, a fourth conductive layer 92, and a sixth insulating layer 94, which are sequentially stacked. The third conductive layer 91 is closer to the second surface 1b of the substrate 1 than the fourth conductive layer 92.

[0273] Exemplarily, the third conductive layer 91 and the fourth conductive layer 92 can each be deposited by a PVD (Physical Vapor Deposition) process using one or more of MO (molybdenum), Ti (titanium), Al (aluminum), Cu (copper), ITO (Indium Tin Oxide), and the like.

[0274] For example, the third conductive layer 91 or the fourth conductive layer 92 can be deposited by a PVD (Physical Vapor Deposition) process using MO / Al / MO (molybdenum / aluminum / molybdenum), MO / Cu / MO (molybdenum / copper / molybdenum), Ti / Cu / Ti (titanium / copper / titanium), or ITO / Cu (Indium Tin Oxide / copper), and the like. The fourth conductive layer 92 has a greater oxidation resistance than the third conductive layer 91.

[0275] In some embodiments, as shown in FIG. 17, which is a cross-sectional view of the display panel 10 along the cross-sectional line G-G in FIG. 15A, the third electrode 51 and the fourth electrode 52 can be disposed in the same layer.

[0276] Exemplarily, the third electrode 51 and the fourth electrode 52 are both located in the third conductive layer 91.

[0277] In other embodiments, as shown in FIG. 16, the third electrode 51 and the fourth electrode 52 can be disposed in different layers, and the third electrode 51 is closer to the second surface 1b of the substrate 1 than the fourth electrode 52.

[0278] By disposing the third electrode 51 and the fourth electrode 52 in different conductive layers (the third conductive layer 91 and the fourth conductive layer 92), the plurality of back electrodes 5 are not located in the same plane, and the arrangement of the plurality of back electrodes 5 (the third electrode 51 and the fourth electrode 52) is changed from a planar arrangement to a three-dimensional arrangement, i.e., the plurality of back electrodes 5 can be arranged in the first direction X and the second direction Y, and can also be arranged in the third direction Z, which can reduce the limitation of the planar space on the arrangement of the back electrodes 5 (the third electrode 51 and the fourth electrode 52), ensure the size of the back electrodes 5, further increase the overlapping area of the connecting leads 2 and the back electrodes 5, avoid the problem of poor overlapping between the connecting leads 2 and the back electrodes 5, and is conducive to further improving the conduction performance of the connecting leads 2 and the back electrodes 5, and ensuring the normal display of the display panel 10.

[0279] Exemplarily, in addition to the conductive layer for disposing the third electrode 51 and the conductive layer for disposing the fourth electrode 52, other conductive layers for disposing the back electrodes 5 can also be formed. The conductive layer for disposing the third electrode 51, the conductive layer for disposing the fourth electrode 52, and the other conductive layers for disposing the back electrodes 5 can be disposed in a stacked manner in the third direction Z. The restriction on the arrangement of the back electrodes 5 in the planar space can be further reduced, the size of the back electrodes 5 can be ensured, the overlapping area between the connecting lead 2 and the back electrodes 5 can be further increased, the problem of poor overlap between the connecting lead 2 and the back electrodes 5 can be avoided, and the conduction performance of the connecting lead 2 and the back electrodes 5 can be further improved, thereby ensuring the normal display of the display panel 10.

[0280] Exemplarily, the third electrode 51 can be located on the third conductive layer 91, and the fourth electrode 52 can be located on the fourth conductive layer 92.

[0281] Exemplarily, as shown in FIG. 16, the orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 does not overlap with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1, i.e., the orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 does not have an overlapping area with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1.

[0282] Alternatively, as shown in FIG. 18, which is a cross-sectional view of the display panel 10 according to some embodiments of the present disclosure, the orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 partially overlaps with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1, i.e., the orthographic projection of the third electrode 51 on the second surface 1b of the substrate 1 has an overlapping area J5 with the orthographic projection of the fourth electrode 52 on the second surface 1b of the substrate 1.

[0283] In some embodiments, as shown in FIGS. 16, 17, and 18, the opening portion K can also be used to expose the plurality of back electrodes 5 (the third electrode 51 and the fourth electrode 52).

[0284] Exemplarily, as shown in FIG. 17, the opening portion K can penetrate the fifth insulating layer 93 and expose the third electrode 51 and the fourth electrode 52 located on the third conductive layer 91.

[0285] Alternatively, as shown in FIGS. 16 and 18, the opening portion K can penetrate the sixth insulating layer 94 and expose the fourth electrode 52 located on the fourth conductive layer 92. The opening portion K can also penetrate the sixth insulating layer 94 and the fifth insulating layer 93 in sequence and expose the third electrode 51 located on the third conductive layer 91.

[0286] In some embodiments, as shown in FIGS. 9A and 9B, the first connecting lead 21 can be used to connect the first electrode 41 and the third electrode 51.

[0287] Please continue to refer to FIG. 10A and FIG. 10B. The second connecting lead 22 can be used to connect the second electrode 42 and the fourth electrode 52.

[0288] Exemplarily, the plurality of front electrodes 4 (i.e. the first electrode 41 and the second electrode 42) and the plurality of back electrodes 5 (i.e. the third electrode 51 and the fourth electrode 52) can have gold-plated surfaces. When the material of the connecting lead 2 (i.e. the first connecting lead 21 and the second connecting lead 22) includes silver (Ag), the combination of gold (Au) and silver (Ag) has good performance, which can reduce the contact resistance between the front electrode 4 and the connecting lead 2, and the contact resistance between the back electrode 5 and the connecting lead 2.

[0289] Exemplarily, the first electrode 41 and the third electrode 51 are correspondingly arranged, and the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 at least partially overlap. For example, the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 can partially overlap; or, as shown in FIG. 16, the orthographic projections of the first electrode 41 and the third electrode 51 on the second surface 1b of the substrate 1 can completely overlap, and there is an overlapping region J6.

[0290] The second electrode 42 and the fourth electrode 52 are correspondingly arranged, and the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 at least partially overlap. For example, the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 can partially overlap; or, as shown in FIG. 16, the orthographic projections of the second electrode 42 and the fourth electrode 52 on the second surface 1b of the substrate 1 can completely overlap, and there is an overlapping region J7.

[0291] In some embodiments, as shown in FIG. 20A, and in combination with FIG. 16, FIG. 20A is a structural diagram of a partial region of the display panel 10 according to some embodiments of the present disclosure. The display panel 10 further includes a plurality of first signal lines 71 located on the first surface 1a of the substrate 1. One end of one of the plurality of first signal lines 71 is connected to one front electrode 4 (the first electrode 41 or the second electrode 42) located on the first surface 1a of the substrate 1, and the other end is connected to a pixel unit P located on the first surface 1a of the substrate 1, for transmitting signals to the pixel unit P and controlling the pixel unit P to emit light.

[0292] Exemplarily, the first signal line 71 can be located on the first conductive layer 81, or the first signal line 71 can also be located on the second conductive layer 82.

[0293] When the first electrode 41 and the second electrode 42 in the front electrode 4 are arranged in different layers, i.e. one of the first electrode 41 and the second electrode 42 is located in the first conductive layer 81, and the other is located in the second conductive layer 82. Among the first electrode 41 and the second electrode 42, the one arranged in the same layer as the first signal line 71 can be directly connected to the first signal line 71, and the other can be connected to the first signal line 71 through the via L.

[0294] For example, as shown in FIG. 20A, and in combination with FIG. 16, the first electrode 41 is located in the first conductive layer 81, the second electrode 42 is located in the second conductive layer 82, and the first signal line 71 is located in the first conductive layer 81, i.e. the first electrode 41 and the first signal line 71 are arranged in the same layer, and the second electrode 42 and the first signal line 71 are arranged in different layers. The first electrode 41 is directly connected to the first signal line 71, and the second electrode 42 is connected to the first signal line 71 through the via L.

[0295] In some embodiments, as shown in FIG. 20B, which is a structural diagram of a partial area of the display panel 10 according to some embodiments of the present disclosure. The display panel 10 further includes a plurality of second signal lines 72 located on the second surface 1b of the substrate 1. One end of one of the plurality of second signal lines 72 is connected to one of the back electrodes 5 (the third electrode 51 or the fourth electrode 52) located on the second surface 1b of the substrate 1, and the other end is connected to a circuit board (not shown in the figure) for transmitting the control signal output by the circuit board.

[0296] For example, the second signal line 72 can be located in the third conductive layer 91, or alternatively, the second signal line 72 can be located in the fourth conductive layer 92.

[0297] When the third electrode 51 and the fourth electrode 52 in the back electrode 5 are arranged in different layers, i.e. one of the third electrode 51 and the fourth electrode 52 is located in the third conductive layer 91, and the other is located in the fourth conductive layer 92. Among the third electrode 51 and the fourth electrode 52, the one arranged in the same layer as the second signal line 72 can be directly connected to the second signal line 72, and the other can be connected to the second signal line 72 through the via L.

[0298] For example, as shown in FIG. 20B, and in combination with FIG. 16, the third electrode 51 is located in the third conductive layer 91, the fourth electrode 52 is located in the fourth conductive layer 92, and the second signal line 72 is located in the third conductive layer 91, i.e. the third electrode 51 and the second signal line 72 are arranged in the same layer, and the fourth electrode 52 and the second signal line 72 are arranged in different layers. The third electrode 51 is directly connected to the second signal line 72, and the fourth electrode 52 is connected to the second signal line 72 through the via L.

[0299] In some embodiments, the pixel units described above can be light emitting units, and the light emitting units can include LEDs, in which case the display panel 10 described above can be considered as a light emitting panel. The embodiments of the display panel 10 described in the present disclosure, including but not limited to the arrangement of the connection leads 2, the arrangement of the front electrodes 4 and the arrangement of the back electrodes 5, the positional relationship between the connection leads 2, the front electrodes 4 and the pixel units P, the arrangement of the recessed areas Q, etc. can be applied to the light emitting panel individually or entirely.

[0300] Exemplarily, the light emitting panel described above can be used as a backlight source.

[0301] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed in the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: a substrate comprising a first surface and a second surface disposed opposite to each other, and at least one side surface connecting the first surface and the second surface, at least one of the side surfaces being a selected side surface; a plurality of connection leads, each of the plurality of connection leads extending from the first surface, through the selected side surface, to the second surface; the plurality of connection leads comprising a first connection lead and a second connection lead, the first connection lead and the second connection lead being adjacent and disposed in different layers in a direction perpendicular to the substrate surface.

2. The display panel of claim 1, wherein, orthographic projections of the first connection lead and the second connection lead on the substrate at least partially overlap.

3. The display panel of claim 1 or 2, wherein, line widths of the first connection lead and the second connection lead are different.

4. The display panel of any one of claims 1-3, wherein, signals transmitted by the first connection lead and the second connection lead are different.

5. The display panel of any one of claims 1-4, wherein, one of the first connection lead and the second connection lead is in contact with a surface of the substrate.

6. The display panel of any one of claims 1-5, wherein, the display panel further comprises: a plurality of front electrodes disposed on a side of the first surface of the substrate; the plurality of front electrodes comprising a first electrode and a second electrode, the first electrode and the second electrode being adjacent to each other; a plurality of back electrodes disposed on a side of the second surface of the substrate; the plurality of back electrodes comprising a third electrode and a fourth electrode, the third electrode and the fourth electrode being adjacent to each other; the first connection lead is configured to connect the first electrode and the third electrode; the second connection lead is configured to connect the second electrode and the fourth electrode; orthographic projections of the first electrode and the third electrode on the second surface at least partially overlap, and orthographic projections of the second electrode and the fourth electrode on the second surface at least partially overlap.

7. The display panel of claim 6, wherein, the first electrode and the second electrode are disposed in the same layer, and / or the third electrode and the fourth electrode are disposed in the same layer.

8. The display panel of claim 7, wherein, one of the first connection lead and the second connection lead is directly connected to the front electrodes and the back electrodes, and the other is connected to the front electrodes and the back electrodes through a via.

9. The display panel of claim 6, wherein, the first electrode and the second electrode are disposed in different layers, and the first electrode is closer to the first surface relative to the second electrode; and / or the third electrode and the fourth electrode are disposed in different layers, and the third electrode is closer to the second surface relative to the fourth electrode.

10. The display panel of claim 8, wherein, the first connection lead is closer to the substrate relative to the second connection lead.

11. The display panel of claim 9 or 10, wherein, an orthographic projection of the first electrode on the first surface at least partially coincides with an orthographic projection of the second electrode on the first surface; and / or an orthographic projection of the third electrode on the second surface at least partially coincides with an orthographic projection of the fourth electrode on the second surface.

12. The display panel of any one of claims 6-11, wherein, the display panel further comprises a plurality of pixel units on the first surface; two pixel units adjacent to each other in a first direction and both closer to the selected side surface are included in the plurality of pixel units, and the first electrode and the second electrode are disposed between the two pixel units.

13. The display panel of any one of claims 1-12, wherein, the display panel further comprises a plurality of pixel units on the first surface; Two pixel units adjacent to each other in the first direction and close to the selected side are included in the plurality of pixel units, and the first connecting lead and the second connecting lead are arranged between the two pixel units.

14. The display panel of any one of claims 6-11, wherein, The display panel further comprises a plurality of pixel units on the first surface; Two pixel units adjacent to each other in the first direction and close to the selected side are included in the plurality of pixel units, and the first electrode and the second electrode at least partially overlap with the two pixel units in the second direction. The second direction is perpendicular to the first direction.

15. The display panel of any one of claims 1-14, wherein, The display panel further comprises a first insulating layer. The first insulating layer is located between the first connecting lead and the second connecting lead.

16. The display panel of any one of claims 1-15, wherein, The display panel further comprises at least one recessed area located at least on the selected side of the substrate; The one of the first connecting lead and the second connecting lead closer to the substrate is located on the selected side of the substrate. The orthographic projection is located in the recessed area.

17. The display panel of claim 16, wherein, The ratio of the size of the recessed area along the first direction to the size of the first connecting lead along the first direction is 1-2.

18. The display panel of any one of claims 6-17, wherein, The display panel further comprises a protective layer; the protective layer covers at least the second connecting lead, and the front electrode and the back electrode connected with the second connecting lead.

19. A display device comprising: The display panel according to any one of claims 1-18; A circuit board electrically connected with the display panel; The circuit board is configured to drive the display panel to display an image.

20. A tiled display device comprising a plurality of display panels according to any one of claims 1-18 and at least one circuit board; The plurality of display panels are tiled, and each of the at least one circuit board is electrically connected with at least one of the display panels.

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