Imaging signal sampling circuit and method

Abstract

The present application provides an imaging signal sampling circuit and method. The circuit comprises: a first sampling module, which samples an imaging signal N times under the control of N first sampling signals and a second sampling signal to obtain 2N reset voltages; a second sampling module, which samples the imaging signal N times under the control of N third sampling signals and a fourth sampling signal to obtain 2N signal voltages; and an amplification module, wherein within each cycle of the imaging signal, when the imaging signal is sampled, the amplification module is controlled by means of a reset signal to perform a reset operation, and after sampling, 2N-1 instances of differential amplification processing are sequentially performed on the 2N reset voltages and the 2N signal voltages to obtain 2N-1 sampled signals. Two sampling modules sampling an imaging signal multiple times enhances the noise suppression strength of a circuit. In addition, sequentially performing amplification processing on reset voltages and signal voltages that are obtained after multiple instances of sampling to obtain multiple sampled signals, and performing multiple instances of averaging reduce an offset error in an output signal.

Description

Imaging signal sampling circuit and method Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to an imaging signal sampling circuit and method. Background Art

[0002] A CCD (Charge-Coupled Device) is an image sensor that converts light signals into electrical signals through photoelectric conversion. As a mature imaging technology, CCD is widely used. It is characterized by high imaging quality, high sensitivity, low noise, fast response, and high resolution, as well as high pixel integration and precise dimensions. It has extensive applications in astronomy, medical imaging equipment, microscopy, optical recognition, and other fields. In related technologies, traditional imaging signal sampling circuits primarily amplify the reset and signal levels of the imaging signal after each sampling. Imaging signals contain noise, and traditional imaging signal sampling circuits have a weak ability to suppress noise. While noise can be reduced by increasing the sampling capacitor, this also increases the chip area. Due to differences in integrated circuit processes, traditional imaging signal sampling circuits output a sampling signal with offset errors.

[0003] Therefore, how to provide an imaging signal sampling circuit that has strong noise suppression capability and can reduce offset errors is a technical problem that urgently needs to be solved.

[0004] Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides an imaging signal sampling circuit and method to solve at least one of the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.

[0007] According to one aspect of an embodiment of the present application, an imaging signal sampling circuit is provided, comprising:

[0008] A first sampling module is connected to the imaging signal, the first reference voltage, N first sampling signals, and the second sampling signal, and samples the imaging signal N times based on the first reference voltage under the control of the N first sampling signals and the second sampling signal to obtain 2N reset voltages;

[0009] a second sampling module, connected to the imaging signal, the first reference voltage, N third sampling signals, and a fourth sampling signal, and sampling the imaging signal N times based on the first reference voltage under the control of the N third sampling signals and the fourth sampling signal to obtain 2N signal voltages;

[0010] an amplification module connected to the first sampling module, the second sampling module, 2N-1 differential connection signals, a first amplified signal, a second amplified signal, and a reset signal. Within each cycle of the imaging signal, the amplification module alternately performs a reset operation and a differential amplification process. When the reset signal controls the amplification module to perform a reset operation, the amplification module synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling is completed, under the control of the 2N-1 differential connection signals, the first amplified signal, and the second amplified signal, 2N-1 differential amplification processes are successively performed on 2N reset voltages and 2N signal voltages to obtain 2N-1 sampling signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampling signal.

[0011] Wherein, i and N are integers, N≥2, 1≤i≤2N-1.

[0012] In one embodiment of the present invention, the first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling unit is connected to the first sampling signal and samples the imaging signal based on the first sampling signal to obtain the reset voltage. The first reference unit is connected to the reset sampling unit, the first reference voltage and the second sampling signal and uses the first reference voltage as a reference value of the reset sampling unit based on the second sampling signal.

[0013] In one embodiment of the present invention, the reset sampling unit includes a first sampling switch and a first sampling capacitor, one end of the first sampling switch is connected to the imaging signal, the other end of the first sampling switch is connected to one end of the first sampling capacitor, and a control end of the first sampling switch is connected to the first sampling signal. The first reference unit includes a second sampling switch, one end of the second sampling switch is connected to the other end of the first sampling capacitor, the other end of the second sampling switch is connected to the first reference voltage, and the control end of the second sampling switch is connected to the second sampling signal.

[0014] In one embodiment of the present invention, the second sampling module includes 2N signal sampling units and a second reference unit. The signal sampling unit is connected to the third sampling signal and samples the imaging signal N times based on the third sampling signal to obtain the signal voltage. The second reference unit is connected to the signal sampling unit, the first reference voltage and the fourth sampling signal, and uses the first reference voltage as a reference value of the signal sampling unit based on the fourth sampling signal.

[0015] In one embodiment of the present invention, the signal sampling unit includes a third sampling switch and a second sampling capacitor, one end of the third sampling switch is connected to the imaging signal, the other end of the third sampling switch is connected to one end of the second sampling capacitor, and a control end of the third sampling switch is connected to the third sampling signal. The second reference unit includes a fourth sampling switch, one end of the fourth sampling switch is connected to the other end of the second sampling capacitor, the other end of the fourth sampling switch is connected to the first reference voltage, and the control end of the fourth sampling switch is connected to the fourth sampling signal.

[0016] In one embodiment of the present invention, the amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to 2N-1 differential connection signals and the first amplification signal. Under the control of the 2N-1 differential connection signals and the first amplification signal, 2N reset voltages and 2N signal voltages are connected one-to-one to obtain 2N-1 differential signals. The amplification unit is connected to the differential processing unit, the second amplification signal and the reset signal. When the reset signal controls the amplification unit to perform a reset operation, the first sampling module or the second sampling module is synchronously controlled to sample the imaging signal. After sampling is completed, the 2N-1 differential signals are amplified successively under the control of the second amplification signal to obtain 2N-1 sampling signals.

[0017] In one embodiment of the present invention, the differential processing unit includes 2N-1 differential connection switches, a first amplifying switch, and a second amplifying switch; one end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplifying switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplifying switch, a control end of the i-th differential connection switch is connected to the i-th differential connection signal, and the control ends of the first amplifying switch and the second amplifying switch are connected to the first amplified signal. The other end of the first amplifying switch is the first output end of the differential processing unit, and the other end of the second amplifying switch is the second output end of the differential processing unit.

[0018] In one embodiment of the present invention, the amplifying unit includes a first reset switch, a second reset switch, a third reset switch, a fourth reset switch, a fifth reset switch, a sixth reset switch, a third amplifying switch, a fourth amplifying switch, a fifth amplifying switch, a sixth amplifying switch, a first feedback capacitor, a second feedback capacitor, and an operational amplifier. One end of the first reset switch is connected to the non-inverting input of the operational amplifier, and the other end of the first reset switch is connected to the inverting input of the operational amplifier. The non-inverting input of the operational amplifier is connected to the inverting output of the operational amplifier via the third amplifying switch, the first feedback capacitor, and the fourth amplifying switch connected in series. The inverting input of the operational amplifier is connected to the non-inverting output of the operational amplifier via the fifth amplifying switch, the second feedback capacitor, and the sixth amplifying switch connected in series. The inverting output of the operational amplifier is connected to the non-inverting output of the operational amplifier via the second reset switch connected in series. The second reference voltage is connected to the first feedback capacitor via the third reset switch connected in series. The first feedback capacitor is connected to one end of the first feedback capacitor, the third reference voltage is connected to the other end of the first feedback capacitor via the fourth reset switch connected in series, the second reference voltage is connected to one end of the second feedback capacitor via the fifth reset switch connected in series, and the fourth reference voltage is connected to the other end of the second feedback capacitor via the sixth reset switch connected in series. The control end of the first reset switch, the control end of the second reset switch, the control end of the third reset switch, the control end of the fourth reset switch, the control end of the fifth reset switch, and the control end of the sixth reset switch are connected to the reset signal, the control end of the third amplifying switch, the control end of the fourth amplifying switch, the control end of the fifth amplifying switch, and the control end of the sixth amplifying switch are connected to the second amplified signal, the non-inverting input end of the operational amplifier is connected to the first output end of the differential processing unit, the inverting input end of the operational amplifier is connected to the second output end of the differential processing unit, and the non-inverting output end of the operational amplifier and the inverting output end of the operational amplifier cooperate to output the sampling signal.

[0019] According to another aspect of an embodiment of the present application, an imaging signal sampling method is further provided, which is applied to the imaging signal sampling circuit as described above, comprising:

[0020] In the first half cycle of the imaging signal, the imaging signal is sampled N times, each sampling is performed through M sampling capacitors to obtain M*N reset voltages;

[0021] In the second half cycle of the imaging signal, the imaging signal is sampled N times, each sampling is performed through M sampling capacitors to obtain M*N signal voltages;

[0022] In each cycle, a reset operation and a differential amplification process are performed alternately, and 2N samplings are performed sequentially and synchronously with at least part of the reset operation, and M*N reset voltages and M*N signal voltages are differentially amplified M*N-1 times to obtain M*N-1 sampling signals; during the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampling signal;

[0023] Wherein, t, N, and M are integers, N ≥ 2, M ≥ 2, and 1 ≤ t ≤ M*N-1.

[0024] The present application provides an imaging signal sampling circuit and method. The circuit includes: a first sampling module, under the control of N first sampling signals and a second sampling signal, samples the imaging signal N times to obtain 2N reset voltages; a second sampling module, under the control of N third sampling signals and a fourth sampling signal, samples the imaging signal N times to obtain 2N signal voltages; within each cycle of the imaging signal, when sampling the imaging signal, the amplification module is controlled by the reset signal to perform a reset operation; after the sampling is completed, the 2N reset voltages and the 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampling signals. The present application uses two sampling modules to sample the imaging signal multiple times to enhance the sampling circuit's ability to suppress imaging signal noise. The reset voltages and signal voltages obtained from the multiple samplings are sequentially amplified to obtain multiple sampling signals. The offset error of the output signal is reduced by multiple averaging. The sampling circuit both enhances noise suppression and reduces output signal error, thereby improving the precision and accuracy of signal sampling.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a specific structure of a conventional imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0027] FIG2 is a timing diagram of a conventional imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0028] FIG3 is an exploded diagram of sampling and differential amplification of a conventional imaging signal sampling circuit according to an exemplary embodiment of the present invention;

[0029] FIG4 is a block diagram of an imaging signal sampling circuit according to an exemplary embodiment of the present invention;

[0030] FIG5 is a specific structural diagram of an imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0031] FIG6 is a timing diagram of an imaging signal sampling circuit according to an exemplary embodiment of the present invention;

[0032] FIG7 is an exploded diagram of sampling and differential amplification of an imaging signal sampling circuit according to an exemplary embodiment of the present invention;

[0033] FIG8 is a comparison diagram of a conventional sampling signal and a sampling signal of the present application, shown in an exemplary embodiment of the present invention;

[0034] FIG9 is a specific structural diagram of an imaging signal sampling circuit shown in another exemplary embodiment of the present invention;

[0035] FIG. 10 is a timing control diagram of an imaging signal sampling circuit according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0037] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0038] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0039] CCD (Charge-Coupled Device) imaging technology is a mature imaging technology with a wide range of applications. It features high-quality imaging, high sensitivity, low noise, fast response, and high resolution, as well as high pixel integration and precise dimensions. It has extensive applications in astronomy, medical imaging, microscopy, optical recognition, and other fields. These characteristics make CCD imaging a commonly used image sensor in machine vision.

[0040] Please refer to FIG. 1 , which shows a specific structure of a traditional imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0041] Please refer to FIG. 2 , which is a timing diagram of a conventional imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0042] Please refer to FIG. 3 , which is an exploded diagram illustrating sampling and differential amplification of a conventional imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0043] As shown in FIG1 , the conventional imaging signal sampling circuit includes switches S11, S13, S15, S22, S23 and a sampling capacitor C S1_1 and C S1_2 The first sampling network consists of switches S11', S13', S15, S22', S23 and sampling capacitor C S2_1 、C S2_2 The second sampling network is composed of Cf, the feedback capacitor, and the operational amplifier AMP is the amplifier of the sampling signal. As shown in Figure 1 and Figure 2, when the imaging signal V CCD In the Nth cycle, the imaging signal V CCD The first state is the imaging signal V CCD When the value of is reset level Vr, sampling is performed through the first sampling network, the switch S11 is turned on by the signal K11, and the first sampling capacitor Cs1_1 is connected to the imaging signal V CCD At the same time, the switch S22' is turned on by the signal K22', and the switch S23 is turned on by the signal K23. The operational amplifier AMP samples the imaging signal V obtained by the previous cycle. CCD The output voltage of the operational amplifier AMP is VOP'-VON', and the imaging signal sampling circuit is V CCD The equivalent circuit diagram for sampling the first state is shown in FIG3( a ).

[0044] Secondly, if the imaging signal V CCD When it is in the second state, the imaging signal V CCD The value of the signal level V S1 When the switch S13 is turned on by the signal K13, the second sampling capacitor C S1_2 Imaging signal V CCD The signal level V S1 Sampling is performed, the switch S15 is turned on by the signal K15, the operational amplifier AMP is in the reset state, and the equivalent circuit diagram of the imaging signal sampling circuit in the reset state is shown in Figure 3(b). At this time, the first sampling capacitor C S1_1 and the second sampling capacitor C S2_1 The reset level Vr and signal level V of the imaging signal are completed respectively.S1 of sampling.

[0045] Next, when the imaging signal V CCD In the N+1th cycle, the imaging signal V CCD The first state is the imaging signal V CCD When the value of is the reset level Vr, the switch S11' is turned on by the signal K11', and the third sampling capacitor C S2_1 Imaging signal V CCD The reset level Vr is sampled, the switch S22 is turned on by the signal K22, and the switch S23 is turned on by the signal K23. The operational amplifier AMP performs differential amplification on the reset level and the signal level obtained by sampling in the Nth cycle. The output voltage of the operational amplifier AMP is VOP-VON. The imaging signal sampling circuit performs differential amplification on the imaging signal V CCD The equivalent circuit diagram for sampling the first state is shown in FIG3(c).

[0046] Then, the imaging signal V CCD The second state is the imaging signal V CCD The value of the signal level V S2 When the switch S13' is turned on by the signal K13', the fourth sampling capacitor C S2_2 Imaging signal V CCD The signal level V S2 Sampling is performed, the switch S15 is turned on by the signal K15, and the operational amplifier AMP is in the reset state. The equivalent circuit diagram of the imaging signal sampling circuit in the reset state is shown in FIG3( d ).

[0047] It can be seen from the traditional imaging signal sampling circuit that the traditional imaging signal sampling circuit completes a sampling for each state of the imaging signal and then performs amplification. Therefore, there are two main problems. Because the imaging signal itself has noise, the above-mentioned traditional imaging signal sampling circuit has a relatively weak noise suppression ability for the imaging signal; if the noise of the imaging signal sampling device is to be improved, it is necessary to increase the sampling capacitor, but this will increase the chip area; at the same time, the operational amplifier AMP and the subsequent quantization analog-to-digital converter both have noise, and the traditional imaging signal sampling circuit cannot suppress the noise caused by the operational amplifier AMP and the subsequent quantization analog-to-digital converter; and because it uses switches S11, S13, S15, S22, S23 and sampling capacitor C S1_1 and C S1_2 The first sampling network consists of switches S11', S13', S15, S22', S23 and sampling capacitor C S2_1 and C S2_2Due to the errors in the integrated circuit manufacturing process, there is a mismatch between the two sampling networks, which causes the sampling signal obtained by the operational amplifier AMP to have an inherent offset error when it is in the amplification state.

[0048] Please refer to FIG. 4 , which is a block diagram of an imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0049] As shown in FIG4 , in an exemplary embodiment, an imaging signal sampling circuit includes:

[0050] The first sampling module receives the imaging signal V CCD , a first reference voltage V1, N first sampling signals K11_j, and a second sampling signal K2, and under the control of the N first sampling signals K11_j and the second sampling signal K2, the imaging signal V is rectified based on the first reference voltage V1. CCD Perform N sampling times to obtain 2N reset voltages;

[0051] The second sampling module receives the imaging signal V CCD , the first reference voltage V1, N third sampling signals K13_j, and the fourth sampling signal K4, under the control of the N third sampling signals K13_j and the fourth sampling signal K4, the imaging signal V is regulated based on the first reference voltage V1. CCD Perform N sampling times to obtain 2N signal voltages;

[0052] The amplification module is connected to the first sampling module, the second sampling module, 2N-1 differential connection signals K22_i, the first amplified signal K22, the second amplified signal K23 and the reset signal K15. In each cycle of the imaging signal, the amplification module alternately performs a reset operation and a differential amplification process. When the reset signal K15 controls the amplification module to perform a reset operation, the first sampling module or the second sampling module is synchronously controlled to perform a differential amplification process on the imaging signal V CCD When sampling is performed, after the sampling is completed, under the control of the 2N-1 differential connection signals K22_i, the first amplified signal K22, and the second amplified signal K23, the 2N reset voltages and the 2N signal voltages are differentially amplified 2N-1 times in succession to obtain 2N-1 sampling signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampling signal.

[0053] Wherein, i and N are integers, N≥2, 1≤i≤2N-1.

[0054] It should be noted that j is an integer, 1≤j≤N.

[0055] Example 1

[0056] Please refer to FIG. 5 , which is a detailed structural diagram of an imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0057] In detail, the first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling unit receives a first sampling signal and samples the imaging signal based on the first sampling signal to obtain a reset voltage. The first reference unit receives the reset sampling unit, the first reference voltage, and the second sampling signal and uses the first reference voltage as a reference value for the reset sampling unit based on the second sampling signal. Specifically, as shown in FIG5 , the first sampling module includes four reset sampling units and a first reference unit. The first reset sampling unit and the second reset sampling unit receive a first first sampling signal K11_1, and the second reset sampling unit and the third reset sampling unit receive a second first sampling signal K11_2. Under the control of the first first sampling signal K11_1 and the second first sampling signal K11_2, the imaging signal V is sampled. CCD Perform two samplings to obtain four reset voltages; the first reference unit is connected to the four reset sampling units, the first reference voltage V1 and the second sampling signal K2. During sampling, based on the control of the second sampling signal K2, the first reference voltage V1 is used as the reference value of the reset sampling unit.

[0058] In more detail, the reset sampling unit includes a first sampling switch and a first sampling capacitor, one end of the first sampling switch is connected to the imaging signal, the other end of the first sampling switch is connected to one end of the first sampling capacitor, and the control end of the first sampling switch is connected to the first sampling signal. The first reference unit includes a second sampling switch, one end of the second sampling switch is connected to the other end of the first sampling capacitor, the other end of the second sampling switch is connected to the first reference voltage, and the control end of the second sampling switch is connected to the second sampling signal.

[0059] Specifically, as shown in FIG5 , the first reset sampling unit includes a first sampling switch S11_11 and a first sampling capacitor C S1_1 One end of the first sampling switch S11_11 is connected to the imaging signal V CCD The other end of the first sampling switch S11_11 is connected to the first sampling capacitor C S1_1 The control end of the first sampling switch S11_11 is connected to the first sampling signal K11_1; the second reset sampling unit includes the first sampling switch S11_12 and the first sampling capacitor C S1_2 One end of the first sampling switch S11_12 is connected to the imaging signal V CCD The other end of the first sampling switch S11_12 is connected to the first sampling capacitor C S1_2 One end of the first sampling switch S11_12 is connected to the first sampling signal K11_1.

[0060] Similarly, the third reset sampling unit includes a first sampling switch S11_21 and a first sampling capacitor C S1_3 One end of the first sampling switch S11_21 is connected to the imaging signal V CCD The other end of the first sampling switch S11_21 is connected to the first sampling capacitor C S1_3 The control end of the first sampling switch S11_21 is connected to the second first sampling signal K11_2; the fourth reset sampling unit includes the first sampling switch S11_22 and the first sampling capacitor C S1_4 One end of the first sampling switch S11_22 is connected to the imaging signal V CCD The other end of the first sampling switch S11_22 is connected to the first sampling capacitor C S1_4 The first reference unit includes a second sampling switch S1_1, one end of which is connected to a first sampling capacitor (C S1_1 、C S1_2 、C S1_3 、C S1_4 ), the other end of the second sampling switch S1_1 is connected to the first reference voltage V1, and the control end of the second sampling switch S1_1 is connected to the second sampling signal K2.

[0061] In detail, the second sampling module includes 2N signal sampling units and second reference units. The signal sampling units are connected to the third sampling signal and sample the imaging signal based on the third sampling signal to obtain a signal voltage. The second reference unit is connected to the signal sampling unit, the first reference voltage, and the fourth sampling signal and uses the first reference voltage as a reference value for the signal sampling unit based on the fourth sampling signal. As shown in Figure 5, the second sampling module includes four signal sampling units and second reference units. The first signal sampling unit and the second signal sampling unit are connected to the first third sampling signal K13_1, and the third signal sampling unit and the fourth signal sampling unit are connected to the second third sampling signal K13_2. Under the control of the first third sampling signal K13_1 and the second third sampling signal K13_2, the imaging signal V is sampled. CCD Perform two samplings to obtain four signal voltages; the second reference unit is connected to the four signal sampling units, the first reference voltage V1 and the fourth sampling signal K4. During sampling, based on the control of the fourth sampling signal K4, the first reference voltage V1 is used as the reference value of the signal sampling unit.

[0062] In more detail, the signal sampling unit includes a third sampling switch and a second sampling capacitor, one end of the third sampling switch is connected to the imaging signal, the other end of the third sampling switch is connected to one end of the second sampling capacitor, and the control end of the third sampling switch is connected to the third sampling signal. The second reference unit includes a fourth sampling switch, one end of the fourth sampling switch is connected to the other end of the second sampling capacitor, the other end of the fourth sampling switch is connected to the first reference voltage, and the control end of the fourth sampling switch is connected to the fourth sampling signal.

[0063] Specifically, as shown in FIG5 , the first signal sampling unit includes a third sampling switch S13_11 and a second sampling capacitor C S2_1 One end of the third sampling switch S13_11 is connected to the imaging signal V CCD The other end of the third sampling switch S13_11 is connected to the second sampling capacitor C S2_1 The control end of the third sampling switch S13_11 is connected to the first third sampling signal K13_1; the second signal sampling unit includes a third sampling switch S13_12 and a second sampling capacitor C S2_2 One end of the third sampling switch S13_12 is connected to the imaging signal V CCD The other end of the third sampling switch S13_12 is connected to the second sampling capacitor C S2_2 One end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1, and the control end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1.

[0064] Similarly, the third signal sampling unit includes a third sampling switch S13_21 and a second sampling capacitor C S2_3 One end of the third sampling switch S13_21 is connected to the imaging signal V CCD The other end of the third sampling switch S13_21 is connected to the second sampling capacitor C S2_3 The control end of the third sampling switch S13_21 is connected to the second third sampling signal K13_2; the fourth signal sampling unit includes a third sampling switch S13_22 and a second sampling capacitor C S2_4 One end of the third sampling switch S13_22 is connected to the imaging signal V CCD The other end of the third sampling switch S13_22 is connected to the second sampling capacitor C S2_4 The control terminal of the third sampling switch S13_22 is connected to the second third sampling signal K13_2. The second reference unit includes a fourth sampling switch S1_2, one end of which is connected to the second sampling capacitor (C S2_1 、C S2_2 、C S2_3 、C S2_4 ), the other end of the fourth sampling switch S1_2 is connected to the first reference voltage V1, and the control end of the fourth sampling switch S1_2 is connected to the fourth sampling signal K4.

[0065] It should be noted that the capacitance value of the first sampling capacitor is equal to the capacitance value of the second sampling capacitor.

[0066] In detail, the amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to 2N-1 differential connection signals and a first amplification signal. Under the control of the 2N-1 differential connection signals and the first amplification signal, 2N reset voltages and 2N signal voltages are connected one-to-one to obtain 2N-1 differential signals; the amplification unit is connected to the differential processing unit, the second amplification signal and the reset signal. When the reset signal controls the amplification unit to perform a reset operation, the first sampling module or the second sampling module is synchronously controlled to sample the imaging signal. After the sampling is completed, the 2N-1 differential signals are amplified successively under the control of the second amplification signal to obtain 2N-1 sampling signals. It should be noted that, as shown in FIG5 , the amplification module includes a differential processing unit and an amplification unit. The differential processing unit receives three differential connection signals K22_i and a first amplified signal K22. Under the control of the three differential connection signals K22_i and the first amplified signal K22, three reset voltages are connected to three signal voltages in a one-to-one correspondence to obtain three differential signals. The amplification unit receives a second amplified signal K23 and a reset signal K15. When the reset signal K15 controls the amplification unit to perform a reset operation, the first sampling module is controlled to process the imaging signal V CCD Sampling or controlling the second sampling module to sample the imaging signal V CCD Sampling is performed. After the sampling is completed, the three differential signals are amplified in succession under the control of the second amplification signal K23 to obtain three sampling signals.

[0067] In more detail, the differential processing unit includes N-1 differential connection switches, a first amplifying switch, and a second amplifying switch; one end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplifying switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplifying switch, the control end of the i-th differential connection switch is connected to the i-th differential connection signal, the control end of the first amplifying switch and the control end of the second amplifying switch are connected to the first amplified signal, wherein the other end of the first amplifying switch is the first output end of the differential processing unit, and the other end of the second amplifying switch is the second output end of the differential processing unit.

[0068] Specifically, as shown in FIG5 , the differential processing unit includes a first differential connection switch S21_1, a second differential connection switch S21_2, a third differential connection switch S21_3, a first amplifying switch S22_1, and a second amplifying switch S22_2. One end of the first differential connection switch S21_1 is connected to the first first sampling capacitor C S1_1One end of the first sampling capacitor C S1_1 The other end of the first differential connection switch S21_1 is connected to one end of the first amplifying switch S22_1, and the other end of the first differential connection switch S21_1 is connected to the first second sampling capacitor C S2_1 One end of the first and second sampling capacitors C S2_1 The other end of the differential connection switch S21_1 is connected to one end of the second amplifying switch S22_2, the control end of the first differential connection switch S21_1 is connected to the first differential connection signal K21_1; one end of the second differential connection switch S21_2 is connected to the second first sampling capacitor C S1_2 One end of the second first sampling capacitor C S1_2 The other end of the second differential connection switch S21_2 is connected to the second sampling capacitor C S2_2 One end of the second sampling capacitor C S2_2 The other end is connected to one end of the second amplifying switch S22_2, the control end of the second differential connection switch S21_2 is connected to the second differential connection signal K21_2; one end of the third differential connection switch S21_3 is connected to the third first sampling capacitor C S1_3 One end of the third first sampling capacitor C S1_3 The other end of the third differential connection switch S21_3 is connected to one end of the first amplifying switch S22_1, and the other end of the third differential connection switch S21_3 is connected to the third second sampling capacitor C S2_3 One end of the third second sampling capacitor C S2_3 The other end of the differential connection switch S21_3 is connected to one end of the second amplifying switch S22_2. The control end of the third differential connection switch S21_3 is connected to the third differential connection signal K21_3. The control end of the first amplifying switch S22_1 and the control end of the second amplifying switch S22_2 are connected to the first amplified signal K22. The other end of the first amplifying switch S22_1 is the first output end of the differential processing unit, and the other end of the second amplifying switch S22_2 is the second output end of the differential processing unit.

[0069] In more detail, as shown in FIG5 , the amplifying unit includes a first reset switch S15_1, a second reset switch S15_2, a third reset switch S15_3, a fourth reset switch S15_4, a fifth reset switch S15_5, a sixth reset switch S15_6, a third amplifying switch S23_1, a fourth amplifying switch S23_2, a fifth amplifying switch S23_3, a sixth amplifying switch S23_4, a first feedback capacitor C1, a second feedback capacitor C2, and an operational amplifier AMP. One end of the first reset switch S15_1 is connected to the non-inverting input end of the operational amplifier AMP, and the other end of the first reset switch S15_1 is connected to the inverting input end of the operational amplifier AMP. The non-inverting input terminal of the operational amplifier AMP is connected to the inverting output terminal of the operational amplifier AMP in sequence through the third amplifier switch S23_1, the first feedback capacitor C1, and the fourth amplifier switch S23_2 connected in series. The inverting output terminal of the operational amplifier AMP is connected to the non-inverting output terminal of the operational amplifier AMP in sequence through the fifth amplifier switch S23_3, the second feedback capacitor C2, and the sixth amplifier switch S23_4 connected in series. The inverting output terminal of the operational amplifier AMP is connected to the non-inverting output terminal of the operational amplifier AMP through the second reset switch S15_2 connected in series. The second reference voltage V2 is connected to one end of the first feedback capacitor C1 through the third reset switch S15_3 connected in series. The reference voltage V3 is connected to the other end of the first feedback capacitor C1 via the fourth reset switch S15_4 connected in series. The second reference voltage V2 is connected to one end of the second feedback capacitor C2 via the fifth reset switch S15_5 connected in series. The fourth reference voltage V4 is connected to the other end of the second feedback capacitor C2 via the sixth reset switch S15_6 connected in series. The control ends of the first reset switch S15_1, the second reset switch S15_2, the third reset switch S15_3, the fourth reset switch S15_4, the fifth reset switch S15_5, and the sixth reset switch S15_6 are connected to the reset signal K15. The third amplification switch The control end of S23_1, the control end of the fourth amplifying switch S23_2, the control end of the fifth amplifying switch S23_3, and the control end of the sixth amplifying switch S23_4 are connected to the second amplified signal K23, the non-inverting input end of the operational amplifier AMP is connected to the first output end of the differential processing unit, the non-inverting input end of the operational amplifier AMP is connected to the other end of the first amplifying switch S22_1, the inverting input end of the operational amplifier AMP is connected to the second output end of the differential processing unit, the inverting input end of the operational amplifier AMP is connected to the other end of the second amplifying switch S22_2, and the non-inverting output end of the operational amplifier AMP and the inverting output end of the operational amplifier AMP cooperate to output the sampling signal.

[0070] As shown in FIG4 to FIG7 , the principle of the imaging signal sampling circuit in an embodiment provided by the present application is specifically as follows:

[0071] When N is 2, the first sampling module includes four reset sampling units, the control ends of the first sampling switches in the first reset sampling unit and the second reset sampling unit are connected to the first first sampling signal K11_1, and the control ends of the first sampling switches in the third reset sampling unit and the fourth reset sampling unit are connected to the second first sampling signal K11_2; the second sampling module includes four signal sampling units, the control ends of the third sampling switches in the first reset sampling unit and the second reset sampling unit are connected to the first third sampling signal K13_1, and the control ends of the third sampling switches in the third reset sampling unit and the fourth reset sampling unit are connected to the second third sampling signal K13_2.

[0072] As shown in FIG6 , the imaging signal V CCD In the Nth cycle, the imaging signal V CCD The first state is the imaging signal V CCD When the value of is the reset level Vr, the first sampling signal K11_1 and the second sampling signal K2 are set to high level, the reset signal K15 is set to high level, the first sampling switch S11_11 and the second sampling switch S11_12 are turned on, the second sampling switch S1_1 is turned on, and based on the first sampling capacitor C S1_1 and the second first sampling capacitor C S1_2 Imaging signal V CCD Sampling is performed twice, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram of the imaging signal sampling is shown in FIG7( a ).

[0073] After sampling is completed, the third differential connection signal K21_3 is set to a high level, the first amplified signal K22 and the second amplified signal K23 are set to a high level, the third differential connection switch S21_3 is turned on, the first amplified switch S22_1 and the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are turned on, and the third first sampling capacitor C in the N-1th cycle is turned on. S1_3 The reset voltage and the third second sampling capacitor C S2_3 The signal voltage is differentially amplified to obtain a sampling signal, which is VOP1'-VON1'. The equivalent circuit diagram of imaging signal sampling is shown in Figure 7(b).

[0074] After the amplification is completed, the second first sampling signal K11_2 and the second sampling signal K2 are set to a high level, the reset signal K15 is set to a high level, the third first sampling switch S11_21 and the fourth first sampling switch S11_22 are turned on, the second sampling switch S1_1 is turned on, and based on the third first sampling capacitor C S1_3and the fourth first sampling capacitor C S1_4 Imaging signal V CCD Sampling is performed twice, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram of the imaging signal sampling is shown in FIG7( c ).

[0075] After sampling is completed, the imaging signal V CCD In the Nth cycle, the imaging signal V CCD Change to the second state, that is, the imaging signal V CCD The value of the signal level V S1 When the first third sampling signal K13_1 and the fourth sampling signal K4 are set to a high level, the reset signal K15 is set to a high level, the first third sampling switch S13_11 and the second third sampling switch S13_12 are turned on, the fourth sampling switch S1_2 is turned on, and based on the first second sampling capacitor C S2_1 and the second sampling capacitor C S2_2 Imaging signal V CCD Sampling is performed twice, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram of the imaging signal sampling is shown in FIG7( d ).

[0076] After the sampling is completed, the first differential connection signal K21_1 is set to a high level, the first amplified signal K22 and the second amplified signal K23 are set to a high level, the first differential connection switch S21_1 is turned on, the first amplified switch S22_1 and the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are turned on, and the first first sampling capacitor C in the Nth cycle is turned on. S1_1 The reset voltage and the first and second sampling capacitors C S2_1 The signal voltage is differentially amplified to obtain a sampling signal, which is VOP0-VON0. The equivalent circuit diagram of imaging signal sampling is shown in Figure 7(e).

[0077] After the amplification is completed, the second third sampling signal K13_2 and the fourth sampling signal K4 are set to a high level, the reset signal K15 is set to a high level, the third third sampling switch S13_21 and the fourth third sampling switch S13_22 are turned on, the fourth sampling switch S1_2 is turned on, and based on the third second sampling capacitor C S2_3 and the fourth second sampling capacitor C S2_4 Imaging signal V CCD Sampling is performed twice, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram of the imaging signal sampling is shown in FIG7(f).

[0078] After the sampling is completed, the second differential connection signal K21_2 is set to a high level, the first amplified signal K22 and the second amplified signal K23 are set to a high level, the second differential connection switch S21_2 is turned on, the first amplified switch S22_1 and the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are turned on, and the second first sampling capacitor C in the Nth cycle is turned on. S1_2 and the second sampling capacitor C S2_2 Perform differential amplification to obtain a sampling signal, which is VOP1-VON1. The equivalent circuit diagram of imaging signal sampling is shown in Figure 7(g).

[0079] It should be noted that the sampling signal in the Nth cycle is determined as shown in expression (1) or (2): VOP-VON=C1 / C S1_m ((Vr-V S1 )-(V3-V4)) (1) VOP-VON=C2 / C S2_m ((Vr-V S1 )-(V3-V4)) (2)

[0080] In expressions (1) and (2), VOP-VON is the sampling signal, C1 is the first feedback capacitor, C2 is the second feedback capacitor, and C S1_m is the first sampling capacitor, C S2_m is the second sampling capacitor, Vr is the reset voltage of the imaging signal in the first state, V S1 is the signal voltage of the imaging signal in the second state, V3 is the third reference voltage, and V4 is the fourth reference voltage, wherein m is an integer, 1≤m≤2N.

[0081] Similarly, the principle of determining the sampling signal in other periods is the same, except that when the imaging signal is in the second state, the value of the signal voltage is different, which will not be described here.

[0082] Please refer to FIG8 , which is a comparison diagram of a traditional sampling signal and a sampling signal of the present application shown in an exemplary embodiment of the present invention.

[0083] Under the same conditions, a conventional imaging signal sampling circuit and the imaging signal sampling circuit provided by the present application were simulated, as shown in Figure 8. The sampling signal of the conventional imaging signal sampling circuit is shown in Figure 8(a). This shows that after the two sampling networks alternately sample, there is a significant offset between the output signals of the operational amplifier AMP. At the same time, after sampling by the same sampling network, the output signal of the operational amplifier AMP has significant noise. The sampling signal output of the imaging signal sampling circuit provided by the present application is shown in Figure 8(b). As shown in Figure 8(b), the noise of the output signal is significantly suppressed, and the offset caused by the conventional imaging signal sampling circuit is eliminated.

[0084] Example 2

[0085] Please refer to FIG. 9 , which is a detailed structural diagram of an imaging signal sampling circuit according to another exemplary embodiment of the present invention.

[0086] Please refer to FIG. 10 , which is a timing control diagram of an imaging signal sampling circuit according to another exemplary embodiment of the present invention.

[0087] In detail, as shown in FIG9 , when N is 3, the first sampling module includes 6 reset sampling units and a first reference unit. The first reset sampling unit and the second reset sampling unit are connected to the first first sampling signal K11_1, the third reset sampling unit and the fourth reset sampling unit are connected to the second first sampling signal K11_2, and the fifth reset sampling unit and the sixth reset sampling unit are connected to the third first sampling signal K11_3. Under the control of the first first sampling signal K11_1, the second first sampling signal K11_2 and the third first sampling signal K11_3, the imaging signal V CCD Perform three samplings to obtain six reset voltages; the first reference unit is connected to the six reset sampling units, the first reference voltage V1 and the second sampling signal K2. During sampling, based on the control of the second sampling signal K2, the first reference voltage V1 is used as the reference value of the six reset sampling units.

[0088] In more detail, as shown in FIG9 , the first reset sampling unit includes a first sampling switch S11_11 and a first sampling capacitor C S1_1 One end of the first sampling switch S11_11 is connected to the imaging signal V CCD The other end of the first sampling switch S11_11 is connected to the first sampling capacitor C S1_1 The control end of the first sampling switch S11_11 is connected to the first sampling signal K11_1; the second reset sampling unit includes the first sampling switch S11_12 and the first sampling capacitor C S1_2 One end of the first sampling switch S11_12 is connected to the imaging signal V CCDThe other end of the first sampling switch S11_12 is connected to the first sampling capacitor C S1_2 One end of the first sampling switch S11_12 is connected to the first sampling signal K11_1.

[0089] As shown in FIG9 , the third reset sampling unit includes a first sampling switch S11_21 and a first sampling capacitor C S1_3 One end of the first sampling switch S11_21 is connected to the imaging signal V CCD The other end of the first sampling switch S11_21 is connected to the first sampling capacitor C S1_3 The control end of the first sampling switch S11_21 is connected to the second first sampling signal K11_2; the fourth reset sampling unit includes the first sampling switch S11_22 and the first sampling capacitor C S1_4 One end of the first sampling switch S11_22 is connected to the imaging signal V CCD The other end of the first sampling switch S11_22 is connected to the first sampling capacitor C S1_4 One end of the first sampling switch S11_22 is connected to the second first sampling signal K11_2.

[0090] As shown in FIG9 , the fifth reset sampling unit includes a first sampling switch S11_31 and a first sampling capacitor C S1_5 One end of the first sampling switch S11_31 is connected to the imaging signal V CCD The other end of the first sampling switch S11_31 is connected to the first sampling capacitor C S1_5 The control end of the first sampling switch S11_31 is connected to the third first sampling signal K11_3; the sixth reset sampling unit includes the first sampling switch S11_32 and the first sampling capacitor C S1_6 One end of the first sampling switch S11_32 is connected to the imaging signal V CCD The other end of the first sampling switch S11_32 is connected to the first sampling capacitor C S1_6 The first reference unit includes a second sampling switch S1_1, one end of which is connected to the first sampling capacitor (C S1_1 、C S1_2 、C S1_3 、C S1_4 、C S1_5 、C S1_6 ), the other end of the second sampling switch S1_1 is connected to the first reference voltage V1, and the control end of the second sampling switch S1_1 is connected to the second sampling signal K2.

[0091] In detail, as shown in FIG9 , the second sampling module includes 6 signal sampling units and a second reference unit. The first signal sampling unit and the second signal sampling unit are connected to the first third sampling signal K13_1, the third signal sampling unit and the fourth signal sampling unit are connected to the second third sampling signal K13_2, and the fifth signal sampling unit and the sixth signal sampling unit are connected to the third third sampling signal K13_3. Under the control of the first third sampling signal K13_1, the second third sampling signal K13_2 and the third third sampling signal K13_3, the imaging signal V CCD Perform three samplings to obtain six signal voltages; the second reference unit is connected to the six signal sampling units, the first reference voltage V1 and the fourth sampling signal K4. During sampling, based on the control of the fourth sampling signal K4, the first reference voltage V1 is used as the reference value of the signal sampling unit.

[0092] In more detail, as shown in FIG9 , the first signal sampling unit includes a third sampling switch S13_11 and a second sampling capacitor C S2_1 One end of the third sampling switch S13_11 is connected to the imaging signal V CCD The other end of the third sampling switch S13_11 is connected to the second sampling capacitor C S2_1 The control end of the third sampling switch S13_11 is connected to the first third sampling signal K13_1; the second signal sampling unit includes a third sampling switch S13_12 and a second sampling capacitor C S2_2 One end of the third sampling switch S13_12 is connected to the imaging signal V CCD The other end of the third sampling switch S13_12 is connected to the second sampling capacitor C S2_2 One end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1, and the control end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1.

[0093] As shown in FIG9 , the third signal sampling unit includes a third sampling switch S13_21 and a second sampling capacitor C S2_3 One end of the third sampling switch S13_21 is connected to the imaging signal V CCD The other end of the third sampling switch S13_21 is connected to the second sampling capacitor C S2_3 The control end of the third sampling switch S13_21 is connected to the second third sampling signal K13_2; the fourth signal sampling unit includes a third sampling switch S13_22 and a second sampling capacitor C S2_4 One end of the third sampling switch S13_22 is connected to the imaging signal V CCD The other end of the third sampling switch S13_22 is connected to the second sampling capacitor C S2_4 One end of the third sampling switch S13_22 is connected to the second third sampling signal K13_2.

[0094] As shown in FIG9 , the fifth signal sampling unit includes a third sampling switch S13_31 and a second sampling capacitor C S2_5 One end of the third sampling switch S13_31 is connected to the imaging signal V CCD The other end of the third sampling switch S13_31 is connected to the second sampling capacitor C S2_5 The control end of the third sampling switch S13_31 is connected to the third sampling signal K13_3; the sixth signal sampling unit includes a third sampling switch S13_32 and a second sampling capacitor C S2_6 One end of the third sampling switch S13_32 is connected to the imaging signal V CCD The other end of the third sampling switch S13_32 is connected to the second sampling capacitor C S2_6 The control terminal of the third sampling switch S13_32 is connected to the third sampling signal K13_3. The second reference unit includes a fourth sampling switch S1_2, one end of which is connected to the second sampling capacitor (C S2_1 、C S2_2 、C S2_3 、C S2_4 、C S2_5 、C S2_6 ), the other end of the fourth sampling switch S1_2 is connected to the first reference voltage V1, and the control end of the fourth sampling switch S1_2 is connected to the fourth sampling signal K4.

[0095] In more detail, as shown in FIG9 , the differential processing unit includes a first differential connection switch S21_1, a second differential connection switch S21_2, a third differential connection switch S21_3, a fourth differential connection switch S21_4, a fifth differential connection switch S21_5, a first amplifying switch S22_1, and a second amplifying switch S22_2. One end of the first differential connection switch S21_1 is connected to the first first sampling capacitor C S1_1 One end of the first sampling capacitor C S1_1 The other end of the first differential connection switch S21_1 is connected to one end of the first amplifying switch S22_1, and the other end of the first differential connection switch S21_1 is connected to the first second sampling capacitor C S2_1 One end of the first and second sampling capacitors C S2_1 The other end of the differential connection switch S21_1 is connected to one end of the second amplifying switch S22_2, the control end of the first differential connection switch S21_1 is connected to the first differential connection signal K21_1; one end of the second differential connection switch S21_2 is connected to the second first sampling capacitor C S1_2 One end of the second first sampling capacitor C S1_2 The other end of the second differential connection switch S21_2 is connected to the second sampling capacitor C S2_2One end of the second sampling capacitor C S2_2 The other end is connected to one end of the second amplifying switch S22_2, and the control end of the second differential connection switch S21_2 is connected to the second differential connection signal K21_2.

[0096] Similarly, one end of the third differential connection switch S21_3 is connected to the third first sampling capacitor C S1_3 One end of the third first sampling capacitor C S1_3 The other end of the third differential connection switch S21_3 is connected to one end of the first amplifying switch S22_1, and the other end of the third differential connection switch S21_3 is connected to the third second sampling capacitor C S2_3 One end of the third second sampling capacitor C S2_3 The other end of the differential connection switch S21_3 is connected to one end of the second amplifying switch S22_2, the control end of the third differential connection switch S21_3 is connected to the third differential connection signal K21_3; one end of the fourth differential connection switch S21_4 is connected to the fourth first sampling capacitor C S1_4 One end of the fourth first sampling capacitor C S1_4 The other end of the fourth differential connection switch S21_4 is connected to one end of the first amplifying switch S22_1, and the other end of the fourth differential connection switch S21_4 is connected to the fourth second sampling capacitor C S2_4 One end of the fourth second sampling capacitor C S2_4 The other end of the differential connection switch S21_4 is connected to one end of the second amplifying switch S22_2, the control end of the fourth differential connection switch S21_4 is connected to the fourth differential connection signal K21_4; one end of the fifth differential connection switch S21_5 is connected to the fifth first sampling capacitor C S1_5 One end of the fifth first sampling capacitor C S1_5 The other end of the fifth differential connection switch S21_5 is connected to one end of the first amplifying switch S22_1, and the other end of the fifth differential connection switch S21_5 is connected to the fifth second sampling capacitor C S2_5 One end of the fifth second sampling capacitor C S2_5 The other end of the differential connection switch S21_5 is connected to one end of the second amplifying switch S22_2. The control end of the fifth differential connection switch S21_5 is connected to the fifth differential connection signal K21_5. The control end of the first amplifying switch S22_1 and the control end of the second amplifying switch S22_2 are connected to the first amplified signal K22. The other end of the first amplifying switch S22_1 is the first output end of the differential processing unit, and the other end of the second amplifying switch S22_2 is the second output end of the differential processing unit.

[0097] As shown in Figures 9-10, the principle of the imaging signal sampling circuit in another embodiment provided by the present application is specifically as follows:

[0098] In the first half of the Nth cycle of the imaging signal, in combination with FIG9 and FIG10, the first sampling module, under the control of the three first sampling signals and the second sampling signal K2, samples the imaging signal VCCD The reset level Vr is sampled:

[0099] The first sampling signal K11_1 and the second sampling signal K2 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is reset by the first reset sampling unit and the second reset sampling unit. CCD Two samples are taken to obtain two reset voltages. At the same time, under the control of the reset signal K15, the amplifier unit is in the reset state. After the sampling is completed, the first amplified signal K22, the second amplified signal K23 and the fourth differential connection signal K21_4 are high. The amplifier unit samples the reset voltage of the N-1th cycle (the fourth first sampling capacitor C S1_4 The storage voltage) and the signal voltage (the fourth second sampling capacitor C S2_4 The stored voltage) is amplified to obtain a sampling signal.

[0100] The second first sampling signal K11_2 and the second sampling signal K2 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is reset by the third reset sampling unit and the fourth reset sampling unit. CCD Two samples are taken to obtain two reset voltages. At the same time, under the control of the reset signal K15, the amplifier unit is in the reset state. After the sampling is completed, the first amplified signal K22, the second amplified signal K23 and the fifth differential connection signal K21_5 are high. The amplifier unit samples the reset voltage of the N-1th cycle (the fifth first sampling capacitor C S1_5 The storage voltage) and the signal voltage (the fifth second sampling capacitor C S2_5 The stored voltage) is amplified to obtain a sampling signal.

[0101] The third first sampling signal K11_3 and the second sampling signal K2 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is reset by the fifth reset sampling unit and the sixth reset sampling unit. CCD Sampling is performed twice to obtain two reset voltages. At the same time, under the control of the reset signal K15, the amplifying unit is in the reset state. After the sampling is completed, as shown in FIG9 , the imaging signal V CCD Entering the second half of the cycle.

[0102] In the second half of the Nth cycle of the imaging signal, the second sampling module, under the control of the three third sampling signals and the fourth sampling signal, samples the imaging signal V CCD The signal level V S1 To take a sample:

[0103] The first second sampling signal K13_1 and the fourth sampling signal K4 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is sampled by the first signal sampling unit and the second signal sampling unit.CCD Two samplings are performed to obtain two signal voltages. At the same time, under the control of the reset signal K15, the amplifying unit is in the reset state. After the sampling is completed, the first amplified signal K22, the second amplified signal K23 and the first differential connection signal K21_1 are high level, and the amplifying unit samples the reset voltage of the Nth cycle (the first first sampling capacitor C S1_1 The storage voltage) and the signal voltage (the first and second sampling capacitors C S2_1 The stored voltage) is amplified to obtain a sampling signal.

[0104] The second sampling signal K13_2 and the fourth sampling signal K4 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is sampled by the third signal sampling unit and the fourth signal sampling unit. CCD Two samplings are performed to obtain two signal voltages. At the same time, under the control of the reset signal K15, the amplifier unit is in the reset state. After the sampling is completed, the first amplified signal K22, the second amplified signal K23 and the second differential connection signal K21_2 are high level, and the amplifier unit samples the reset voltage of the Nth cycle (the second first sampling capacitor C S1_2 The storage voltage) and the signal voltage (the second sampling capacitor C S2_2 The stored voltage) is amplified to obtain a sampling signal.

[0105] The third second sampling signal K13_3 and the fourth sampling signal K4 are high level, and the first voltage V1 is used as a reference, and the imaging signal V is sampled by the fifth signal sampling unit and the sixth signal sampling unit. CCD Two samplings are performed to obtain two signal voltages. At the same time, under the control of the reset signal K15, the amplifier unit is in the reset state. After the sampling is completed, the first amplified signal K22, the second amplified signal K23 and the third differential connection signal K21_3 are high level, and the amplifier unit samples the reset voltage of the Nth cycle (the third first sampling capacitor C S1_3 The storage voltage) and the signal voltage (the third second sampling capacitor C S2_3 The stored voltage) is amplified to obtain a sampling signal.

[0106] In summary, the imaging signal sampling circuit in Example 2 samples the voltage of the upper half cycle and the voltage of the lower half cycle of the imaging signal six times, and performs differential amplification processing on the sampled voltages five times to obtain five sampling signals. This suppresses the noise of the output sampling signal to a certain extent and eliminates the imbalance caused by the traditional imaging signal sampling circuit.

[0107] It should be noted that in the imaging signal sampling circuit provided by the present application, since the difference between the reset voltage and the signal voltage sampled by the 2Nth first sampling capacitor and the 2Nth second sampling capacitor has not been amplified, the first first sampling capacitor C S1_2 and the first and second sampling capacitors C S2_2 The next sampling is to be performed, therefore, only the imaging signal of 2N-1 sampling times is amplified, and the 2Nth first sampling capacitor and the 2Nth second sampling capacitor are placed in the circuit as matching capacitors.

[0108] In addition, based on the same inventive design concept as the above-mentioned imaging signal sampling circuit, the present invention also provides an imaging signal sampling method, comprising:

[0109] In the first half cycle of the imaging signal, the imaging signal is sampled N times, and each sampling is performed through M sampling capacitors to obtain M*N reset voltages;

[0110] In the second half cycle of the imaging signal, the imaging signal is sampled N times, and each sampling is performed through M sampling capacitors to obtain M*N signal voltages;

[0111] In each cycle, a reset operation and a differential amplification process are performed alternately, and 2N samplings are performed sequentially and synchronously with at least part of the reset operation, and M*N reset voltages and M*N signal voltages are differentially amplified M*N-1 times to obtain M*N-1 sampling signals; during the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampling signal;

[0112] Wherein, t, N, and M are integers, N ≥ 2, M ≥ 2, and 1 ≤ t ≤ M*N-1.

[0113] The present application provides an imaging signal sampling circuit and method. The circuit includes: a first sampling module, under the control of N first sampling signals and a second sampling signal, samples the imaging signal N times to obtain 2N reset voltages; a second sampling module, under the control of N third sampling signals and a fourth sampling signal, samples the imaging signal N times to obtain 2N signal voltages; within each cycle of the imaging signal, when sampling the imaging signal, the amplification module is controlled by the reset signal to perform a reset operation; after the sampling is completed, the 2N reset voltages and the 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampling signals. The present application uses two sampling modules to sample the imaging signal multiple times to enhance the sampling circuit's ability to suppress imaging signal noise. The reset voltages and signal voltages obtained from the multiple samplings are sequentially amplified to obtain multiple sampling signals. The offset error of the output signal is reduced by multiple averaging. The sampling circuit both enhances noise suppression and reduces output signal error, thereby improving the precision and accuracy of signal sampling.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An imaging signal sampling circuit, characterized in that: include: a first sampling module, connected to an imaging signal, a first reference voltage, N first sampling signals, and a second sampling signal, and sampling the imaging signal N times based on the first reference voltage under the control of the N first sampling signals and the second sampling signal to obtain 2N reset voltages; a second sampling module, receiving the imaging signal, the first reference voltage, N third sampling signals, and a fourth sampling signal, and sampling the imaging signal N times based on the first reference voltage under the control of the N third sampling signals and the fourth sampling signal to obtain 2N signal voltages; an amplification module connected to the first sampling module, the second sampling module, 2N-1 differential connection signals, a first amplified signal, a second amplified signal, and a reset signal. Within each cycle of the imaging signal, the amplification module alternately performs a reset operation and a differential amplification process. When the reset signal controls the amplification module to perform a reset operation, the amplification module synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling is completed, under the control of the 2N-1 differential connection signals, the first amplified signal, and the second amplified signal, 2N-1 differential amplification processes are successively performed on 2N reset voltages and 2N signal voltages to obtain 2N-1 sampling signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampling signal. Wherein, i and N are integers, N≥2, 1≤i≤2N-1.

2. The imaging signal sampling circuit according to claim 1, wherein: The first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling unit receives the first sampling signal and samples the imaging signal based on the first sampling signal to obtain the reset voltage. The first reference unit receives the reset sampling unit, the first reference voltage, and the second sampling signal and uses the first reference voltage as a reference value of the reset sampling unit based on the second sampling signal.

3. The imaging signal sampling circuit according to claim 2, characterized in that: The reset sampling unit includes a first sampling switch and a first sampling capacitor, one end of the first sampling switch is connected to the imaging signal, the other end of the first sampling switch is connected to one end of the first sampling capacitor, and a control end of the first sampling switch is connected to the first sampling signal. The first reference unit includes a second sampling switch, one end of the second sampling switch is connected to the other end of the first sampling capacitor, the other end of the second sampling switch is connected to the first reference voltage, and the control end of the second sampling switch is connected to the second sampling signal.

4. The imaging signal sampling circuit according to claim 3, characterized in that: The second sampling module includes 2N signal sampling units and a second reference unit. The signal sampling unit is connected to the third sampling signal and samples the imaging signal based on the third sampling signal to obtain the signal voltage. The second reference unit is connected to the signal sampling unit, the first reference voltage and the fourth sampling signal, and uses the first reference voltage as a reference value of the signal sampling unit based on the fourth sampling signal.

5. The imaging signal sampling circuit according to claim 4, characterized in that: The signal sampling unit includes a third sampling switch and a second sampling capacitor, one end of the third sampling switch is connected to the imaging signal, the other end of the third sampling switch is connected to one end of the second sampling capacitor, and a control end of the third sampling switch is connected to the third sampling signal. The second reference unit includes a fourth sampling switch, one end of the fourth sampling switch is connected to the other end of the second sampling capacitor, the other end of the fourth sampling switch is connected to the first reference voltage, and the control end of the fourth sampling switch is connected to the fourth sampling signal.

6. The imaging signal sampling circuit according to claim 5, characterized in that: The amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to 2N-1 differential connection signals and the first amplification signal. Under the control of the 2N-1 differential connection signals and the first amplification signal, 2N reset voltages and 2N signal voltages are connected in a one-to-one correspondence to obtain 2N-1 differential signals. The amplification unit is connected to the differential processing unit, the second amplification signal and the reset signal. When the reset signal controls the amplification unit to perform a reset operation, the first sampling module or the second sampling module is synchronously controlled to sample the imaging signal. After sampling is completed, the 2N-1 differential signals are amplified in sequence under the control of the second amplification signal to obtain 2N-1 sampling signals.

7. The imaging signal sampling circuit according to claim 6, characterized in that: The differential processing unit includes 2N-1 differential connection switches, a first amplifying switch, and a second amplifying switch; one end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplifying switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplifying switch, a control end of the i-th differential connection switch is connected to the i-th differential connection signal, and the control ends of the first amplifying switch and the second amplifying switch are connected to the first amplified signal. The other end of the first amplifying switch is the first output end of the differential processing unit, and the other end of the second amplifying switch is the second output end of the differential processing unit.

8. The imaging signal sampling circuit according to claim 6, wherein: The amplifying unit includes a first reset switch, a second reset switch, a third reset switch, a fourth reset switch, a fifth reset switch, a sixth reset switch, a third amplifying switch, a fourth amplifying switch, a fifth amplifying switch, a sixth amplifying switch, a first feedback capacitor, a second feedback capacitor, and an operational amplifier. One end of the first reset switch is connected to the non-inverting input of the operational amplifier, and the other end of the first reset switch is connected to the inverting input of the operational amplifier. The non-inverting input of the operational amplifier is connected to the inverting output of the operational amplifier via the third amplifying switch, the first feedback capacitor, and the fourth amplifying switch connected in series. The inverting input of the operational amplifier is connected to the non-inverting output of the operational amplifier via the fifth amplifying switch, the second feedback capacitor, and the sixth amplifying switch connected in series. The inverting output of the operational amplifier is connected to the non-inverting output of the operational amplifier via the second reset switch connected in series. The second reference voltage is connected to one end of the first feedback capacitor via the third reset switch connected in series. The third reference voltage is connected to the other end of the first feedback capacitor via the fourth reset switch connected in series, the second reference voltage is connected to one end of the second feedback capacitor via the fifth reset switch connected in series, and the fourth reference voltage is connected to the other end of the second feedback capacitor via the sixth reset switch connected in series. The control end of the first reset switch, the control end of the second reset switch, the control end of the third reset switch, the control end of the fourth reset switch, the control end of the fifth reset switch, and the control end of the sixth reset switch are connected to the reset signal, the control end of the third amplifying switch, the control end of the fourth amplifying switch, the control end of the fifth amplifying switch, and the control end of the sixth amplifying switch are connected to the second amplified signal, the non-inverting input end of the operational amplifier is connected to the first output end of the differential processing unit, the inverting input end of the operational amplifier is connected to the second output end of the differential processing unit, and the non-inverting output end of the operational amplifier and the inverting output end of the operational amplifier cooperate to output the sampling signal.

9. An imaging signal sampling method, characterized in that: The imaging signal sampling circuit according to any one of claims 1 to 8 comprises: In the first half cycle of the imaging signal, the imaging signal is sampled N times, each sampling is performed through M sampling capacitors to obtain M*N reset voltages; In the second half cycle of the imaging signal, the imaging signal is sampled N times, and each sampling is performed through M sampling capacitors to obtain M*N signal voltages; In each cycle, a reset operation and a differential amplification process are performed alternately, and 2N samplings are performed sequentially and synchronously with at least part of the reset operation. M*N reset voltages and M*N signal voltages are differentially amplified M*N-1 times to obtain M*N-1 sampling signals. During the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampling signal. Wherein, t, N, and M are integers, N ≥ 2, M ≥ 2, and 1 ≤ t ≤ M*N-1.

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