High-speed germanium-silicon HBT structure having low base region connection resistance and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductor devices, and provides a high-speed germanium-silicon HBT structure having low base region connection resistance and a manufacturing method therefor. The structure comprises: a substrate; isolation regions formed by etching and backfilling the substrate; a first dielectric layer arranged on the side of the substrate close to the isolation regions; a second dielectric layer arranged on the side of the first dielectric layer facing away from the substrate; an outer base region arranged on the side of the second dielectric layer facing away from the first dielectric layer; first side walls formed by etching the outer base region and depositing a dielectric material; and an inner base region formed by etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon and germanium, the inner base region being in contact with the outer base region. In the present invention, the first dielectric layer and the second dielectric layer are etched and silicon and germanium are epitaxially grown to form the inner base region, so that the problems that the connection region of the inner base region and the outer base region is narrow, and the resistance and capacitance optimization have a large bottleneck are overcome; the outer base region and the inner base region are connected to form a self-aligned structure, base region connection resistance is reduced, and the highest oscillation frequency of a device is improved.

Description

A high-speed silicon-germanium HBT structure with low base connection resistance and its manufacturing method Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a high-speed SiGe HBT structure with low base region connection resistance and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor device technology, the introduction of germanium (Ge) into silicon (Si) significantly alters the material's properties. First and foremost, because Ge has a larger lattice constant than Si, SiGe's bandgap is smaller than Si's, making SiGe the most important means of regulating silicon's energy bandgap in semiconductor processes. Furthermore, because SiGe HBTs (heterojunction bipolar transistors) offer high-frequency characteristics comparable to compound heterojunction transistors such as InP HBTs and GaAs HBTs, and more crucially, because SiGe HBTs are perfectly compatible with silicon CMOS processes for large-scale monolithic integration, SiGe BiCMOS processes based on SiGe HBTs are among the best candidates for modern microwave, RF, millimeter-wave, and even terahertz integrated circuit applications.

[0003] SiGe HBT uses silicon germanium material as the base region to form a silicon / silicon germanium heterojunction, which can achieve a higher injection efficiency; the heterojunction base region can be heavily doped to form a built-in accelerating electric field through a concentration gradient, and band engineering is used to adjust the base region carrier mobility. The prepared SiGe HBT device has the advantages of high characteristic frequency, good matching, strong driving capability and high linearity. However, in the current traditional double polysilicon self-aligned (DPSA) structure SiGe HBT, on the one hand, it is necessary to minimize the contact area between the external base region polysilicon and the selective SiGe internal base region to reduce the collector region / base region junction capacitance, thereby increasing the device's maximum oscillation frequency f max On the other hand, it is necessary to achieve good contact between the external base polycrystalline and the selective SiGe epitaxial layer to reduce the base resistance R B , thereby increasing the device characteristic frequency f T In the actual process, the collector / base junction capacitance and base resistance R are optimized at the same time. B There are contradictions, and it is difficult to achieve a good compromise within an acceptable range.

[0004] Therefore, how to reduce the base resistance without increasing the collector / base junction capacitance is a problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a high-speed SiGe HBT structure with low base connection resistance and a manufacturing method thereof, so as to solve the problem in the prior art of how to reduce the base resistance without increasing the collector / base junction capacitance.

[0007] To achieve the above-mentioned and other related objectives, the present application provides a high-speed SiGe HBT structure with low base region connection resistance, the high-speed SiGe HBT structure comprising:

[0008] substrate;

[0009] an isolation region formed by etching and backfilling the substrate;

[0010] A first dielectric layer is provided on a side of the substrate close to the isolation region;

[0011] a second dielectric layer, disposed on a side of the first dielectric layer facing away from the substrate;

[0012] an external base region, disposed on a side of the second dielectric layer away from the first dielectric layer;

[0013] A first sidewall spacer is formed by etching the external base region and depositing a dielectric material;

[0014] An intrinsic base region is formed by etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon germanium, and the intrinsic base region is in contact with the extrinsic base region.

[0015] In one embodiment of the present application, the high-speed SiGe HBT structure further includes:

[0016] a third dielectric layer, disposed on a side of the extrinsic base region away from the second dielectric layer;

[0017] a fourth dielectric layer, disposed on a side of the third dielectric layer away from the extrinsic base region;

[0018] a second side wall, disposed on one side of the first side wall;

[0019] An emitter region is arranged in the middle of the second sidewall and on the fourth dielectric layer, and the emitter region is in contact with the intrinsic base region.

[0020] In one embodiment of the present application, the isolation region includes a shallow trench isolation region and a deep trench isolation region;

[0021] Implanting N+ type impurities on the substrate to form a buried layer, epitaxially growing silicon on the buried layer, etching the epitaxial silicon and backfilling with polysilicon or silicon oxide to obtain the isolation region;

[0022] The first dielectric layer has a higher density than the second dielectric layer.

[0023] In one embodiment of the present application, the concentration of the N+ type impurities is 3e15-1e16 cm -3 ;

[0024] The thickness of the epitaxial silicon is 1000-5000 angstroms;

[0025] The thickness of the first dielectric layer is 200-500 angstroms, the thickness of the second dielectric layer is 150-300 angstroms, the thickness of the second dielectric layer is less than that of the first dielectric layer, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is 400-700 angstroms.

[0026] The material of the external base region is polysilicon, and the thickness of the external base region is 1000-2000 angstroms;

[0027] The thickness of the third dielectric layer is 200-600 angstroms;

[0028] The thickness of the fourth dielectric layer is 300-600 angstroms.

[0029] In one embodiment of the present application, the external base region, the third dielectric layer, and the fourth dielectric layer are etched and dielectric material is deposited to form two first side walls. The area between the two first side walls is an emission region window, and the width of the emission region window is 0.09-0.25um.

[0030] In one embodiment of the present application, the first dielectric layer and the second dielectric layer are etched to form a bowl-shaped groove, wherein the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm, and the width of the bowl-shaped groove in the second dielectric layer is 0.1-0.3 μm, and the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm greater than the width in the second dielectric layer;

[0031] Germanium silicon is epitaxially grown in the bowl-shaped groove to form the intrinsic base region, and the thickness of the intrinsic base region is equal to the sum of the thicknesses of the first dielectric layer and the second dielectric layer.

[0032] In one embodiment of the present application, a silicon oxide layer and a silicon nitride layer are sequentially deposited on the intrinsic base region, the silicon nitride layer is dry-etched, and the silicon oxide layer is wet-etched to form the second sidewall spacer; wherein,

[0033] The thickness of the silicon oxide layer is 100-600 angstroms, the thickness of the silicon nitride layer is 300-1000 angstroms, and the thickness of the silicon nitride layer is 400-1500 angstroms after dry etching.

[0034] In one embodiment of the present application, in the middle of the second sidewall and on the fourth dielectric layer, in-situ doped silicon is epitaxially or deposited to form an N+ type emitter region, and the dopant of the in-situ doped silicon is As or P, and the concentration of the dopant is 5e19-2e20cm -3 .

[0035] In one embodiment of the present application, the high-speed SiGe HBT structure further includes:

[0036] A protective layer is provided on the emitting region, wherein the thickness of the protective layer is 100-1000 angstroms;

[0037] An emitter region etching area is formed by etching the protective layer, and the line width of the emitter region etching area is 0.25-0.5 μm;

[0038] The emitting area side walls are provided on both sides of the protective layer and the emitting area;

[0039] The external base region sidewall is arranged on a side of the external base region, the third dielectric layer, and the fourth dielectric layer away from the first sidewall.

[0040] In one embodiment of the present application, a method for manufacturing a high-speed SiGe HBT structure with low base connection resistance as described above is further provided, the method comprising:

[0041] obtaining a substrate;

[0042] Etching and backfilling the substrate to form an isolation region;

[0043] Disposing a first dielectric layer on a side of the substrate close to the isolation region;

[0044] Disposing a second dielectric layer on a side of the first dielectric layer facing away from the substrate;

[0045] Disposing an external base region on a side of the second dielectric layer away from the first dielectric layer;

[0046] Etching the external base region and depositing a dielectric material to form a first sidewall spacer;

[0047] The first dielectric layer and the second dielectric layer are etched, and silicon germanium is epitaxially grown to form an intrinsic base region, wherein the intrinsic base region is in contact with the extrinsic base region.

[0048] Beneficial effects of the present invention:

[0049] The present invention provides a high-speed silicon-germanium HBT structure with low base region connection resistance, comprising: a substrate; an isolation region formed by etching and backfilling the substrate; a first dielectric layer disposed on a side of the substrate close to the isolation region; a second dielectric layer disposed on a side of the first dielectric layer facing away from the substrate; an extrinsic base region disposed on a side of the second dielectric layer facing away from the first dielectric layer; a first sidewall formed by etching the extrinsic base region and depositing a dielectric material; and an intrinsic base region formed by etching the first and second dielectric layers and epitaxially growing silicon germanium, the intrinsic base region being in contact with the extrinsic base region. In the present invention, the first dielectric layer and the second dielectric layer are etched and silicon germanium is epitaxially grown to form an intrinsic base region, thereby overcoming the problem of a narrow connection area between the inner and outer base regions and a major bottleneck in the optimization of resistance and capacitance in the traditional structure; the external base region and the internal base region are connected to form a self-aligned structure, which solves the problem of large connection resistance between the inner and outer base regions and difficulty in simultaneously optimizing the collector / base junction capacitance and the base resistance in the traditional structure, significantly reducing the base connection resistance of the traditional selective epitaxial structure silicon germanium HBT, thereby improving the maximum oscillation frequency of the device.

[0050] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, serving to explain the principles of the present application. It is obvious that the drawings described below are merely some embodiments of the present application, and a person of ordinary skill in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0052] FIG1 is a schematic structural diagram of a high-speed SiGe HBT structure with low base region connection resistance shown in an exemplary embodiment of the present application;

[0053] FIG2 is a schematic flow chart of a method for manufacturing a high-speed SiGe HBT structure with low base region connection resistance according to an exemplary embodiment of the present application;

[0054] FIG3 is a schematic diagram showing the effect of forming an isolation region according to an exemplary embodiment of the present application;

[0055] FIG4 is a schematic diagram showing the formation effect of the first dielectric layer and the second dielectric layer according to an exemplary embodiment of the present application;

[0056] FIG5 is a schematic diagram showing the formation effect of an external base region, a third dielectric layer, and a fourth dielectric layer according to an exemplary embodiment of the present application;

[0057] FIG6 is a schematic diagram showing the effect of forming a first sidewall spacer according to an exemplary embodiment of the present application;

[0058] FIG7 is a schematic diagram showing the effect of forming a bowl-shaped groove according to an exemplary embodiment of the present application;

[0059] FIG8 is a schematic diagram showing the formation effect of an intrinsic base region according to an exemplary embodiment of the present application;

[0060] FIG9 is a schematic diagram showing the effect of forming a second sidewall according to an exemplary embodiment of the present application;

[0061] FIG10 is a schematic diagram showing the formation effect of the emission region according to an exemplary embodiment of the present application.

[0062] Description of Figure Numbers:

[0063] 101-substrate, 102-isolation region, 201-first dielectric layer, 202-second dielectric layer, 301-extrinsic base region, 302-third dielectric layer, 303-fourth dielectric layer, 401-first sidewall, 501-intrinsic base region, 601-second sidewall, 701-emitter region, 702-protective layer, 801-emitter region sidewall, 901-extrinsic base region sidewall. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0065] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0066] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0067] In one embodiment of the present application, in order to solve the existing problem of how to reduce the base resistance without increasing the collector / base junction capacitance, a high-speed SiGe HBT structure with low base connection resistance is proposed. The high-speed SiGe HBT structure includes:

[0068] substrate;

[0069] an isolation region formed by etching and backfilling the substrate;

[0070] A first dielectric layer is provided on a side of the substrate close to the isolation region;

[0071] a second dielectric layer, disposed on a side of the first dielectric layer facing away from the substrate;

[0072] an external base region, disposed on a side of the second dielectric layer away from the first dielectric layer;

[0073] A first sidewall spacer is formed by etching the external base region and depositing a dielectric material;

[0074] An intrinsic base region is formed by etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon germanium, and the intrinsic base region is in contact with the extrinsic base region.

[0075] For example, refer to FIG1 , which is a schematic diagram of a high-speed SiGe HBT structure with low base connection resistance shown in an exemplary embodiment of the present application. As shown in FIG1 , the substrate 101 is at the bottom; the substrate 101 is etched and backfilled to form two isolation regions 102 on the left and right; the first dielectric layer 201 is arranged on the side of the substrate 101 close to the isolation region 102, and the bottom end of the first dielectric layer 201 is in contact with the top end of the isolation region 102; the second dielectric layer 202 is arranged on the side of the first dielectric layer 201 away from the substrate 101, and the bottom end of the second dielectric layer 202 is in contact with the top end of the first dielectric layer 201; the external base region 301 is arranged at On the side of the second dielectric layer 202 facing away from the first dielectric layer 201, the bottom end of the external base region 301 contacts the top end of the second dielectric layer 202; the left and right first sidewalls 401 are formed by etching the external base region 301 and depositing dielectric material; the intrinsic base region 501 is formed by etching the first dielectric layer 201 and the second dielectric layer 202 and epitaxially growing silicon germanium, the top end of the intrinsic base region 501 contacts the bottom end of the external base region 301, and the top end of the intrinsic base region 501 also contacts the bottom ends of the two first sidewalls 401.

[0076] Exemplarily, substrate 101 is a silicon-based substrate. Grooves are etched in the silicon-based substrate, and then the grooves are filled with silicon oxide to form left and right isolation regions 102. It should be noted that in this embodiment, the materials of the substrate and isolation regions are merely illustrative and are not limiting. In actual manufacturing processes, substrates of other materials may be used, and other dielectric materials may be filled to form isolation regions 102.

[0077] For example, the materials of the first dielectric layer 201 and the second dielectric layer 202 can be silicon oxide. Silicon oxide is deposited on the substrate 101 to form the first dielectric layer 201; silicon oxide is deposited on the first dielectric layer 201 to form the second dielectric layer 202. The first dielectric layer 201 has a higher density than the second dielectric layer 202. It should be noted that in actual manufacturing processes, other processes such as epitaxy can also be used to add other dielectric materials to the substrate 101 to form the first dielectric layer 201 and the second dielectric layer 202. This application does not limit this.

[0078] Exemplarily, the material of the extrinsic base region 301 is polysilicon, and polysilicon is deposited on the second dielectric layer 202 to form the extrinsic base region 301. It should be noted that in the actual manufacturing process, other processes such as epitaxy can also be selected to form the extrinsic base region 301 on the second dielectric layer 202, and this application does not limit this.

[0079] Exemplarily, a third dielectric layer 302 and a fourth dielectric layer 303 are sequentially prepared on the external base region 301, and the external base region 301, the third dielectric layer 302, and the fourth dielectric layer 303 are etched to form an emitter region window. Then, a dielectric material is deposited in the emitter region window, and the dielectric material is dry-etched to form a first side wall 401. The material of the first side wall 401 may be, for example, silicon nitride.

[0080] Exemplarily, the first dielectric layer 201 and the second dielectric layer 202 are etched to form a bowl-shaped groove, the bottom of which is connected to the substrate 101, and silicon germanium is added to the bowl-shaped groove through an epitaxial process or a deposition process to form an intrinsic base region 501.

[0081] In one embodiment of the present application, the high-speed SiGe HBT structure further includes:

[0082] a third dielectric layer, disposed on a side of the extrinsic base region away from the second dielectric layer;

[0083] a fourth dielectric layer, disposed on a side of the third dielectric layer away from the extrinsic base region;

[0084] a second side wall, disposed on one side of the first side wall;

[0085] An emitter region is arranged in the middle of the second sidewall and on the fourth dielectric layer, and the emitter region is in contact with the intrinsic base region.

[0086] For example, as shown in FIG1 , a third dielectric layer 302 is disposed on the side of the extrinsic base region 301 facing away from the second dielectric layer 202; a fourth dielectric layer 303 is disposed on the side of the third dielectric layer 302 facing away from the extrinsic base region 301. The third dielectric layer 302 can be formed by depositing or epitaxially growing silicon oxide; the fourth dielectric layer 303 can be formed by depositing or epitaxially growing silicon nitride. The third and fourth dielectric layers 302 and 303 serve a protective function. After forming the third and fourth dielectric layers 302 and 303, the extrinsic base region 301, the third and fourth dielectric layers 302 and 303 are photolithographically etched to form an emitter window. Silicon nitride is deposited in the emitter window, and the silicon nitride is dry-etched to form the first sidewall spacer 401. Silicon oxide and silicon nitride are deposited in the new emitter window surrounded by the first spacer 401. The silicon nitride is dry-etched, stopping at the silicon oxide. The silicon oxide is then wet-etched to form the second spacer 601. In the new emitter window surrounded by the second spacer 601, an N+ in-situ doped emitter region 701 is formed by epitaxial growth or deposition above the fourth dielectric layer 303.

[0087] In one embodiment of the present application, the isolation region includes a shallow trench isolation region and a deep trench isolation region;

[0088] Implanting N+ type impurities on the substrate to form a buried layer, epitaxially growing silicon on the buried layer, etching the epitaxial silicon and backfilling with polysilicon or silicon oxide to obtain the isolation region;

[0089] The first dielectric layer has a higher density than the second dielectric layer.

[0090] Exemplarily, a high dose of N+ type impurities is implanted into a silicon substrate to form a buried layer, and N-type doped silicon is epitaxially grown on the buried layer; the N-type doped silicon is photolithographically etched and then backfilled with polysilicon or silicon oxide to form shallow trench isolation regions and deep trench isolation regions.

[0091] In one embodiment of the present application, the concentration of the N+ type impurities is 3e15-1e16cm -3 ;

[0092] The thickness of the epitaxial silicon is 1000-5000 angstroms;

[0093] The thickness of the first dielectric layer is 200-500 angstroms, the thickness of the second dielectric layer is 150-300 angstroms, the thickness of the second dielectric layer is less than that of the first dielectric layer, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is 400-700 angstroms.

[0094] The material of the external base region is polysilicon, and the thickness of the external base region is 1000-2000 angstroms;

[0095] The thickness of the third dielectric layer is 200-600 angstroms;

[0096] The thickness of the fourth dielectric layer is 300-600 angstroms.

[0097] In one embodiment of the present application, the external base region, the third dielectric layer, and the fourth dielectric layer are etched and dielectric material is deposited to form two first side walls. The area between the two first side walls is an emission region window, and the width of the emission region window is 0.09-0.25um.

[0098] Exemplarily, after the third dielectric layer 302 and the fourth dielectric layer 303 are generated, the external base region 301, the third dielectric layer 302 and the fourth dielectric layer 303 are photolithographically etched to form an emitter window, silicon nitride is deposited in the emitter window, and the silicon nitride is dry-etched to form a first sidewall 401.

[0099] In one embodiment of the present application, the first dielectric layer and the second dielectric layer are etched to form a bowl-shaped groove, wherein the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm, and the width of the bowl-shaped groove in the second dielectric layer is 0.1-0.3 μm, and the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm greater than the width in the second dielectric layer;

[0100] Germanium silicon is epitaxially grown in the bowl-shaped groove to form the intrinsic base region, and the thickness of the intrinsic base region is equal to the sum of the thicknesses of the first dielectric layer and the second dielectric layer.

[0101] Illustratively, dry etching is combined with wet etching of the first dielectric layer 201 and the second dielectric layer 202 to form a bowl-shaped groove, the bottom of which is connected to the substrate 101, and silicon germanium is added to the bowl-shaped groove through an epitaxial process or a deposition process to form an intrinsic base region 501.

[0102] In one embodiment of the present application, a silicon oxide layer and a silicon nitride layer are sequentially deposited on the intrinsic base region, the silicon nitride layer is dry-etched, and the silicon oxide layer is wet-etched to form the second sidewall spacer; wherein,

[0103] The thickness of the silicon oxide layer is 100-600 angstroms, the thickness of the silicon nitride layer is 300-1000 angstroms, and the thickness of the silicon nitride layer is 400-1500 angstroms after dry etching.

[0104] In one embodiment of the present application, in the middle position of the second sidewall and on the fourth dielectric layer, epitaxial or deposited in-situ doped silicon forms an N+ type emitter region, and the dopant of the in-situ doped silicon is As or P, and the concentration of the dopant is 5e19-2e20cm -3 .

[0105] In one embodiment of the present application, the high-speed SiGe HBT structure further includes:

[0106] A protective layer is provided on the emitting region, wherein the thickness of the protective layer is 100-1000 angstroms;

[0107] An emitter region etching area is formed by etching the protective layer, and the line width of the emitter region etching area is 0.25-0.5 μm;

[0108] The emitting area side walls are provided on both sides of the protective layer and the emitting area;

[0109] The external base region sidewall is arranged on a side of the external base region, the third dielectric layer, and the fourth dielectric layer away from the first sidewall.

[0110] For example, referring to FIG1 , an N+ emitter region 701 is formed by epitaxial growth or deposition of in-situ doped silicon; silicon oxide is deposited on the emitter region 701 to form a protective layer 702; the emitter region is photolithographically etched to form an emitter region etching area; and through other conventional processes of SiGe HBT, emitter region sidewalls 801 are formed on both sides of the protective layer and the emitter region, and external base region sidewalls 901 are formed on both sides of the external base region, the third dielectric layer, and the fourth dielectric layer.

[0111] In the high-speed SiGe HBT structure with low base connection resistance of the above-mentioned embodiment, the first dielectric layer and the second dielectric layer are etched and SiGe is epitaxially grown to form an intrinsic base region, thereby overcoming the problem of a narrow connection area between the inner and outer base regions and a major bottleneck in resistance and capacitance optimization in the traditional structure; the outer base region and the inner base region are connected to form a self-aligned structure, which solves the problem of large inner and outer base connection resistance and difficulty in simultaneously optimizing the collector / base junction capacitance and base resistance in the traditional structure, significantly reducing the base connection resistance of the traditional selective epitaxial SiGe HBT, thereby improving the maximum oscillation frequency of the device.

[0112] In one embodiment of the present application, a method for manufacturing a high-speed SiGe HBT structure with low base connection resistance is proposed. Referring to FIG. 2 , FIG. 2 is a flow chart illustrating a method for manufacturing a high-speed SiGe HBT structure with low base connection resistance according to an exemplary embodiment of the present application. The method shown in FIG. 2 includes seven steps, S210-S270, as follows:

[0113] S210: Obtain a substrate.

[0114] S220 , etching and backfilling the substrate to form an isolation region.

[0115] For example, see FIG3 , which is a schematic diagram illustrating the formation of an isolation region according to an exemplary embodiment of the present application. In step S220 , a high dose of N+-type impurities is implanted into substrate 101 to form a buried layer, followed by epitaxial silicon growth. The silicon is then photolithographically etched and backfilled with polysilicon or silicon oxide to form isolation region 102 as shown in FIG3 . In this embodiment, isolation region 102 is a deep trench isolation region.

[0116] S230 , disposing a first dielectric layer on a side of the substrate close to the isolation region.

[0117] S240 , disposing a second dielectric layer on a side of the first dielectric layer facing away from the substrate.

[0118] For example, see Figure 4, which is a schematic diagram illustrating the formation of the first and second dielectric layers according to an exemplary embodiment of the present application. In steps S230 and S240, two silicon oxides with significantly different densities are deposited to form the first and second dielectric layers 201 and 202, as shown in Figure 4.

[0119] S250 , disposing an external base region on a side of the second dielectric layer away from the first dielectric layer.

[0120] For example, see Figure 5, which is a schematic diagram illustrating the formation of an extrinsic base region, a third dielectric layer, and a fourth dielectric layer according to an exemplary embodiment of the present application. As shown in Figure 5, polysilicon is deposited on the second dielectric layer 202 to form an extrinsic base region 301. A third dielectric layer 302 and a fourth dielectric layer 303 are then sequentially formed on the extrinsic base region 301.

[0121] S260, etching the outer base region and depositing a dielectric material to form a first sidewall spacer.

[0122] For example, see Figure 6, which is a schematic diagram illustrating the formation of a first sidewall spacer according to an exemplary embodiment of the present application. As shown in Figure 6, the extrinsic base region 301, the third dielectric layer 302, and the fourth dielectric layer 303 are etched to form an emitter window. A dielectric material is then deposited within the emitter window and dry-etched to form a first sidewall spacer 401.

[0123] S270 , etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon germanium to form an intrinsic base region, wherein the intrinsic base region is in contact with the extrinsic base region.

[0124] For example, see FIG7 , which is a schematic diagram illustrating the formation effect of a bowl-shaped groove according to an exemplary embodiment of the present application. As shown in FIG7 , dry etching is combined with wet etching of the first dielectric layer 201 and the second dielectric layer 202 to form a bowl-shaped groove, the bottom of which is in contact with the substrate 101.

[0125] For example, see Figure 8, which is a schematic diagram illustrating the formation effect of an intrinsic base region according to an exemplary embodiment of the present application. As shown in Figure 8, silicon germanium is added to the bowl-shaped groove through an epitaxial process or a deposition process to form an intrinsic base region 501.

[0126] For example, see Figure 9, which is a schematic diagram illustrating the formation of a second sidewall spacer according to an exemplary embodiment of the present application. As shown in Figure 9, silicon oxide and silicon nitride are deposited within the new emitter window surrounded by the first sidewall spacer 401. The silicon nitride is dry-etched, stopping at the silicon oxide. The silicon oxide is then wet-etched to form the second sidewall spacer 601.

[0127] For example, see Figure 10, which is a schematic diagram illustrating the formation of an emitter region according to an exemplary embodiment of the present application. As shown in Figure 10, an N+ in-situ doped emitter region 701 is formed by epitaxial growth or deposition within the new emitter region window surrounded by the second sidewall 601 and above the fourth dielectric layer 303; silicon oxide is deposited on the emitter region 701 to form a protective layer 702.

[0128] In one embodiment of the present application, referring to FIG1 , through conventional processes of other SiGe HBTs, emitter sidewalls 801 are formed on both sides of the protective layer 702 and the emitter region 701, and external base sidewalls 901 are formed on both sides of the external base region, the third dielectric layer, and the fourth dielectric layer.

[0129] It should be noted that, through the manufacturing method of the high-speed SiGe HBT structure with low base connection resistance in the embodiment of the present application, the first dielectric layer and the second dielectric layer are etched and SiGe is epitaxially grown to form an internal base region, thereby breaking through the problem that the connection area between the internal and external base regions is narrow and there is a major bottleneck in the optimization of resistance and capacitance in the traditional structure; the external base region and the internal base region are connected to form a self-aligned structure, which solves the problem that the connection resistance between the internal and external base regions is large and the collector / base junction capacitance and the base resistance are difficult to optimize at the same time in the traditional structure, significantly reducing the base connection resistance of the traditional selective epitaxial structure SiGe HBT, thereby improving the maximum oscillation frequency of the device.

[0130] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A high-speed SiGe HBT structure with low base connection resistance, characterized in that: The high-speed SiGe HBT structure includes: substrate; an isolation region formed by etching and backfilling the substrate; A first dielectric layer is provided on a side of the substrate close to the isolation region; a second dielectric layer, disposed on a side of the first dielectric layer facing away from the substrate; an external base region, disposed on a side of the second dielectric layer away from the first dielectric layer; A first sidewall spacer is formed by etching the external base region and depositing a dielectric material; An intrinsic base region is formed by etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon germanium, and the intrinsic base region is in contact with the extrinsic base region.

2. The high-speed SiGe HBT structure with low base connection resistance according to claim 1, characterized in that: The high-speed SiGe HBT structure further includes: a third dielectric layer, disposed on a side of the extrinsic base region away from the second dielectric layer; a fourth dielectric layer, disposed on a side of the third dielectric layer away from the extrinsic base region; a second side wall, disposed on one side of the first side wall; An emitter region is arranged in the middle of the second sidewall and on the fourth dielectric layer, and the emitter region is in contact with the intrinsic base region.

3. The high-speed SiGe HBT structure with low base connection resistance according to claim 1, characterized in that: The isolation region includes a shallow trench isolation region and a deep trench isolation region; Implanting N+ type impurities on the substrate to form a buried layer, epitaxially growing silicon on the buried layer, etching the epitaxial silicon and backfilling with polysilicon or silicon oxide to obtain the isolation region; The first dielectric layer has a higher density than the second dielectric layer.

4. The high-speed SiGe HBT structure with low base connection resistance according to claim 3, characterized in that: The concentration of the N+ type impurity is 3e15-1e16cm -3 ; The thickness of the epitaxial silicon is 1000-5000 angstroms; The thickness of the first dielectric layer is 200-500 angstroms, the thickness of the second dielectric layer is 150-300 angstroms, the thickness of the second dielectric layer is less than that of the first dielectric layer, and the sum of the thicknesses of the first dielectric layer and the second dielectric layer is 400-700 angstroms. The material of the external base region is polysilicon, and the thickness of the external base region is 1000-2000 angstroms; The thickness of the third dielectric layer is 200-600 angstroms; The thickness of the fourth dielectric layer is 300-600 angstroms.

5. The high-speed SiGe HBT structure with low base connection resistance according to claim 3, characterized in that: The external base region, the third dielectric layer, and the fourth dielectric layer are etched and dielectric material is deposited to form two first sidewalls. The area between the two first sidewalls is an emitter window. The width of the emitter window is 0.09-0.25um.

6. The high-speed SiGe HBT structure with low base connection resistance according to claim 1, characterized in that: Etching the first dielectric layer and the second dielectric layer to form a bowl-shaped groove, wherein the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm, the width of the bowl-shaped groove in the second dielectric layer is 0.1-0.3 μm, and the width of the bowl-shaped groove in the first dielectric layer is 0.05-0.2 μm greater than the width in the second dielectric layer; Germanium silicon is epitaxially grown in the bowl-shaped groove to form the intrinsic base region, and the thickness of the intrinsic base region is equal to the sum of the thicknesses of the first dielectric layer and the second dielectric layer.

7. The high-speed SiGe HBT structure with low base connection resistance according to claim 2, characterized in that: A silicon oxide layer and a silicon nitride layer are sequentially deposited on the intrinsic base region, the silicon nitride layer is dry-etched, and the silicon oxide layer is wet-etched to form the second sidewall spacer; wherein, The thickness of the silicon oxide layer is 100-600 angstroms, the thickness of the silicon nitride layer is 300-1000 angstroms, and the thickness of the silicon nitride layer is 400-1500 angstroms after dry etching.

8. The high-speed SiGe HBT structure with low base connection resistance according to claim 2, characterized in that: In the middle of the second sidewall and on the fourth dielectric layer, epitaxially or deposited in-situ doped silicon forms an N+ type emitter region, wherein the dopant of the in-situ doped silicon is As or P, and the concentration of the dopant is 5e19-2e20cm -3 .

9. The high-speed SiGe HBT structure with low base connection resistance according to claim 2, characterized in that: The high-speed SiGe HBT structure further includes: A protective layer is provided on the emitting region, wherein the thickness of the protective layer is 100-1000 angstroms; An emitter region etching area is formed by etching the protective layer, and the line width of the emitter region etching area is 0.25-0.5 μm; The emitting area side walls are provided on both sides of the protective layer and the emitting area; The external base region sidewall is arranged on a side of the external base region, the third dielectric layer, and the fourth dielectric layer away from the first sidewall.

10. A method for manufacturing a high-speed SiGe HBT structure with low base connection resistance according to any one of claims 1 to 9, characterized in that: The manufacturing method comprises: obtaining a substrate; Etching and backfilling the substrate to form an isolation region; Disposing a first dielectric layer on a side of the substrate close to the isolation region; Disposing a second dielectric layer on a side of the first dielectric layer facing away from the substrate; Disposing an external base region on a side of the second dielectric layer away from the first dielectric layer; Etching the external base region and depositing a dielectric material to form a first sidewall spacer; The first dielectric layer and the second dielectric layer are etched, and silicon germanium is epitaxially grown to form an intrinsic base region, wherein the intrinsic base region is in contact with the extrinsic base region.

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