Parameterization instruction selection method and related apparatus

Abstract

A parameterization instruction selection method, applied to optimizing a compilation process executed by a compiler. In the parameterization instruction selection method, during compiling, corresponding machine instruction sets are pre-generated for instructions in a code to be compiled, and one or more corresponding machine instructions that can be selected by each instruction in the code during compiling are indicated on the basis of the machine instruction sets, so that a compiler does not select a default machine instruction for the instruction in the code any more, and the compiler is guided to select different machine instruction combinations during compiling, so as to obtain a plurality of different target files; finally, a target file having optimal execution performance is selected by executing the plurality of target files. Thus, the flexibility of an instruction selection process is improved, and the target file having higher execution performance is obtained by means of compiling.

Description

A parameterized instruction selection method and related apparatus

[0001] This application claims priority to Chinese Patent Application No. 202410234625.8, filed on February 29, 2024, entitled "A Parameterized Instruction Selection Method and Related Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a parameterized instruction selection method and related apparatus. Background Technology

[0003] Compilation is the process of translating source code written in a high-level language into object files written in machine language. Simply put, compilation is turning a high-level language into a binary language that a computer can understand.

[0004] Generally, the compilation process is performed by a compiler. The compiler first compiles the source code into intermediate code, and then converts the instructions in the intermediate code into machine instructions to obtain the object file. In most cases, an instruction indicated in the intermediate code can often be implemented using different machine instructions. Therefore, the conversion of instructions in the intermediate code into machine instructions often involves an instruction selection process.

[0005] However, current compilers usually have fixed instruction selection methods. That is, for a certain type of instruction in the intermediate code, they will often select the default machine instruction for that type of instruction. This makes the instruction selection process relatively fixed, which can easily lead to poor execution performance of the final compiled object file.

[0006] Summary of the Invention

[0007] This application provides a parameterized instruction selection method that can guide the compiler to select better machine instructions during the compilation process, thereby compiling an object file with higher execution performance.

[0008] The first aspect of this application provides a parameterized instruction selection method applied to the compilation process of code by a compiler. In this method, firstly, first code is obtained. This first code is the code that the compiler needs to compile, for example, intermediate code obtained after the compiler performs a preliminary compilation of the source code. Furthermore, the first code includes multiple instructions, and the compiler needs to further compile the first code to obtain an object file.

[0009] Then, an instruction table is generated based on the multiple instructions in the first code. The instruction table includes multiple sets of machine instructions corresponding to the multiple instructions. During compilation, the multiple instructions select machine instructions for compilation from their corresponding machine instruction sets. That is, each of the multiple machine instruction sets has a corresponding instruction in the multiple instructions, meaning that the multiple machine instruction sets correspond one-to-one with the multiple instructions in the first code. Each machine instruction set is used to indicate one or more machine instructions that can be selected during compilation for its corresponding instruction in the first code. In other words, for the multiple instructions in the first code, a machine instruction set can be generated for some instructions or for each of all instructions in the first code, and the machine instruction set indicates the machine instructions that can be selected during compilation for that instruction. The machine instruction set can include one or more machine instructions. If the machine instruction set includes only one machine instruction, it means that the instruction corresponding to that machine instruction set can only have one corresponding machine instruction during compilation; if the machine instruction set includes multiple machine instructions, it means that the instruction corresponding to that machine instruction set can be arbitrarily selected from multiple machine instructions during compilation.

[0010] Secondly, based on the instruction list, multiple rounds of machine instruction selection are performed for multiple instructions to obtain multiple target files. These multiple target files are obtained by selecting different combinations of machine instructions from multiple machine instruction sets. In other words, based on the instruction list, corresponding machine instructions can be selected for multiple instructions in the first code to obtain multiple target files. Each round of machine instruction selection selects a machine instruction from the corresponding machine instruction set for each of the multiple instructions, ensuring that a target file composed of multiple machine instructions is obtained after each round of selection. Since the instructions in the first code have corresponding machine instruction sets, and these machine instruction sets may include multiple selectable machine instructions, each target file can be generated by arbitrarily selecting one machine instruction from the machine instruction set corresponding to the instructions in the first code. Thus, for instructions in the first code corresponding to machine instruction sets containing multiple machine instructions, multiple different target files can be obtained by selecting different combinations of machine instructions from these machine instruction sets. That is, a target file is equivalent to a combination of machine instructions.

[0011] For example, suppose the first code includes instructions A and B, and the machine instruction set corresponding to instruction A includes machine instruction 1 and machine instruction 2, while the machine instruction set corresponding to instruction B includes machine instruction 3 and machine instruction 4. Thus, when generating target file 1, machine instruction 1 can be selected for instruction A, and machine instruction 3 can be selected for instruction B, meaning the machine instruction combination for target file 1 is machine instruction 1 + machine instruction 3; when generating target file 2, machine instruction 2 can be selected for instruction A, and machine instruction 3 can be selected for instruction B, meaning the machine instruction combination for target file 2 is machine instruction 2 + machine instruction 3; when generating target file 3, machine instruction 1 can be selected for instruction A, and machine instruction 4 can be selected for instruction B, meaning the machine instruction combination for target file 3 is machine instruction 1 + machine instruction 4; and when generating target file 4, machine instruction 2 can be selected for instruction A, and machine instruction 4 can be selected for instruction B, meaning the machine instruction combination for target file 1 is machine instruction 2 + machine instruction 4.

[0012] Finally, the target file with the highest execution performance is selected from multiple target files. For example, multiple target files are executed separately, and one or more target files with the highest execution performance are selected based on their execution performance. The execution performance of a target file can refer to performance information such as its startup speed or response speed.

[0013] In this scheme, during the compilation process, a set of corresponding machine instructions is pre-generated for the instructions in the code to be compiled. Based on the set of machine instructions, one or more corresponding machine instructions can be selected for each instruction in the code during compilation. This means that the compiler no longer selects default machine instructions for the instructions in the code, but guides the compiler to select different combinations of machine instructions during the compilation process, thereby obtaining multiple different object files. Finally, by executing multiple object files, the object file with the best execution performance is selected, which improves the flexibility of the instruction selection process and thus compiles an object file with higher execution performance.

[0014] Because the traditional compilation process is a closed system, the compiler compiles code according to a predetermined flow, often resulting in only one fixed object file from the same code. Furthermore, in traditional compilation processes, the compiler tends to choose the default machine instructions, which is inflexible and makes it difficult to select the optimal ones, especially since the default instructions chosen are often not optimal. This solution addresses this by generating multiple sets of machine instructions for the code, essentially providing an external interface to the compilation process. This allows the compiler to arbitrarily select appropriate machine instructions for each set, resulting in different combinations. Finally, by executing the object file, the performance of these different machine instruction combinations is determined, identifying the one or more machine instruction combinations (i.e., the object file) with the best execution performance.

[0015] In one possible implementation, the method can generate multiple instruction configuration files based on multiple instructions. Each instruction configuration file includes at least one configuration information corresponding to a single instruction, wherein the configuration information indicates the conditions that the corresponding instruction must meet when selecting machine instructions. Then, multiple rounds of machine instruction selection are performed for the multiple instructions based on the multiple instruction configuration files to obtain multiple target files, with each target file corresponding one-to-one with the multiple instruction configuration files.

[0016] In other words, multiple instruction configuration files are first generated based on multiple instructions in the first code. Each instruction configuration file is generated independently based on the first code, and each configuration file includes at least one piece of configuration information; that is, each configuration file generates configuration information for at least one instruction in the first code. The configuration information configured for each instruction differs across the multiple configuration files. Specifically, each instruction configuration file includes at least one piece of configuration information, and each piece of configuration information has a corresponding instruction in the multiple instructions (i.e., each instruction that needs to generate configuration information has a unique corresponding configuration information). Each piece of configuration information indicates the conditions that must be met when selecting the corresponding machine instruction for an instruction in the first code. In other words, the configuration information acts as a reference for selecting the machine instruction corresponding to the instruction in the first code, ensuring that the selection process is completed by referring to the configuration information when selecting a machine instruction for an instruction in the first code.

[0017] In this way, based on multiple instruction configuration files, corresponding machine instructions can be selected for multiple instructions in the first code, thereby obtaining multiple object files corresponding to the multiple instruction configuration files. That is, there is a one-to-one correspondence between the multiple instruction configuration files and the multiple object files, and the multiple object files are obtained based on different instruction configuration files.

[0018] Finally, multiple target files are executed separately, and based on the execution performance of these target files, one or more target files with the highest execution performance are selected. The execution performance of a target file can refer to performance information such as its startup speed and response speed.

[0019] This solution generates different configuration information combinations (i.e., instruction configuration files) for instructions within the same codebase. This allows for specifying different conditions when selecting corresponding machine instructions, enabling the compilation of different target files from the same codebase. By comparing the execution performance of different target files, the target file with the optimal execution performance can be effectively determined. This is beneficial even when the optimal configuration information for each instruction in the code is difficult to determine, allowing for the compilation of the best target file. Furthermore, generating multiple independent instruction configuration files isolates the configuration information combinations and allows for separate backups of each combination. This enables the parallel generation of multiple target files based on multiple instruction configuration files, improving the efficiency of target file generation. Moreover, after finally selecting the target file with the best performance, the corresponding instruction configuration file can be traced back, facilitating further analysis of the configuration information (e.g., investigating what configuration information makes it easier to select the optimal machine instruction).

[0020] In one possible implementation, at least one configuration information includes one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value.

[0021] In other words, when selecting a machine instruction for an instruction with corresponding configuration information in the first code, it is necessary to ensure that the selected machine instruction satisfies one or more of the conditions indicated by the configuration information.

[0022] In one possible implementation, during the process of generating multiple instruction configuration files based on multiple instructions in the first code, the configuration information of each instruction configuration file in the multiple instruction configuration files can be generated sequentially based on the execution order and context of the multiple instructions in the first code. The context of the instruction can include the execution status of the instruction and / or the configuration information generated for the instruction. Furthermore, the generation order of the configuration information in the instruction configuration files is related to the execution order of the instructions corresponding to this configuration information.

[0023] In other words, the earlier the execution order of the instruction corresponding to the configuration information is in the first code, the earlier the configuration information will be generated in the instruction configuration file. Furthermore, when generating configuration information for an instruction, in addition to analyzing the instruction itself, the context of the instruction can also be analyzed to generate the optimal configuration information.

[0024] This solution generates configuration information corresponding to each instruction sequentially based on the execution order and context of the instructions in the code. This ensures that the influence of the instruction context on the selection of machine instructions is taken into account during the configuration information generation process, so as to generate configuration information that can select the optimal machine instructions and ensure the quality of the final target file generated based on the configuration information.

[0025] In one possible implementation, during the process of sequentially generating the configuration information in the instruction configuration file, an instruction configuration template can first be generated based on the execution order of multiple instructions in the first code. This instruction configuration template is used to indicate the target instructions among the multiple instructions that need to generate configuration information and the position of the target instructions among the multiple instructions. The target instructions can include one or more instructions, and the number of instructions included in the target instructions is the same as the number of configuration information items in the instruction configuration file. That is, the instruction configuration template is used to specify the instructions in the first code that need to generate configuration information and their relative positions within the first code.

[0026] Then, based on the context of the target instruction, the corresponding configuration information is sequentially filled into the instruction configuration template to obtain the first instruction configuration file. The context of the target instruction is obtained based on its position among multiple instructions. Multiple instruction configuration files include the first instruction configuration file.

[0027] In this solution, instruction configuration templates are pre-generated based on the execution order of instructions in the code. These templates indicate the instructions in the code that require configuration information and their locations within the code. Subsequently, when generating configuration information for instructions in the code, the configuration information is simply filled into the template based on the instructions, thus completing the construction of the instruction configuration file. Furthermore, a single instruction configuration template can be reused to generate multiple different instruction configuration files, improving the efficiency of instruction configuration file generation.

[0028] In one possible implementation, when the configuration information in the first instruction configuration file indicates the type of functional unit used by the machine instruction, the target instruction for which the configuration information needs to be generated supports compilation into machine instructions using multiple functional units. That is, only if the instruction in the first code itself supports compilation into machine instructions using multiple functional units does this instruction need to specify the type of functional unit used by the machine instruction during the instruction selection stage; if the instruction in the first code itself does not support compilation into machine instructions using multiple functional units, then this instruction does not need to specify the type of functional unit used by the machine instruction during the instruction selection stage.

[0029] In this solution, the target instruction for which configuration information needs to be generated is determined from the perspective of the type of configuration information that needs to be generated for the instruction. This ensures that the configuration information generated for the target instruction can indeed affect the process of selecting machine instructions for the target instruction, and ensures that the configuration information generated for the target instruction is valid, thus avoiding the generation of invalid configuration information.

[0030] In one possible implementation, the plurality of instructions includes a first instruction and a second instruction, both of which can be compiled into machine instructions that use either the first functional unit or the second functional unit.

[0031] In the process of generating corresponding configuration information for the instructions in the first code, first configuration information can be generated for the first instruction based on the first instruction and its context. The first configuration information is used to indicate that the machine instruction selected for the first instruction uses the first functional unit, and the context of the first instruction is used to indicate that the first functional unit and the second functional unit are not occupied. That is, based on the context of the first instruction, it can be determined that neither the first functional unit nor the second functional unit is occupied by any instruction. Therefore, the machine instruction that uses either the first or second functional unit can be selected for the first instruction. For example, in this embodiment, the machine instruction that uses the first functional unit is selected by default for the first instruction.

[0032] Then, based on the second instruction and its context, corresponding second configuration information is generated for the second instruction. The second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit, and the context of the second instruction is used to indicate that the first instruction executed before the second instruction has occupied the first functional unit.

[0033] In other words, if it is determined from the context of the second instruction that other instructions prior to the execution of the second instruction have occupied the first functional unit, the machine instruction of the unoccupied second functional unit can be selected for the second instruction. This avoids selecting the machine instruction of the same functional unit for both the first and second instructions, so as to prevent subsequent instructions from waiting to be executed.

[0034] In this solution, for instructions in the code that can be compiled into machine instructions that use different functional units, configuration information is generated for the instructions by combining the instruction context. This allows different machine instructions to be selected for different functional units as much as possible, avoiding situations where different machine instructions are executed by the same functional unit and causing instructions to wait for execution, thereby improving the execution speed of the compiled target file.

[0035] A second aspect of this application provides a parameterized instruction selection apparatus, comprising: an acquisition module for acquiring first code, the first code including multiple instructions; a processing module for generating multiple sets of machine instructions corresponding to the multiple instructions, the multiple instructions being used to select machine instructions for compilation from the corresponding machine instruction sets; the processing module further comprising performing multiple rounds of machine instruction selection for the multiple instructions to obtain multiple object files, the multiple object files being obtained by selecting different combinations of machine instructions for the multiple instructions from the multiple machine instruction sets; and the processing module further comprising selecting the object file with the highest execution performance from the multiple object files.

[0036] In one possible implementation, the processing module is further configured to: generate multiple instruction configuration files based on multiple instructions, each instruction configuration file including at least one configuration information corresponding to a single instruction, the configuration information being used to indicate the conditions that the corresponding instruction needs to satisfy when selecting machine instructions; and perform multiple rounds of machine instruction selection for multiple instructions based on the multiple instruction configuration files to obtain multiple target files, the multiple target files corresponding one-to-one with the multiple instruction configuration files.

[0037] In one possible implementation, at least one configuration information includes one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value.

[0038] In one possible implementation, the processing module is further configured to: generate configuration information in multiple instruction configuration files based on the execution order of multiple instructions in the first code and the context of the instructions.

[0039] In one possible implementation, the processing module is further configured to: generate an instruction configuration template based on the execution order of multiple instructions in the first code, the instruction configuration template indicating the target instruction among the multiple instructions for which configuration information needs to be generated and the position of the target instruction among the multiple instructions; and, based on the context of the target instruction, sequentially fill the corresponding configuration information of the target instruction in the instruction configuration template to obtain a first instruction configuration file, wherein the context of the target instruction is obtained based on the position of the target instruction among the multiple instructions, and the multiple instruction configuration files include the first instruction configuration file.

[0040] In one possible implementation, when the configuration information in the instruction configuration file is used to indicate the type of functional unit used by the machine instruction, the target instruction that needs to generate the configuration information supports compilation into machine instructions that use multiple functional units.

[0041] In one possible implementation, the plurality of instructions includes a first instruction and a second instruction, both of which can be compiled into machine instructions that use either the first functional unit or the second functional unit. The processing module is further configured to: generate corresponding first configuration information for the first instruction based on the first instruction and its context, wherein the first configuration information is used to indicate that the machine instruction selected for the first instruction uses the first functional unit, and the context of the first instruction is used to indicate that the first and second functional units are not occupied; and generate corresponding second configuration information for the second instruction based on the second instruction and its context, wherein the second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit, and the context of the second instruction is used to indicate that the first instruction executed before the second instruction has occupied the first functional unit.

[0042] In one possible implementation, the first code is intermediate code.

[0043] A third aspect of this application provides a parameterized instruction selection device, which may include a processor, a processor coupled to a memory, and the memory storing program instructions. When the program instructions stored in the memory are executed by the processor, the method described in the first aspect or any implementation thereof is implemented. For details regarding the steps of the various possible implementations of the first aspect executed by the processor, please refer to the first aspect; further details will not be repeated here.

[0044] The fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the method of any implementation of the first aspect described above.

[0045] The fifth aspect of this application provides a circuit system including a processing circuit configured to perform the method of any implementation of the first aspect described above.

[0046] The sixth aspect of this application provides a computer program product that, when run on a computer, causes the computer to perform any implementation of the first aspect described above.

[0047] A seventh aspect of this application provides a chip system including a processor for supporting a server or feature filtering device in implementing the functions involved in any implementation of the first aspect described above, such as processing data and / or information involved in the methods described above. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the server or feature filtering device. This chip system may be composed of chips or may include chips and other discrete devices.

[0048] The beneficial effects of the second to seventh aspects mentioned above can be referred to the introduction of the first aspect above, and will not be repeated here. Attached Figure Description

[0049] Figure 1 is a schematic diagram of the structure of an electronic device 101 provided in an embodiment of this application;

[0050] Figure 2 is a flowchart illustrating a parameterized instruction selection method provided in an embodiment of this application;

[0051] Figure 3 is a schematic diagram of the application process of a parameterized instruction selection method provided in an embodiment of this application;

[0052] Figure 4 is a schematic diagram of the execution flow of a parameterized instruction selection method provided in this application embodiment during practical application;

[0053] Figure 5 is a schematic diagram illustrating the establishment of a mapping relationship between instructions and indexes for functions in intermediate code, provided by an embodiment of this application.

[0054] Figure 6 is a schematic diagram of an instantiation process for an instruction configuration template to generate different instruction configuration files, provided in an embodiment of this application.

[0055] Figure 7 is a schematic diagram of generating a target file based on an instruction configuration file according to an embodiment of this application;

[0056] Figure 8 is a schematic diagram of the generation of an instruction configuration table provided in an embodiment of this application;

[0057] Figure 9 is a schematic diagram of the process of instantiating an instruction configuration template according to an embodiment of this application;

[0058] Figure 10 is a schematic diagram of a parameterized instruction selection process provided in an embodiment of this application;

[0059] Figure 11 is a schematic diagram of a parameterized instruction selection device provided in an embodiment of this application;

[0060] Figure 12 is a schematic diagram of the structure of an execution device provided in an embodiment of this application;

[0061] Figure 13 is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, and not all, of the embodiments of this application. Those skilled in the art will understand that, with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0063] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such descriptions can be used interchangeably where appropriate to allow embodiments to be implemented in a sequence other than that illustrated or described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved.

[0064] The division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interface, and the indirect coupling or communication connection between units may be electrical or other similar forms, none of which are limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed among multiple circuit units. Some or all of the units can be selected to achieve the purpose of the solution in this application according to actual needs.

[0065] For ease of understanding, some technical terms involved in the embodiments of this application will be introduced below.

[0066] (1) Source code

[0067] Source code (also called source program) refers to an uncompiled text file written according to a specific programming language specification; it is a series of human-readable computer language instructions. In modern programming languages, source code can appear in the form of books or tapes, but the most common format is a text file. This typical format is designed to be compiled into a computer program. The ultimate goal of computer source code is to translate human-readable text into binary instructions that a computer can execute. This process is called compilation and is accomplished by a compiler.

[0068] (2) Compilation

[0069] Compilation is the process of using a compiler to transform source code into an executable file. Simply put, compilation is turning source code written in a high-level language into a binary language that computers can understand. Since computers only understand 1s and 0s, a compiler is essentially converting a language familiar to humans into binary.

[0070] Generally, the process of a compiler translating source code into an executable file consists of five stages: lexical analysis; syntax analysis; semantic analysis and intermediate code generation; code optimization; and target code generation.

[0071] (3) Intermediate code

[0072] Intermediate code is a syntax-oriented, equivalent internal representation of the source code that is easily translated into the target program. Its understandability and ease of generating target code fall between those of the source and target languages. Commonly used intermediate languages ​​include Reverse Polish Notation, quadruples, triples, and tree representations.

[0073] (4) Target file

[0074] The file generated by a compiler after compiling source code is called an object file. Generally speaking, object files consist of machine instructions that a computer can directly understand.

[0075] (5) Machine instructions

[0076] Machine instructions are instructions that the Central Processing Unit (CPU) can directly recognize and execute. They are represented in binary code. Machine instructions typically consist of two parts: an opcode and operands. The opcode indicates the operation that the instruction will perform, i.e., the function of the instruction, while the operands indicate the objects involved in the operation and the location where the result will be stored.

[0077] (6) Command Selection

[0078] Instruction selection is an important step in the compilation process. It is mainly used to convert intermediate code into machine instructions, that is, to select the corresponding machine instructions for the instructions in the intermediate code.

[0079] During the compilation of source code, the compiler first compiles the source code into intermediate code, and then converts the instructions in the intermediate code into machine instructions to obtain the object file. Since an instruction in the intermediate code can often be implemented using different machine instructions, the conversion of instructions in the intermediate code into machine instructions usually involves an instruction selection process. Furthermore, the quality of the machine instructions selected for the instructions in the intermediate code during the conversion process often affects the quality of the final generated object file.

[0080] However, current compilers usually have fixed instruction selection methods. That is, for a certain type of instruction in the intermediate code, they will often select the default machine instruction for that type of instruction. This makes the instruction selection process relatively fixed, which can easily lead to poor execution performance of the final compiled object file (i.e., a poor quality object file). For example, the object file may have a slow startup or response speed.

[0081] Based on this, this embodiment provides a parameterized instruction selection method. During the compilation process, an instruction configuration file is generated in advance for the code to be compiled. The configuration information in the instruction configuration file indicates the conditions that the instructions in the code must meet when selecting the corresponding machine instructions. This limits the range of machine instructions that the instructions in the code can select during the code compilation process. This prevents the compiler from selecting default machine instructions for the instructions in the code. Instead, it guides the compiler to select better machine instructions during the compilation process, improves the flexibility of the instruction selection process, and ultimately compiles a target file with higher execution performance.

[0082] The parameterized instruction selection method provided in this application can be applied to electronic devices equipped with compilers. For example, such electronic devices may be servers, smartphones, personal computers (PCs), laptops, tablets, etc.

[0083] Referring to Figure 1, which is a schematic diagram of the structure of an electronic device 101 provided in an embodiment of this application, the electronic device 101 includes a processor 103 coupled to a system bus 105. The processor 103 can be one or more processors, each of which can include one or more processor cores. A video adapter 107 drives a display 109, which is coupled to the system bus 105. The system bus 105 is coupled to an input / output (I / O) bus via a bus bridge 111. An I / O interface 115 is coupled to the I / O bus. The I / O interface 115 communicates with various I / O devices, such as an input device 117 (e.g., a touchscreen), an external storage device 121 (e.g., a hard disk, floppy disk, optical disk, or USB flash drive), a multimedia interface, etc. A transceiver 123 (capable of sending and / or receiving radio communication signals), a camera 155 (capable of capturing still and moving digital video images), and an external USB port 125. Optionally, the interface connected to the I / O interface 115 can be a USB interface.

[0084] The processor 103 can be any conventional processor, including reduced instruction set computing (RISC) processors, complex instruction set computing (CISC) processors, or combinations thereof. Optionally, the processor can be a special-purpose device such as an ASIC.

[0085] Electronic device 101 can communicate with software deployment server 149 via network interface 129. Exemplarily, network interface 129 is a hardware network interface, such as a network interface card (NIC). Network 127 can be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (VPN). Optionally, network 127 can also be a wireless network, such as a WiFi network or a cellular network.

[0086] Hard disk drive interface 131 is coupled to system bus 105. Hardware driver interface is connected to hard disk drive 133. Internal memory 135 is coupled to system bus 105. Data running in internal memory 135 may include operating system (OS) 137, applications 143, and schedules of electronic device 101.

[0087] An operating system consists of the Shell 139 and the kernel 141. The Shell 139 is an interface between the user and the operating system kernel. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input for the operating system, and processing various operating system outputs.

[0088] Kernel 141 consists of the parts of the operating system used to manage memory, files, peripherals, and system resources. Kernel 141 interacts directly with the hardware. The operating system kernel typically runs processes and provides inter-process communication, CPU time-slice management, interrupts, memory management, I / O management, and so on.

[0089] The parameterized instruction selection method provided in the embodiments of this application will be described in detail below. Please refer to Figure 2, which is a flowchart illustrating a parameterized instruction selection method provided in the embodiments of this application. As shown in Figure 2, the parameterized instruction selection method includes the following steps 201-204.

[0090] Step 201: Obtain the first code, which includes multiple instructions.

[0091] In this embodiment, the first code is, for example, the intermediate code obtained by the compiler after initial compilation of the source code. Furthermore, the first code includes multiple instructions, and the compiler needs to further compile the first code to obtain the object file.

[0092] Step 202: Generate an instruction table based on multiple instructions in the first code. The instruction table includes multiple sets of machine instructions corresponding to multiple instructions. Each set of machine instructions has corresponding instructions in the multiple instructions. Each set of machine instructions is used to indicate one or more machine instructions that can be selected at compile time for the corresponding instruction.

[0093] That is, multiple machine instruction sets correspond one-to-one with multiple instructions in the first code. Each machine instruction set indicates one or more machine instructions that can be selected at compile time for its corresponding instruction in the first code. In other words, for multiple instructions in the first code, a machine instruction set can be generated for each instruction in the first code (either some or all), and this machine instruction set indicates the machine instructions that can be selected at compile time. A machine instruction set can include one or more machine instructions. If a machine instruction set includes only one machine instruction, it means that the instruction corresponding to that machine instruction set can only have one corresponding machine instruction at compile time; if a machine instruction set includes multiple machine instructions, it means that the instruction corresponding to that machine instruction set can be arbitrarily selected from multiple machine instructions at compile time.

[0094] Step 203: Based on the instruction list, perform multiple rounds of machine instruction selection for multiple instructions in the first code to obtain multiple target files. The multiple target files are obtained by selecting different combinations of machine instructions for multiple instructions from multiple machine instruction sets.

[0095] Since the instructions in the first code have corresponding machine instruction sets, and these machine instruction sets may include multiple selectable machine instructions, each object file can be generated by arbitrarily selecting one machine instruction from the machine instruction set corresponding to the instructions in the first code. Thus, for each instruction in the first code corresponding to a machine instruction set containing multiple machine instructions, by selecting different combinations of machine instructions from that set, multiple different object files can be obtained. In other words, an object file is essentially a combination of machine instructions.

[0096] For example, suppose the first code includes instructions A and B, and the machine instruction set corresponding to instruction A includes machine instruction 1 and machine instruction 2, while the machine instruction set corresponding to instruction B includes machine instruction 3 and machine instruction 4. Thus, when generating target file 1, machine instruction 1 can be selected for instruction A, and machine instruction 3 can be selected for instruction B, meaning the machine instruction combination for target file 1 is machine instruction 1 + machine instruction 3; when generating target file 2, machine instruction 2 can be selected for instruction A, and machine instruction 3 can be selected for instruction B, meaning the machine instruction combination for target file 2 is machine instruction 2 + machine instruction 3; when generating target file 3, machine instruction 1 can be selected for instruction A, and machine instruction 4 can be selected for instruction B, meaning the machine instruction combination for target file 3 is machine instruction 1 + machine instruction 4; and when generating target file 4, machine instruction 2 can be selected for instruction A, and machine instruction 4 can be selected for instruction B, meaning the machine instruction combination for target file 1 is machine instruction 2 + machine instruction 4.

[0097] Step 204: Execute multiple target files respectively, and select one or more target files with the highest execution performance based on the execution performance of the multiple target files.

[0098] The execution performance of the target file can refer to performance information such as the target file's startup speed and response speed.

[0099] In this scheme, during the compilation process, a set of corresponding machine instructions is pre-generated for the instructions in the code to be compiled. Based on the set of machine instructions, one or more corresponding machine instructions can be selected for each instruction in the code during compilation. This means that the compiler no longer selects default machine instructions for the instructions in the code, but guides the compiler to select different combinations of machine instructions during the compilation process, thereby obtaining multiple different object files. Finally, by executing multiple object files, the object file with the best execution performance is selected, which improves the flexibility of the instruction selection process and thus compiles an object file with higher execution performance.

[0100] Because the traditional compilation process is a closed system, the compiler compiles code according to a predetermined flow, often resulting in only one fixed object file from the same code. Furthermore, in traditional compilation processes, the compiler tends to choose the default machine instructions, which is inflexible and makes it difficult to select the optimal ones, especially since the default instructions chosen are often not optimal. This solution addresses this by generating multiple sets of machine instructions for the code, essentially providing an external interface to the compilation process. This allows the compiler to arbitrarily select appropriate machine instructions for each set, resulting in different combinations. Finally, by executing the object file, the performance of these different machine instruction combinations is determined, identifying the one or more machine instruction combinations (i.e., the object file) with the best execution performance.

[0101] Optionally, in the above embodiments, multiple instruction configuration files can be generated based on multiple instructions in the first code. Each instruction configuration file is independently generated based on the first code, and each instruction configuration file includes at least one configuration information; that is, each instruction configuration file generates configuration information for at least one instruction in the first code. The configuration information configured for the multiple instructions differs among the multiple instruction configuration files. Specifically, each instruction configuration file includes at least one configuration information, and each configuration information has a corresponding instruction in the multiple instructions (i.e., each instruction that needs to generate configuration information has a unique corresponding configuration information). Each configuration information is used to indicate the conditions that must be met when selecting the corresponding machine instruction for the instruction in the first code. In other words, the configuration information is equivalent to machine instruction selection reference information corresponding to the instruction in the first code, ensuring that the selection process for the machine instruction in the first code is completed by referring to the configuration information.

[0102] Specifically, the instruction configuration file records the configuration information corresponding to the instructions in the first code. For multiple instructions in the first code, corresponding configuration information can be generated for all or some of the instructions, and each instruction requiring configuration information has a unique corresponding configuration information. In this way, the configuration information in the instruction configuration file has a correspondence with the instructions in the first code. Furthermore, each configuration information in the instruction configuration file indicates the conditions that must be met when selecting the corresponding machine instruction for an instruction in the first code. That is, the configuration information is essentially reference information for selecting the machine instruction corresponding to the instruction in the first code, ensuring that the selection process is completed by referring to the configuration information when selecting a machine instruction for an instruction in the first code.

[0103] For example, assuming the instructions that need to generate configuration information in the first code are instruction A and instruction B, then when generating the instruction configuration file, the instruction configuration file can include configuration information A corresponding to instruction A and configuration information B corresponding to instruction B. Furthermore, configuration information A is a condition A that needs to be satisfied when selecting the corresponding machine instruction for instruction A; configuration information B is a condition B that needs to be satisfied when selecting the corresponding machine instruction for instruction B.

[0104] In other words, by generating an instruction configuration file, the conditions that the instructions in the first code must meet when selecting machine instructions are specified are defined, thus narrowing down the set of selectable machine instructions for the instructions in the first code and ensuring that a specific machine instruction can be selected when choosing the corresponding machine instruction for the instructions in the first code.

[0105] It should be noted that the instruction configuration file can configure corresponding configuration information for all instructions in the first code, or it can configure corresponding configuration information for only some instructions in the first code. In practical applications, it can be determined according to the specific situation of the first code. This embodiment does not limit the number of instructions in the first code that need to generate configuration information. In addition, the configuration information in the instruction configuration file can be automatically generated by the electronic device based on the instructions in the first code (e.g., based on an automatic script), or it can be generated by the user through manual filling; or, part of the configuration information in the instruction configuration file can be automatically generated by the electronic device, and the other part can be generated by the user through manual filling. This embodiment does not specifically limit the method of generating this configuration information.

[0106] In this way, based on multiple instruction configuration files, corresponding machine instructions can be selected for multiple instructions in the first code, resulting in multiple object files corresponding to the instruction configuration files. That is, there is a one-to-one correspondence between the multiple instruction configuration files and the multiple object files, and each object file is obtained based on a different instruction configuration file. In other words, after obtaining the instruction configuration files, the conditions that the instructions in the first code must meet when selecting machine instructions can be determined based on the configuration information in the instruction configuration files, thereby ensuring that the requirements are met when selecting the corresponding machine instructions for each instruction.

[0107] In other words, during the compilation of the first code, for instructions in the first code that have corresponding configuration information, it is also necessary to select the corresponding machine instructions for the instructions in the first code based on the configuration information in the instruction configuration file, so as to ensure that the selected machine instructions can meet the conditions indicated in the configuration information.

[0108] Understandably, for instructions that do not have configuration information in the first code, the compiler can select machine instructions based on the traditional instruction selection method.

[0109] Finally, multiple target files are executed separately, and based on the execution performance of these target files, one or more target files with the highest execution performance are selected. The execution performance of a target file can refer to performance information such as its startup speed and response speed.

[0110] In this approach, by generating different combinations of configuration information (i.e., instruction configuration files) for instructions within the same codebase, different conditions can be specified when selecting corresponding machine instructions. This allows for the compilation of different target files based on the same code. By comparing the execution performance of these different target files, the target file with the optimal execution performance can be effectively determined. This approach is beneficial even when it is difficult to determine the best configuration information for each instruction in the code, enabling the compilation of the optimal target file.

[0111] Optionally, for any configuration information in the instruction configuration file, the configuration information may include one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value. That is, when selecting a machine instruction for an instruction with corresponding configuration information in the first code, it must be ensured that the selected machine instruction satisfies one or more of the above conditions indicated by the configuration information. Besides the conditions described above, the configuration information may also be used to indicate other conditions; this embodiment does not impose specific limitations.

[0112] The functional unit used by machine instructions can refer to the functional unit in an electronic device used to run machine instructions, such as a scalar arithmetic unit or a logic arithmetic unit.

[0113] In this embodiment, by generating a corresponding instruction configuration file for the code, an external interface is provided for the compilation process. This allows users to freely configure the range of instructions selected during code compilation, ensuring that the compiler considers the conditions indicated in the instruction configuration file when selecting the corresponding machine instructions for the instructions in the code. This guides the compiler to select better machine instructions, ultimately compiling a target file with higher execution performance.

[0114] Since the instructions in the first code can generate configuration information from different perspectives—such as the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains immediate values—it is often difficult to generate optimal configuration information for each instruction in the first code (i.e., it is difficult to determine from which perspectives to generate the optimal configuration information), and thus select the optimal machine instruction.

[0115] Based on this, in this embodiment, multiple different instruction configuration files can be generated, and the same code can be compiled based on the different instruction configuration files to obtain different target files. Finally, the optimal target file can be selected from the multiple different target files.

[0116] For example, after obtaining the first code, multiple instruction configuration files can be generated based on multiple instructions in the first code. Each instruction configuration file is generated independently based on the first code, and each instruction configuration file includes at least one piece of configuration information; that is, each instruction configuration file generates configuration information for at least one instruction in the first code. In the multiple instruction configuration files, the configuration information configured for the various instructions differs between the different configuration files.

[0117] For example, in multiple instruction configuration files, instruction configuration file A generates configuration information for instructions in the first code that indicates the type of functional unit used by the machine instruction; instruction configuration file B generates configuration information for instructions in the first code that indicates the highest bit count of the machine instruction. Similarly, instruction configuration file C generates configuration information for instruction A in the first code that indicates the type of functional unit used by the machine instruction, and for instruction B in the first code that indicates the highest bit count of the machine instruction; instruction configuration file D generates configuration information for instruction A in the first code that indicates the highest bit count of the machine instruction, and for instruction A in the first code that indicates the type of functional unit used by the machine instruction. In general, by generating corresponding configuration information for instructions in the first code from different perspectives, multiple instruction configuration files with different combinations of configuration information can be obtained.

[0118] Then, based on multiple instruction configuration files, corresponding machine instructions can be selected for each instruction in the first code, resulting in multiple object files corresponding to the instruction configuration files. That is, each instruction configuration file can be used to guide the compilation process of the first code, thereby generating the corresponding object file. In other words, there is a one-to-one correspondence between the multiple instruction configuration files and the multiple object files; each object file is obtained based on a different instruction configuration file.

[0119] After obtaining multiple target files, each target file can be executed separately, and the execution performance of each target file can be obtained, such as the startup speed, response speed, and other performance information of each target file.

[0120] In this way, based on the execution performance of multiple target files, one or more target files with the highest execution performance can be selected as the target files to be finally deployed to specific application scenarios, thereby completing the compilation of the first code.

[0121] It should be noted that during the generation of multiple instruction configuration files and the subsequent generation of multiple object files based on these configuration files, methods for achieving optimal parameter configurations (such as Autotuner technology) can be employed to analyze which configuration information to generate for the instructions in order to improve the performance of the final compiled object file. In this way, by continuously generating different configuration information for the instructions in the first code and analyzing the impact of these different configurations on the compilation of the first code, the optimal configuration information for the instructions in the first code can be gradually determined, thereby ensuring that the optimal object file can be compiled based on the instruction configuration files.

[0122] In this approach, by generating different combinations of configuration information (i.e., instruction configuration files) for instructions within the same codebase, different conditions can be specified when selecting corresponding machine instructions. This allows for the compilation of different target files based on the same code. By comparing the execution performance of these different target files, the target file with the optimal execution performance can be effectively determined. This approach is beneficial even when it is difficult to determine the best configuration information for each instruction in the code, enabling the compilation of the optimal target file.

[0123] To make it easier to understand, the following will explain how to generate the corresponding instruction configuration file for the instructions in the first code.

[0124] Optionally, after obtaining the first code, configuration information in the instruction configuration file can be generated sequentially based on the execution order of multiple instructions in the first code and the context of the instructions. The context of the instructions may include the execution status of the instructions and / or the configuration information generated for the instructions.

[0125] In other words, the configuration information in the instruction configuration file is generated sequentially based on the execution order of the corresponding instructions in the first code. The earlier the instruction corresponding to the configuration information is executed in the first code, the earlier the configuration information is generated in the instruction configuration file. Furthermore, when generating configuration information for an instruction, in addition to analyzing the instruction itself, the context of the instruction can also be analyzed to generate the optimal configuration information.

[0126] Understandably, the execution order of multiple instructions in the first code is often fixed. Therefore, the execution order of machine instructions in the object file compiled from the first code is also often fixed and matches the execution order of instructions in the first code. Furthermore, given the fixed execution order of instructions, the execution of some instructions that execute earlier in the order can often influence the execution of some instructions that execute later in the order. Therefore, when selecting corresponding machine instructions for instructions in the first code, considering the instruction context often makes it easier to select the optimal machine instructions. For example, if some instructions that execute earlier in the order are selected with a certain number of bits, then related instructions that execute later in the order can also be selected with the same number of bits to improve the execution speed of the machine instructions.

[0127] Based on this, this solution generates configuration information corresponding to each instruction sequentially by considering the execution order and context of the instructions in the code. This ensures that the influence of the instruction context on the selection of machine instructions is taken into account during the configuration information generation process, so as to generate configuration information that can select the optimal machine instructions and ensure the quality of the target file generated based on the final configuration information.

[0128] For example, in obtaining the first code, an instruction configuration template may be generated based on the execution order of multiple instructions in the first code. The instruction configuration template indicates the target instructions among the multiple instructions that require configuration information generation, and the position of the target instructions within the multiple instructions. The target instructions may include one or more instructions, and the number of instructions included in the target instructions is the same as the number of configuration information items in the instruction configuration file. For instance, the instruction configuration template may contain the specific instructions (i.e., target instructions) in the first code that require configuration information generation, and the index corresponding to each instruction in the target instructions. The index corresponding to each instruction may be used to indicate the position of the instruction among the multiple instructions in the first code.

[0129] Then, based on the context of the target instruction, the corresponding configuration information is populated into the instruction configuration template in sequence to obtain the instruction configuration file. The context of the target instruction is obtained based on the position of the target instruction among multiple instructions.

[0130] In this solution, instruction configuration templates are pre-generated based on the execution order of instructions in the code. These templates indicate the instructions in the code that require configuration information and their locations within the code. Subsequently, when generating configuration information for instructions in the code, the configuration information is simply filled into the template based on the instructions, thus completing the construction of the instruction configuration file. Furthermore, a single instruction configuration template can be reused to generate multiple different instruction configuration files, improving the efficiency of instruction configuration file generation.

[0131] Since configuration information for instructions can be generated from different perspectives in this embodiment, the target instruction in the first code that needs to generate configuration information may also be related to the type of configuration information. For example, if the configuration information in the instruction configuration file is used to indicate the type of functional unit used by the machine instruction, then the target instruction that needs to generate configuration information needs to support compilation into machine instructions using multiple functional units. That is, only if the instruction in the first code itself supports being compiled into machine instructions using multiple functional units does this instruction need to specify the type of functional unit used by the machine instruction during the instruction selection stage; if the instruction in the first code itself does not support being compiled into machine instructions using multiple functional units (for example, the instruction can only be compiled into machine instructions using a specific functional unit), then this instruction does not need to specify the type of functional unit used by the machine instruction during the instruction selection stage.

[0132] In this solution, the target instruction for which configuration information needs to be generated is determined from the perspective of the type of configuration information that needs to be generated for the instruction. This ensures that the configuration information generated for the target instruction can indeed affect the process of selecting machine instructions for the target instruction, and ensures that the configuration information generated for the target instruction is valid, thus avoiding the generation of invalid configuration information.

[0133] In addition, the following examples illustrate how configuration information can be generated based on the execution order and context of the instructions.

[0134] Specifically, the first code includes multiple instructions, including a first instruction and a second instruction, both of which can be compiled into machine instructions using either a first functional unit or a second functional unit. That is, during the instruction selection phase, the first and second instructions can select from a variety of machine instructions; the compiler can choose either a machine instruction using the first functional unit or a machine instruction using the second functional unit. Furthermore, the first instruction is executed before the second instruction in the first code; that is, the first instruction executes before the second instruction.

[0135] During the process of generating configuration information in the instruction configuration file, based on the first instruction and its context, corresponding first configuration information is first generated for the first instruction. This first configuration information indicates that the machine instruction selected for the first instruction uses the first functional unit. The context of the first instruction indicates that neither the first nor the second functional unit is occupied. That is, based on the context of the first instruction, it can be determined that neither the first nor the second functional unit is occupied by any instruction. Therefore, a machine instruction using either the first or second functional unit can be selected for the first instruction. For example, in this embodiment, the machine instruction using the first functional unit is selected by default for the first instruction.

[0136] Then, based on the second instruction and its context, corresponding second configuration information is generated for the second instruction. The second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit, and the context of the second instruction is used to indicate that the first instruction executed before the second instruction has occupied the first functional unit.

[0137] In other words, if the context of the second instruction determines that another instruction prior to the execution of the second instruction is already occupying the first functional unit, the machine instruction of the unoccupied second functional unit can be selected for the second instruction. This avoids selecting the same machine instruction for both the first and second instructions. Thus, when executing the object file, using the first functional unit to execute the machine instruction corresponding to the first instruction and using the second functional unit to execute the machine instruction corresponding to the second instruction minimizes the possibility of instruction waiting when different machine instructions are executed by the same functional unit, thereby improving the execution speed of machine instructions.

[0138] In this solution, for instructions in the code that can be compiled into machine instructions that use different functional units, configuration information is generated for the instructions by combining the instruction context. This allows different machine instructions to be selected for different functional units as much as possible, avoiding situations where different machine instructions are executed by the same functional unit and causing instructions to wait for execution, thereby improving the execution speed of the compiled target file.

[0139] The parameterized instruction selection method provided in this embodiment has been introduced above. To facilitate understanding, the following will describe in detail how to implement the parameterized instruction selection method provided in this embodiment in practical applications, using specific examples.

[0140] For example, please refer to Figure 3, which is a schematic diagram of the application flow of a parameterized instruction selection method provided in an embodiment of this application. As shown in Figure 3, in the initial compilation stage, the compiler first translates the source code into intermediate code, and then the configuration template generation module outputs the corresponding instruction configuration template according to the input intermediate code. Then, different instantiation processes are performed on the same instruction configuration template (that is, different combinations of configuration information are configured for the instructions in the intermediate code), thereby obtaining multiple different instruction configuration files (such as instruction configuration file A and instruction configuration file B in Figure 3).

[0141] During the secondary compilation stage, the compiler takes the instruction configuration file and the corresponding intermediate code as compilation input. When the parameterized instruction selection module executes its steps, it selects machine instructions that meet the configuration requirements based on the configuration information indicated in the instruction configuration file, thereby obtaining the object file. In this way, when compiling the same intermediate code, the compiler can output different object files depending on the different instruction configuration files input. For example, based on instruction configuration file A, the compiler's parameterized instruction selection module outputs object file A; based on instruction configuration file B, the compiler's parameterized instruction selection module outputs object file B.

[0142] In summary, this embodiment extends the interface between the compiler and external systems. By configuring instruction selection based on instruction configuration file A during the instruction selection phase of the compilation process, it enables interaction between external input and the instruction selection phase.

[0143] Please refer to Figure 4, which is a schematic diagram of the execution flow of a parameterized instruction selection method provided in this application embodiment during practical application. As shown in Figure 4, in practical application, the execution flow of the parameterized instruction selection method includes the following steps 401-405.

[0144] Step 401: Analyze the intermediate code to establish the mapping relationship between instructions and indices in the intermediate code.

[0145] For example, please refer to Figure 5, which is a schematic diagram of establishing a mapping relationship between instructions and indices for functions in intermediate code according to an embodiment of this application. As shown in Figure 5, for function A in the intermediate code, a mapping relationship between instructions and indices in function A can be established to indicate the relative positions of instructions in the intermediate code that need to generate configuration information. Specifically, the established mapping relationship includes three items: index, instruction, and configuration information. Among these three items, the index is used to indicate the relative position of the instruction in the intermediate code, and the index value starts from 1; the instruction is used to indicate the instruction in the intermediate code corresponding to the current index; the configuration information refers to the configuration information corresponding to the instruction in the current mapping relationship. Since the configuration information has not yet been generated, the specific content of the configuration information can be "no data," indicating that the current configuration information is yet to be generated.

[0146] For example, consider the following intermediate code:

[0147] In the index table corresponding to Function A::Basic Block A1, the index value of Instr a is 1, and the index value of Instr b is 2.

[0148] Step 402: Generate an instruction configuration template based on the mapping relationship between instructions and indexes.

[0149] After obtaining the mapping relationship between instructions and indices, the template data object can be initialized, and then the instruction configuration template (source.config) can be output according to a specific file format. Specifically, the instruction configuration template can be further generated based on the original intermediate code by combining the mapping relationship between instructions and indices, so that the index and configuration information can be explicitly indicated in the original intermediate code, so as to determine the location of each instruction that needs to generate configuration information and the context of the instruction.

[0150] For example, the following is a schematic diagram of the format of a generated instruction configuration template.

[0151] Step 403: Instantiate the instruction configuration template to obtain multiple instruction configuration files.

[0152] This step involves performing multiple different instantiations of the instruction configuration template to obtain multiple different instruction configuration files. Specifically, the instruction configuration template already indicates the mapping relationship between the index, instructions, and configuration information. The instantiation process can generate specific configuration information for instructions that have configuration information. Furthermore, different instantiation processes for the same instruction configuration template can generate different configuration information for the same instruction, so that different instruction configuration information actually indicates different combinations of configuration information.

[0153] For example, for the same instruction configuration template, corresponding configuration information can be generated from different perspectives. For instance, based on the instruction configuration template, configuration information can be generated for each instruction from the perspective of the type of functional unit used by the machine instruction, indicating the type of functional unit used by the machine instruction selected by each instruction, resulting in instruction configuration file A; or, based on the instruction configuration template, configuration information can be generated for each instruction from the perspective of the highest bit length of the machine instruction, indicating the highest bit length of the machine instruction selected by each instruction, resulting in instruction configuration file B.

[0154] Please refer to Figure 6, which is a schematic diagram of an instantiation process for an instruction configuration template to generate different instruction configuration files according to an embodiment of this application. As shown in Figure 6, for the same instruction configuration template (i.e., the instruction configuration template corresponding to Function A), different configuration information can be generated for the instructions within it, thereby generating different combinations of configuration information for the same set of instructions to obtain different instruction configuration files. For example, in instruction configuration file A, the configuration information generated for instruction a (Instr a) is config-Aa, the configuration information generated for instruction b (Instr b) is config-Ab, and so on, and the configuration information generated for instruction f (Instr f) is config-Af. In instruction configuration file B, the configuration information generated for instruction a (Instr a) is config-Ba, the configuration information generated for instruction b (Instr b) is config-Bb, and so on, and the configuration information generated for instruction f (Instr f) is config-Bf.

[0155] It should be noted that for any two different instruction configuration files, the two instruction configuration files may differ only in the configuration information corresponding to some instructions, or the configuration information corresponding to all instructions may differ. This embodiment does not make a specific limitation in this regard.

[0156] Step 404: Implement parameterized instruction selection based on the instruction configuration file and output multiple target files.

[0157] This step, for the same intermediate code, can use multiple different instruction configuration files to select machine instructions for the instructions in the intermediate code, thereby outputting multiple different target files. Furthermore, there is a one-to-one correspondence between the multiple target files and the multiple instruction configuration files.

[0158] For example, please refer to Figure 7, which is a schematic diagram of generating a target file based on an instruction configuration file according to an embodiment of this application. As shown in Figure 7, in the instruction configuration file, the instructions in the intermediate code (i.e., instr a to instr f) all indicate corresponding configuration information. For example, the corresponding configuration information for instr a and instr c is config-Aa, the corresponding configuration information for instr b, instr e, and instr f is config-Ab, and instr d has no corresponding configuration information. Therefore, in the instruction selection stage, the corresponding machine instruction can be selected based on the configuration information corresponding to each instruction to obtain the target file. For example, for instr a in the intermediate code, the machine instructions Instr a-11 and Instr a-12 can be selected based on the configuration information config-Aa, that is, the instruction instr a in the intermediate code is implemented by the machine instructions in the target file. For instr b in the intermediate code, the machine instruction Instr b-11 can be selected based on the configuration information config-Ab. For the intermediate code in instr d, since there is no corresponding configuration information for instr d, the machine instructions Instr d-11, Instr d-12 and Instr d-13 can be selected based on the default configuration information.

[0159] Step 405: Filter through multiple target files to obtain the optimal target file.

[0160] After obtaining multiple target files, each target file can be executed in the same runtime environment to obtain the execution performance of each target file, such as the startup speed or the response speed during operation. The target file with the best execution performance can then be selected as the optimal target file, so as to facilitate the deployment of the optimal target file in the actual application environment.

[0161] To facilitate understanding, the following will use examples to explain in detail the execution process of multiple steps in the embodiment shown in Figure 4 from the perspective of using the type of functional unit used by machine instructions as configuration information.

[0162] Specifically, in this embodiment, an instruction configuration template generator module is added to the compilation framework based on the Low Level Virtual Machine (LLVM). An output interface for external interaction is defined: -mllvm-linglong-autotuner-for-agx-mvu=true. The instruction selection module is identified and modified. Combined with Autotuner technology, parameterized instruction selection technology is used to perform configurable instruction selection optimization on the vector instruction functional unit, resulting in a performance improvement in the final result.

[0163] First, during the instruction mapping establishment phase, the source code file Source.c is input, and the compiler outputs intermediate code Source.ll. The parameterized instruction selection takes the intermediate code Source.ll as input and generates an instruction configuration table for all instructions in Source.ll. The instruction configuration table initializes the Config_info entry to "no data" only for configurable instructions. Figure 8 illustrates the generation of an instruction configuration table according to an embodiment of this application. In Figure 8, since the Load and Store instructions use only a single functional unit, no configuration information needs to be generated, and the instruction configuration table generation process does not initialize Config_info. However, the Vadd and Vsub instructions can use two functional units and require configuration information; therefore, the instruction configuration table generation process initializes Config_info to "no data".

[0164] Then, based on the generated instruction configuration table and intermediate code, an instruction configuration template can be further generated. Taking Function B in the intermediate code shown in Figure 8 as an example, the specific generated instruction configuration template can be described below.

[0165] Secondly, by instantiating the command configuration template, the command configuration file can be obtained.

[0166] Specifically, in this example, a script can be used to identify commands in the command configuration template that have been marked with "no data" and to populate the Config info item data of the commands marked with "no data" in the command configuration template, thereby obtaining the command configuration file.

[0167] Specifically, in the process of filling in the configuration information corresponding to the instruction in the instruction configuration template, the corresponding configuration information can actually be selected from the set of optional configuration information for each instruction based on the context of the instruction, and the selected configuration information can be filled into the Config info item data corresponding to the instruction, thereby generating corresponding configuration information for each instruction.

[0168] Please refer to Figure 9, which is a schematic diagram illustrating the instantiation process of an instruction configuration template according to an embodiment of this application. As shown in Figure 9, the instructions marked with "no data" in the instruction configuration template include the vadd instruction and the vsub instruction. For the vadd instruction, the optional configuration information set is {@axu,@mvu}; the optional configuration information set for the vsub instruction is {@axu,@mvu}. That is, both vadd and vsub are multi-functional unit instructions and can be executed in either the axu or mvu functional unit.

[0169] During the instantiation of the instruction configuration template, based on the context of the vadd instruction, it is known that when the vadd instruction is executed, neither the axu nor the mvu functional unit is occupied by other instructions. At this time, the axu and mvn functional units can be selected. For example, the axu functional unit is selected by default. Therefore, the instruction selected by the vadd instruction during the instantiation process is vadd@axu, and the vadd instruction configuration information is updated to @axu.

[0170] When configuring the vsub instruction in the instantiation instruction configuration template, based on the context of the vsub instruction, it can be known that the axu functional unit has been occupied by the vadd instruction when the vsub instruction is executed. At this time, the mvu functional unit can be selected for the vsub instruction. Therefore, the instruction selected for the vsub instruction during the instantiation process is vsub@mvu, and the vsub instruction configuration information is updated to @mvu.

[0171] Finally, based on the obtained instruction configuration file, the corresponding machine instruction is selected for each instruction with configuration information in the intermediate code, thereby realizing the parameterized instruction selection process.

[0172] For example, please refer to Figure 10, which is a schematic diagram of a parameterized instruction selection process provided by an embodiment of this application. As shown in Figure 10, in the instruction configuration file, the instructions vadd, vasub, and add, which have configuration information, are all multi-functional unit instructions. The parameterized instruction selection process can select the machine instruction of the corresponding functional unit according to the configuration information of the instruction. The configuration information corresponding to the instruction vadd%a%a%b with an index value of 5 is @axu. Therefore, the machine instruction generated for this instruction can specifically be vadd.v4i16@axu a15,a15,a14. The configuration information corresponding to the instruction vsub%c%c%d with an index value of 6 is @@mvu. Therefore, the machine instruction generated for this instruction can specifically be vsud.v4i16@mvu a7,a7,a8. The configuration information corresponding to the instruction add%g1,%g2,%g3 with an index value of 9 is @axu. Therefore, the machine instruction generated for this instruction can specifically be vadd.v4i16@axu a20,a21,a21.

[0173] The methods provided in the embodiments of this application have been described in detail above. Next, the device for performing the above methods provided in the embodiments of this application will be described.

[0174] Please refer to Figure 11, which is a schematic diagram of a parameterized instruction selection device provided in an embodiment of this application. As shown in Figure 11, the parameterized instruction selection device provided in this embodiment includes: an acquisition module 1101, used to acquire first code, the first code including multiple instructions; a processing module 102, used to generate multiple machine instruction sets corresponding to the multiple instructions based on the multiple instructions, the multiple instructions being used to select machine instructions for compilation from the corresponding machine instruction sets; the processing module 102 is also used to perform multiple rounds of machine instruction selection for the multiple instructions to obtain multiple target files, the multiple target files being obtained by selecting different combinations of machine instructions for the multiple instructions from the multiple machine instruction sets; the processing module 102 is also used to select the target file with the highest execution performance from the multiple target files.

[0175] In one possible implementation, the processing module 1102 is further configured to: generate multiple instruction configuration files based on multiple instructions, each instruction configuration file including at least one configuration information corresponding to a single instruction, the configuration information being used to indicate the conditions that the corresponding instruction needs to satisfy when selecting the corresponding machine instruction; and perform multiple rounds of machine instruction selection for multiple instructions based on the multiple instruction configuration files to obtain multiple target files, the multiple target files corresponding one-to-one with the multiple instruction configuration files.

[0176] In one possible implementation, at least one configuration information includes one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value.

[0177] In one possible implementation, the processing module 1102 is further configured to: generate configuration information in multiple instruction configuration files based on the execution order of multiple instructions in the first code and the context of the instructions.

[0178] In one possible implementation, the processing module 1102 is further configured to: generate an instruction configuration template based on the execution order of multiple instructions in the first code, wherein the instruction configuration template is used to indicate the target instruction among the multiple instructions for which configuration information needs to be generated and the position of the target instruction among the multiple instructions; and, based on the context of the target instruction, sequentially fill the corresponding configuration information of the target instruction in the instruction configuration template to obtain a first instruction configuration file, wherein the context of the target instruction is obtained based on the position of the target instruction among the multiple instructions, and the multiple instruction configuration files include the first instruction configuration file.

[0179] In one possible implementation, when the configuration information in the instruction configuration file is used to indicate the type of functional unit used by the machine instruction, the target instruction that needs to generate the configuration information supports compilation into machine instructions that use multiple functional units.

[0180] In one possible implementation, the plurality of instructions includes a first instruction and a second instruction, both of which can be compiled into machine instructions that use either the first functional unit or the second functional unit; the processing module 1102 is further configured to: generate corresponding first configuration information for the first instruction based on the first instruction and the context of the first instruction, wherein the first configuration information is used to indicate that the machine instruction selected for the first instruction uses the first functional unit, and the context of the first instruction is used to indicate that the first functional unit and the second functional unit are not occupied; and generate corresponding second configuration information for the second instruction based on the second instruction and the context of the second instruction, wherein the second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit, and the context of the second instruction is used to indicate that the first instruction executed before the second instruction has occupied the first functional unit.

[0181] In one possible implementation, the first code is intermediate code.

[0182] Please refer to Figure 12, which is a schematic diagram of the structure of an execution device provided in an embodiment of this application. As shown in Figure 12, the execution device 1200 is used to execute the parameterized instruction selection method described in the above embodiments, and the execution device 1200 can specifically be a server, which is not limited here. Specifically, the execution device 1200 includes: a receiver 1201, a transmitter 1202, a processor 1203, and a memory 1204 (the number of processors 1203 in the execution device 1200 can be one or more, and Figure 12 shows one processor as an example), wherein the processor 1203 may include an application processor 12031 and a communication processor 12032. In some embodiments of this application, the receiver 1201, transmitter 1202, processor 1203, and memory 1204 can be connected via a bus or other means.

[0183] Memory 1204 may include read-only memory and random access memory, and provides instructions and data to processor 1203. A portion of memory 1204 may also include non-volatile random access memory (NVRAM). Memory 1204 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0184] Processor 1203 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses in the diagram are referred to as the bus system.

[0185] The methods disclosed in the embodiments of this application described above can be applied to processor 1203, or implemented by processor 1203. Processor 1203 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of processor 1203 or by instructions in the form of software. The processor 1203 described above can be a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0186] The processor 1203 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 1204. The processor 1203 reads information from memory 1204 and, in conjunction with its hardware, completes the steps of the above methods.

[0187] Receiver 1201 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1202 can be used to output digital or character information through the first interface; transmitter 1202 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1202 may also include a display device such as a display screen.

[0188] The execution device provided in this application embodiment can specifically be a chip, which includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip in the execution device to execute the methods described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. The storage unit can also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, such as random access memory (RAM).

[0189] Referring to Figure 13, which is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of this application. This application also provides a computer-readable storage medium in some embodiments, whereby the method disclosed in Figure 2 can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0190] Figure 13 schematically illustrates a conceptual partial view of an example computer-readable storage medium arranged according to at least some of the embodiments shown herein, the example computer-readable storage medium including a computer program for executing computer processes on a computing device.

[0191] In one embodiment, the computer-readable storage medium 1300 is provided using a signal bearer medium 1301. The signal bearer medium 1301 may include one or more program instructions 1302, which, when executed by one or more processors, can provide the functions or parts thereof described above with reference to FIG2.

[0192] In some examples, the signal carrying medium 1301 may include a computer-readable medium 1303, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video optical disc (DVD), a digital magnetic tape, a memory, ROM, or RAM, etc.

[0193] In some embodiments, the signal-bearing medium 1301 may include a computer-recordable medium 1304, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, the signal-bearing medium 1301 may include a communication medium 1305, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Therefore, for example, the signal-bearing medium 1301 may be transmitted by a wireless communication medium 1305 (e.g., a wireless communication medium conforming to the IEEE 802.X standard or other transmission protocols).

[0194] One or more program instructions 1302 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 1302 conveyed to the computing device via a computer-readable medium 1303, a computer-recordable medium 1304, and / or a communication medium 1305.

[0195] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0196] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods of the various embodiments of this application.

[0197] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0198] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, computer instructions may be transferred from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method for selecting parameterized instructions, characterized in that, include: Obtain the first code, which includes multiple instructions; Based on the plurality of instructions, a plurality of machine instruction sets corresponding to the plurality of instructions are generated, and the plurality of instructions are used to select machine instructions for compilation from the corresponding machine instruction sets; Multiple rounds of machine instruction selection are performed for the multiple instructions to obtain multiple target files, wherein the multiple target files are obtained by selecting different combinations of machine instructions for the multiple instructions from the multiple machine instruction sets; Select the target file with the highest execution performance from the multiple target files.

2. The method according to claim 1, characterized in that, The method further includes: Multiple instruction configuration files are generated based on the multiple instructions. Each instruction configuration file includes at least one configuration information corresponding to a single instruction. The configuration information is used to indicate the conditions that the corresponding instruction needs to meet when selecting machine instructions. The process involves executing multiple rounds of machine instruction selection for the multiple instructions to obtain multiple target files, including: Based on the multiple instruction configuration files, multiple rounds of machine instruction selection are performed for the multiple instructions to obtain the multiple target files, and the multiple target files correspond one-to-one with the multiple instruction configuration files.

3. The method according to claim 2, characterized in that, The at least one configuration information includes one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value.

4. The method according to any one of claims 2-3, characterized in that, The generation of multiple instruction configuration files based on multiple instructions in the first code includes: Based on the execution order and context of the multiple instructions in the first code, configuration information in the multiple instruction configuration files is generated.

5. The method according to claim 4, characterized in that, The step of generating configuration information in the multiple instruction configuration files based on the execution order and context of the multiple instructions in the first code includes: An instruction configuration template is generated based on the execution order of multiple instructions in the first code. The instruction configuration template is used to indicate the target instruction among the multiple instructions that needs to generate configuration information and the position of the target instruction among the multiple instructions. Based on the context of the target instruction, the corresponding configuration information is sequentially filled into the instruction configuration template to obtain a first instruction configuration file, wherein the context of the target instruction is obtained based on the position of the target instruction among the plurality of instructions, and the plurality of instruction configuration files include the first instruction configuration file.

6. The method according to claim 5, characterized in that, When the configuration information in the first instruction configuration file is used to indicate the type of functional unit used by the machine instruction, the target instruction for which configuration information needs to be generated supports compilation into machine instructions that use multiple functional units.

7. The method according to claim 4, characterized in that, The plurality of instructions includes a first instruction and a second instruction, both of which can be compiled into machine instructions that use a first functional unit or a second functional unit. The step of generating configuration information in the multiple instruction configuration files based on the execution order and context of the multiple instructions in the first code includes: Based on the first instruction and its context, corresponding first configuration information is generated for the first instruction. The first configuration information is used to indicate that the machine instruction selected for the first instruction uses the first functional unit. The context of the first instruction is used to indicate that the first functional unit and the second functional unit are not occupied. Based on the second instruction and its context, corresponding second configuration information is generated for the second instruction. The second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit. The context of the second instruction is used to indicate that a first instruction executed before the second instruction has occupied the first functional unit.

8. The method according to any one of claims 1-7, characterized in that, The first code is intermediate code.

9. A parameterized instruction selection device, characterized in that, include: The acquisition module is used to acquire the first code, which includes multiple instructions; The processing module is configured to generate multiple sets of machine instructions corresponding to the multiple instructions based on the multiple instructions, wherein the multiple instructions are used to select machine instructions for compilation from the corresponding sets of machine instructions; The processing module is further configured to perform multiple rounds of machine instruction selection for the plurality of instructions to obtain a plurality of target files, wherein the plurality of target files are obtained by selecting different combinations of machine instructions for the plurality of instructions from the plurality of machine instruction sets; The processing module is also used to select the target file with the highest execution performance from the plurality of target files.

10. The apparatus according to claim 9, characterized in that, The processing module is further configured to: Multiple instruction configuration files are generated based on the multiple instructions. Each instruction configuration file includes at least one configuration information corresponding to a single instruction. The configuration information is used to indicate the conditions that the corresponding instruction needs to meet when selecting machine instructions. Based on the multiple instruction configuration files, multiple rounds of machine instruction selection are performed for the multiple instructions to obtain the multiple target files, and the multiple target files correspond one-to-one with the multiple instruction configuration files.

11. The apparatus according to claim 10, characterized in that, The at least one configuration information includes one or more of the following conditions: the type of functional unit used by the machine instruction, whether the machine instruction updates the status register, the highest bit of the machine instruction, the addressing mode of the machine instruction, or whether the machine instruction contains an immediate value.

12. The apparatus according to any one of claims 9-11, characterized in that, The processing module is further configured to: Based on the execution order and context of the multiple instructions in the first code, configuration information in the multiple instruction configuration files is generated.

13. The apparatus according to claim 12, characterized in that, The processing module is further configured to: An instruction configuration template is generated based on the execution order of multiple instructions in the first code. The instruction configuration template is used to indicate the target instruction among the multiple instructions that needs to generate configuration information and the position of the target instruction among the multiple instructions. Based on the context of the target instruction, the corresponding configuration information is sequentially filled into the instruction configuration template to obtain a first instruction configuration file, wherein the context of the target instruction is obtained based on the position of the target instruction among the plurality of instructions, and the plurality of instruction configuration files include the first instruction configuration file.

14. The apparatus according to claim 13, characterized in that, When the configuration information in the first instruction configuration file is used to indicate the type of functional unit used by the machine instruction, the target instruction for which configuration information needs to be generated supports compilation into machine instructions that use multiple functional units.

15. The apparatus according to claim 12, characterized in that, The plurality of instructions includes a first instruction and a second instruction, both of which can be compiled into machine instructions that use a first functional unit or a second functional unit. The processing module is further configured to: Based on the first instruction and its context, corresponding first configuration information is generated for the first instruction. The first configuration information is used to indicate that the machine instruction selected for the first instruction uses the first functional unit. The context of the first instruction is used to indicate that the first functional unit and the second functional unit are not occupied. Based on the second instruction and its context, corresponding second configuration information is generated for the second instruction. The second configuration information is used to indicate that the machine instruction selected for the second instruction uses the second functional unit. The context of the second instruction is used to indicate that a first instruction executed before the second instruction has occupied the first functional unit.

16. The apparatus according to any one of claims 9-15, characterized in that, The first code is intermediate code.

17. A parameterized instruction selection device, characterized in that, The device includes a memory and a processor; the memory stores code, and the processor is configured to execute the code, wherein when the code is executed, the device performs the method as described in any one of claims 1 to 8.

18. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed by the computer, cause the computer to perform the method according to any one of claims 1 to 8.

19. A computer program product, characterized in that, The computer program product stores instructions that, when executed by a computer, cause the computer to perform the method according to any one of claims 1 to 8.

Images