Pixel circuit, pixel circuit driving method, display panel and display device

Abstract

Provided are a pixel circuit, a pixel circuit driving method, a display panel, and a display device. The pixel circuit comprises a driving transistor (T8), a first transistor (T1) and a second transistor (T2); one end of the driving transistor (T8) is used for being connected in series to a light-emitting element (D); the driving transistor (T8) is used for controlling the driving current of the light-emitting element (D); a first end of the first transistor (T1) is connected to a first initialization voltage (VINIT1), the first initialization voltage (VINIT1) is used for initializing an anode of the light-emitting element (D), and a second end of the first transistor (T1) is connected to the anode of the light-emitting element (D); and a first end of the second transistor (T2) is connected to a second initialization voltage (VINIT2), the second initialization voltage (VINIT2) is used for initializing a source electrode and a drain electrode of the driving transistor (T8), and a third end of the first transistor (T1) and a third end of the second transistor (T2) are respectively connected to different control signals. The pixel circuit, the pixel circuit driving method, the display panel and the display device can improve the display image quality of a display screen.

Description

Pixel circuit, pixel circuit driving method, display panel, and display device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 29, 2024, with application number 202410234517.0 and invention name “Pixel circuit, driving method of pixel circuit, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a pixel circuit, a driving method for a pixel circuit, a display panel, and a display device. Background Art

[0003] Pixel circuits are an important component of display panels. Pixel circuits usually include devices such as transistors and capacitors. Currently, mainstream pixel circuits include 7T (transistor) 1C (capacity) and 8T1C. Among them, 8T1C is widely used due to its better display quality.

[0004] Some 8T1C pixel circuits introduce an on-bias stress (OBS) signal, which can reduce the flicker of the display at low refresh rates and improve the ghosting phenomenon of motion images. However, the transistor that controls the OBS process is usually controlled by the same control signal as other transistors, for example, the same control signal as the anode reset transistor. Furthermore, the frequency of the control signal during the anode reset and OBS processes is the same, and in order to reduce the hysteresis of the driving transistor so that the display refresh does not flicker at 1Hz, the frequency of the control signal is usually set to a high frequency, such as 360Hz.

[0005] Using the same 360Hz frequency as the OBS process for the anode reset signal can easily affect display quality. For example, it can easily cause a three-part screen problem in low-brightness, low-grayscale images, with black bands appearing at 1 / 3 or 2 / 3 of the screen. Another example is poor screen brightness uniformity at the same brightness level. Furthermore, after reliability analysis (RA), the screen is prone to a greenish tint. Therefore, it is necessary to provide a pixel circuit to improve display quality.

[0006] Summary of the Invention

[0007] The present application provides a pixel circuit, a driving method for the pixel circuit, a display panel, and a display device, which can improve the display quality of a display screen.

[0008] In a first aspect, a pixel circuit is provided, comprising: a driving transistor, a first transistor, and a second transistor, wherein one end of the driving transistor is used to be connected in series with a light-emitting element, and the driving transistor is used to control the driving current of the light-emitting element; the first end of the first transistor is connected to a first initialization voltage, the first initialization voltage is used to initialize the anode of the light-emitting element, and the second end of the first transistor is connected to the anode of the light-emitting element; the first end of the second transistor is connected to a second initialization voltage, the second initialization voltage is used to initialize the source and drain of the driving transistor, and the third end of the first transistor and the third end of the second transistor are respectively connected to different control signals.

[0009] In the embodiments provided in the present application, the first transistor is a transistor for initializing the anode of the light-emitting element, and the second transistor is a transistor for initializing the source and drain of the driving transistor. The third end of the first transistor and the third end of the second transistor are respectively controlled by different control signals, which can facilitate the use of control signals of different frequencies for the anode reset stage and the on-state bias stress OBS stage, respectively, thereby improving the split screen problem caused by the fluctuation of the anode reset load, and can improve the display uniformity of the display screen, improve the greening problem of the display screen after reliability analysis, and improve the display quality of the display screen.

[0010] In combination with the first aspect, in some implementations of the first aspect, the second end of the second transistor is connected to the second end of the driving transistor, or the second end of the second transistor is connected to the first end of the driving transistor.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the pixel circuit further includes a third transistor and a fourth transistor, the third transistor being connected between the second end and the third end of the driving transistor, the first end of the fourth transistor being connected to a third initialization voltage, the third initialization voltage being used to initialize the gate of the driving transistor, and the second end of the fourth transistor being connected to the second end of the driving transistor; the third transistor and the fourth transistor are controlled by the same scan driving circuit, and there is a phase difference between the control signal connected to the third end of the third transistor and the control signal connected to the third end of the fourth transistor.

[0012] In the embodiment provided in the present application, the third transistor and the fourth transistor are controlled by the same scan driving circuit, which can save the scan driving circuit and achieve the effect of a narrow frame of the electronic device.

[0013] In combination with the first aspect, in some implementations of the first aspect, a driving frequency of the third transistor and the fourth transistor is the same as a refresh rate of a display panel corresponding to the pixel circuit.

[0014] In the embodiment provided in the present application, the driving frequency of the third transistor and the fourth transistor is the same as the refresh rate of the display panel corresponding to the pixel circuit. Each time the display panel is refreshed, the pixel circuit performs a gate reset to clear the gate charge of the driving transistor after the previous frame is refreshed, so that the display of the current frame is not affected by the previous frame, thereby improving the display quality of the display screen.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the pixel circuit further includes a fourth transistor, the first end of the fourth transistor is connected to a third initialization voltage, the third initialization voltage is used to initialize the gate of the driving transistor, the second end of the fourth transistor is connected to the second end of the driving transistor, the third end of the first transistor is connected to the third end of the fourth transistor, and the third end of the first transistor and the third end of the fourth transistor are connected to the same control signal.

[0016] In the embodiment provided in the present application, the third end of the first transistor and the third end of the fourth transistor are connected to the same control signal, that is, they can be controlled by the same scan driving circuit, which can save the scan driving circuit and achieve a narrow frame of the electronic device.

[0017] In combination with the first aspect, in some implementations of the first aspect, a driving frequency of the first transistor and the fourth transistor is 1 to 120 Hz.

[0018] In the embodiment provided in the present application, the driving frequency of the first transistor and the fourth transistor is 1 to 120 Hz, which can improve the three-screen problem of the display screen, improve the display uniformity of the display screen, and improve the greening phenomenon after reliability analysis, thereby improving the display quality.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the magnitude of the second initialization voltage changes dynamically within a refresh period.

[0020] In the embodiment provided in the present application, the second initialization voltage varies dynamically, which can reduce the power consumption of the pixel circuit, reduce the flicker problem of the display screen, and improve the display quality.

[0021] In combination with the first aspect, in some implementations of the first aspect, the driving frequency of the second transistor is an integer multiple of a first refresh rate, and the first refresh rate is the maximum refresh rate of the display panel corresponding to the pixel circuit.

[0022] In the embodiment provided in the present application, the driving frequency of the second transistor is an integer multiple of the first refresh rate, which can reduce the flickering problem of the display screen at a low refresh rate.

[0023] In combination with the first aspect, in some implementations of the first aspect, the pixel circuit further includes a fifth transistor, a first end of the fifth transistor is connected to the data voltage, and a second end of the fifth transistor is connected to the first end of the driving transistor.

[0024] In combination with the first aspect, in some implementations of the first aspect, the pixel circuit further includes a first emission transistor and a second emission transistor, and the first emission transistor and the second emission transistor are connected in series with the light-emitting element.

[0025] In combination with the first aspect, in some implementations of the first aspect, the first transistor is a low-temperature polycrystalline oxide thin film transistor.

[0026] In the embodiment provided in the present application, the first transistor is a low-temperature polycrystalline oxide thin film transistor, which can facilitate the writing of the anode reset voltage.

[0027] In combination with the first aspect, in some implementations of the first aspect, the driving transistor is a low-temperature polysilicon thin film transistor.

[0028] In a second aspect, a driving method for a pixel circuit is provided, the driving method being used to drive the pixel circuit according to the first aspect or any one of the implementations of the first aspect, the driving method comprising a first stage, a second stage, a third stage, a fourth stage, and a fifth stage. In the first stage, the first transistor is turned on, and the first initialization voltage is written into the anode of the light-emitting element to reset the anode of the light-emitting element; in the second stage, the third transistor and the fourth transistor are turned on, and the third initialization voltage is written into the third end of the driving transistor through the fourth transistor and the third transistor in sequence to reset the gate of the driving transistor; in the third stage, the fifth transistor and the third transistor are turned on, and a data voltage is written into the gate of the driving transistor through the fifth transistor, the driving transistor, and the third transistor in sequence to perform threshold voltage compensation on the driving transistor and store the data voltage in the capacitor; in the fourth stage, the second transistor is turned on, and the second initialization voltage is written into the driving transistor through the second transistor to reset the source and drain of the driving transistor; in the fifth stage, the first emission transistor and the second emission transistor are turned on, and the light-emitting element emits light.

[0029] In combination with the second aspect, in some implementations of the second aspect, before the first stage, the driving method also includes a sixth stage. In the sixth stage, the second transistor is turned on, and the second initialization voltage is written into the driving transistor through the second transistor to reset the source and drain of the driving transistor.

[0030] In a third aspect, a display panel is provided, comprising a plurality of pixel circuits and light-emitting elements as described in the first aspect or any possible implementation of the first aspect, wherein the pixel circuits are used to drive the light-emitting elements to emit light.

[0031] In a fourth aspect, a display screen is provided, comprising the display panel as described in the third aspect.

[0032] In a fifth aspect, a display device is provided, comprising the display panel and a circuit as described in the third aspect, wherein the circuit is used to provide a required control signal to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a pixel circuit diagram provided by an embodiment of the present application;

[0034] FIG2 is a pixel circuit diagram provided by an embodiment of the present application;

[0035] FIG3 is a driving timing diagram provided by an embodiment of the present application;

[0036] FIG4 is a driving timing diagram provided by an embodiment of the present application;

[0037] FIG5 is a pixel circuit diagram provided by an embodiment of the present application;

[0038] FIG6 is a pixel circuit diagram provided by an embodiment of the present application;

[0039] FIG7 is a driving timing diagram provided by an embodiment of the present application;

[0040] FIG8 is a driving timing diagram provided by an embodiment of the present application;

[0041] FIG9 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solution in this application will be described below with reference to the accompanying drawings.

[0043] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0044] In the various embodiments of this application, the terms "first," "second," and so on are merely used to indicate that multiple objects are different. For example, "first transistor" and "second transistor" are merely used to indicate different transistors. These terms should not affect the transistors themselves or their number. The terms "first," "second," and so on should not limit the embodiments of this application in any way.

[0045] The terms "include", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically emphasized otherwise.

[0046] FIG1 is a diagram of a pixel circuit provided by an embodiment of the present application. The pixel circuit may include a driving transistor T8 , a first transistor T1 , and a second transistor T2 .

[0047] The driving transistor T8 can be connected in series with the light-emitting element D, and the driving transistor T8 can be directly connected to the light-emitting element D or indirectly connected to the light-emitting element D. For example, the second end of the driving transistor T8 can be directly connected to the light-emitting element D, or another transistor can be connected between the second end of the driving transistor T8 and the light-emitting element D. The driving transistor T8 can be used to control the light-emitting drive current, that is, it can be used to control the magnitude of the current flowing from the power supply terminal VDD through the light-emitting element D to the power supply terminal VSS.

[0048] The light-emitting element D may be a light-emitting diode (LED) or an organic light-emitting diode (OLED) or other light-emitting devices. The light-emitting element D may emit light when driven by current. The present application does not limit the type of the light-emitting element D.

[0049] The first end of the first transistor T1 can be connected to a first initialization line, and the second end of the first transistor T1 can be connected to the anode of the light-emitting element D. The first initialization line can be used to input a first initialization voltage VINIT1 to the first end of the first transistor T1. The first initialization voltage VINIT1 can be used to control the anode reset process of the pixel circuit, that is, to initialize the anode of the light-emitting element D. Exemplarily, the first initialization voltage VINIT1 can be 0V, or a negative voltage such as -1V, -2V, or -3V. The first initialization voltage VINIT1 can be a dynamically changing voltage.

[0050] In the embodiments provided in the present application, the first end of the transistor can be the source terminal of the transistor, the second end of the transistor can be the drain terminal of the transistor, and the third end of the transistor can be the gate terminal of the transistor. The first end and the second end of the transistor can also be interchanged, and the source terminal of the transistor can be used as the drain terminal, and the drain terminal of the transistor can be used as the source terminal.

[0051] The first end of the second transistor T2 can be connected to a second initialization line, which is used to input a second initialization voltage VINIT2 to the first end of the second transistor T2. The second end of the second transistor T2 can be connected to the second end of the driving transistor T8. The second initialization voltage VINIT2 can be used to control the on-bias stress (OBS) process, or in other words, the second initialization voltage VINIT2 can initialize the source and drain of the driving transistor T8. The pixel circuit includes the second transistor T2 and the second transistor is connected to VINIT2. This can reduce the hysteresis of the driving transistor T8, improve the first frame response of the moving picture, and alleviate the problem of smearing.

[0052] The third end of the second transistor T2 and the third end of the first transistor T1 can be connected to different control signals respectively. For example, the third end of the first transistor T1 can be connected to the S3N signal, and the S3N signal can control the on and off of the first transistor T1. The third end of the second transistor T2 can be connected to the S4N signal, and the S4N signal can control the on and off of the second transistor T2.

[0053] In the embodiment provided by the present application, the third end of the first transistor T1 and the third end of the second transistor T2 are respectively connected to different control signals, and the on and off of the two transistors can be controlled by different control signals. As a result, the driving frequency of the anode reset process does not need to be the same as the driving frequency of the OBS process, which can facilitate the reduction of the frequency of the anode reset process and improve the display quality of the display screen. It alleviates the split screen problem caused by the high anode reset frequency, improves the display uniformity of the screen, and improves the greening phenomenon after RA. Display uniformity includes brightness uniformity and chromaticity uniformity. The brightness unevenness phenomenon is reflected in the difference in brightness and darkness of the screen on the display screen. When displaying a pure white picture, the greater the difference in brightness and darkness of different parts of the screen, the worse the brightness uniformity of the screen, and the lower the quality of the screen; the chromaticity unevenness phenomenon is reflected in the color deviation on the display screen, and different colors are displayed unevenly; the greening phenomenon is that when the display screen displays a pure white picture after the RA test, the picture is not pure white, but greenish.

[0054] Since the third terminal of the second transistor T2 and the third terminal of the first transistor T1 are respectively connected to different control signals, the driving frequency of the second transistor T2 can be different from the driving frequency of the first transistor T1, or in other words, the frequencies of the S4N signal and the S3N signal can be different.

[0055] In some embodiments, the driving frequency of the first transistor T1 may be 1 to 120 Hz. For example, the driving frequency of the first transistor T1 may be 1 Hz, 2 Hz, 30 Hz, 60 Hz, 120 Hz, etc. A driving frequency of 120 Hz for the first transistor T1 can effectively improve the display quality of the display screen, improve the split-screen problem of the display screen, enhance the display uniformity of the display screen, and improve the greening problem of the display screen RA.

[0056] In some embodiments, the driving frequency of the second transistor T2 may be an integer multiple of the first refresh rate, where the first refresh rate may be the maximum refresh rate of the display panel corresponding to the pixel circuit. For example, if the maximum refresh rate of the display panel is 120 Hz, the driving frequency of the second transistor T2 may be 120 Hz, 240 Hz, 360 Hz, 480 Hz, 600 Hz, or 720 Hz.

[0057] In some embodiments, the second initialization voltage VINIT2 may be a voltage that changes dynamically during a refresh cycle. For example, the second initialization voltage VINIT2 may change dynamically within a range of 6 to 7V during a refresh cycle.

[0058] In some embodiments, the pixel circuit may further include a third transistor T3 and a fourth transistor T4. The third transistor T3 may be connected between the second and third terminals of the driving transistor T8. In other words, the first terminal of the third transistor T3 may be connected to the third terminal of the driving transistor T8, and the second terminal of the third transistor T3 may be connected to the second terminal of the driving transistor T8. The first terminal of the fourth transistor T4 may be connected to a third initialization line, and the second terminal of the fourth transistor T4 may be connected to the second terminal of the driving transistor T8. The third initialization line may be used to input a third initialization voltage VINIT3 to the first terminal of the fourth transistor T4. The third initialization voltage VINIT3 may be used to control a gate reset process, that is, to initialize the gate of the driving transistor T8. The third transistor T3 and the fourth transistor T4 may be connected by the same scan drive circuit, or by the same gate driven on array (GOA) circuit, and the control signals connected to the third terminal of the third transistor T3 and the third terminal of the fourth transistor T4 have a phase difference.

[0059] Exemplarily, the third terminal of the third transistor T3 and the third terminal of the fourth transistor T4 can be connected to different output ports of the same GOA circuit. The GOA circuit outputs control signals row by row, so that the third transistor T3 and the fourth transistor T4 can be turned on or off at different times. For example, the third transistor T3 can be turned on first, and after the GOA circuit runs to level K, the fourth transistor T4 is turned on. That is, the phase difference between the control signal connected to the third terminal of the third transistor T3 and the control signal connected to the third terminal of the fourth transistor T4 can differ by K levels. The control signal connected to the third terminal of the third transistor T3 can be recorded as S2N, and the control signal connected to the third terminal of the fourth transistor T4 can be recorded as S2N(N+K).

[0060] The third transistor T3 and the fourth transistor T4 are controlled by the same GOA circuit, which can save the GOA driving circuit, achieve a narrow frame of the electronic device, and reduce the size of the electronic device.

[0061] When the third transistor T3 and the fourth transistor T4 share a GOA circuit, the driving frequency of the third transistor T3 can be the same as the driving frequency of the fourth transistor T4, and the driving frequency of the third transistor T3 and the fourth transistor T4 can be the same as the refresh rate of the display panel corresponding to the pixel circuit. For example, when the refresh rate of the display panel corresponding to the pixel circuit is 120 Hz, the driving frequency of the third transistor T3 and the fourth transistor T4 can also be 120 Hz.

[0062] The driving frequency of the third transistor T3 and the fourth transistor T4 is the same as the refresh rate of the display panel, that is, each time the display screen is refreshed, the pixel circuit performs a gate reset, which can improve the display quality of the display screen.

[0063] The pixel circuit may further include a data loading transistor T5, which may also be referred to as a fifth transistor T5. A first terminal of the data loading transistor T5 may be connected to a data voltage line, which may be used to input a data (DATA) voltage into the data loading transistor T5. This data voltage may be used to control the brightness of the light-emitting element D. A second terminal of the data loading transistor T5 may be connected to a first terminal of the driving transistor T8. The data loading transistor T5 may be controlled by an S1N signal. That is, a third terminal of the data loading transistor T5 may be connected to a control signal S1N, which may control the data writing process of the pixel circuit.

[0064] The pixel circuit may further include a first emission transistor T6 and a second emission transistor T7, which may be connected in series with the light-emitting element D. For example, a first terminal of the first emission transistor T6 may be connected to a power supply voltage VDD, a second terminal of the first emission transistor T6 may be connected to a first terminal of a driving transistor T8, a first terminal of the second emission transistor T7 may be connected to a second terminal of the driving transistor T8, and a second terminal of the second emission transistor T7 may be connected to an anode of the light-emitting element D. The first emission transistor T6 and the second emission transistor T7 may be controlled by the same control signal, that is, they may be controlled by a light-emitting control signal EM. In other words, a third terminal of the first emission transistor T6 and a third terminal of the second emission transistor T7 may both be connected to the light-emitting control signal EM.

[0065] The pixel circuit may further include a capacitor C, one end of which may be connected to the power supply voltage VDD, and the other end of which may be connected to the third end of the driving transistor T8. The capacitor C may be used to store the gate voltage of the driving transistor T8.

[0066] In the pixel circuit shown in FIG1 , the second transistor T2 is connected to the second end of the driving transistor T8. The second transistor T2 may also be connected to the first end of the driving transistor T8, or in other words, the second end of the second transistor T2 may be connected to the first end of the driving transistor T8, as shown in FIG2 . The first end and the second end of the driving transistor T8 may be conductive with each other, and the second end of the second transistor T2 may be connected to the first end of the driving transistor T8 or to the second end of the driving transistor T8, and the second initialization voltage VINIT2 may be written into the driving transistor.

[0067] In the example shown in FIG. 2 , the connection manner of the remaining transistors except the second transistor T2 may be similar to that of the corresponding transistors in the pixel circuit shown in FIG. 1 , and will not be described again here to avoid repetition.

[0068] The pixel circuit provided in an embodiment of the present application may include the above-mentioned eight transistors and one capacitor, and may also be referred to as an 8T1C circuit. The first transistor T1 may be a low-temperature polycrystalline oxide (LTPO) transistor, such as an indium gallium zinc oxide thin-film transistor (IGZO TFT), or may be made of other LTPO materials such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO). The first transistor T1 may be an N-type transistor. The first transistor T1 being an LTPO transistor facilitates the writing of an anode reset voltage.

[0069] The second transistor T2 may be a low temperature polysilicon thin-film transistor (LTPS TFT), and the type of the second transistor T2 may be a P-type transistor.

[0070] The third transistor T3 may be an LTPO transistor, and may be an N-type transistor.

[0071] The fourth transistor T4 may be an LTPO transistor, and may be an N-type transistor.

[0072] The third transistor T3 and the fourth transistor T4 are LTPO, which can reduce the leakage of the transistors, extend the charge retention time, and alleviate the leakage problem on the path where the third transistor T3 and the fourth transistor T4 are located after the data voltage is written.

[0073] The fifth transistor T5 may be an LTPS TFT, and may be a P-type transistor.

[0074] The first emission transistor T6 and the second emission transistor T7 may be LTPS TFTs, and may be P-type transistors.

[0075] The driving transistor T8 may be an LTPS TFT, and may be a P-type transistor.

[0076] Among them, the P-type transistor can be turned on under the control of a low-level control signal and turned off under the control of a high-level control signal; while the N-type transistor can be turned on under the control of a high-level control signal and turned off under the control of a low-level control signal.

[0077] The embodiment of the present application also provides a driving method for a pixel circuit, which divides the working time of the pixel circuit into six stages, which may include, in order of chronological order, a first OBS stage G1, an anode reset stage G2, a gate reset stage G3, a data writing and compensation stage G4, a second OBS stage G5, and a light-emitting stage G6. Figures 3 and 4 are respectively driving timing diagrams corresponding to the driving method for the pixel circuit, wherein Figure 3 may be a driving timing diagram for the pixel circuit at a higher refresh rate, for example, a driving timing diagram at a 120Hz refresh rate, and Figure 4 is a driving timing diagram for the pixel circuit at a lower refresh rate, for example, a driving timing diagram at a 1Hz refresh rate. The driving timings shown in Figures 3 and 4 can be applied to the pixel circuit described in Figures 1 or 2 above. The working process of the pixel circuit provided by the embodiment of the present application is introduced in detail below in conjunction with Figures 3 and 4.

[0078] First OBS phase G1: This first OBS phase can also be called a pre-OBS phase. In this first OBS phase, the S4N signal is a low-level signal. Under the control of the S4N signal, the second transistor T2 is turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4, the first emission transistor T6, and the second emission transistor T7 are turned off. The second initialization voltage VINIT2 can be a positive voltage, and the voltage value can be, for example, 4V, 5V, 6V, 7V, etc.

[0079] For the pixel circuit shown in FIG1 , the second initialization voltage VINIT2 can be written from the second terminal of the driving transistor T8. For the pixel circuit shown in FIG2 , the second initialization voltage VINIT2 can be written from the first terminal of the driving transistor T8. The OBS stage can also be called the source-drain reset stage, which resets the source and drain of the driving transistor and clears the charge between the source and drain of the driving transistor.

[0080] The pixel circuit's operation includes a first OBS phase, which mitigates hysteresis in the driver transistor T8, making the display less susceptible to flicker at low refresh rates, such as 1Hz. Furthermore, executing the first OBS phase before the data writing and compensation phases reduces hysteresis and improves first-frame response in motion, addressing artifacts such as smearing.

[0081] Anode reset phase G2: The S3N signal is a high-level signal, which can control the first transistor T1 to turn on. The first initialization voltage VINIT1 is written to the anode of the light-emitting element D, so that the charge of the anode of the light-emitting element D is cleared. The first initialization voltage VINIT1 can be 0V, -1V, -2V, -3V, or other negative voltage values.

[0082] Gate reset phase G3: Both the S2N and S2N(N+K) signals are high, the third transistor T3 and the fourth transistor T4 are turned on, and the third terminal of the driving transistor T8 is reset by the VINIT1 voltage. This VINIT1 voltage can be -2V, -3V, -4V, -5V, or other negative voltage values. The pixel circuit executes gate reset phase G3 to clear any residual charge on the third terminal of the driving transistor T8 from the previous frame, preventing the previous frame's written voltage from affecting the current frame's written voltage, which in turn could affect the display quality of the current frame.

[0083] Data writing and compensation phase G4: S1N signal is a low level signal, the data loading transistor T5 is turned on, S2N(N+K) signal is a high level signal, the third transistor T3 is turned on, and the data voltage can pass through the data loading transistor T5, the driving transistor T8 and the third transistor T3 in sequence to compensate the threshold voltage of the driving transistor T8 until the threshold voltage of the driving transistor T8 reaches V DATA +Vth , and the data voltage can be written into the storage capacitor C.

[0084] Second OBS stage G5: S4N signal is a low level signal, the second transistor T2 is turned on, the first transistor T1, the third transistor T3, the fourth transistor T4, the first emission transistor T6 and the second emission transistor T7 are turned off, and the VINIT3 voltage is written into the second end of the driving transistor T8.

[0085] Similar to the pre-OBS stage, for the pixel circuit shown in FIG1 , the VINIT3 voltage can be written from the second terminal of the driving transistor T8 , and for the pixel circuit shown in FIG2 , the VINIT3 voltage can be written from the first terminal of the driving transistor T8 .

[0086] Light-emitting stage G6: the EM signal is a low-level signal, the first emission transistor T6 and the second emission transistor T7 are turned on, and the current flows from the power supply end through the first emission transistor T6, the driving transistor T8 and the second emission transistor T7 into the light-emitting element D, causing the light-emitting element D to emit light.

[0087] It should be noted that, in the embodiment of the present application, the working stages of the pixel circuit are divided into the above-mentioned 6 stages only as an example to illustrate the working content of the pixel circuit. The pixel circuit may also include only 5 working stages. For example, the pixel circuit may not execute the first OBS stage G1. That is, in the driving timing diagram shown in FIG3 , the S4N signal may not include the low-level signal corresponding to the first OBS stage G1. The above-mentioned first OBS stage G1 is also the sixth stage, the anode reset stage G2 is also the first stage, the gate reset stage G3 is also the second stage, the data writing and compensation stage G4 is also the third stage, the second OBS stage G5 is also the fourth stage, and the light-emitting stage G6 is also the fifth stage. The working stages of the pixel circuit may include multiple OBS stages. For example, as shown in FIG3 , after the light-emitting stage G6, the pixel circuit may also execute the OBS stage. In the blanking frame, the pixel circuit may also execute the OBS stage to reduce the flicker problem of the pixel circuit during the entire working process.

[0088] Furthermore, the waveforms of the control signals shown in FIG3 are merely examples for illustrating the operation of the pixel circuit. The waveforms of the control signals corresponding to the various transistors may differ from those shown. For example, in the first OBS phase shown in FIG3 , the falling edge of the S4N signal corresponds to the same time as the rising edge of the EM signal. Alternatively, the falling edge of the S4N signal may occur later than the rising edge of the EM signal. For another example, in the first OBS phase shown in FIG3 , the rising edge of the S4N signal corresponds to an earlier time than the rising edge of the S3N signal in the anode reset phase G2. Alternatively, the rising edge of the S4N signal in the first OBS phase may occur at the same time as the rising edge of the S3N signal in the anode reset phase G2. The waveforms of the other signals are similar to those in the above examples, and are only required to enable the pixel circuit to sequentially execute the first OBS phase G1, the anode reset phase G2, the gate reset phase G3, the data write and compensation phase G4, the second OBS phase G5, and the light emission phase G6. FIG3 schematically illustrates the time periods of the refresh frame and the blanking frame. The EM signal corresponding to the end time of the refresh frame in the figure is at a low level. The end time of the refresh frame may also be the same as the time corresponding to the rising edge of the EM signal, or the same as the time corresponding to the falling edge of the EM signal. The present application does not impose any limitation on this. The duration of the refresh frame may be determined according to the refresh rate, and the pulse time of the control signals such as the EM signal and the S4N signal shown in the figure may be adjusted according to actual usage.

[0089] When the refresh rate of the display panel is 120Hz, the refresh frame occupies a higher proportion of the refresh cycle, while the blanking frame occupies a lower proportion. When the refresh rate of the display panel is 1Hz, the blanking frame occupies a higher proportion of the refresh cycle, while the refresh frame occupies a lower proportion. In the refresh frame, data is written to the pixel, while in the blanking frame, no data is written to the pixel. At a 120Hz refresh rate and a 1Hz refresh rate, the pulse duration of the S1N signal in each refresh frame can be the same. In the drive timing sequence shown in FIG4, the shaded portion corresponding to the S1N signal can be the S1N signal in the refresh frame, that is, the portion of the S1N signal in FIG4 before time t. The waveform of the shaded portion of the S1N signal can be the same as the waveform of the S1N signal in the refresh frame in the drive timing sequence shown in FIG3. Since the refresh frame occupies a lower proportion at the 1Hz refresh rate, the S1N signal in FIG4 is represented by the shaded portion. In addition, since the blanking frame occupies a higher proportion at the 1Hz refresh rate, the S1N signal at the 1Hz refresh rate can remain at a high level for a long time. Similarly, at 120Hz and 1Hz refresh rates, the pulse duration of the S2N signal in each refresh frame can also be the same. In the driving timing sequence shown in FIG4 , the shaded portion of the S2N signal can be the S2N signal in the refresh frame. The waveform of the shaded portion of the S2N signal can be the same as the waveform of the S2N signal in the refresh frame in the driving timing sequence shown in FIG3 . Furthermore, the S2N signal at a 1Hz refresh rate can remain at a high level for a long time in the blanking frame. The frequencies of the EM, S4N, and S3N signals at a 120Hz refresh rate and at a 1Hz refresh rate can be the same. The waveforms corresponding to the shaded portions in FIG4 can be the same as the waveforms of the signals in FIG3 .

[0090] The pulse duration of control signals such as the S1N and S2N signals is the same at both 1Hz and 120Hz refresh rates. This means that the duration of stages such as the data writing and compensation phases, as well as the gate reset phase, is the same at both 1Hz and 120Hz refresh rates. This ensures the display has the same brightness at both 1Hz and 120Hz, reducing flicker. The drive frequencies of control signals such as the S1N and S2N signals can also be the same at both 1Hz and 120Hz refresh rates to reduce flicker.

[0091] In the pixel circuits described in Figures 1 and 2 above, the third transistor T3 and the fourth transistor T4 are controlled by the same GOA circuit. In the embodiment provided in the present application, the third transistor T3 and the fourth transistor T4 may also be controlled by different GOA circuits, while the first transistor T1 and the fourth transistor T4 may be controlled by the same GOA circuit.

[0092] In the pixel circuit shown in FIG5 , the third terminal of the first transistor T1 can be connected to the third terminal of the fourth transistor T4, and the third terminal of the first transistor T1 and the third terminal of the fourth transistor T4 can be connected to the same control signal, for example, they can be connected to the control signal S3N. In this example, the type of the first transistor T1 can be the same as that of the fourth transistor T4, for example, they can both be N-type transistors, so that the S3N signal can simultaneously control the on and off of the first transistor T1 and the fourth transistor T4.

[0093] Similar to the pixel circuits described in Figures 1 and 2, the first end of the first transistor T1 can be connected to the first initialization voltage VINIT1, which can be used to initialize the anode of the light-emitting element. The first end of the fourth transistor T4 is connected to the third initialization voltage VINIT3, which can be used to reset the gate of the driving transistor T8. The S3N signal can simultaneously control the anode reset process and the gate reset process of the pixel circuit.

[0094] When the first transistor T1 and the fourth transistor share the GOA circuit, the driving frequency of the first transistor T1 can be 1 to 120 Hz, and the driving frequency of the fourth transistor T4 can also be 1 to 120 Hz, that is, the frequency of the S3N signal connected to the third end of the first transistor T1 and the third end of the fourth transistor T4 can be 1 to 120 Hz. Exemplarily, the driving frequency of the first transistor T1 can be 120 Hz. The driving frequency of the first transistor T1 is 1 to 120 Hz. Compared with the control signal frequency of 360 Hz, the anode reset frequency can be reduced to improve the display quality of the display screen, improve the split-screen problem of the display panel, improve the display uniformity of the display screen, and improve the greening problem after RA.

[0095] Similar to the pixel circuits shown in Figures 1 and 2, when the third end of the first transistor T1 is connected to the third end of the fourth transistor T4, the second transistor T2 can be connected to the second end of the driving transistor T8 (as shown in Figure 5) or to the first end of the driving transistor T8 (as shown in Figure 6).

[0096] The connection, type, driving frequency, etc. of other transistors in FIG. 5 and FIG. 6 may be similar to those of the corresponding transistors in the pixel circuit described in FIG. 1 and FIG. 2 , and will not be described again here to avoid repetition.

[0097] Figures 7 and 8 are driving timing waveforms corresponding to the pixel circuits shown in Figures 5 and 6. The pixel circuits shown in Figures 5 and 6 operate similarly to the pixel circuits shown in Figures 1 and 2, including a first OBS phase G1, an anode reset phase G2, a gate reset phase G3, a data write and compensation phase G4, a second OBS phase G5, and a light-emitting phase G6. Alternatively, the first OBS phase G1 may be excluded, and details thereof will not be repeated herein. Specifically, since the third terminal of the first transistor T1 is connected to the third terminal of the fourth transistor T4 and is controlled by the same signal, the first transistor T1 and the fourth transistor T4 can be turned on or off simultaneously, and the anode reset phase and the gate reset phase can be executed simultaneously.

[0098] Specifically, when the S3N signal is a high-level signal, the first transistor T1 and the fourth transistor T4 are simultaneously turned on. Since the first terminal of the first transistor T1 is connected to the first initialization voltage VINIT1, the VINIT1 voltage is written to the anode of the light-emitting element D, and the anode charge of the light-emitting element D is cleared. During this stage, the S2N signal can also be a high-level signal, the third transistor T3 is turned on, and the second initialization voltage VINIT2 can be sequentially written to the third terminal of the driving transistor T8 through the fourth transistor T4 and the third transistor T3, thereby initializing the third terminal of the driving transistor T8.

[0099] Similar to the drive timing waveforms described in Figures 3 and 4, the drive timing shown in Figure 7 can be a drive timing at a high refresh rate, such as a drive timing at a 120Hz refresh rate, and the drive timing shown in Figure 8 can be a drive timing at a low refresh rate, such as a drive timing at a 1Hz refresh rate. The waveform of each signal in Figure 8 in the refresh frame can be the same as the waveform of the corresponding signal in Figure 7 in the refresh frame, and the frequency of each signal at the low refresh rate and the high refresh rate can also be the same.

[0100] It should be noted that the waveforms of the various driving signals in the pixel circuit may also differ from those in FIG7 . For example, in the anode reset phase G2 and the gate reset phase G3 shown in FIG7 , the high-level duration of the S3N signal is the same as the high-level duration of the S2N signal, and the moment corresponding to the rising edge of the S3N signal is the same as the moment corresponding to the rising edge of the S2N signal, and the moment corresponding to the falling edge of the S3N signal is the same as the moment corresponding to the falling edge of the S2N signal. In the embodiments provided herein, the high-level duration of the S3N signal may also be longer than the high-level duration of the S2N signal, and the moment corresponding to the rising edge of the S3N signal may be earlier than the moment corresponding to the rising edge of the S2N signal, and the moment corresponding to the falling edge of the S3N signal may be later than the moment corresponding to the falling edge of the S2N signal. For another example, in the data writing and compensation phase G4, the rising edge of the S2N signal shown in FIG7 corresponds to an earlier time than the rising edge of the S1N signal, and the falling edge of the S2N signal corresponds to a later time than the falling edge of the S1N signal. Alternatively, the rising edge of the S2N signal corresponds to the same time as the rising edge of the S1N signal, and the falling edge of the S2N signal corresponds to the same time as the falling edge of the S1N signal. The waveforms of other control signals may also differ from the example shown in FIG7 , as long as the pixel circuits shown in FIG5 and FIG6 include the aforementioned six phases. This application does not limit the specific waveforms of each transistor.

[0101] The pixel circuit and its operation according to the embodiment of the present application are described above with reference to FIG1 to FIG8 . The embodiment of the present application further provides a display device, the structure of which may be shown in FIG9 . The display device may include a system driver 100 , which may be used to generate image data. The system driver 100 may be a system on chip (SOC) or an application processor (AP).

[0102] Image data generated by the system driver 100 can be transmitted via the flexible printed circuit board 200 to a data driver integrated circuit (DDIC) 300. The DDIC 300 can include modules such as a storage device, a gamma correction device, and a power converter. The DDIC 300 can convert the image data into an analog signal and transmit it via a data transmission line to a pixel circuit 421. The pixel circuit 421 can be multiple, for example, comprising m rows and n columns of pixel circuits. The pixel circuit 421 can be any of the pixel circuits described in Figures 1, 2, 5, and 6.

[0103] The display device may further include a display panel 400, which may include an active display area (AA) 420 (hereinafter referred to as the AA area 420) and a non-active display area (NA) 410 (hereinafter referred to as the NA area 410), wherein the AA area 420 may be composed of a plurality of the above-mentioned pixel circuits 421, and the NA area 410 may be distributed on the left and right sides of the AA area 420. The NA area 410 may include a GOA circuit 411, or may also be referred to as a scan drive circuit. The DDIC 300 may generate a clock control signal and transmit it to the GOA circuit 411, and the GOA circuit 411 may generate a scan control signal by row and transmit it to the pixel circuit 421 row by row, thereby controlling the thin film transistors in the pixel circuit 421 to turn on or off row by row.

[0104] The display device may further include a peripheral driver circuit 500, which may provide multiple sets of controlled signals (CS), such as a start frame signal, a clock signal, a gate signal high voltage, and a gate signal low voltage. After receiving the CS signal, the GOA circuit may generate corresponding high and low level gate signals. The peripheral driver circuit 500 may also provide multiple sets of pixel operating voltages, such as a power supply voltage VDD, VSS, and an initialization voltage VINIT. The operating voltages may be input into the display panel via multiple signal lines and connected to the pixel circuit components, enabling the pixels to operate normally.

[0105] An embodiment of the present application also provides a display panel, which may include a plurality of pixel circuits of any one type as shown in Figures 1, 2, 5 and 6. The display panel may be the display panel described in Figure 9.

[0106] An embodiment of the present application also provides a display screen, which may include the above-mentioned display panel.

[0107] The present application also provides an electronic device that may include the above-mentioned display device. For example, the electronic device may be a large-screen device such as a mobile phone, tablet computer, laptop computer, television, or a wearable device such as a smartwatch.

[0108] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A pixel circuit, characterized in that: include: a driving transistor, a first transistor, a second transistor, One end of the driving transistor is used to be connected in series with the light emitting element, and the driving transistor is used to control the driving current of the light emitting element; The first end of the first transistor is connected to a first initialization voltage, the first initialization voltage is used to initialize the anode of the light-emitting element, and the second end of the first transistor is connected to the anode of the light-emitting element; The first terminal of the second transistor is connected to a second initialization voltage, which is used to initialize the source and drain of the driving transistor. The third terminal of the first transistor and the third terminal of the second transistor are respectively connected to different control signals.

2. The pixel circuit according to claim 1, wherein: The second end of the second transistor is connected to the second end of the driving transistor, or the second end of the second transistor is connected to the first end of the driving transistor.

3. The pixel circuit according to claim 1 or 2, wherein: The pixel circuit further includes a third transistor and a fourth transistor, the third transistor being connected between the second terminal and the third terminal of the driving transistor, the first terminal of the fourth transistor being connected to a third initialization voltage, the third initialization voltage being used to initialize the gate of the driving transistor, and the second terminal of the fourth transistor being connected to the second terminal of the driving transistor; The third transistor and the fourth transistor are controlled by the same scan driving circuit, and a control signal connected to the third terminal of the third transistor and a control signal connected to the third terminal of the fourth transistor have a phase difference.

4. The pixel circuit according to claim 3, wherein: The driving frequency of the third transistor and the fourth transistor is the same as the refresh rate of the display panel corresponding to the pixel circuit.

5. The pixel circuit according to claim 1 or 2, characterized in that: The pixel circuit further includes a fourth transistor, a first terminal of the fourth transistor being connected to a third initialization voltage, the third initialization voltage being used to initialize the gate of the driving transistor, and a second terminal of the fourth transistor being connected to the second terminal of the driving transistor. The third terminal of the first transistor is connected to the third terminal of the fourth transistor, and the third terminal of the first transistor and the third terminal of the fourth transistor are connected to the same control signal.

6. The pixel circuit according to claim 5, wherein: The driving frequency of the first transistor and the fourth transistor is 1 to 120 Hz.

7. The pixel circuit according to any one of claims 1 to 6, characterized in that: The magnitude of the second initialization voltage changes dynamically during a refresh period.

8. The pixel circuit according to any one of claims 1 to 7, characterized in that: The driving frequency of the second transistor is an integer multiple of a first refresh rate, and the first refresh rate is a maximum refresh rate of a display panel corresponding to the pixel circuit.

9. The pixel circuit according to any one of claims 1 to 8, characterized in that: The pixel circuit further includes a fifth transistor, a first terminal of the fifth transistor is connected to the data voltage, and a second terminal of the fifth transistor is connected to the first terminal of the driving transistor.

10. The pixel circuit according to any one of claims 1 to 9, characterized in that: The pixel circuit further includes a first emission transistor and a second emission transistor, wherein the first emission transistor and the second emission transistor are connected in series with the light emitting element.

11. The pixel circuit according to any one of claims 1 to 10, characterized in that: The first transistor is a low-temperature polycrystalline oxide thin film transistor.

12. The pixel circuit according to any one of claims 1 to 11, characterized in that: The driving transistor is a low-temperature polysilicon thin film transistor.

13. A method for driving a pixel circuit, characterized in that: The driving method is used to drive the pixel circuit according to any one of claims 1 to 12, and the driving method includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage. In the first stage, the first transistor is turned on, and the first initialization voltage is written into the anode of the light-emitting element to reset the anode of the light-emitting element; In the second stage, the third transistor and the fourth transistor are turned on, and the third initialization voltage is sequentially written into the third terminal of the driving transistor through the fourth transistor and the third transistor to reset the gate of the driving transistor; In the third stage, the fifth transistor and the third transistor are turned on, and the data voltage is sequentially written into the gate of the driving transistor through the fifth transistor, the driving transistor, and the third transistor, and the threshold voltage of the driving transistor is compensated, and the data voltage is stored in the capacitor; In the fourth stage, the second transistor is turned on, and the second initialization voltage is written into the driver through the second transistor. a transistor for resetting the source and drain of the driving transistor; In the fifth phase, the first emission transistor and the second emission transistor are turned on, and the light emitting element emits light.

14. The method according to claim 13, wherein: Before the first stage, the driving method further includes a sixth stage. In the sixth stage, the second transistor is turned on, and the second initialization voltage is written into the driving transistor through the second transistor to reset the source and drain of the driving transistor.

15. A display panel, characterized in that: The display panel includes a plurality of pixel circuits and light-emitting elements according to any one of claims 1 to 12, wherein the pixel circuits are used to drive the light-emitting elements to emit light.

16. A display device, characterized in that: The display panel comprises the display panel as claimed in claim 15 and a circuit, wherein the circuit is used to provide required control signals to the display panel.

17. An electronic device, characterized in that: Comprising the display device as claimed in claim 16.

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