Packaging structure, chip structure, and manufacturing method for packaging structure

Abstract

Embodiments of the present application provide a packaging structure, a chip structure, and a manufacturing method for the packaging structure. The packaging structure comprises: a first passivation layer, a redistribution layer, a second passivation layer, and a metallization layer, wherein the redistribution layer covers the first passivation layer, and the second passivation layer covers an edge area of the redistribution layer; and the metallization layer comprises a first metallization layer and a second metallization layer, the first metallization layer and the second metallization layer respectively cover the inner cross-section and an annular area of the second passivation layer, and the first metallization layer further covers a middle area of the redistribution layer, so as to prolong the service life of a chip.

Description

Packaging structure, chip structure, and manufacturing method of packaging structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 28, 2024, with application number 202410225253.2 and application name “Packaging structure, chip structure, and method for manufacturing packaging structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip manufacturing, and specifically to a packaging structure, a chip structure, and a method for manufacturing the packaging structure. Background Art

[0003] Wafer Level Chip Scale Package (WLCSP) or Fan Out Wafer Level Chip Scale Package (FOWLCSP) can be packaged and tested on the entire wafer to reduce the chip package size, reduce current loss, and improve the stability of chip data transmission.

[0004] Currently, as the number of transistors in a wafer-level chip increases, the chip's operating frequency increases, the operating voltage continues to decrease, and the chip's operating current continues to increase. Wafer-level chips can include packaging structures and solder balls. Under the influence of high current, the electromigration rate at the connection between the packaging structure and the solder balls accelerates.

[0005] In the above process, due to the small current flow cross-section at the connection between the packaging structure and the solder ball, electromigration failure is prone to occur, resulting in a shorter service life of the chip. Summary of the Invention

[0006] The embodiments of the present application relate to a packaging structure, a chip structure, and a method for manufacturing the packaging structure, which are used to solve the defect in the prior art that the current flow cross-section at the connection between the packaging structure and the solder ball is small, which makes electromigration failure prone to occur, resulting in a short service life of the chip.

[0007] In a first aspect, an embodiment of the present application provides a packaging structure, comprising: a first passivation layer, a redistribution layer, a second passivation layer, and a metallization layer, wherein:

[0008] The redistribution layer covers the first passivation layer, and the second passivation layer covers an edge region of the redistribution layer;

[0009] The metallization layer includes a first metallization layer and a second metallization layer. The first metallization layer and the second metallization layer cover the inner cross section and the annular region of the second passivation layer respectively. The first metallization layer also covers the middle region of the redistribution layer.

[0010] In a possible implementation, the first metallization layer covers the inner cross-section and the annular region of the second passivation layer, and the second metallization layer covers the inner cross-section and the annular region of the first metallization layer.

[0011] In a possible implementation manner, the annular outer diameter of the second metallization layer is smaller than or equal to the annular outer diameter of the first metallization layer.

[0012] In a possible implementation, the second metallization layer covers the inner cross-section and the annular region of the second passivation layer, and the first metallization layer covers the inner cross-section and the annular region of the second metallization layer.

[0013] In a possible implementation manner, the annular outer diameter of the first metallization layer is the same as the annular outer diameter of the second metallization layer.

[0014] In a possible implementation, the first metallization layer further covers a partial annular region of the second passivation layer, and the annular outer diameter of the first metallization layer is greater than the annular outer diameter of the second metallization layer.

[0015] In a possible implementation manner, the thickness of the second metallization layer is 5-10 um.

[0016] In a second aspect, an embodiment of the present application provides a method for manufacturing a packaging structure, comprising:

[0017] Obtaining a wafer to be packaged, the wafer comprising a first passivation layer, a redistribution layer, and a second passivation layer, wherein the redistribution layer covers the first passivation layer, and the second passivation layer covers an edge region of the redistribution layer;

[0018] A first metallization layer and a second metallization layer are formed on the wafer to obtain a packaging structure, wherein the first metallization layer and the second metallization layer respectively cover the inner cross section and the annular area of ​​the second passivation layer, and the first metallization layer also covers the middle area of ​​the redistribution layer.

[0019] In a possible implementation, forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure includes:

[0020] forming a first metallization layer on the wafer, wherein the first metallization layer covers the inner cross section and the annular region of the second passivation layer;

[0021] A second metallization layer is formed on the first metallization layer to obtain a packaging structure, wherein the second metallization layer covers the inner cross section and the annular area of ​​the first metallization layer.

[0022] In a possible implementation manner, the annular outer diameter of the second metallization layer is smaller than or equal to the annular outer diameter of the first metallization layer.

[0023] In a possible implementation, forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure includes:

[0024] forming a second metallization layer on the wafer, wherein the second metallization layer covers the inner cross section and the annular region of the second passivation layer;

[0025] A first metallization layer is formed on the second metallization layer to obtain a packaging structure, wherein the first metallization layer covers the inner cross section and the annular region of the second metallization layer.

[0026] In a possible implementation, the first metallization layer further covers a partial annular region of the second passivation layer, and the annular outer diameter of the first metallization layer is greater than the annular outer diameter of the second metallization layer.

[0027] In a possible implementation manner, the thickness of the second metallization layer is 5-10 um.

[0028] In a third aspect, an embodiment of the present application provides a chip structure, which includes the packaging structure, solder balls and a printed circuit board PCB described in any one of the first aspects, and the packaging structure is connected to the solder balls.

[0029] In a fourth aspect, the present application provides a chip module, on which the above-mentioned chip structure is stored.

[0030] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which are used to implement any one of the methods described in the second aspect when the computer-executable instructions are executed by a processor.

[0031] In a sixth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which implements any one of the methods described in the second aspect when executed by a processor.

[0032] Embodiments of the present application provide a package structure, a chip structure, and a method for manufacturing the package structure. The package structure includes: a first passivation layer, a rewiring layer, a second passivation layer, and a metallization layer, wherein the rewiring layer covers the first passivation layer, and the second passivation layer covers the edge region of the rewiring layer; the metallization layer includes a first metallization layer and a second metallization layer, the first metallization layer and the second metallization layer respectively covering the inner cross-section and annular region of the second passivation layer, and the first metallization layer also covering the middle region of the rewiring layer. Thus, the inner cross-section and annular region of the second passivation layer 303 are locally thickened to enhance the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in this application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] FIG1 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0035] FIG2 is a schematic diagram of a packaging process flow provided by an embodiment of the present application;

[0036] FIG3 is a schematic diagram of electromigration of a packaging structure provided in an embodiment of the present application;

[0037] FIG4 is a top view schematic diagram of an electron flow path provided in an embodiment of the present application;

[0038] FIG5 is a schematic structural diagram of a packaging structure provided in an embodiment of the present application;

[0039] FIG6 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0040] FIG7 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0041] FIG8 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0042] FIG9 is a schematic flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present application;

[0043] FIG10 is a schematic flow chart of another method for manufacturing a packaging structure according to an embodiment of the present application;

[0044] FIG11 is a schematic flow chart of a method for manufacturing another packaging structure provided in an embodiment of the present application;

[0045] FIG12 is a schematic diagram of a chip structure provided in an embodiment of the present application;

[0046] FIG13 is a schematic diagram of another chip structure provided in an embodiment of the present application;

[0047] FIG14 is a schematic diagram of another chip structure provided in an embodiment of the present application;

[0048] FIG15 is a schematic diagram of another chip structure provided in an embodiment of the present application.

[0049] Explanation of the accompanying reference numerals: 101-WLCSP; 102-solder ball; 103-printed circuit board; 104-FOWLCSP; 301-first passivation layer; 302-rewiring layer; 303-second passivation layer; 304-metallization layer; 305-solder mask layer; 306-PCB pad; 307-PCB body; 308-PCB trace; 501-first metallization layer; 502-second metallization layer.

[0050] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] It should be noted that although the terms "first" and "second" are used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from each other. Alternatively, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0053] It should be understood that the terms "comprise" and "include" indicate the presence of the previously mentioned features, steps, or operations, but do not exclude the presence, occurrence, or addition of one or at least one other feature, step, or operation. The terms "and / or" and the like used in this application may be interpreted as inclusive, or may mean any one or any combination. Alternatively, "A and / or B" means "any of the following: A; B; A and B." In addition, the character " / " in this document generally indicates that the preceding and following objects are in an "or" relationship.

[0054] FIG1 is a schematic diagram of an application scenario provided by an embodiment of the present application. Please refer to FIG1 , which includes two packaging structures. Package structure a can be a wafer-level chip scale package (WLCSP) structure, and package structure b can be a fan-out wafer-level chip scale package (FOWLCSP) structure. Among them, package structure a can include WLCSP 101 and solder balls 102. Package structure b can include FOWLCSP 104 and solder balls 102. Package structure a and package structure b can be soldered on a printed circuit board (PCB) 103. Electromigration also occurs in package structure a and package structure b.

[0055] 2 , the packaging process of the packaging structure will be described in detail by taking the WLCSP structure as an example.

[0056] Figure 2 is a schematic diagram of a packaging process flow provided by an embodiment of the present application. The packaging process flow may include: 1) inspecting incoming wafers to confirm that there are no abnormalities; 2) pre-treating incoming wafers; 3) cleaning; 4) fabricating a first passivation layer; 5) fabricating a redistribution layer (RDL); and 6) fabricating a second passivation layer. After the second passivation layer is opened, the under-bump metallization (UBM) layer is fabricated: 7a) sputtering a 0.1um titanium layer and a 0.5um seed copper layer using physical vapor deposition; 7b) applying photoresist; 7c) exposure; 7d) developing to form a metallization layer opening; 7e) electroplating pre-treatment; 7f) then electroplating the entire wafer with copper, typically to a thickness of approximately 8um; 7g) removing the photoresist; 7h) etching the metallization layer to remove excess titanium and copper; 8) ball implantation; 9) final inspection; and 10) shipping.

[0057] 3 and 4 , the electromigration of the package structure a and the package structure b will be further explained.

[0058] FIG3 is a schematic diagram of electromigration of a package structure provided in an embodiment of the present application. FIG3 may include a package structure, solder balls, and a PCB. The package structure may include a first passivation layer 301, a redistribution layer 302, a second passivation layer 303, and a metallization layer 304. The PCB may include a solder mask layer 305, a PCB pad 306, and a PCB body 307. The PCB body 307 may include a routing layer and a via layer. PCB traces 308 may be provided within the routing layer. FIG4 is a top view schematic diagram of an electron flow path provided in an embodiment of the present application. FIG4 may include a redistribution layer 302, a metallization layer 304, solder balls 102, a PCB pad 306, and a PCB trace 308.

[0059] Electromigration can be a metal migration phenomenon caused by the action of current and temperature on metal wires. The moving electrons and the main metal lattice exchange momentum with each other, and metal atoms migrate along the direction of the electron flow, forming voids at their original positions. The migration and accumulation of metal atoms form protrusions, which may cause the circuit to open.

[0060] When current flows from the PCB to the package structure through the solder balls, electrons can flow from the package structure to the PCB through the solder balls. The electrons can pass through the redistribution layer, metallization layer, solder balls, PCB pads and PCB traces in sequence.

[0061] Currently, as the number of transistors in a wafer-level chip increases, the chip's operating frequency increases, the operating voltage continues to decrease, and the chip's operating current continues to increase. Under the action of high current, the electromigration rate at the connection between the package structure and the solder ball accelerates.

[0062] As shown in Figure 3, under the impact of electron flow from the metallization layer to the PCB pad, the corner area of ​​the metallization layer (the area within the circular dashed box in Figure 3) is the weakest area in the entire link, prone to severe electromigration, which can increase channel resistance and even cause an open circuit. As shown in Figure 4, electrons flowing from the redistribution layer to the PCB flow in a specific direction through the metallization layer into the solder ball, then from the PCB pad to the PCB trace, and then out of the PCB trace. The circular area of ​​the metallization layer may cause an open circuit failure due to electromigration.

[0063] In the above process, due to the small current flow cross-section at the connection between the packaging structure and the solder ball, electromigration failure is prone to occur, resulting in a shorter service life of the chip.

[0064] In order to solve the above technical problems, an embodiment of the present application provides a packaging structure and a manufacturing method thereof. On the basis of the original metallization layer structure, the annular area of ​​the metallization layer is locally thickened to enhance the ability to resist electromigration failure between the metallization layer and the solder balls, thereby improving the service life of the chip.

[0065] Below, combined with Figure 5, the packaging structure is described in detail:

[0066] FIG5 is a schematic structural diagram of a packaging structure provided in an embodiment of the present application.

[0067] As shown in FIG. 5 , the package structure may include: a first passivation layer 301 , a redistribution layer 302 , a second passivation layer 303 and a metallization layer 304 .

[0068] The rewiring layer 302 covers the first passivation layer 301, and the second passivation layer 303 covers the edge region of the rewiring layer 302. In the embodiment of the present application, the specific types of the first passivation layer 301, the rewiring layer 302, and the second passivation layer 303 are not further limited.

[0069] The metallization layer 304 may include a first metallization layer 501 and a second metallization layer 502. The first metallization layer 501 or the second metallization layer 502 may include a copper layer, a nickel layer, and a metal compound layer between the copper layer and the nickel layer. In the embodiment of the present application, the specific structures of the first metallization layer 501 and the second metallization layer 502 are not further limited.

[0070] The first metallization layer 501 and the second metallization layer 502 cover the inner cross section and the annular region of the second passivation layer 303 , respectively. The first metallization layer 501 also covers the middle region of the redistribution layer 302 .

[0071] The first metallization layer 501 and the second metallization layer 502 respectively cover the inner cross section and the annular area of ​​the second passivation layer 303 , and there may be two types of coverage:

[0072] Covering type 1: the first metallization layer 501 covers the inner cross-section and the annular region of the second passivation layer 303 , and the second metallization layer 502 covers the inner cross-section and the annular region of the first metallization layer 501 .

[0073] Covering type 2: the second metallization layer 502 covers the inner cross-section and the annular region of the second passivation layer 303 , and the first metallization layer 501 covers the inner cross-section and the annular region of the second metallization layer 502 .

[0074] For ease of explanation, FIG5 takes coverage type 1 as an example to explain the packaging structure.

[0075] The package structure provided in this embodiment includes: a first passivation layer, a rewiring layer, a second passivation layer, and a metallization layer. The rewiring layer covers the first passivation layer, and the second passivation layer covers the edge region of the rewiring layer. The metallization layer includes a first metallization layer and a second metallization layer, the first metallization layer and the second metallization layer respectively covering the inner cross-section and annular region of the second passivation layer, and the first metallization layer also covering the middle region of the rewiring layer. Thus, the inner cross-section and annular region of the second passivation layer 303 are locally thickened to enhance the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip.

[0076] Below, in conjunction with FIG5 , the coverage type 1 of the metallization layer in the embodiment of the present application is described in detail:

[0077] As shown in FIG5 , the first metallization layer 501 can cover the inner cross-section and annular region of the second passivation layer 303. The first metallization layer 501 can also cover the middle region of the redistribution layer 302. The thickness of the first metallization layer 501 can be approximately 8 μm. In the embodiment of the present application, the thickness of the first metallization layer 501 is not further limited.

[0078] The second metallization layer 502 may cover the inner cross-section and the annular region of the first metallization layer 501. The shape of the second metallization layer 502 may be annular.

[0079] The annular outer diameter of the second metallization layer 502 may be equal to the annular outer diameter of the first metallization layer 501 .

[0080] Optionally, the annular outer diameter of the second metallization layer 502 is smaller than the annular outer diameter of the first metallization layer 501, as shown in Figure 6. Figure 6 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application.

[0081] Optionally, the thickness of the second metallization layer 502 is 5-10 um.

[0082] The packaging structure provided in this embodiment includes: a first passivation layer, a rewiring layer, a second passivation layer, and a metallization layer, wherein the rewiring layer covers the first passivation layer, and the second passivation layer covers the edge region of the rewiring layer; the metallization layer includes a first metallization layer and a second metallization layer, the first metallization layer and the second metallization layer respectively covering the inner cross-section and annular region of the second passivation layer, the first metallization layer also covering the middle region of the rewiring layer, the first metallization layer covering the inner cross-section and annular region of the second passivation layer, and the second metallization layer covering the inner cross-section and annular region of the first metallization layer. In this way, the inner cross-section and annular region of the second passivation layer are locally thickened, thereby enhancing the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip.

[0083] Next, in conjunction with FIG7 , the coverage type 2 of the metallization layer in the embodiment of the present application is described in detail:

[0084] FIG7 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application.

[0085] 7 , the second metallization layer 502 may cover the inner cross-section and the annular region of the second passivation layer 303. The second metallization layer 502 may be in the shape of an annular shape.

[0086] The first metallization layer may cover the inner cross-section and the annular region of the second metallization layer 502 .

[0087] The first metallization layer may also cover a middle region of the redistribution layer 302 .

[0088] The thickness of the first metallization layer may be about 8 μm. In the embodiment of the present application, the thickness of the first metallization layer is not further limited.

[0089] Optionally, the first metallization layer also covers a partial annular region of the second passivation layer 303 , and the annular outer diameter of the first metallization layer is greater than the annular outer diameter of the second metallization layer 502 .

[0090] Optionally, the annular outer diameter of the first metallization layer may be larger than the annular outer diameter of the second metallization layer 502 by 5-10 um.

[0091] Optionally, the annular outer diameter of the first metallization layer may be the same as the annular outer diameter of the second metallization layer 502, as shown in Figure 8. Figure 8 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application.

[0092] Optionally, the thickness of the second metallization layer 502 is 5-10 um.

[0093] The packaging structure provided in this embodiment includes: a first passivation layer, a rewiring layer, a second passivation layer, and a metallization layer, wherein the rewiring layer covers the first passivation layer, and the second passivation layer covers the edge region of the rewiring layer; the metallization layer includes a first metallization layer and a second metallization layer, the first metallization layer and the second metallization layer respectively covering the inner cross-section and annular region of the second passivation layer, the first metallization layer also covering the middle region of the rewiring layer, the second metallization layer covering the inner cross-section and annular region of the second passivation layer, and the first metallization layer covering the inner cross-section and annular region of the second metallization layer. In this way, the inner cross-section and annular region of the second passivation layer are locally thickened, thereby enhancing the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip.

[0094] The following is a detailed description of the manufacturing method shown in this application through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be repeated in different embodiments.

[0095] FIG9 is a flow chart of a method for manufacturing a packaging structure provided by an embodiment of the present application. The execution subject of the embodiment of the present application can be an electronic device or a control device provided in the electronic device. The control device can be implemented by software or by a combination of software and hardware. Referring to FIG9, the method includes:

[0096] S901: Obtain wafers to be packaged.

[0097] The wafer may include a first passivation layer, a redistribution layer, and a second passivation layer. The redistribution layer may cover the first passivation layer. The second passivation layer may cover an edge region of the redistribution layer.

[0098] The original wafer can be inspected for incoming materials. When it is confirmed that there is no abnormality, the incoming materials are pre-processed and then cleaned, and the first passivation layer, the rewiring layer and the second passivation layer are made to obtain the wafer to be packaged.

[0099] S902 , forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure.

[0100] The first metallization layer and the second metallization layer may cover the inner cross-section and the annular region of the second passivation layer, respectively, and the first metallization layer may also cover the middle region of the redistribution layer.

[0101] A first electroplating layer and a second electroplating layer are performed on the wafer to form a first metallization layer and a second metallization layer to obtain a packaging structure.

[0102] The electroplating process may include process flows such as sputtering, photoresist coating, exposure, development, UBM electroplating, photoresist stripping and UBM etching, which are not limited here.

[0103] The method for manufacturing a packaging structure provided in this embodiment comprises obtaining a wafer to be packaged, the wafer comprising a first passivation layer, a rewiring layer, and a second passivation layer, wherein the rewiring layer covers the first passivation layer, and the second passivation layer covers the edge region of the rewiring layer; and forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure, wherein the first metallization layer and the second metallization layer respectively cover the inner cross-section and annular region of the second passivation layer, and the first metallization layer also covers the middle region of the rewiring layer. In this way, adding a secondary electroplating process to the metallization layer does not significantly increase processing time, has little impact on the process window, and facilitates switching of process routes. Furthermore, the inner cross-section and annular region of the second passivation layer are locally thickened, thereby enhancing the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip.

[0104] 10 , the process of forming a first metallization layer and a second metallization layer on a wafer to obtain a package structure ( S902 ) will be explained.

[0105] FIG10 is a flow chart of another method for manufacturing a packaging structure according to an embodiment of the present application. Based on the above embodiment, please refer to FIG10. The method includes:

[0106] S1001 , forming a first metallization layer on a wafer.

[0107] The first metallization layer covers the inner cross section and the annular region of the second passivation layer. The first metallization layer also covers the middle region of the redistribution layer.

[0108] A layer of 0.1um titanium and about 0.5um seed copper can be sputtered by physical vapor deposition, photoresist is coated on the surface, exposed, and developed to form a UBM opening, electroplating pretreatment is performed, and copper electroplating is performed on the entire surface to form the first metallization layer on the wafer.

[0109] The electroplating thickness of the copper electroplating process can be about 8 μm, which is not limited here.

[0110] S1002 , forming a second metallization layer on the first metallization layer to obtain a packaging structure.

[0111] The second metallization layer may cover the inner cross-section and the annular area of ​​the first metallization layer.

[0112] Photoresist is re-coated on the inner cross section and annular area of ​​the first metallization layer, exposed and developed, and the inner cross section and annular area are locally electroplated to the target thickness to form a second metallization layer. The photoresist is removed and the excess seed copper and titanium metal are etched away to obtain a packaging structure.

[0113] The implementation content of each step in the embodiment of the present application can refer to the description of the corresponding steps or operations in the above method embodiment, and repeated content will not be repeated.

[0114] The method for manufacturing a package structure provided in this embodiment comprises forming a first metallization layer on a wafer, the first metallization layer covering the inner cross-section and annular region of a second passivation layer, and then forming a second metallization layer on the first metallization layer to obtain the package structure, the second metallization layer covering the inner cross-section and annular region of the first metallization layer. In this way, adding a secondary electroplating process to the metallization layer does not significantly increase processing time, has minimal impact on the process window, and facilitates switching of process routes. Furthermore, the inner cross-section and annular region of the second passivation layer are locally thickened, thereby enhancing the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the service life of the chip.

[0115] 11 , the process of forming a first metallization layer and a second metallization layer on a wafer to obtain a package structure ( S902 ) will be explained.

[0116] FIG11 is a flow chart of another method for manufacturing a packaging structure provided in an embodiment of the present application. Based on the above embodiment, please refer to FIG11. The method includes:

[0117] S1101 , forming a second metallization layer on the wafer.

[0118] The second metallization layer covers the inner cross section and the annular region of the second passivation layer.

[0119] A layer of 0.1um titanium and about 0.5um seed copper can be sputtered by physical vapor deposition, and photoresist is applied to the inner cross section and annular area of ​​the second passivation layer. After exposure and development, an opening in the UBM corner area is formed, and electroplating pretreatment is performed. Copper electroplating is performed in the UBM corner area to form a second metallization layer, and the photoresist is stripped.

[0120] S1102 , forming a first metallization layer on the second metallization layer to obtain a packaging structure.

[0121] The first metallization layer covers the inner cross-section and the annular area of ​​the second metallization layer.

[0122] Photoresist is re-applied on the wafer surface, and the inner cross-section and annular area of ​​the second metallization layer and the middle area of ​​the redistribution layer are exposed. After development, electroplating is performed to the target thickness, the photoresist is removed, and the excess seed copper and titanium metal are etched away.

[0123] The target thickness may be about 8 μm, which is not limited here.

[0124] The implementation content of each step in the embodiment of the present application can refer to the description of the corresponding steps or operations in the above method embodiment, and repeated content will not be repeated.

[0125] The method for manufacturing a package structure provided in this embodiment comprises forming a second metallization layer on a wafer, the second metallization layer covering the inner cross-section and annular region of the second passivation layer; and forming a first metallization layer on the second metallization layer, thereby obtaining the package structure, the first metallization layer covering the inner cross-section and annular region of the second metallization layer. This method adds a secondary electroplating process to the metallization layer without significantly increasing processing time, having minimal impact on the process window, and facilitating switching of process routes. Furthermore, the inner cross-section and annular region of the second passivation layer are locally thickened, thereby enhancing the resistance to electromigration failure between the metallization layer and the solder balls, thereby increasing the lifespan of the chip.

[0126] Figure 12 is a schematic diagram of a chip structure provided in an embodiment of the present application. Referring to Figure 12 , Figure 12 includes a chip structure, which may include the package structure and solder balls described in Figure 5 , with the package structure connected to the solder balls. The corresponding details and effects can be found in the embodiment corresponding to Figure 5 , and will not be further described. The chip structure may be soldered to a PCB, which may include a solder mask layer 305, PCB pads 306, and a PCB body 307.

[0127] Figure 13 is a schematic diagram of another chip structure provided in an embodiment of the present application. Referring to Figure 13 , Figure 13 includes a chip structure, which may include the package structure and solder balls described in Figure 6 above, with the package structure connected to the solder balls. The corresponding details and effects can be found in the embodiment corresponding to Figure 6 , and will not be further described. The chip structure may be soldered to a PCB, which may include a solder mask layer 305, PCB pads 306, and a PCB body 307.

[0128] FIG14 is a schematic diagram of another chip structure provided in an embodiment of the present application. Referring to FIG14 , FIG14 includes a chip structure, which may include: the package structure and solder balls described in FIG7 , with the package structure connected to the solder balls. The corresponding contents and effects can be referred to in the embodiment corresponding to FIG7 , and will not be further described. The chip structure may be soldered to a PCB, which may include a solder mask layer 305, PCB pads 306, and a PCB body 307.

[0129] Figure 15 is a schematic diagram of another chip structure provided in an embodiment of the present application. Referring to Figure 15 , Figure 15 includes a chip structure, which may include the package structure and solder balls described in Figure 8 above, with the package structure connected to the solder balls. The corresponding details and effects can be found in the embodiment corresponding to Figure 8 , and will not be further described. The chip structure may be soldered to a PCB, which may include a solder mask layer 305, PCB pads 306, and a PCB body 307.

[0130] The present application also provides a chip module, on which any chip structure of Figures 12 to 15 is stored. The corresponding content and effects can be referred to the above embodiment part, which will not be described in detail.

[0131] An embodiment of the present application also provides a computer program product, which can be executed by a processor. When the computer program product is executed, the manufacturing method of the above-mentioned packaging structure can be implemented.

[0132] All or part of the steps of the above-mentioned method embodiments are implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above-mentioned method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof.

[0133] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be realized by computer execution instructions. These computer execution instructions can be provided to the processing unit of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0134] These computer-executable instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0135] These computer-executable instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0136] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations.

Claims

1. A packaging structure, characterized in that: include: a first passivation layer, a redistribution layer, a second passivation layer, and a metallization layer, wherein: The redistribution layer covers the first passivation layer, and the second passivation layer covers an edge region of the redistribution layer; The metallization layer includes a first metallization layer and a second metallization layer. The first metallization layer and the second metallization layer cover the inner cross section and the annular region of the second passivation layer respectively. The first metallization layer also covers the middle region of the redistribution layer.

2. The packaging structure according to claim 1, wherein: The first metallization layer covers the inner cross-section and the annular region of the second passivation layer, and the second metallization layer covers the inner cross-section and the annular region of the first metallization layer.

3. The packaging structure according to claim 2, wherein: The annular outer diameter of the second metallization layer is smaller than or equal to the annular outer diameter of the first metallization layer.

4. The packaging structure according to claim 1, wherein: The second metallization layer covers the inner cross-section and the annular region of the second passivation layer, and the first metallization layer covers the inner cross-section and the annular region of the second metallization layer.

5. The packaging structure according to claim 4, wherein: The annular outer diameter of the first metallization layer is the same as the annular outer diameter of the second metallization layer.

6. The packaging structure according to claim 4, wherein: The first metallization layer also covers a partial annular region of the second passivation layer, and an annular outer diameter of the first metallization layer is greater than an annular outer diameter of the second metallization layer.

7. The packaging structure according to any one of claims 2 to 6, wherein: The thickness of the second metallization layer is 5-10 μm.

8. A chip structure, characterized in that: include: The package structure and solder ball according to any one of claims 1 to 7, wherein the package structure is connected to the solder ball.

9. A method for manufacturing a packaging structure, characterized in that: include: Obtaining a wafer to be packaged, the wafer comprising a first passivation layer, a redistribution layer, and a second passivation layer, wherein the redistribution layer covers the first passivation layer, and the second passivation layer covers an edge region of the redistribution layer; A first metallization layer and a second metallization layer are formed on the wafer to obtain a packaging structure, wherein the first metallization layer and the second metallization layer respectively cover the inner cross section and the annular area of ​​the second passivation layer, and the first metallization layer also covers the middle area of ​​the redistribution layer.

10. The method for manufacturing a packaging structure according to claim 9, wherein: Forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure, comprising: forming a first metallization layer on the wafer, wherein the first metallization layer covers the inner cross section and the annular region of the second passivation layer; A second metallization layer is formed on the first metallization layer to obtain a packaging structure, wherein the second metallization layer covers the inner cross section and the annular area of ​​the first metallization layer.

11. The method for manufacturing a packaging structure according to claim 10, wherein: The annular outer diameter of the second metallization layer is smaller than or equal to the annular outer diameter of the first metallization layer.

12. The method for manufacturing a packaging structure according to claim 9, wherein: Forming a first metallization layer and a second metallization layer on the wafer to obtain a packaging structure, comprising: forming a second metallization layer on the wafer, wherein the second metallization layer covers the inner cross section and the annular region of the second passivation layer; A first metallization layer is formed on the second metallization layer to obtain a packaging structure, wherein the first metallization layer covers the inner cross section and the annular region of the second metallization layer.

13. The method for manufacturing a packaging structure according to claim 12, wherein: The first metallization layer also covers a partial annular region of the second passivation layer, and an annular outer diameter of the first metallization layer is greater than an annular outer diameter of the second metallization layer.

14. The method for manufacturing a packaging structure according to any one of claims 9 to 13, characterized in that: The thickness of the second metallization layer is 5-10 μm.

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