Stacked film having passivated contact structure and preparation method therefor, and topcon cell

Abstract

The present invention provides a stacked film having a passivated contact structure and a preparation method therefor, and a TOPCon cell. The preparation method comprises: A) forming a pretreated oxide layer on the back surface of a silicon wafer; B) depositing a tunneling oxide layer by means of PECVD, wherein the tunneling oxide layer is provided with n sub-films, and the plasma power of deposition of the n sub-films is increased in a gradient mode along with the deposition time; C) depositing a doped amorphous silicon layer by means of the PECVD to obtain a stacked film intermediate, wherein the doping concentration of the doped amorphous silicon layer is changed in a gradient mode along with the deposition time; and D) performing gradient annealing crystallization on the stacked film intermediate to obtain a stacked film having a passivated contact structure. The present invention can improve the chemical passivation property and the precision of the tunneling oxide layer, avoid the film delamination caused by hydrogen overflow during annealing of an intrinsic Poly layer, also reduce, by means of gradient heating annealing treatment, the intra-wafer / inter-wafer crystallization difference caused by insufficient annealing temperature of each work station, and improve the yield rate of mass production.

Description

A passivated contact structure laminated film, preparation method thereof and TOPCon battery

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on February 27, 2024, with application number 202410218226.2 and invention name “A Passivated Contact Structure Laminated Film, Its Preparation Method and TOPCon Battery”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention belongs to the technical field of solar cells, and in particular relates to a passivation contact structure laminated film, a preparation method thereof, and a TOPCon cell. Background Art

[0003] Tunnel Oxide Passivated Contact solar cell (TOPcon) is a new type of passivated contact solar cell first proposed by the Fraunhofer Institute for Solar Energy in Germany at the 28th European PVSEC Photovoltaic Conference in 2013. TOPCon cells have the advantages of high efficiency, low equipment cost, and high compatibility with PERC production lines. They are the first third-generation photovoltaic cell technology to achieve large-scale mass production.

[0004] The front of the TOPcon cell is essentially the same as a conventional N-type solar cell or N-PERT solar cell. The core technology of the cell is the back-side passivation contact. First, a tunneling oxide layer is prepared on the back of the cell, and then a layer of doped polysilicon is deposited. The two together form a passivation contact structure. The passivation performance is activated through an annealing process. During this annealing process, the crystallinity of the Si film changes, transforming from a microcrystalline amorphous mixed phase to a polycrystalline. This structure can block the recombination of minority carriers and holes, thereby improving the open circuit voltage and short-circuit current of the cell. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority carriers and holes. The good passivation effect of the ultra-thin silicon oxide and heavily doped silicon film causes the energy bands on the silicon wafer surface to bend, thereby forming a field passivation effect. The probability of electron tunneling is greatly increased, the contact resistance is reduced, and the open circuit voltage and short-circuit current of the cell are improved, thereby improving the cell conversion efficiency.

[0005] As the conversion efficiency of TOPCon cells in mass production continues to increase, the requirements for the passivation quality of their contact layers are also becoming increasingly stringent. In particular, the development of alkaline polishing can improve the cell's opening voltage. However, due to the smoother interface, the film can easily crack during the deposition of doped polysilicon, becoming a process bottleneck. This not only narrows the process window but also significantly affects the passivation quality, which further affects cell efficiency. Existing TOPCon cells also generally suffer from low yields. Summary of the Invention

[0006] The purpose of the present invention is to provide a passivation contact structure laminated film, a preparation method thereof and a TOPCon battery. The preparation method of the present invention can produce higher quality interface passivation, improve battery efficiency and battery production yield.

[0007] The present invention provides a method for preparing a passivation contact structure laminated film, comprising the following steps:

[0008] A) performing oxidation pretreatment on the back side of the silicon wafer to form a pretreated oxide layer;

[0009] B) depositing a tunneling oxide layer on the surface of the pretreated oxide layer by PECVD, wherein the tunneling oxide layer includes n stacked sub-films, the plasma power for depositing the n sub-films increases gradually with deposition time, and the plasma power for depositing the first sub-film on the surface of the pretreated oxide layer is 1 kW to 12 kW; n is an integer ≥ 2;

[0010] C) depositing a doped amorphous silicon layer on the surface of the tunnel oxide layer by PECVD to obtain a laminated film intermediate, wherein the doping concentration of the doped amorphous silicon layer changes gradually with deposition time;

[0011] D) annealing and crystallizing the stacked film intermediate to obtain a passivation contact structure stacked film;

[0012] The annealing temperature is 800-1100° C., and a gradient temperature increase is adopted.

[0013] Preferably, the oxidation pretreatment is wet oxidation or dry oxidation;

[0014] The oxidizing liquid used in the wet oxidation comprises 1 wt% to 40 wt% of H2O2 and 1 wt% to 10 wt% of an alkali, or the oxidizing liquid used in the wet oxidation comprises 5 wt% to 70 wt% of nitric acid;

[0015] The oxidizing gas used in the dry oxidation is oxygen and / or ozone.

[0016] Preferably, in the step B), the plasma power for depositing the first sub-film is 1kW to 12kW, and the deposition thickness is 0.01nm to 0.5nm;

[0017] The plasma power for depositing the nth sub-film is 12kW to 20kW, and the deposition thickness is 0.01nm to 1nm.

[0018] Preferably, in step B), the gas used for tunnel oxide layer deposition includes raw gas and process optimization gas, the raw gas is one or more of N2O, O2 and CO2, with a flow rate of 0.5slm to 15slm, the process optimization gas is an inert gas, and the RF on-off ratio is 1:50 to 1:300.

[0019] Preferably, the doped amorphous silicon layer includes a doping layer A, a doping layer B and a doping layer C;

[0020] When depositing the doping layer A, the flow rate of the doping source gas is 100 sccm to 600 sccm, and the plasma power is 4 kW to 10 kW;

[0021] When depositing the doping layer B, the flow rate of the doping source gas is 500 sccm to 1000 sccm, and the plasma power is 4 kW to 20 kW;

[0022] When depositing the doping layer C, the flow rate of the doping source gas is 600 sccm to 2000 sccm, and the plasma power is 4 kW to 40 kW.

[0023] Preferably, the gases used in the deposition process of the doped amorphous silicon layer in step C) include reaction gases and process optimization gases, the reaction gases include hydrogen, silicon source gas and doping source gas, and the process optimization gas is an inert gas; the flow rates of the hydrogen or inert gas are 1000sccm to 15000sccm, respectively, and the flow rate of the silicon source gas is 300sccm to 5000sccm; the reaction pressure is 350Pa to 600Pa; the RF on-off ratio is 1:4 to 1:20; the time for depositing each doping layer is 30s to 3600s; and the reaction temperature is 300°C to 600°C.

[0024] Preferably, the annealing crystallization specifically includes:

[0025] The first stage of heating: the furnace temperature is heated to 20℃~40℃ lower than the annealing temperature, and kept warm for 800s~1000s;

[0026] The second stage of heating: heating from 20℃~40℃ lower than the annealing temperature to 10℃~30℃ lower than the annealing temperature, and keeping warm for 300s~600s;

[0027] The third stage of heating: heating from 10°C to 30°C below the annealing temperature to 0°C to 20°C below the annealing temperature, and keeping warm for 600s to 4200s.

[0028] Preferably, after the annealing and crystallization, SiO is deposited on the surface of the doped polysilicon layer. x mask layer;

[0029] Alternatively, after obtaining the stacked film intermediate, SiO is deposited on the surface of the doped amorphous silicon layer. x The mask layer is then annealed and crystallized.

[0030] The present invention provides a passivation contact structure laminated film, which is prepared according to the preparation method described above.

[0031] The present invention provides a TOPCon battery, comprising the above-mentioned passivation contact structure laminated film or the above-mentioned passivation contact structure laminated film.

[0032] The present invention provides a method for preparing a stacked film with a passivation contact structure, comprising the following steps: A) performing oxidation pretreatment on the back side of a silicon wafer to form a pretreated oxide layer; B) depositing a tunneling oxide layer on the surface of the pretreated oxide layer by PECVD, wherein the tunneling oxide layer has n sub-films, the plasma power for depositing the n sub-films increases gradiently with deposition time, and the plasma power of the first sub-film deposited on the surface of the pretreated oxide layer is 1kW to 12kW; n is an integer ≥ 2; C) depositing a doped amorphous silicon layer on the surface of the tunneling oxide layer by PECVD to obtain a stacked film intermediate, wherein the doping concentration of the doped amorphous silicon layer changes gradiently with deposition time; D) annealing and crystallizing the stacked film intermediate to obtain a stacked film with a passivation contact structure; the annealing temperature is 800 to 1100°C, and gradient heating is adopted. The present invention first improves the uniformity of the tunnel oxide layer through pre-oxidation treatment, and then stacks and deposits the tunnel oxide layer with multiple sub-films, which can not only effectively reduce substrate damage and accurately control the thickness of the oxide layer, but also can regulate the process power to optimize the density of the oxide layer, thereby obtaining a dense and ultra-thin oxide layer, and improving the chemical passivation and precision of the tunnel oxide layer; then, by stacking and depositing multiple doped layers to replace the intrinsic Poly layer, the film explosion phenomenon caused by hydrogen overflow during annealing of the intrinsic Poly layer is avoided; finally, by adopting a gradient heating process during the annealing treatment, the consistency of the silicon wafer temperature at different workstations is effectively balanced, the intra-wafer / inter-wafer crystallization difference caused by insufficient annealing temperature at each workstation is reduced, and the mass production yield is improved. DETAILED DESCRIPTION

[0033] The present invention provides a method for preparing a passivation contact structure laminate film, comprising the following steps:

[0034] A) performing oxidation pretreatment on the back side of the silicon wafer to form a pretreated oxide layer;

[0035] B) depositing a tunneling oxide layer on the surface of the pretreated oxide layer by PECVD, wherein the tunneling oxide layer has n sub-films, the plasma power for depositing the n sub-films increases gradually with deposition time, and the plasma power for depositing the first sub-film on the surface of the pretreated oxide layer is 1 kW to 12 kW; n is an integer ≥ 2;

[0036] C) depositing a doped amorphous silicon layer on the surface of the tunnel oxide layer by PECVD to obtain a laminated film intermediate, wherein the doping concentration of the doped amorphous silicon layer changes gradually with deposition time;

[0037] D) annealing and crystallizing the stacked film intermediate to obtain a passivation contact structure stacked film;

[0038] The annealing temperature is 800-1100° C., and a gradient temperature increase is adopted.

[0039] In the present invention, the silicon wafer is a silicon wafer after the front side is morphologically etched, preferably a silicon wafer after the front side is textured, more preferably a silicon wafer with a textured surface on the front side and the textured surface is doped; the silicon wafer with a textured surface on the front side and the textured surface is doped is preferably prepared according to the following steps: the front side of the silicon wafer raw material is textured, and then a PN junction is formed by doping, and then the back side is chain cleaned and alkaline polished to obtain a silicon wafer with a textured surface on the front side and the textured surface is doped.

[0040] In the present invention, the oxidation pretreatment is a method for forming an oxide layer well known to those skilled in the art. In the present invention, wet oxidation or dry oxidation can be used.

[0041] In the present invention, the wet oxidation is to perform oxidation pretreatment on the back side of the silicon wafer using an oxidation solution to form an oxide layer.

[0042] The oxidizing liquid is an aqueous solution containing 1wt% to 40wt% of H2O2 and 1wt% to 10wt% of an alkali, or the oxidizing liquid is a nitric acid solution containing 5wt% to 70wt%.

[0043] In the present invention, the mass fraction of H2O2 is preferably 1wt% to 40wt%, more preferably 1wt% to 5wt% or 5wt% to 40wt%; the alkali is preferably sodium hydroxide and / or potassium hydroxide, and the mass fraction of the alkali is preferably 1wt% to 10wt%, more preferably 5wt% to 10wt%, and preferably 8wt% to 10wt%; the mass fraction of nitric acid is preferably 5wt% to 90wt%, more preferably 10wt% to 70wt%, further preferably 30wt% to 68wt%, and most preferably 50wt% to 68wt%.

[0044] When the oxidizing liquid is an aqueous solution containing H2O2 and an alkali, the temperature of the wet oxidation is preferably 40°C to 80°C, more preferably 50°C to 80°C; when the oxidizing liquid is a nitric acid solution, the temperature of the wet oxidation is preferably 40°C to 95°C; the time of the wet oxidation is preferably 10s to 400s, more preferably 50s to 300s, more preferably 100s to 300s, and most preferably 150s to 250s;

[0045] In the present invention, after the wet oxidation, hydrochloric acid solution is preferably used for cleaning; the mass concentration of the hydrochloric acid solution is preferably 1% to 10%, more preferably 2% to 8%; the cleaning is preferably carried out at room temperature; the cleaning time is preferably 10s to 400s, more preferably 50s to 300s, more preferably 100s to 250s, and most preferably 120s to 200s.

[0046] In the present invention, the dry oxidation is to use oxygen and / or ozone as reaction gas to perform chemical vapor deposition on the back side of the silicon wafer to form a pre-treated oxide layer.

[0047] In the present invention, the flow rate of oxygen and / or ozone in the dry oxidation is preferably 1000sccm~15000sccm, more preferably 5000sccm~10000sccm; the pressure of the dry oxidation is preferably 50Pa~350Pa, more preferably 100Pa~300Pa; the temperature of the dry oxidation is preferably 300℃~600℃, more preferably 300℃~500℃; the time of the dry oxidation is preferably 10s~100s, more preferably 30s~80s; the thickness of the pre-oxidation layer is preferably 0.5~1.5nm, more preferably 0.5~1nm.

[0048] After obtaining the pretreated oxide layer, the present invention deposits a tunneling oxide layer on the surface of the pretreated oxide layer through a plasma enhanced chemical vapor deposition method (PECVD), wherein the tunneling oxide layer includes n sub-films, and the plasma power for depositing the n sub-films increases gradually with the deposition time, and the plasma power of the first sub-film deposited on the surface of the pretreated oxide layer is 1kW to 12kW; n is an integer ≥2.

[0049] In the present invention, during the deposition of the tunnel oxide layer, the gases used include feed gas and process optimization gas; the feed gas used is preferably one or more of N2O, O2, and CO2; the volume ratio of the process optimization gas to the feed gas is preferably 5:1 to 30:1, more preferably 5:1 to 20:1, and even more preferably 5:1 to 10:1; the process optimization gas does not participate in the reaction, but can assist in ignition and act like a catalyst. The process optimization gas can be any process optimization gas known to those skilled in the art without particular limitation, and in the present invention, argon is preferably used. The flow rate of the feed gas is preferably 0.5 slm to 15 slm, more preferably 1 slm to 10 slm; the RF on-off ratio is preferably 1:50 to 1:300, more preferably 1:80 to 1:200, and even more preferably 1:100 to 1:150. In the present invention, the tunnel oxide layer includes n sub-membranes, and the types, flow rates, and RF on-off ratios of the feed gas and process optimization gas used for the n sub-membranes can be the same or different, as long as they are within the above requirements.

[0050] In the present invention, the number n of sub-films is preferably an integer ≥ 2. The plasma power for depositing the first sub-film, i.e., the sub-film in direct contact with the pre-treated oxide layer, is the lowest, and the plasma power for depositing the remaining sub-films can be increased or converged according to actual process requirements. Compared to the traditional method of using a direct high-power scheme to bombard the silicon surface for tunneling oxide deposition, which causes significant damage to the lattice structure and morphology of the silicon liner, the present invention first deposits the tunneling oxide layer at low power and then increases the power gradient, which can improve the quality of the tunneling oxide layer. In addition, the number of tunneling oxide sub-films can be adjusted according to the requirements of different process routes.

[0051] Preferably, the plasma power for depositing the first sub-film is preferably 1kW~12kW, more preferably 4~12kW, and even more preferably 4~10kW; the deposition thickness is preferably 0.01nm~0.5nm, more preferably 0.1~0.4nm; the plasma power for depositing the nth sub-film is preferably 12kW~20kW, more preferably 15kW~19kW, and the deposition thickness is preferably 0.01nm~1nm, more preferably 0.1~0.8nm.

[0052] Specifically, in one embodiment of the present invention, the number n of sub-films is 3, that is, the tunneling oxide layer includes a first sub-film, a second sub-film and a third sub-film in sequence; the plasma power for depositing the first sub-film is preferably 1kW~12kW, more preferably 4kW~12kW, more preferably 4kW~10kW, and most preferably 6kW~8kW; the thickness of the first sub-film is preferably 0.01nm~0.5nm, more preferably 0.2nm~0.4nm, and more preferably 0.3nm; the plasma power for depositing the second sub-film is preferably 8kW~16kW, more preferably 10kW~14kW, and more preferably 12kW~14kW; the thickness of the second sub-film is preferably 0.5nm~1nm, more preferably 0.6nm~0.8nm; the plasma power for depositing the third sub-film is preferably 12kW~20kW, more preferably 12kW~16kW, and more preferably 12kW~14kW; the thickness of the third sub-film is preferably 0.01~1nm, more preferably 0.01~0.5nm.

[0053] After forming the tunnel oxide layer, the present invention introduces a doping source gas through a PECVD method to deposit a doped amorphous silicon layer on the surface of the tunnel oxide layer, thereby obtaining a laminated film intermediate. The doping concentration of the doped amorphous silicon layer varies gradiently with deposition time, forming multiple doped layers with varying doping concentrations. The present invention utilizes a gradient doping deposition method to flexibly control the doping profile, meeting the doping profile and concentration requirements of high-efficiency batteries. It also addresses the bottleneck of film explosion in the process. Gradient doping reduces unsaturated and unstable bonds at the interface, as well as the potential H content. This improves the uniformity and doping concentration of the doped layer and meets the requirements of high-concentration doping gases.

[0054] In the present invention, the gas used for depositing the doped amorphous silicon layer includes a reaction gas and a process optimization gas, wherein the reaction gas preferably includes hydrogen, a silicon source gas and a doping source gas, and the process optimization gas is an inert gas, preferably argon in the present invention; the flow rates of the hydrogen and inert gases are preferably 1000 to 15000 sccm, more preferably 3000 to 12000 sccm, more preferably 5000 to 10000 sccm, and most preferably 8000 sccm; the flow rate of the silicon source gas is preferably 300 to 5000 sccm, more preferably 500 to 3000 sccm, more preferably 800 to 2000 sccm, and most preferably 1000 to 1500 sccm; the doped amorphous silicon layer is deposited The pressure is preferably 350-600 Pa, more preferably 350-550 Pa, more preferably 400-500 Pa, and most preferably 450 Pa; the RF on-off ratio of the deposited doped amorphous silicon layer is preferably 1:4-1:20, more preferably 1:8-1:20, more preferably 1:10-1:20, and most preferably 1:15-1:20; the time for depositing each doped layer is preferably 30-3600 s, more preferably 50-3000 s, more preferably 100-2000 s, more preferably 100-1000 s, and most preferably 100-600 s; the temperature for depositing the doped amorphous silicon layer is preferably 300°C-600°C, more preferably 350°C-550°C, and more preferably 400°C-500°C.

[0055] The doped amorphous silicon layer contains at least two doping layers with different doping concentrations; the doping concentration of the doping layer can be achieved by changing one or more of the concentration of the doping source in the doping source gas, the flow rate of the doping source gas and the power during deposition; specifically, in one embodiment of the present invention, gradient doping is achieved by changing the flow rate of the doping source gas.

[0056] In the present invention, the doping source gas includes a doping source and a carrier gas; the doping source can be any doping source well known to those skilled in the art and is not particularly limited. In the present invention, it is preferably a phosphorus source or a boron source, the boron source is preferably boron trichloride and / or boron tribromide, and the phosphorus source is preferably phosphorus oxychloride; the carrier gas can be any carrier gas well known to those skilled in the art and is not particularly limited. In the present invention, it is preferably an inert gas such as argon; the volume concentration of the doping source in the doping source gas is preferably 5% to 10%, more preferably 5% to 8%.

[0057] In the present invention, the doped amorphous silicon layer contains at least two doping layers with different doping concentrations, wherein the flow rate of the doping source gas during the deposition of the low-concentration doping layer is preferably 100-1000scm, more preferably 100-800scm, more preferably 100-600scm, more preferably 200-400scm; the plasma power during the deposition of the low-concentration doping layer is preferably 4-20kW, more preferably 4-15kW, more preferably 4-10kW, and most preferably 6-10kW; the two amorphous silicon layers are preferably deposited at a low concentration of 100-1000scm, more preferably 100-800scm, more preferably 100-600scm, and most preferably 200-400scm; the plasma power during the deposition of the low-concentration doping layer is preferably 4-20kW, more preferably 4-15kW, more preferably 4-10kW, and most preferably 6-10kW; The flow rate of the doping source gas during the deposition of a high-concentration doping layer among doping layers with the same doping concentration is preferably 600-2000scm, more preferably 600-1500scm, even more preferably 600-1200scm, even more preferably 600-1000scm, and most preferably 600-800scm; the plasma power during the deposition of the high-concentration doping layer is preferably 4-40kW, more preferably 6-30kW, even more preferably 8-20kW, even more preferably 10-15kW, and most preferably 10-12kW.

[0058] In the present invention, the number of doping layers in the multi-layer doping layer is greater than or equal to 2, and the specific number of layers can be enhanced and adjusted according to the requirements of different process routes. In the present invention, the number of doping layers is preferably 2 to 5 layers, more preferably 2 to 4 layers, and even more preferably 3 layers. Specifically, in one embodiment of the present invention, the stacked deposited multi-layer doping layer includes at least a deposited doping layer A, a deposited doping layer B, and a deposited doping layer C.

[0059] When depositing the doping layer A, the flow rate of the doping source gas is preferably 100-600 sccm, more preferably 100-400 sccm, and more preferably 200-300 sccm; the plasma power for depositing the doping layer A is preferably 4-10 kW, more preferably 4-8 kW, and more preferably 6-8 kW; the thickness of the doping layer A is preferably 1-20 nm, more preferably 5-15 nm, more preferably 8-12 nm, and most preferably 10 nm; when depositing the doping layer B, the flow rate of the doping source gas is preferably 500-1000 sccm, more preferably 500-800 sccm, and more preferably 600-700 sccm;

[0060] The plasma power for depositing the doping layer B is preferably 4-20 kW, more preferably 6-15 kW, more preferably 6-12 kW, and most preferably 8-10 kW; the thickness of the doping layer B is preferably 10-200 nm, more preferably 30-150 nm, more preferably 50-100 nm, and most preferably 80 nm; the flow rate of the doping source gas for depositing the doping layer C is preferably 600-2000 sccm, more preferably 600-1500 sccm, more preferably 600-1200 sccm, more preferably 600-1000 sccm, and most preferably 800-1000 sccm;

[0061] The plasma power for depositing the doped layer C is preferably 4 to 40 kW, more preferably 6 to 35 kW, more preferably 8 to 30 kW, more preferably 8 to 25 kW, more preferably 10 to 20 kW, more preferably 10 to 15 kW, and most preferably 10 to 12 kW; the thickness of the doped layer C is preferably 1 to 80 nm, more preferably 5 to 60 nm, more preferably 20 to 50 nm, and most preferably 30 to 40 nm.

[0062] The present invention has no special restrictions on the order of doping layers with different doping concentrations in the doped amorphous silicon layer. The low-concentration doping layer of two doping layers with different doping concentrations can be deposited first, or the high-concentration doping layer of two doping layers with different doping concentrations can be deposited first. When the doped amorphous silicon layer is multi-layer, the doping layers can be deposited in the order of gradually increasing doping concentrations, or in the order of gradually decreasing doping concentrations. The deposition can also be performed in a non-increasing or decreasing order of doping concentrations. There are no special restrictions and it can be adjusted according to the actual process route.

[0063] After obtaining the laminated intermediate, the present invention performs annealing and crystallization on the laminated film intermediate to obtain a passivated contact structure laminated film; the annealing utilizes a gradient temperature ramp. Using a gradient temperature ramp during the annealing and crystallization process effectively balances the temperature consistency of the silicon wafer and the substrate at different stations in the quartz boat, reducing intra-wafer and / or inter-wafer variations in crystallization caused by uneven annealing temperatures at each station, thereby achieving higher quality and more uniform passivation effects within and / or between wafers.

[0064] In the present invention, the gradient heating preferably includes 3 to 5 stages, more preferably 3 to 4 stages, and the temperature difference between adjacent heating stages is preferably 5°C to 15°C, more preferably 5°C to 10°C.

[0065] Preferably, in one embodiment of the present invention, the annealing crystallization includes the following four stages:

[0066] The first stage of heating: the furnace temperature is heated to 20℃~40℃ lower than the annealing temperature, and kept warm for 800~1000s;

[0067] The second stage of heating: heating from 20℃~40℃ below the annealing temperature to 10℃~30℃ below the annealing temperature, and keeping warm for 300~600s;

[0068] The third stage of heating: heating from 10℃~30℃ below the annealing temperature to 0℃~20℃ below the annealing temperature, and keeping warm for 600~1200s;

[0069] The fourth stage of heating: heating from 0°C to 20°C below the annealing temperature to the annealing temperature, and keeping the temperature for 1200 to 3000 seconds.

[0070] More preferably,

[0071] The first stage of heating: the furnace temperature is heated to 20℃~30℃ lower than the annealing temperature, and kept warm for 800~1000s;

[0072] The second stage of heating: heating from 20℃ to 30℃ below the annealing temperature to 10℃ to 20℃ below the annealing temperature, and keeping warm for 300 to 600s;

[0073] The third stage of heating: heating from 10℃ to 20℃ below the annealing temperature to 0℃ to 10℃ below the annealing temperature, and keeping warm for 600 to 1200s;

[0074] The fourth stage of heating: heating to the annealing holding temperature at 0℃~10℃ lower than the annealing holding temperature, and keeping the temperature for 1200~3000s;

[0075] Most preferably,

[0076] The first stage of heating: the furnace temperature is heated to 20℃ lower than the annealing temperature and kept warm for 800-1000s;

[0077] Second stage heating: heating from 20℃ below the annealing temperature to 10℃ below the annealing temperature, keeping warm for 300~600s;

[0078] The third stage of heating: heating from 10°C below the annealing temperature to 0°C to 5°C below the annealing temperature, and keeping warm for 600 to 1200 seconds;

[0079] The fourth stage of heating: heating from 0℃ to 5℃ below the annealing temperature to the annealing temperature, and keeping it for 1200 to 3000 seconds;

[0080] Specifically, in another embodiment of the present invention,

[0081] The first stage of heating: the furnace temperature is heated to 20℃ lower than the annealing temperature and kept warm for 800-1000s;

[0082] Second stage heating: heating from 20℃ below the annealing temperature to 10℃ below the annealing temperature, keeping warm for 300~600s;

[0083] The third stage of heating: heating to a temperature 10°C below the annealing temperature and keeping the temperature for 600 to 3000 seconds.

[0084] In the present invention, unless otherwise specified, if the heating start temperature and the holding temperature during the heating process are the same, it means that the stage directly enters the holding program; the heating rate of the first stage heating, the second stage heating, the third stage heating and the fourth stage heating is 10 to 30°C / min; the annealing holding temperature is preferably 880°C to 950°C, more preferably 900°C to 950°C, more preferably 910°C to 940°C, and most preferably 910°C to 920°C.

[0085] The present invention can grow a mask layer on the surface of the doped amorphous silicon layer before annealing and crystallization to protect the polysilicon cell from being damaged during the subsequent wet cleaning process. The method for depositing and growing the silicon oxide mask layer is preferably plasma enhanced chemical vapor deposition (PECVD); the reaction gas for depositing and growing the silicon oxide mask layer includes a silicon source gas and an oxygen source gas; the silicon source gas can be a silicon source gas well known to those skilled in the art, and there is no special limitation, and in the present invention, it is preferably silane; the flow rate of the silicon source gas is preferably 200 to 3000 sccm, more preferably 500 to 2500 sccm, and more preferably 1000 to 2000 sccm; the oxygen source gas can be an oxygen source gas well known to those skilled in the art, and there is no special limitation, and in the present invention, it is preferably N2O; the flow rate of the oxygen source gas is preferably 2000 to 15000 sccm, more preferably 2000 to 10000 sccm, and more preferably 2000 to 5000 sccm; the pressure of the deposited silicon oxide mask layer is preferably The pressure is selected to be 150-400Pa, more preferably 200-300Pa; the power of the deposited growth silicon oxide mask layer is preferably 4-40kW, more preferably 8-30kW, and even more preferably 10-20kW; the RF on-off ratio of the deposited growth silicon oxide mask layer is preferably 1:4-1:320, more preferably 1:20-1:300, even more preferably 1:50-1:200, even more preferably 1:80-1:150, and most preferably 1:100; the temperature of the deposited growth silicon oxide mask layer is preferably 300°C-600°C; the time of the deposited growth silicon oxide mask layer is preferably 30-300s, more preferably 50-200s, even more preferably 50-150s, and most preferably 80-100s; the thickness of the silicon oxide mask layer is preferably 5-15nm, more preferably 8-12nm, and even more preferably 10nm.

[0086] The present invention also allows for the use of dry oxidation to grow a silicon oxide mask layer on the surface of the doped polysilicon layer after annealing and crystallization. Growing the silicon oxide mask layer after annealing can prevent the mask layer from undergoing dual-phase diffusion due to the doped polysilicon layer at the high annealing temperature and / or denaturation of the SiOx film due to the high temperature environment. The dry oxidation process is preferably performed using oxygen and / or ozone combined with a subsequent annealing process. The thickness of the silicon oxide mask layer is preferably 5 to 15 nm, more preferably 8 to 12 nm, and even more preferably 10 nm.

[0087] The present invention also provides a passivation contact structure stacked film prepared by the preparation method described above, comprising a pre-treated oxide layer, a tunneling oxide layer and a doped polysilicon layer arranged on the back of a silicon wafer.

[0088] In the present invention, the thickness of the pre-oxidation layer is preferably 0.5 to 1.5 nm, more preferably 0.5 to 1 nm.

[0089] In the present invention, the thickness of the tunneling oxide layer is preferably 0.5-2.5 nm, more preferably 0.5-1.5 nm; the tunneling oxide layer includes n sub-films, n≥2, preferably, 2≤n≤4, specifically, in one embodiment of the present invention, n is 3.

[0090] In the present invention, the thickness of the doped polysilicon layer is preferably 50 to 300 nm, more preferably 80 to 250 nm, more preferably 100 to 200 nm, more preferably 100 to 150 nm, and most preferably 120 to 140 nm. The doped polysilicon layer includes at least two doping layers with different doping concentrations. In one embodiment of the present invention, the doping layer includes three doping layers with different doping concentrations, and the doping concentrations increase in a gradient.

[0091] In the present invention, a mask layer is preferably further provided on the surface of the doped polysilicon layer; the mask layer is a silicon oxide mask layer; the thickness of the mask layer is preferably 5 to 15 nm, more preferably 8 to 12 nm, and even more preferably 10 nm.

[0092] The present invention also provides a TOPCon battery, comprising a passivation contact structure laminated film prepared by the above preparation method.

[0093] In the present invention, since a localized doped polysilicon layer and an extremely thin Mask (SiOx) film will be formed on the front side of the silicon wafer during the preparation of the doped polysilicon layer and the mask, it is necessary to etch the doped polysilicon wrap-around and the extremely thin mask layer at the front edge to prevent edge leakage and conduction between the front and back electrodes. After etching, cleaning is continued to ensure the purity of the subsequently deposited substrate film layer; therefore, after the preparation of the passivation contact structure stacked film is completed, it is preferably also included to remove the mask layer by chain cleaning and to remove the polysilicon wrap-around by trough cleaning.

[0094] In the present invention, the chain cleaning to remove the mask layer is preferably specifically as follows: the mask surface of the silicon wafer having the passivation contact structure stacked film is passed through the chain equipment with the mask surface facing upward, a suitable amount of water film is attached to the surface to protect the polysilicon surface, and the coating surface is faced downward, and passed through a mixed solution of 10% to 80% HF and H2O at a certain speed and then sprayed and dried, in order to destroy the SiOx film layer at the edge of the coating surface and expose the polysilicon structure of the coating surface to the process environment.

[0095] In the present invention, the trough cleaning to remove polysilicon plating is preferably specifically as follows: placing the silicon wafer with the mask layer removed by chain cleaning in a trough equipment fixture, sequentially entering the etching tank, alkaline cleaning tank, pickling tank, slow pulling tank, and finally performing a drying treatment. The solution in the etching tank is preferably an alkaline solution, the alkaline substance in the alkaline solution is preferably an alkali metal hydroxide, more preferably sodium hydroxide and / or potassium hydroxide, the mass concentration of the alkaline substance in the alkaline solution is preferably 1% to 20%, the solution in the etching tank preferably also includes additives, the temperature of the solution in the etching tank is preferably 50°C to 90°C, and the cleaning time in the etching tank is preferably 100 to 800s. The cleaning of the etching tank can remove the doped polysilicon at the edge of the plating surface, thereby avoiding problems such as poor battery appearance and poor passivation effect. After cleaning the etching tank, it is preferably rinsed with deionized water and then cleaned in an alkaline washing tank. The solution in the alkaline washing tank is preferably a hydrogen peroxide solution containing an alkali metal hydroxide, and the alkali metal hydroxide is preferably sodium hydroxide and / or potassium hydroxide. The mass concentration of the alkali metal hydroxide in the hydrogen peroxide solution containing an alkali metal hydroxide is preferably 1% to 10%, and the mass concentration of H2O2 in the hydrogen peroxide solution containing an alkali metal hydroxide is preferably 1% to 40%. The temperature of the solution in the alkaline washing tank is preferably room temperature to 90°C, more preferably 25°C to 90°C. The cleaning time in the alkaline washing tank is preferably 100 to 800s. Cleaning in the alkaline washing tank can remove residual additives in the etching tank and impurities on the surface of the silicon wafer. After the alkali cleaning tank is cleaned, it is preferably rinsed with deionized water and then cleaned in an acid cleaning tank. The solution in the acid cleaning tank is preferably a mixed acid solution, and the mixed acid solution includes HF and HCl. The mass concentration of HF in the mixed acid solution is preferably 1% to 60%, and the mass concentration of HCl in the mixed acid solution is preferably 1% to 20%. The temperature of the solution in the acid cleaning tank is preferably room temperature to 90°C, more preferably 25°C to 90°C. The cleaning time in the acid cleaning tank is preferably 100 to 800s. The acid cleaning tank can neutralize the previous alkali residue and remove the doped polysilicon surface SiO xMasking removes metal impurity ions. After cleaning in the pickling tank, it is preferably rinsed with deionized water before entering the slow pull tank. An appropriate amount of room temperature deionized water is used in the slow pull tank. The robot slowly pulls the flower basket to prevent water marks on the surface of the silicon wafer. The temperature in the slow pull tank is room temperature to 90°C, more preferably 25°C to 90°C, and the time in the slow pull tank is preferably 10 to 200 seconds. The silicon wafer and flower basket are then dried. The drying temperature is preferably 50°C to 100°C, and the drying process is preferably carried out under nitrogen or compressed air. This drying process prevents liquid residue on the silicon wafer and flower basket during unloading, which may affect subsequent processes.

[0096] Compared with the prior art, the method for preparing the passivation contact structure laminated film provided by the present invention has the following advantages:

[0097] 1) Can provide higher quality passivation contact film layer;

[0098] 2) Reducing film burst anomalies in the original process structure - The development of alkaline polishing in the morphology of passivated contact cells has the advantage of increasing the cell opening voltage. However, due to the smoother interface, film burst anomalies (after the amorphous silicon growth is completed and the free hydrogen bubbles are enriched and overflow locally, causing local film rupture and destroying the integrity of the original film layer) gradually become a process bottleneck, resulting in a narrow process window. The introduction of the gradient doping layer in this invention, especially the light doping of the first layer, can cleverly solve this bottleneck without adding additional steps.

[0099] 3) Improved mass production stability - Avoiding process defects caused by a thick natural oxide layer due to abnormal workshop environment (such as equipment working environment humidity > 50%), which may occur when silicon wafers are left waiting for more than 2 hours, thereby improving process stability;

[0100] 4) Reduce PE route jam marks - by using different thickness ratios of wet chemical / PE tunneling, the thickness of the chemical tunneling layer is increased, the PE tunneling growth time is reduced, and the local tunneling thickness abnormality caused by abnormal discharge in the PE route jam area is reduced;

[0101] 5) Improve the density of the tunneling layer - remove HF in the wet process to eliminate the probability of fluoride ions remaining in the silicon substrate and increase the integrity of the silicon oxide film process growth environment;

[0102] 6) Improve the uniformity of the tunneling layer - reduce the PE tunneling superposition growth caused by uneven growth of the natural oxide layer on the entire surface of the silicon substrate in a non-process environment after the back etch is completed;

[0103] 7) Improve chemical passivation of the tunneling layer - multiple layers of tunneling oxide layers are prepared at different powers, which not only ensures that the oxide layer does not cause damage to the silicon substrate during the initial low-power preparation, but also ensures the density of the tunneling layer during subsequent high-power preparation;

[0104] 8) Improve the precision of the tunneling layer - Gradient power stacking can effectively reduce substrate damage, accurately control the thickness of the oxide layer, and can regulate the process power to optimize the density of the oxide layer, thereby obtaining a dense and ultra-thin oxide layer;

[0105] 9) Reduce back-end EL / PL defects - Eliminate the intrinsic Poly layer and replace it with a low-doped layer to avoid the film explosion caused by hydrogen overflow during annealing of the intrinsic Poly;

[0106] 10) Improve the passivation effect of polysilicon layer - Use high pressure to prepare doped Poly, which can not only produce Poly films with better uniformity, but also match various concentrations of doping gases;

[0107] 11) Improve mass production yield - Gradient heating can effectively balance the temperature consistency of silicon wafers and substrates at different stations in the quartz boat, reducing the intra-wafer / inter-wafer crystallization differences caused by insufficient annealing temperature at each station;

[0108] 12) Improve the hydrophilicity of the mask layer - a mask layer with good hydrophilicity can be prepared, avoiding the existing scheme of high-temperature doping layer doping source two-phase diffusion leading to high-temperature denaturation of the original mask layer, resulting in poor hydrophilicity, resulting in various process defects and increased acid consumption caused by the lack of water film.

[0109] To further illustrate the present invention, a passivation contact structure laminated film, a preparation method thereof, and a TOPCon battery provided by the present invention are described in detail below in conjunction with examples, but they should not be construed as limiting the scope of protection of the present invention.

[0110] Example 1

[0111] 1.1 Texturing: Place the above-mentioned monocrystalline silicon cell into an alkaline solution with a mass concentration of 1-5% NaOH, and perform texturing treatment at 82° C. for 420 seconds to form a surface morphology with dense pyramids on its surface.

[0112] 1.2 Boron diffusion: Place the velvet sheet in a high-temperature quartz tube, introduce boron trichloride as a boron source and diffuse it at 1020°C to form a PN junction.

[0113] 1.3BSG+alkali polishing: Enter the chain cleaning equipment to remove the BSG on the back, and then place it in the tank machine to react with the liquid medicine to form a uniformly clean back surface.

[0114] After the silicon wafer morphology etching is completed, the cell is placed in a 5wt% H2O2 / 10wt% NaOH / H2O mixed solution for oxidation to form a 0.5nm thick pre-treated oxide layer SiOx, the temperature is 550℃, and the time is 180s; then it is wet-cleaned with 1wt%~10wt% HCl solution / without HF at room temperature for 120s, followed by slow pulling and drying to prepare for the subsequent back passivation process.

[0115] 1.4 Back-side stacking tunneling + stacking Poly + mask:

[0116] Overlay tunneling

[0117] Gradient 1: Using a 6 kW power process, a process time of 30 seconds, a process thickness of 0.3 nm, 1 slm N2O as the raw material gas during deposition, 0.2 slm Ar as the process optimization gas, and a RF on-off ratio of 2:200 ms.

[0118] Gradient 2: Using a 12 kW power process, a process time of 30 seconds, a process thickness of 0.5 nm, 1 slm N2O as the raw material gas during deposition, 0.2 slm Ar as the process optimization gas, and a RF on-off ratio of 2:200 ms.

[0119] Poly

[0120] Gradient 1: Deposition of doped layer, the reaction gases are silane, hydrogen and PH3, the silane flow rate is 1000sccm, the hydrogen flow rate is 8000sccm, 8% PH3, the flow rate is 200sccm; the pressure is 450Pa, the plasma power is 6kW, the RF on-off ratio is 1:20, the deposition time is 130s, the reaction temperature is 400℃, and the film thickness is 10nm.

[0121] Gradient 2: Deposition of doping layer, the reaction gases are silane, hydrogen and PH3, the silane flow rate is 1000sccm, the hydrogen flow rate is 8000sccm, 8% PH3, the flow rate is 600sccm; the pressure is 450Pa, the plasma power is 10kw, the RF on-off ratio is 1:20, the deposition time is 600s, the reaction temperature is 400℃, and the film thickness is 80nm.

[0122] Gradient three: Deposition of doping layer, the reaction gases are silane, hydrogen and PH3, the silane flow rate is 1000sccm, the hydrogen flow rate is 8000sccm, 8% PH3, the flow rate is 800sccm; the pressure is 450Pa, the plasma power is 12kw, the RF on-off ratio is 1:20, the deposition time is 240s, the reaction temperature is 400℃, and the film thickness is 30nm.

[0123] mask

[0124] A 10 kW power process was used, the process thickness was 10 nm, the process time was 80 s, the process pressure was 200 Pa, the raw material gas types during deposition were 2 slm N2O, 0.2 slm SiH4, and the RF on-off ratio was 2:200 ms.

[0125] 1.5 step annealing:

[0126] N2 was introduced and the temperature was slowly increased to 890°C at a heating rate of 17°C / min and the holding time was about 300s;

[0127] Slowly increase the temperature to 900℃ at a heating rate of 17℃ / min and keep at this temperature for about 600s;

[0128] The temperature was slowly raised to 910°C at a heating rate of 17°C / min to activate the phosphorus atoms in the poly process deposited film, forming an effective doping time of about 3000s.

[0129] 1.6 Rewind Cleaning (RCA): Remove the winding plating from the annealed cell and then place it in a slot machine to clean the silicon wafer in preparation for the subsequent plating of the front and back passivation films;

[0130] 1.7ALD and SiNx: Placed in related equipment to generate 4nm thick AlOx and 85nm thick SiNx films on the front of the cell;

[0131] 1.8 Back film: Placed in relevant equipment to form a 95nm thick SiNx film on the back of the cell;

[0132] 1.9 Printing and sintering.

[0133] The battery obtained in Example 1 was tested. The test platform electrical probes need to be in electrical contact with the front and back electrodes of the battery. The efficiency test process requires the probe holders with the front and back electrode grid lines to be pressed against the main grid lines of the battery to be tested. The results are as follows:

[0134] Battery efficiency: Eta 25.75%, FF 85%, Voc 722mV, Isc13.88A, Rser 0.0006, Rsh.2100;

[0135] Battery yield: card point print 0.03%, dark film 0.01%.

[0136] Comparative Example 1

[0137] 1.1 Texturing and 1.2 Boron diffusion are both carried out according to the operations in Example 1.

[0138] 1.3BSG+alkali polishing: Enter the chain cleaning equipment to remove the BSG on the back, and then place it in the tank machine to react with the liquid medicine to form a uniformly clean back surface.

[0139] HF ends to prepare for the subsequent back passivation process.

[0140] 1.4 Back-side single-layer tunneling + stacked Poly + mask:

[0141] Single-layer tunneling

[0142] The process adopts 12kw power, 100s process time, 1.2nm process thickness, 1slm N2O raw material gas type during deposition, and 2:200ms RF on-off ratio.

[0143] Poly

[0144] Gradient 1: Deposition of the intrinsic layer, the reaction gases are silane and hydrogen, the silane flow rate is 1000sccm, the hydrogen flow rate is 8000sccm, the pressure is 450Pa, the plasma power is 10kW, the RF on-off ratio is 1:20, the deposition time is 200s, the reaction temperature is 400℃, and the film thickness is 20nm.

[0145] Gradient 2: Deposition of doped layer, the reaction gases are silane, hydrogen and PH3, the silane flow rate is 1000sccm, the hydrogen flow rate is 8000sccm, 8% PH3, the flow rate is 600sccm; the pressure is 450Pa, the plasma power is 12kw, the RF on-off ratio is 1:20, the deposition time is 650s, the reaction temperature is 400℃, and the film thickness is 100nm.

[0146] mask

[0147] A 10 kW power process was used, with a process thickness of 10 nm, a process time of 80 s, a process pressure of 200 Pa, 2 slm N2O and 0.2 slm SiH4 as the raw material gases during deposition, and a RF on-off ratio of 2:200 ms.

[0148] 1.5 Curve annealing:

[0149] N2 was introduced and the temperature was raised to 910°C for about 900s. Phosphorus atoms in the poly film deposited by the process were activated and effective doping lasted for about 3000s.

[0150] 1.6 Rewinding and Cleaning (RCA): The annealed cell is removed from the winding process and then placed in a slot machine to clean the silicon wafer in preparation for the subsequent plating of the front and back passivation films.

[0151] 1.7 ALD&SiNx: Place in related equipment to generate AlOx and SiNx films of a certain thickness on the front of the cell.

[0152] 1.8 Back film: Placed in relevant equipment to form a SiNx film of a certain thickness on the back of the battery cell.

[0153] 1.9 Printing and sintering.

[0154] The battery obtained in Comparative Example 1 was tested and the following results were obtained:

[0155] Battery efficiency: Eta 25.3%, FF84.3%, Voc 715.2mV, Isc13.85A, Rser 0.0007, Rsh.1501, IRev2 0.207;

[0156] Battery yield: card point print 5%-10%, dark film 2%.

[0157] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for preparing a passivation contact structure laminate film, comprising the following steps: A) performing oxidation pretreatment on the back side of the silicon wafer to form a pretreated oxide layer; B) depositing a tunneling oxide layer on the surface of the pretreated oxide layer by PECVD, wherein the tunneling oxide layer includes n stacked sub-films, the plasma power for depositing the n sub-films increases gradually with deposition time, and the plasma power for depositing the first sub-film on the surface of the pretreated oxide layer is 1 kW to 12 kW; n is an integer ≥ 2; C) depositing a doped amorphous silicon layer on the surface of the tunnel oxide layer by PECVD to obtain a laminated film intermediate, wherein the doping concentration of the doped amorphous silicon layer changes gradually with deposition time; D) annealing and crystallizing the stacked film intermediate to obtain a passivation contact structure stacked film; The annealing temperature is 800-1100° C., and a gradient temperature increase is adopted.

2. The preparation method according to claim 1, characterized in that The oxidation pretreatment is wet oxidation or dry oxidation; The oxidizing liquid used in the wet oxidation comprises 1 wt% to 40 wt% of H2O2 and 1 wt% to 10 wt% of an alkali, or the oxidizing liquid used in the wet oxidation comprises 5 wt% to 70 wt% of nitric acid; The oxidizing gas used in the dry oxidation is oxygen and / or ozone.

3. The preparation method according to claim 1, characterized in that In the step B), the plasma power for depositing the first sub-film is 1 kW to 12 kW, and the deposition thickness is 0.01 nm to 0.5 nm; The plasma power for depositing the nth sub-film is 12kW to 20kW, and the deposition thickness is 0.01nm to 1nm.

4. The preparation method according to claim 3, characterized in that In the step B), the gas used for tunnel oxide layer deposition includes raw gas and process optimization gas, the raw gas is one or more of N2O, O2 and CO2, with a flow rate of 0.5slm to 15slm, the process optimization gas is an inert gas, and the RF on-off ratio is 1:50 to 1:

300.

5. The preparation method according to claim 1, characterized in that The doped amorphous silicon layer includes a doping layer A, a doping layer B and a doping layer C; When depositing the doping layer A, the flow rate of the doping source gas is 100 sccm to 600 sccm, and the plasma power is 4 kW to 10 kW; When depositing the doping layer B, the flow rate of the doping source gas is 500 sccm to 1000 sccm, and the plasma power is 4 kW to 20 kW; When depositing the doping layer C, the flow rate of the doping source gas is 600 sccm to 2000 sccm, and the plasma power is 4 kW to 40 kW.

6. The preparation method according to claim 5, characterized in that The gases used in the deposition process of the doped amorphous silicon layer in step C) include reaction gas and process optimization gas, the reaction gas includes hydrogen, silicon source gas and doping source gas, and the process optimization gas is an inert gas; the flow rate of the hydrogen or inert gas is 1000sccm to 15000sccm, respectively, and the flow rate of the silicon source gas is 300sccm to 5000sccm; the reaction pressure is 350Pa to 600Pa; the radio frequency on-off ratio is 1:4 to 1:20; the time for depositing each doping layer is 30s to 3600s; and the reaction temperature is 300°C to 600°C.

7. The preparation method according to claim 1, characterized in that The annealing crystallization specifically includes: The first stage of heating: the furnace body temperature is heated to 20℃~40℃ lower than the annealing temperature, and kept warm for 800s~1000s; The second stage of heating: heating from 20℃~40℃ lower than the annealing temperature to 10℃~30℃ lower than the annealing temperature, and keeping warm for 300s~600s; The third stage of heating: heating from 10°C to 30°C below the annealing temperature to 0°C to 20°C below the annealing temperature, and keeping warm for 600s to 4200s.

8. The preparation method according to claim 1, characterized in that After the annealing and crystallization, SiO is deposited on the surface of the doped polysilicon layer. x mask layer; Alternatively, after obtaining the stacked film intermediate, SiO is deposited on the surface of the doped amorphous silicon layer. x The mask layer is then annealed and crystallized.

9. A passivation contact structure laminated film, prepared according to the preparation method according to any one of claims 1 to 8.

10. A TOPCon battery, characterized in that: The invention comprises a passivation contact structure stacked film prepared by the preparation method of any one of claims 1 to 8 or a passivation contact structure stacked film according to claim 9.