Semiconductor device, computation device, and electronic equipment

Abstract

Provided is a semiconductor device that can retain data to be used for computation for a long period of time. The semiconductor device comprises a computation cell and a drive cell. The computation cell and the drive cell each include first to third transistors, first and second capacitor elements, and a first amplification circuit. A first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplification circuit, and a first terminal of the first capacitor element. A second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplification circuit, and a first terminal of the second capacitor element. The first amplification circuit functions as a buffer circuit that outputs an analog potential. Electric charge is replenished to the first terminal of the second capacitor element by the first amplification circuit on the basis of the electric potential of the first terminal of the first capacitor element, thereby preventing leakage current between the source and the drain of each of the first transistor and the second transistor.

Description

Semiconductor device, arithmetic device and electronic device

[0001] One embodiment of the present invention relates to a semiconductor device, a computing device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There are also attempts to use a computing device that configures an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing device that configures an artificial neural network to adjust the brightness, color tone, etc. of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al. , “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. J. Zhang et al. , “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924. H. Baba et al. ,”Novel analog in-memory compute with > 1 nA current / cell and 143.9 TOPS / W enabled by monolithic normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS technology,” IEEE International Electron Devices Meeting (IEDM), pp. 21.2.1-21.2.4, 2021.

[0008] There are various models of artificial neural networks. For example, a model called a convolutional neural network (CNN) is used in image analysis. CNN is a type of neural network that exhibits excellent performance in the field of image recognition, but the amount of calculation is determined by factors such as the image resolution and the filter size. Specifically, for example, the higher the image resolution, the larger the filter size, or the smaller the stride, the greater the amount of calculation in the CNN, which tends to result in longer processing time by the calculation device. Furthermore, the greater the amount of calculation, the higher the power consumption by the calculation device.

[0009] Furthermore, in a CNN, feature extraction is performed for each of the divided images using the same filter. Therefore, the filter is repeatedly used for each calculation, resulting in frequent read operations of the filter from a memory circuit or the like. Because the power consumption of both the read operation and the data transmission operation of the filter or the like is high, it is desirable for the calculation circuit that performs the calculation of the convolutional neural network to have a configuration called computing-in-memory (CiM) or in-memory computing (iMC), which has a function of retaining the filter value as a multiplier for a long period of time in addition to the calculation function.

[0010] An object of one embodiment of the present invention is to provide an arithmetic circuit with reduced power consumption.An object of one embodiment of the present invention is to provide an arithmetic circuit that can retain data for a long period of time.An object of one embodiment of the present invention is to provide a novel arithmetic circuit.An object of one embodiment of the present invention is to provide an arithmetic device including the above-described arithmetic circuit.An object of one embodiment of the present invention is to provide an electronic device including the above-described arithmetic device.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0012] In the convolution process used in a convolutional neural network, each of the divided images is used as input data and multiplied by the same filter value. Therefore, in one aspect of the present invention, a retention node that retains the same filter value as a potential is required to perform the multiplication with each input data. Furthermore, by inputting a potential corresponding to the input data to the retention node via a capacitive element, the potential of the retention node becomes the sum of the potential of the filter value and the potential corresponding to the input data due to capacitive coupling.

[0013] When an n-channel transistor operates in the subthreshold region, the source-drain current (sometimes called the subthreshold current) is calculated by dividing the gate-source voltage by V ＧＳ As a result, exp[V ＧＳ -V ｔｈ ] is proportional to V ｔｈ is the threshold voltage of the transistor. At this time, the gate potential is set to the potential V Ｆ and the potential V corresponding to the input data ＩＮ The source potential is the sum of V ＧＮＤ When this is done, exp[V ＧＳ -V ｔｈ ] is exp[V Ｆ ]exp[V ＩＮ ]exp[V ＧＮＤ -V ｔｈ ] and the subthreshold current is Ｆ ] and exp[V ＩＮ ].

[0014] As described above, an arithmetic circuit according to one embodiment of the present invention includes a circuit in which one of a pair of electrodes of a capacitor and a gate of a transistor are connected to each other. The connection point is a retention node. Furthermore, since input data is multiplied by the same filter value, the circuit is preferably configured to be able to retain the filter value for a long period of time. For example, two or more switches are preferably provided in series between the retention node and a wiring that transmits the filter value to be written to the retention node. Furthermore, in order to reduce leakage current related to the switches, a potential corresponding to the potential of the retention node is preferably supplied between the switches. Specifically, the configuration preferably functions as, for example, a buffer circuit that outputs an analog potential. This prevents the potential of the retention node from fluctuating due to leakage current through the switches.

[0015] A specific configuration of one embodiment of the present invention will be described below.

[0016] (1) One embodiment of the present invention is a semiconductor device including a first cell and a second cell. The first cell includes first to third transistors, a first capacitor, a second capacitor, and a first amplifier circuit. The second cell includes fourth to sixth transistors, a third capacitor, a fourth capacitor, and a second amplifier circuit.

[0017] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. The second terminal of the second transistor and the first terminal of the third transistor are each electrically connected to a first wiring. The second terminal of the fifth transistor, the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are each electrically connected to a second wiring. Furthermore, the gate of the first transistor, the gate of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are each electrically connected to the third wiring.

[0018] Furthermore, each of the first amplifier circuit and the second amplifier circuit functions as a buffer circuit that outputs an analog potential.

[0019] (2) Alternatively, in one embodiment of the present invention, in the above (1), each of the first to sixth transistors may have an oxide semiconductor in a channel formation region, and each of the transistors included in the first amplifier circuit and the second amplifier circuit may have an oxide semiconductor or silicon in a channel formation region. In particular, the oxide semiconductor preferably contains one or more elements selected from the group consisting of indium, zinc, and an element M.

[0020] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0021] (3) Alternatively, in one embodiment of the present invention, in the above-described (2), the channel length of the switching transistor may be longer than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be longer than the channel width of the switching transistor.

[0022] The switching transistors here refer to the first, second, fourth, and fifth transistors, and the amplification transistors here refer to the third and sixth transistors.

[0023] (4) One embodiment of the present invention is an arithmetic circuit including a first cell and a second cell, and different from the arithmetic circuit of (1). The first cell includes first to third transistors, a seventh transistor, a first capacitor, a second capacitor, and a first amplifier circuit. The second cell includes fifth to sixth transistors, an eighth transistor, a third capacitor, a fourth capacitor, and a second amplifier circuit.

[0024] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. The first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. The second terminal of the second transistor and the first terminal of the seventh transistor are each electrically connected to a first wiring. The second terminal of the sixth transistor, the second terminal of the eighth transistor, the second terminal of the first capacitance element, and the second terminal of the third capacitance element are electrically connected to the second wiring, and the gate of the first transistor, the gate of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are electrically connected to the third wiring.

[0025] Furthermore, each of the first amplifier circuit and the second amplifier circuit functions as a buffer circuit that outputs an analog potential.

[0026] (5) Alternatively, in one embodiment of the present invention, in the above (4), each of the first to eighth transistors may have an oxide semiconductor in a channel formation region, and each of the transistors included in the first amplifier circuit and the second amplifier circuit may have an oxide semiconductor or silicon in a channel formation region. In particular, the oxide semiconductor preferably contains one or more elements selected from indium, zinc, and an element M.

[0027] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0028] (6) Alternatively, in one embodiment of the present invention, in the above-described (5), the channel length of the switching transistor may be longer than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be longer than the channel width of the switching transistor.

[0029] The switching transistors here refer to the first, second, fourth, and fifth transistors, and the amplification transistors here refer to the third and sixth transistors.

[0030] (7) Another embodiment of the present invention is a semiconductor device including a first cell and a second cell, which is different from the semiconductor device described in (1) or (4). The first cell includes first to third transistors, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor. The second cell includes fourth to sixth transistors, an eighth transistor, an eleventh transistor, a twelfth transistor, a third capacitor, and a fourth capacitor.

[0031] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the ninth transistor, the first terminal of the tenth transistor, and the first terminal of the second capacitor. The first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. The first terminal of the fourth transistor is electrically connected to the gate of the fifth transistor, the gate of the eleventh transistor, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the eleventh transistor, the first terminal of the twelfth transistor, and the first terminal of the fourth capacitor. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. The second terminal of the second transistor and the second terminal of the seventh transistor are each electrically connected to a first wiring. The second terminal of the fifth transistor, the second terminal of the eighth transistor, the second terminal of the first capacitance element, and the second terminal of the third capacitance element are electrically connected to the second wiring, and the gate of the first transistor, the gate of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are electrically connected to the third wiring.

[0032] (8) In another embodiment of the present invention, in the above (7), each of the first to eighth transistors may include an oxide semiconductor in a channel formation region, and each of the ninth to twelfth transistors may include an oxide semiconductor or silicon in a channel formation region. In particular, the oxide semiconductor preferably includes one or more elements selected from indium, zinc, and an element M.

[0033] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0034] (9) Alternatively, in one embodiment of the present invention, in the above-described (8), the channel length of the switching transistor may be longer than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be longer than the channel width of the switching transistor.

[0035] Note that the switching transistors here refer to the first, second, fourth, and fifth transistors, and the amplification transistors here refer to the third, sixth, ninth, and twelfth transistors.

[0036] (10) Another embodiment of the present invention is a semiconductor device including a first cell and a second cell, which is different from the semiconductor device described above in (1), (4), and (7). The first cell includes first to third transistors, a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor. The second cell includes fourth to sixth transistors, an eleventh transistor, a twelfth transistor, a third capacitor, and a fourth capacitor.

[0037] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitance element, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the ninth transistor, the first terminal of the tenth transistor, and the first terminal of the second capacitance element, the first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the gate of the eleventh transistor, and the first terminal of the third capacitance element, the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the eleventh transistor, the first terminal of the twelfth transistor, and the first terminal of the fourth capacitance element, the second terminal of the second transistor and the second terminal of the third transistor are each electrically connected to a first wiring, and the second terminal of the fifth transistor, the second terminal of the sixth transistor, the second terminal of the first capacitance element, and the second terminal of the third capacitance element are each electrically connected to a second wiring. The gate of the first transistor, the gate of the second transistor, the gate of the fourth transistor, and the gate of the fifth transistor are each electrically connected to the third wiring.

[0038] (11) Alternatively, in one embodiment of the present invention, in the above (10), each of the first to sixth transistors may include an oxide semiconductor in a channel formation region, and each of the ninth to twelfth transistors may include an oxide semiconductor or silicon in a channel formation region. In particular, the oxide semiconductor preferably includes one or more elements selected from indium, zinc, and an element M.

[0039] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0040] (12) Alternatively, in one embodiment of the present invention, in the above-described (11), the channel length of the switching transistor may be longer than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be longer than the channel width of the switching transistor.

[0041] Note that the switching transistors here refer to the first, second, fourth, and fifth transistors, and the amplification transistors here refer to the third, sixth, ninth, and twelfth transistors.

[0042] (13) Alternatively, in one embodiment of the present invention, in any one of (1) to (12), selected one or more of the first to fourth capacitors may include a first conductive layer and a second conductive layer functioning as a pair of electrodes, and a first insulating layer functioning as a dielectric. In particular, the first conductive layer is preferably provided on a bottom of an opening in the second insulating layer that reaches the third conductive layer and on a side surface of the opening. Furthermore, the first insulating layer is preferably provided on an upper surface of the first conductive layer, a side surface of the opening, and an upper surface of the second insulating layer. Furthermore, the second conductive layer is preferably provided in a region of the first insulating layer that includes the opening.

[0043] (14) Another embodiment of the present invention is an arithmetic device including the arithmetic circuit of (13) and first to fourth drive circuits, wherein the first drive circuit and the fourth drive circuit are electrically connected to a first wiring, the second drive circuit is electrically connected to a second wiring, and the third drive circuit is electrically connected to a third wiring.

[0044] The first drive circuit has a function of generating a first current corresponding to first data and passing it through the first wiring. The second drive circuit has a function of generating a second current corresponding to second data and passing it through the second wiring. The third drive circuit has a function of applying a high-level potential or a low-level potential to the third wiring. The fourth drive circuit has a function of obtaining a third current corresponding to the product of the first data and the second data, generated in the first cell, from the first wiring, calculating a function using a value corresponding to the third current as an input value, and outputting the result of the calculation.

[0045] The amounts of the first to third currents are within the ranges in which the third and sixth transistors operate in their subthreshold regions.

[0046] (15) Another embodiment of the present invention is an electronic device including the arithmetic device according to (14) and a housing.

[0047] In the configuration of the first cell described above in (1), the first terminal of the first capacitance element is a first holding node, and the first terminal of the second capacitance element is a second holding node. The first holding node can hold a filter value as a potential, and can write the filter value when the first transistor and the second transistor are both on, and can hold the filter value when the first transistor and the second transistor are both off.

[0048] Furthermore, when the third transistor is operated in the subthreshold region and the filter value is held at the first hold node, a subthreshold current corresponding to the multiplication result of the input data and the filter value flows through the third transistor by applying a potential corresponding to the input data to the second terminal of the first capacitance element. In this way, the configuration of (1) above allows the multiplication of the filter value and the input data to be performed in one go.

[0049] Furthermore, since the input terminal of the first amplifier circuit is electrically connected to the first hold node, a potential corresponding to the filter value held in the first hold node is input to the input terminal of the first amplifier circuit. Since the first amplifier circuit functions as a buffer circuit that outputs an analog potential, ideally, the output terminal of the first amplifier circuit outputs a potential equal to the potential of the input terminal. As a result, a potential corresponding to the filter value is also applied to the second hold node. Furthermore, when the potential of the second hold node fluctuates due to a malfunction, charge is replenished by the buffer circuit that outputs the analog potential, thereby maintaining the potential of the second hold node. As a result, the voltage between the first terminal and the second terminal of the first transistor becomes 0 V, thereby reducing the leakage current between the source and drain of the first transistor. As a result, a potential corresponding to the filter value of the first cell can be maintained for a long period of time.

[0050] The same applies to the second cell.

[0051] Furthermore, the first amplifier circuit and the second amplifier circuit function as a voltage follower or a source follower as a buffer circuit that outputs an analog potential. In particular, since a source follower has fewer transistors than a voltage follower, the circuit area of ​​the arithmetic circuit can be reduced by each of the first amplifier circuit and the second amplifier circuit functioning as a source follower.

[0052] Furthermore, as described in (4) above, by providing the fourth and eighth transistors, it is possible to prevent drain-induced barrier lowering (DIBL) in the third and sixth transistors, thereby preventing a decrease in the threshold voltages of the third and sixth transistors. Furthermore, as described in (7) above, by providing the fourth and tenth transistors, it is possible to prevent DIBL in the third and ninth transistors, thereby preventing a decrease in the threshold voltages of the third and ninth transistors.

[0053] As described in (2), (5), (8), and (11), by including an oxide semiconductor in the channel formation region of each of the plurality of transistors included in the first cell and the second cell, all of the transistors can be fabricated in the same process, thereby shortening the takt time required for fabricating the arithmetic circuit. Furthermore, in (2), (5), (8), and (11), the first transistor, the second transistor, the fourth transistor, and the fifth transistor each function as a switching transistor. Therefore, by including an oxide semiconductor in the channel formation region of each of these transistors, the off-state current of each of these transistors can be reduced. This allows the potential of the first terminal of each of the first to fourth capacitors to be maintained for a long period of time.

[0054] As shown in (2) and (5) above, by using silicon for the channel formation regions of the transistors included in each of the first and second amplifier circuits, the on-current of those transistors can be increased. This allows the drive speed of the first and second amplifier circuits to be increased, and charge can be replenished more quickly. As shown in (8) above, by using silicon for the channel formation regions of the fifth, sixth, eleventh, and twelfth transistors, the on-current of those transistors can be increased. This allows the source follower included in the configuration of (8) to operate faster, and charge can be replenished more quickly. As shown in (11) above, by using silicon for the channel formation regions of the fourth, fifth, ninth, and tenth transistors, the on-current of those transistors can be increased. This allows the source follower included in the configuration of (11) to operate faster, and charge can be replenished more quickly.

[0055] According to one embodiment of the present invention, an arithmetic circuit with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, an arithmetic circuit capable of retaining data for a long period of time can be provided. Alternatively, according to one embodiment of the present invention, a novel arithmetic circuit can be provided. Alternatively, according to one embodiment of the present invention, an arithmetic device including the above-described arithmetic circuit can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described arithmetic device can be provided.

[0056] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0057] FIG. 1 is a circuit diagram showing an example of the configuration of a arithmetic device including an arithmetic circuit and a drive circuit. FIGS. 2A to 2C are circuit diagrams showing an example of the configuration of a circuit included in the drive circuit. FIGS. 3A to 3D are circuit diagrams showing an example of the configuration of a circuit included in the drive circuit. FIG. 4 is a circuit diagram showing an example of the configuration of a circuit included in the drive circuit. FIGS. 5A to 5C are circuit diagrams showing an example of the configuration of a circuit included in the drive circuit. FIG. 6 is a circuit diagram showing an example of the configuration of a circuit included in the drive circuit. FIG. 7 is a timing chart showing an example of the operation of a arithmetic device. FIGS. 8A to 8C are circuit diagrams showing an example of the configuration of a arithmetic circuit. FIG. 9 is a circuit diagram showing an example of the configuration of a arithmetic circuit. FIGS. 10A and 10B are circuit diagrams showing an example of the configuration of a arithmetic circuit. FIG. 11 is a circuit diagram showing an example of the configuration of a arithmetic circuit. FIG. 12 is a schematic plan view showing an example of the configuration of a arithmetic circuit. FIG. 13 is a schematic plan view showing an example of the configuration of a arithmetic circuit. FIG. 14 is a schematic plan view showing an example of the configuration of a arithmetic circuit. FIG. 15 is a circuit diagram showing an example of the configuration of a arithmetic device including an arithmetic circuit and a drive circuit. FIG. 16 is a circuit diagram showing an example of the configuration of a arithmetic device including an arithmetic circuit and a drive circuit. FIG. 17 is a circuit diagram showing an example of the configuration of a circuit included in the drive circuit. FIG. 18 is a circuit diagram showing an example of the configuration of a circuit included in the drive circuit. FIG. 19 is a timing chart showing an example of the operation of a circuit included in the drive circuit. FIG. 20 is a diagram showing an example of a convolutional neural network. FIG. 21 is a diagram explaining an example of convolution processing. FIG. 22 is a diagram explaining an example of convolution processing. FIG. 23 is a block diagram showing an example of the operation of convolution processing in a arithmetic device. FIG. 24 is a block diagram showing an example of the operation of convolution processing in a arithmetic device. FIGS. 25A and 25B are diagrams explaining an example of pooling processing. FIG. 26 is a schematic perspective view showing an example of the configuration of a arithmetic device. FIG. 27 is a block diagram showing an example of the configuration of a arithmetic device. FIG. 28 is a schematic cross-sectional view showing an example of the configuration of a arithmetic device. FIGS. 29A and 29B are schematic cross-sectional views showing example configurations of transistors. Fig. 30A is a schematic plan view showing an example of the configuration of a transistor, Fig. 30B to Fig. 30D are schematic cross-sectional views showing an example of the configuration of a transistor, and Fig. 31A to Fig. 31C are schematic cross-sectional views showing an example of the configuration of a transistor.FIG. 32 is a cross-sectional view showing an example of the configuration of a computing device. FIG. 33A is a plan view showing an example of the configuration of a transistor, FIGS. 33B and 33C are cross-sectional views showing an example of the configuration of a transistor, and FIG. 33D is a perspective view showing an example of the configuration of a transistor. FIG. 34A is a cross-sectional view showing an example of the configuration of a capacitive element that can be applied to the computing device, and FIG. 34B is a plan view showing an example of the configuration of a capacitive element that can be applied to the computing device. FIG. 35 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 36A to 36D are diagrams showing an example of electronic components. FIGS. 37A and 37B are diagrams showing an example of electronic equipment, and FIG. 37C is a diagram showing an example of a mainframe computer. FIG. 38 is a diagram showing an example of space equipment. FIG. 39 is a diagram showing an example of a storage system that can be applied to a data center. FIGS. 40A and 40B are circuit diagrams showing the circuit configuration of a computing circuit used in a simulation according to the examples. FIGS. 41A to 41C are graphs showing the retention characteristics of the computing circuit obtained by the simulation according to the examples. FIG. 42 is a graph showing multiplication characteristics of an arithmetic circuit by simulation according to an example. FIG. 43 is a graph showing multiplication characteristics of an arithmetic circuit according to an example. FIG. 44 is a graph showing retention characteristics of an arithmetic circuit according to an example. FIG. 45A is a photograph of a die including a semiconductor device according to an example. FIG. 45B is a cross-sectional photograph of a semiconductor device. FIG. 46 is a block diagram showing an example configuration of a semiconductor device according to an example. FIGS. 47A and 47B are circuit diagrams showing an example configuration of a circuit included in a semiconductor device according to an example. FIGS. 48A and 48B are circuit diagrams showing an example configuration of a circuit included in a semiconductor device according to an example. FIG. 49 is a circuit diagram showing an example configuration of a circuit included in a semiconductor device according to an example. FIG. 50A is a graph showing input / output characteristics of a DAC according to an example. FIG. 50B is a graph showing input / output characteristics of a circuit according to an example. FIG. 51 is a graph showing input / output characteristics of a SAR ADC according to an example. FIG. 52 is a graph showing multiplication characteristics of an arithmetic cell according to an example. FIG. 53A is a graph showing the relationship between the expected value of the current, which is the multiplication result of the arithmetic cell, and the difference between the expected value and the actual measured value, according to an example.FIG. 53B is a graph showing the relationship between the expected value of current, which is the multiplication result of the arithmetic cell, and the actual measured value, according to an example. FIG. 54 is a histogram showing the distribution of the difference between the expected value and the actual measured value of current, which is the multiplication result of the arithmetic cell. FIG. 55 is a graph showing the range of variation in current, which is the multiplication result of the arithmetic cell, according to an example. FIG. 56A is a graph showing the relationship between the expected value and the actual measured value, which is the calculation result of the semiconductor device, according to an example. FIG. 56B is a histogram showing the distribution of the difference between the actual measured value and the expected value, which is the calculation result of the semiconductor device, according to an example. FIG. 57A is a graph showing the dependence of power consumption during inference and inference accuracy on inference time in a semiconductor device according to an example. FIG. 57B is a graph showing the change in inference accuracy over time according to an example. FIG. 57C is a graph showing the power consumption of a semiconductor device according to an example. FIG. 58 is a graph showing the results of calculation accuracy of a semiconductor device according to an example. 59A1 to 59A7 and 59B1 to 59B6 are circuit diagrams for explaining electrical connections.

[0058] (Additional Notes Related to This Specification) In this specification, etc., a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0059] In this specification, "connection" includes, for example, "electrical connection."

[0060] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0061] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0062] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 59A1 and 59A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases in which a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 59A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0063] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 59A4. Another example of a case where A and B are connected via an insulator is when a transistor gate insulating film or the like is interposed between A and B, as shown in FIG. 59A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0064] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing at which an electrical signal is exchanged or there is no interaction of potential between A and B. An example of this is when, as shown in Figures 59A6 and 59A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 59A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 59A6 and 59A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0065] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0066] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 59B1, 59B2, and 59B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 59B4 and 59B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 59B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0067] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0068] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0069] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0070] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0071] In this specification, a switch refers to a device that can be turned on or off and has the function of controlling whether or not a current flows, or a device that has the function of selecting and switching a path through which a current flows.

[0072] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0073] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0074] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0075] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0076] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain may be referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain may be referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0077] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0078] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0079] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0080] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0081] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0082] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0083] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0084] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0085] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0086] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0087] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0088] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0089] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term such as "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0090] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. To clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally shifted.

[0091] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0092] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0093] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0094] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0095] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0096] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0097] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0098] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0099] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0100] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0101] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0102] Embodiment 1 In this embodiment, an arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0103] <Configuration Example 1 of Arithmetic Device> The arithmetic circuit is a circuit that can hold one multiplier and multiply the multiplier by an input multiplicand. In particular, the arithmetic circuit can hold the multiplier for a long period of time. As a result, the arithmetic circuit can sequentially multiply one multiplier by each of multiple multiplicands by sequentially inputting multiplicands while holding the multiplier.

[0104] As described above, a convolutional neural network, which is a type of artificial neural network, is an example of a case in which one multiplier is multiplied by each of multiple multiplicands. Convolutional neural networks will be described in detail in the second embodiment. In one example, a convolutional neural network multiplies a filter containing a certain feature value by image data. In particular, a convolutional neural network multiplies a feature value of one filter as a multiplier by multiple image data as multiplicands, and therefore, it is preferable to use the above-described arithmetic cell to perform this multiplication.

[0105] In this specification, the multiplier is referred to as the first data, and each of the multiple multiplicands is referred to as the second data. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the multiplier can be referred to as the second data, and each of the multiple multiplicands can be interchangeable as the first data.

[0106] 1 shows an example of a calculation device CDV according to one aspect of the present invention. The calculation device CDV is a calculation device that can multiply first data, which is 0 or a positive number, by second data, which is 0 or a positive number. As shown in FIG. 1, the calculation device CDV includes a calculation circuit CC, a drive circuit WCD, a drive circuit XCD, a drive circuit WSD, and a drive circuit ITS.

[0107] The calculation circuit CC includes, for example, a calculation cell IM and a driving cell IMD. The calculation cell IM includes, for example, transistors M1 to M3, capacitors C1 and C2, and an amplifier circuit SF. The driving cell IMD includes, for example, transistors M1d to M3d, capacitors C1d and C2d, and an amplifier circuit SFd.

[0108] Each of the amplifier circuits SF and SFd is provided with a terminal Sin that functions as an input terminal and a terminal Sout that functions as an output terminal.

[0109] In the operation cell IM, the transistors M1 and M2 each function as a switching transistor, for example, and the transistor M3 functions as a transistor (sometimes called an amplifying transistor) for outputting the multiplication result of the multiplier and the multiplicand, for example.

[0110] In the driver cell IMD, the transistors M1d and M2d each function as a write transistor, for example, and the transistor M3d functions as an amplifier transistor, similar to the transistor M3.

[0111] In the arithmetic circuit CC, the transistors M1, M2, M1d, and M2d, which are switching transistors, may be called write transistors or hold transistors.

[0112] In particular, in the operational circuit CC, unless otherwise specified, when the transistors M1, M2, M1d, and M2d are in an on-state, the saturation region includes the case where they ultimately operate in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors include the case where they are appropriately biased to voltages within the range in which they operate in the linear region. However, one aspect of the present invention is not limited to this. For example, when the transistors M1, M2, M1d, and M2d are in an on-state, one or both of them may operate in the saturation region, or may operate in both the linear region and the saturation region.

[0113] Furthermore, unless otherwise specified, the transistors M3 and M3d in the operational circuit CC are assumed to operate in the subthreshold region (i.e., in the transistor M3 or M3d, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are assumed to be appropriately biased to voltages within the range in which they operate in the subthreshold region. Therefore, the transistors M3 and M3d also operate in such a way that an off-current (sometimes called a leakage current) flows between their source and drain.

[0114] 1, each of the transistors M1 to M3 and the transistors M1d to M3d is preferably an OS transistor, for example. Examples of metal oxides in the channel formation regions of OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from indium, the element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0115] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail in Embodiment 3.

[0116] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider a two-layer oxide layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0117] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0118] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0119] In order to reduce the off-state current of a transistor, it is preferable to use, for example, IGZO as a metal oxide used in a semiconductor layer of the transistor. When the semiconductor layer of the transistor contains IGZO, the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0120] In particular, by using transistors including the oxide in their semiconductor layers as the transistors M1, M2, M1d, and M2d, the off-state current of each of the transistors M1, M2, M1d, and M2d can be extremely small. As described above, the transistors M1 and M2 function as write transistors in the calculation cell IM, and the transistors M1d and M2d function as write transistors in the driver cell IMD. Therefore, it is preferable to use OS transistors with extremely low off-state current for each of the transistors M1, M2, M1d, and M2d.

[0121] Furthermore, for example, by using transistors including the oxide in their semiconductor layers as the transistors M3 and M3d, the subthreshold current can also be reduced, thereby reducing the amount of current flowing between the source and drain of the transistor M3 or the transistor M3d, and thus reducing the power consumption of the computing device CDV.

[0122] For example, when OS transistors are used as the transistors M3 and M3d, the range of subthreshold current per 1 μm of channel width of these transistors is 1.0×10 −８ A (1.0 x 10 −２ μA) or less, 1.0×10 −１２ A (1.0 pA) or less, or 1.0 x 10 −１５ In particular, when the threshold voltage of these transistors is higher than 0 V, the range of the subthreshold current per 1 μm of channel width can be, for example, 1.0×10 −２０ A (10zA) or more 1.0 x 10 −８ A (1.0 x 10 −２ μA) or less, 1.0×10 −２０ A (10zA) or more 1.0 x 10 −１２ A (1.0 pA) or less, or 1.0 x 10 −２０A (10zA) or more 1.0 x 10 −１５ A (1.0 fA) or less can be set. Therefore, by using OS transistors for the transistors M3 and M3d, the range of current that can be output as the multiplication result in the arithmetic circuit CC can be widened. Strictly speaking, within the above range of subthreshold current, the range in which the drain current increases exponentially with respect to the gate-source voltage is the range of current that can be output as the multiplication result in the arithmetic circuit CC.

[0123] For example, if the multiplier and multiplicand are each set to 0 to 64, and the amount of current when the multiplier or multiplicand is 1 is set to 0.03 nA, the range of the output current as the multiplication result that the transistor should ensure is 0 to 3.7 nA, which can be kept within the above-mentioned subthreshold current range.

[0124] Furthermore, each of the transistors M1 to M3 and the transistors M1d to M3d can be a transistor containing silicon in a channel formation region (hereinafter referred to as a Si transistor) other than an OS transistor. Si transistors have a higher on-state current than OS transistors and are therefore suitable for passing a large current.

[0125] In addition to OS transistors and Si transistors, each of the transistors M1 to M3 and the transistors M1d to M3d can be a transistor containing germanium in a channel formation region, a transistor containing a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor containing a carbon nanotube in a channel formation region, or a transistor containing an organic semiconductor in a channel formation region.

[0126] 1, the transistors M1 to M3 and the transistors M1d to M3d are illustrated as n-channel transistors, but they may be changed to p-channel transistors depending on the situation. In this case, the potentials applied to the arithmetic circuit CC may differ from those in the case of n-channel transistors. In this specification, unless otherwise specified, the transistors M1 to M3 and the transistors M1d to M3d are described as n-channel transistors.

[0127] In the operation cell IM, a first terminal of the transistor M1 is connected to the gate of the transistor M3, the terminal Sin of the amplifier circuit SF, and the first terminal of the capacitance element C1, and a second terminal of the transistor M1 is connected to the first terminal of the transistor M2, the terminal Sout of the amplifier circuit SF, and the first terminal of the capacitance element C2. The first terminal of the transistor M3 and the second terminal of the transistor M2 are each connected to a wiring WCL, and the gate of the transistor M1 and the gate of the transistor M2 are each connected to a wiring WSL. The second terminal of the capacitance element C1 is connected to a wiring XCL.

[0128] A second terminal of the capacitance element C2 is connected to the wiring VEG. A second terminal of the transistor M3 is connected to the wiring VEL.

[0129] In addition, in this specification, the connection point between the first terminal of transistor M1, the gate of transistor M3, the first terminal of capacitance element C1, and terminal Sin of amplifier circuit SF is referred to as node N, and the connection point between the second terminal of transistor M1, the first terminal of transistor M2, the first terminal of capacitance element C2, and terminal Sout of amplifier circuit SF is referred to as node Nm.

[0130] In the drive cell IMD, a first terminal of the transistor M1d is connected to a gate of the transistor M3d, a first terminal of the capacitance element C1d, and a terminal Sin of the amplifier circuit SFd, a second terminal of the transistor M1d is connected to a first terminal of the transistor M2d, a first terminal of the capacitance element C2d, and a terminal Sout of the amplifier circuit SFd, and the first terminal of the transistor M3d, the second terminal of the transistor M2d, and the second terminal of the capacitance element C1d are each connected to a wiring XCL, and the gates of the transistor M1d and the transistor M2d are each connected to a wiring WSL.

[0131] A second terminal of the capacitance element C2d is connected to the wiring VEG, and a second terminal of the transistor M3d is connected to the wiring VEL.

[0132] In addition, in this specification, the connection point between the first terminal of transistor M1d, the gate of transistor M3d, the first terminal of capacitance element C1d, and the terminal Sin of amplifier circuit SFd is referred to as node Nd, and the connection point between the second terminal of transistor M1d, the first terminal of transistor M2d, the first terminal of capacitance element C2d, and the terminal Sout of amplifier circuit SFd is referred to as node Nmd.

[0133] Each of the amplifier circuits SF and SFd has a function of outputting a potential from the terminal Sout that is substantially equal to the potential input to the terminal Sin. That is, each of the amplifier circuits SF and SFd functions as a buffer circuit that outputs an analog potential. The buffer circuit that outputs an analog potential can be, for example, a source follower or a voltage follower.

[0134] The drive circuit WCD is connected to the wiring WCL and the wiring IWL. The drive circuit ITS is connected to the wiring IWL and the wiring OL. The drive circuit XCD is connected to the wiring XCL and the wiring IXL. The drive circuit WSD is connected to the wiring WSL.

[0135] For example, the wiring WCL functions as a wiring that supplies a current corresponding to the first data to the operation cell IM. Note that, as will be described in detail later, the current is generated by the drive circuit WCD.

[0136] The wiring XCL functions as a wiring for supplying a current corresponding to the reference data or a current corresponding to the second data to the processing cell IM and the driving cell IMD. As will be described in detail later, each of the currents is generated by a driving circuit XCD. The reference data will also be described later.

[0137] The wiring WSL functions as a wiring for transmitting a selection signal for selecting the computing cell IM to which the first data is to be written. The selection signal is also transmitted to the driving cell IMD. The selection signal is generated by the driving circuit WSD, as will be described in more detail later.

[0138] The wiring VEG functions as a wiring for applying a fixed potential. Specifically, the wiring VEG functions as a wiring for applying the fixed potential to the second terminals of the capacitors C2 and C2d. This allows the potentials of the nodes Nm and Nmd to be maintained when the nodes Nm and Nmd are in a floating state. Note that the fixed potential may be, for example, a low-level potential, a ground potential, or a negative potential.

[0139] For example, the wiring VEL functions as a wiring that applies a fixed potential. Specifically, the wiring VEL functions as a wiring that applies the fixed potential to the second terminals of the transistors M3 and M3d. In particular, the fixed potential is set to a potential within a range in which the transistors M3 and M3d operate in the subthreshold region. Specifically, the fixed potential may be, for example, a low-level potential, a ground potential, a negative potential, or the like. Alternatively, depending on the situation, the fixed potential may be a high-level potential, a positive potential, or the like.

[0140] The driving circuit WCD functions as a driving circuit for writing first data to the computation cell IM. Specifically, for example, the driving circuit WCD has a function of acquiring first data W, which is digital data read from an external circuit such as a memory device or a control circuit, converting the first data W into an analog potential, and outputting the analog potential to the wiring WCL. In FIG. 1 , the first data W is transmitted via the wiring IWL.

[0141] 1, the drive circuit WCD includes, for example, a circuit WCDa and a switch SA. An output terminal of the circuit WCDa is connected to a first terminal of the switch SA, and a second terminal of the switch SA is connected to a wiring WCL. A control terminal of the switch SA is connected to a wiring SWLA.

[0142] The switch SA can be, for example, an electrical switch such as an analog switch or a transistor. In particular, the above-described transistor is preferably used as the electrical switch for the switch SA, and an OS transistor is more preferably used. When an electrical switch is used for the switch SA, a Si transistor or the like can be used as the electrical switch other than an OS transistor. Alternatively, a mechanical switch, for example, can be used for the switch SA.

[0143] In this specification, the switch SA shown in FIG. 1 is assumed to be in an on state when a high-level potential is applied to the control terminal, and in an off state when a low-level potential is applied to the control terminal.

[0144] The wiring SWLA functions as a wiring for transmitting a signal for controlling switching between an on state and an off state of the switch SA. For example, a high-level potential or a low-level potential is supplied to the wiring SWLA.

[0145] For example, the circuit WCDa has a function of converting digital data input to an input terminal into an analog current and outputting the analog current to an output terminal, and therefore preferably includes a digital potential-analog current conversion circuit.

[0146] In the digital potential-analog current conversion circuit, the first data is W as digital data input to the input terminal, and the current output to the output terminal is I Ｗ Then, W and I Ｗ It is preferable that the analog current I output from the circuit WCDa is proportional to the Ｗ is the current within the range in which the transistor M3 operates in the subthreshold region, I Ｗ satisfies the following formula (1.1).

[0147]

[0148] In addition, V ｇ (W) is the potential of the gate of the transistor M3 according to the first data W.

[0149] When writing the first data W to the computation cell IM, the circuit WCDa acquires the first data W, which is digital data, from the outside and converts the first data W into an analog current. After that, a high-level potential is applied to the wiring SWLA to turn on the switch SA. As a result, the analog current I is output as the first data W from the output terminal of the circuit WCDa. Ｗ flows into the wiring WCL.

[0150] As will be described in detail later, the nodes N and Nm of the calculation cell IM are connected to an analog current I Ｗ , and the potential at the output terminal of the circuit WCDa becomes a potential corresponding to the potential at the output terminal of the circuit WCDa. This allows the first data W to be written to the processing cell IM. After the writing is completed, it is preferable to apply a low-level potential to the wiring SWLA to turn off the switch SA. This increases the impedance of the output terminal of the circuit WCDa, making it possible to stop the transmission of the first data W from the output terminal of the circuit WCDa to the wiring WCL and reduce the power consumption of the circuit WCDa.

[0151] The driving circuit XCD functions as a driving circuit for transmitting second data X to the operation cell IM. Specifically, for example, the driving circuit XCD acquires the second data X, which is digital data, from the outside and converts X into an analog current I ＸFurthermore, when the operation cell IM multiplies the first data W by the second data X, the driving circuit XCD converts the analog current I Ｘ has the function of passing the signal to the wiring XCL.

[0152] The driving circuit XCD also has a function of applying a reference current to the line XCL when the first data W is written in the calculation cell IM.

[0153] 1, the driver circuit XCD includes, for example, a circuit XCDa. An input terminal of the circuit XCDa is connected to a wiring IXL, and an output terminal of the circuit XCDa is connected to a wiring XCL.

[0154] For example, the circuit XCDa has a function of converting digital data input to an input terminal into an analog current, and therefore preferably includes a digital potential-analog current conversion circuit.

[0155] As will be described in detail later, when the first data W is written to the computation cell IM, the circuit XCDa acquires reference data as digital data from the input terminal and flows an analog current (sometimes referred to as a reference current) corresponding to the reference data to the wiring XCL connected to the output terminal. ｒ When this is the case, the capacitance element C1 of the processing cell IM has a potential difference V between the potential of the node N1 and the potential of the wiring XCL. Ｗ -V ｒ In this specification, unless otherwise specified, the reference data is described as 1.

[0156] After the first data W is stored in the operation cell IM, the circuit XCDa acquires the second data X, which is digital data, from the input terminal and generates an analog current I Ｘ is passed through the wiring XCL connected to the output terminal. The circuit XCDa generates an analog current I ＸBy passing this current through the wiring XCL, the potential of the node N in the processing cell IM can be varied by capacitive coupling through the capacitive element C1. In particular, the potential of the node N1 varied by the capacitive coupling through the capacitive element C1 is set to a potential within the range in which the transistor M3 operates in the subthreshold region. Similarly, in the driver cell IMD, the potential of the node Nd can be varied by capacitive coupling through the capacitive element C1d. In particular, the potential of the node Nd varied by the capacitive coupling through the capacitive element C1d is set to a potential within the range in which the transistor M3d operates in the subthreshold region.

[0157] That is, the circuit XCDa has a function of acquiring reference data from the wiring IXL while the first data W is being written to the calculation cell IM, and causing a reference current corresponding to the reference data to flow through the wiring XCL, and a function of acquiring second data X from the wiring IXL while the first data W is being held in the calculation cell IM, and causing an analog current I corresponding to X to flow through the wiring XCL. Ｘ and a function of passing the signal through the wiring XCL.

[0158] In the digital potential-analog current conversion circuit of the circuit XCDa, the second data X is input to the input terminal and the current I is output from the output terminal. Ｘ It is preferable that the analog current I output from the circuit XCDa is proportional to the Ｘ is a current within the range in which the transistor M3d operates in the subthreshold region, I Ｘ satisfies the following formula (1.2).

[0159]

[0160] In addition, V ｇｍ (X) is the potential of the gate of the transistor M3d according to the second data X.

[0161] The driver circuit WSD has a function of applying a selection signal to the wiring WSL to turn on the write transistors M1 and M2 when selecting the calculation cell IM to which the first data is to be written. When the first data is not to be written, the driver circuit WSD has a function of applying a non-selection signal to the wiring WSL to turn off the transistors M1 and M2 in the calculation cell IM. In the circuit configuration of FIG. 1, it is preferable that the selection signal be a high-level potential and the non-selection signal be a low-level potential.

[0162] Furthermore, since the wiring WSL is also connected to the driver cell IMD, the driver circuit WSD transmits a select signal or a non-select signal to the driver cell IMD as well as to the processing cell IM. As a result, when a select signal is transmitted to the wiring WSL, the write transistors M1d and M2d of the driver cell IMD are both turned on. Furthermore, when a non-select signal is transmitted to the wiring WSL, the transistors M1d and M2d are both turned off.

[0163] As an example, the drive circuit ITS has the function of acquiring an amount of current flowing through the wiring WCL corresponding to the multiplication of the first data W output by the calculation cell IM and the second data X, calculating an activation function F using the amount of current as an input value as a function system (e.g., a nonlinear function system), and outputting output data Z = F (W × X) which is the result of the calculation.

[0164] The activation function may be a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. In particular, a configuration example of the driver circuit ITS that performs the calculation of the ReLU function will be described later.

[0165] In addition, when it is not necessary for the calculation device CDV to perform the calculation of the activation function by the drive circuit ITS, the drive circuit ITS can obtain a current amount corresponding to the multiplication of the first data W and the second data X, and output the multiplication value Z = WX. Alternatively, when it is not necessary to perform the calculation of the activation function by the drive circuit ITS, the calculation device CDV may be configured not to include the drive circuit ITS.

[0166] 1, the drive circuit ITS includes, for example, a circuit ITSa and a switch SB. A first terminal of the switch SB is connected to a wiring WCL, a second terminal of the switch SB is connected to an input terminal of the circuit ITSa, and a control terminal of the switch SB is connected to a wiring SWLB. An output terminal of the circuit ITSa is connected to a wiring OL.

[0167] For example, a switch applicable to the switch SA can be used as the switch SB. Therefore, the description of the switch SA can be referred to for the switch SB.

[0168] The wiring SWLB functions as a wiring for transmitting a signal for controlling the switching between the on state and the off state of the switch SB. For example, a high-level potential or a low-level potential is supplied to the wiring SWLB.

[0169] For example, the circuit ITSa has a function of performing a functional calculation using a value corresponding to the amount of current input to an input terminal as an input value, and also has a function of converting the result of the calculation into digital data, an analog potential, or an analog current, and outputting the result to an output terminal.

[0170] Next, examples of the configurations of the drive circuits WCD, XCD, and ITS for driving the processing cells IM and the drive cells IMD will be described.

[0171] <<Driver Circuit WCD>> The driver circuit WCD shown in Fig. 1 can have, for example, the configuration shown in Fig. 2A. Note that Fig. 2A also illustrates wiring SWLA, wiring IWL, and wiring WCL to show connections between the driver circuit WCD and peripheral circuits. For convenience, it is assumed that the switch SA is included in the circuit SWCA, and that the circuit SWCA is included in the driver circuit WCD.

[0172] The circuit WCDa has a function of supplying a signal to the wiring WCL in an amount corresponding to the first data W. Note that in the case of the calculation device CDV in FIG. 1 , the signal is a current. Therefore, the circuit WCDa is preferably a digital potential-analog current conversion circuit.

[0173] The circuit WCDa shown in FIG. 2A includes, as an example, a switch SWW. A first terminal of the switch SWW is connected to a second terminal of the switch SA, and the second terminal of the switch SWW is connected to a wiring VINI1. The wiring VINI1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when an initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0174] The switch SWW may be, for example, a switch that can be applied to the switch SA.

[0175] 2A includes a plurality of current sources CS. Ｋ value) (K is an integer of 1 or more) as a current amount. In this case, the circuit WCDa has a function of outputting the first data W of 2 Ｋ The circuit WCDa has, for example, one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (K-1)th bit as a current. Ｋ−１ There are individual ones.

[0176] 2A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to the second terminal of the switch SA of the circuit SWCA. The terminal T2 of one current source CS is connected to the wiring DW[0], and each of the terminals T2 of the two current sources CS is connected to the wiring DW[1]. Ｋ−１ Each of the terminals T2 of the current sources CS is connected to a wiring DW[K-1].

[0177] In particular, the wirings DW[0] to DW[K-1] can be the wiring IWL shown in Fig. 1. That is, the wiring IWL can be a wiring group including the wirings DW[0] to DW[K-1].

[0178] The multiple current sources CS of the circuit WCDa each supply the same constant current I Ｗｕｔ from the terminal T1. In reality, during the manufacturing stage of the arithmetic unit CDV, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS is Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCDa is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0179] The wirings DW[0] to DW[K-1] receive a constant current I from the connected current source CS. Ｗｕｔ This allows the circuit WCDa to pass a current corresponding to the K-bit data transmitted from the wirings DW[0] to DW[K-1] to the wiring WCL. Specifically, for example, when a high-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] supplies a constant current I Ｗｕｔ flows to the second terminal of the switch SA, and when a low level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] flows as follows: ＷｕｔFor example, when a high-level potential is applied to the wiring DW[1], the two current sources CS connected to the wiring DW[1] output a total of 2I Ｗｕｔ When a constant current of 2I flows through the second terminal of the switch SA and a low-level potential is applied to the wiring DW[1], the current source CS connected to the wiring DW[1] has a total of 2I Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[K-1], the constant current of the second Ｋ−１ The current sources CS are a total of 2 Ｋ−１ I Ｗｕｔ When a constant current of 2 flows through the second terminal of the switch SA and a low-level potential is applied to the wiring DW[K-1], the current source CS connected to the wiring DW[K-1] has a total of 2 Ｋ−１ I Ｗｕｔ It does not output a constant current.

[0180] The current flowing from one current source CS connected to the wiring DW[0] corresponds to the value of the 0th bit, the current flowing from two current sources CS connected to the wiring DW[1] corresponds to the value of the 1st bit, and the amount of current flowing from K current sources CS connected to the wiring DW[K-1] corresponds to the value of the (K-1)th bit. Now, consider the circuit WCDa when K is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DW[0] and a low-level potential is applied to the wiring DW[1]. At this time, a constant current I is supplied from the circuit WCDa to the second terminal of the switch SA of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, a constant current of 3I flows from the circuit WCDa to the second terminal of the switch SA of the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, no constant current flows from the circuit WCDa to the second terminal of the switch SA of the circuit SWCA.

[0181] 2A illustrates the circuit WCDa when K is an integer of 3 or more, but when K is 1, it is preferable that the circuit WCDa in FIG. 2A does not have a current source CS connected to the wirings DW[1] to DW[K-1]. When K is 2, it is preferable that the circuit WCDa in FIG. 2A does not have a current source CS connected to the wirings DW[2] to DW[K-1].

[0182] Next, a specific example of the configuration of the current source CS will be described.

[0183] The current source CS1 shown in FIG. 3A is a circuit that can be applied to the current source CS included in the circuit WCDa in FIG. 2A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0184] A first terminal of the transistor Tr1 is connected to the wiring VEH, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal T1, and a gate of the transistor Tr2 is connected to the terminal T2. The terminal T2 is also connected to the wiring DW.

[0185] The wiring DW is any one of the wirings DW[0] to DW[K-1] in FIG. 2A.

[0186] The wiring VEH functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0187] When the fixed potential applied by the wiring VEH is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a subthreshold current (source-drain current) flows between the first terminal and the second terminal of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of the current per 1 μm of channel width is, for example, 1.0×10 −８ A (1.0 x 10 −２ μA) or less, and −１２ A (1.0 pA) or less is more preferable, and 1.0 × 10 −１５ It is more preferable that the current is equal to or less than 1.0 fA. For example, it is more preferable that the current is within a range in which it increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current when operating in the subthreshold region. Note that the current is the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ Corresponds to.

[0188] The transistor Tr2 functions as a switching transistor. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal, the first terminal functions as a drain and the second terminal functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected to each other, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, the subthreshold current flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the subthreshold current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0189] Note that circuits applicable to the current source CS included in the circuit WCDa of FIG. 2A are not limited to the current source CS1 of FIG. 3A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 3B. In the current source CS2 shown in FIG. 3B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0190] Also, for example, although the current source CS1 is configured such that the back gate of the transistor Tr1 is connected to the second terminal, the voltage between the back gate and the second terminal of the transistor Tr2 may be held by a capacitive element. Such a configuration example is shown in FIG. 3C. The current source CS3 shown in FIG. 3C includes a transistor Tr3 and a capacitive element C6 in addition to the transistors Tr1 and Tr2. The current source CS3 is different from the current source CS1 in that a capacitive element C6 is provided between the second terminal and the back gate of the transistor Tr1, and the back gate of the transistor Tr1 is connected to the first terminal of the transistor Tr3. Further, the current source CS3 is configured such that the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. The current source CS3 can make the connection between the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal and the back gate of the transistor Tr1 can be held by the capacitive element C6. That is, by determining the potential applied by the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitive element C6.

[0191] Also, for example, as a circuit applicable to the current source CS included in the circuit WCDa of FIG. 2A, it may be the current source CS4 shown in FIG. 3D. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 3C, the back gate of the transistor Tr2 is connected to the wiring VTHL instead of the second terminal of the transistor Tr2. That is, similar to the current source CS2 of FIG. 3B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0192] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0193] 2A includes the current source CS, and the circuit WCDa can output a current corresponding to the K-bit first data by using any one of the current sources CS1 to CS4 shown in FIGS. 3A to 3D. The amount of the current can be, for example, a current amount flowing between the first terminal and the second terminal within a range in which the transistor M3 operates in the subthreshold region.

[0194] 2B may be used as the circuit WCDa of Fig. 2A. The circuit WCDa of Fig. 2B has a configuration in which the current source CS of Fig. 3A is connected to each of the wirings DW[0] to DW[K-1]. When the channel width of the transistor Tr1[0] is w[0], the channel width of the transistor Tr1[1] is w[1], and the channel width of the transistor Tr1[K-1] is w[K-1], the ratio of the channel widths is w[0]:w[1]:w[K-1]=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCDa shown in FIG. 2B can output a current corresponding to the K-bit first data W, similar to the circuit WCDa in FIG. 2A.

[0195] Note that the transistor Tr1 (including transistors Tr1[0] to Tr1[K-1]), the transistor Tr2 (including transistors Tr2[0] to Tr2[K-1]), and the transistor Tr3 can be, for example, a transistor that can be used for the transistor F1 or the transistor F2. In particular, OS transistors are preferably used for the transistor Tr1 (including transistors Tr1[0] to Tr1[K-1]), the transistor Tr2 (including transistors Tr2[0] to Tr2[K-1]), and the transistor Tr3.

[0196] In particular, the circuits shown in FIGS. 2A and 2B are sometimes called K-bit current ladder type DACs (Digital to Analog Converters), which are a type of digital potential-analog current conversion circuit.

[0197] 2B may be modified to a CMOS (Complementary MOS) circuit configuration including n-channel transistors and p-channel transistors. For example, the circuit WCDa in FIG. 2A may be modified to a circuit configuration shown in FIG. 4.

[0198] The circuit WCDa shown in Figure 4 has a circuit configuration including n-channel transistors and p-channel transistors, and is an example of a configuration of a K-bit current-type ladder DAC. The circuit WCDa has K current sources CS and a current mirror circuit CRM. The current source CS shown in Figure 4 differs from each of the current sources CS1 to CS4 shown in Figures 3A to 3D in terms of connection configuration.

[0199] Next, each current source CS shown in FIG. 4 will be described.

[0200] A first terminal of the transistor Tr1[0] is electrically connected to the wiring VSSL, a second terminal of the transistor Tr1[0] is connected to the first terminal of the transistor Tr2[0], and a gate of the transistor Tr1[0] is connected to the wiring BIS. Also, a gate of the transistor Tr2[0] is connected to the wiring DW[0].

[0201] Similarly, a first terminal of the transistor Tr1[1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[1] is connected to the first terminal of the transistor Tr2[2], and a gate of the transistor Tr1[1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[1] is connected to the wiring DW[1].

[0202] Similarly, a first terminal of the transistor Tr1[K-1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[K-1] is connected to the first terminal of the transistor Tr2[K-1], and a gate of the transistor Tr1[K-1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[K-1] is connected to the wiring DW[K-1].

[0203] Further, second terminals of the transistors Tr2[0] to Tr2[K-1] are connected to a terminal CTi of a current mirror circuit CRM, which will be described later.

[0204] In FIG. 4, the channel widths of the transistors Tr1[0] to Tr1[K-1] can be determined by referring to the description of the transistors Tr1[0] to Tr1[K-1] in FIG. 2B.

[0205] 4, the transistors Tr2[0] to Tr2[K-1] function as transistors capable of adjusting the amount of current flowing between the source and drain of each of the transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS functions as a wiring that applies a fixed potential. Note that the fixed potential may be a high-level potential, a positive potential, or the like. Depending on the situation, the fixed potential may also be a low-level potential, a ground potential, a negative potential, or the like.

[0206] For example, the wiring VSSL functions as a wiring that applies a fixed potential. The fixed potential may be, for example, a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential.

[0207] Each current source CS shown in FIG. 4 has the above-described connection configuration, and therefore functions as a current sink circuit that causes a current to flow from the terminal T1 of the current source CS to the wiring VSSL via the transistor Tr1 and the transistor Tr2.

[0208] Next, the current mirror circuit CRM will be described.

[0209] The current mirror circuit CRM has a terminal CTi that functions as an input terminal and a terminal CTo that functions as an output terminal, and has a function of outputting a current to the terminal CTo that is equal to the amount of current flowing through the terminal CTi, for example.

[0210] The current mirror circuit CRM includes a transistor Tr5, a transistor Tr5m, a transistor Tr6, and a transistor Tr6m.

[0211] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and the wiring CPE. The second terminal of transistor Tr6 is connected to the wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to the wiring VEH.

[0212] For the wiring VEH, reference can be made to the description of the wiring VEH shown in FIG. 2A.

[0213] For example, the wiring CPE functions as a wiring that applies a fixed potential. The fixed potential may be a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential, or the like.

[0214] In the current mirror circuit CRM, the second terminals of the transistors Tr6 and Tr6m are connected such that a potential is applied from the wiring VDDL, and the gates of the transistors Tr6 and Tr6m are connected such that a potential of the terminal CTi is applied. Ideally, therefore, equal amounts of current flow between the source and drain of the transistors Tr6 and Tr6m.

[0215] Furthermore, transistor Tr5 functions as a transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a transistor cascode-connected to transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, this prevents the potential of the first terminal of transistor Tr6 from suddenly fluctuating, thereby stabilizing the operation of the current mirror circuit CRM.

[0216] <<Driver Circuit XCD>> The driver circuit XCD shown in FIG. 1 can have, for example, the configuration shown in FIG. 2C.

[0217] The circuit XCDa has a function of supplying a signal to the wiring XCL in an amount corresponding to the second data X. In the case of the arithmetic unit CDV in FIG. 1, the signal is a current.

[0218] The circuit XCDa shown in FIG. 2C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL, and a second terminal of the switch SWX is connected to the wiring VINI2. The wiring VINI2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINI2 may be equal to the potential applied by the wiring VINI1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0219] The switch SWX may be, for example, a switch that can be applied to the switch SA.

[0220] The circuit configuration of the circuit XCDa in Fig. 2C can be substantially the same as that of the circuit WCDa in Fig. 2A. Specifically, the circuit XCDa has a function of outputting reference data as a current amount and a function of outputting L bits (2 Ｌ and a function of outputting second data X of a value (L is an integer of 1 or more) as a current amount. In this case, the circuit XCDa has a function of outputting second data X of a value (L is an integer of 1 or more) as a current amount. Ｌ The circuit XCDa has one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (L-1)th bit as a current. Ｌ−１ There are individual ones.

[0221] Incidentally, the reference data output as a current by the circuit XCDa can be, for example, information in which the value of the 0th bit is "1" and the values ​​of the 1st and subsequent bits are "0".

[0222] In FIG. 2C, the terminal T2 of one current source CS is connected to the wiring DX[0], and each of the terminals T2 of the two current sources CS is connected to the wiring DX[1]. Ｌ−１ Each of the terminals T2 of the current sources CS is connected to the wiring DX[L-1].

[0223] In particular, the wirings DX[0] to DX[L-1] can be the wiring IXL shown in Fig. 1. That is, the wiring IXL can be a wiring group including the wirings DX[0] to DX[L-1].

[0224] The multiple current sources CS of the circuit XCDa are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX[0] to DX[L-1] are connected to the current source CS and output I Ｘｕｔ This allows the circuit XCDa to pass, to the wiring XCL, an amount of current corresponding to the L-bit data transmitted from the wirings DX[0] to DX[L-1].

[0225] Specifically, consider the circuit XCDa when L is set to 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DX[0] and a low-level potential is applied to the wiring DX[1]. At this time, a constant current I is supplied from the circuit XCDa to the wiring XCL. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, a constant current of 3I flows from the circuit XCDa to the wiring XCL. Ｘｕｔ flows. Also, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, no constant current flows from the circuit XCDa to the wiring XCL. Note that in this specification and the like, this may be rephrased as a current of zero amount flows from the circuit XCDa to the wiring XCL. Also, the current of zero amount, I, output from the circuit XCDa Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ The second data output by the circuit XCDa can be, in particular, the amount of current I Ｘｕｔ can be the reference data output by the circuit XCDa.

[0226] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCDa, the constant current I output from each of the terminals T1 of the multiple current sources CS Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCDa is Ｘｕｔ In this embodiment, the constant current I output from the terminal T1 of each of the plurality of current sources CS included in the circuit WCDa is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0227] 3A to 3D can be applied as the current source CS of the circuit XCDa, similar to the current source CS of the circuit WCDa. In this case, the wiring DW shown in FIGS. 3A to 3D can be replaced with the wiring DX. This allows the circuit XCDa to pass a subthreshold current through the wiring XCL as reference data or L-bit second data.

[0228] 2C can be configured similarly to the circuit WCDa shown in Fig. 2B In this case, in the reference symbols shown in Fig. 2B , the circuit WCDa can be replaced with the circuit XCDa, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], the wiring DW[K-1] with the wiring DX[L-1], the switch SWW with the switch SWX, and the wiring VINI1 with the wiring VINI2.

[0229] 2C can be configured similarly to the circuit WCDa shown in Fig. 4. In this case, in the symbols shown in Fig. 4, the circuit WCDa can be replaced with the circuit XCDa, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], and the wiring DW[K-1] with the wiring DX[L-1].

[0230] <<Driver Circuit WSD>> The driver circuit WSD shown in FIG. 1 has a function of turning on the write transistor included in the computation cell IM by supplying a predetermined signal to the wiring WSL when writing first data W to the computation cell IM. In other words, the driver circuit WSD can function as a write word line for the computation cell IM and the driver cell IMD. For example, the driver circuit WSD can turn on the transistors M1 and M2 included in the computation cell IM and the transistors M1d and M2d included in the driver cell IMD by supplying a high-level potential as a select signal to the wiring WSL. Furthermore, the driver circuit WSD can turn off the transistors M1 and M2 included in the computation cell IM and the transistors M1d and M2d included in the driver cell IMD by supplying a low-level potential as a deselect signal to the wiring WSL. As described above, the driver circuit WSD can select either data writing or data retention in each of the processing cell IM and the driver cell IMD by transmitting a selection signal or a non-selection signal to the wiring WSL.

[0231] <<Drive Circuit ITS>> The drive circuit ITS shown in Fig. 1 can have, for example, the configuration shown in Fig. 5A. Note that Fig. 5A also illustrates wiring SWLB, wiring WCL, and wiring OL to show the connection of the drive circuit ITS with peripheral circuits. For convenience, it is assumed that the switch SB is included in the circuit SWCB, and that the circuit SWCB is included in the drive circuit ITS.

[0232] 5A includes a circuit for calculating an activation function as a function system (e.g., a nonlinear function system) and an analog-to-digital conversion circuit, as described above. In particular, the circuit for calculating the function system preferably has a function of calculating the function system using, as an input value, a value corresponding to the amount of input current, and outputting digital data (voltage) corresponding to the result of the calculation.

[0233] 5A includes, for example, a circuit RL that performs a function-based operation and an analog-to-digital conversion circuit ATDC. The circuit RL also includes, for example, a terminal RTi and a terminal RTo.

[0234] A second terminal of the switch SB is connected to a terminal RTi of the circuit RL via an input terminal of the circuit ITSa. A terminal RTo of the circuit RL is connected to an input terminal of the analog-to-digital conversion circuit ATDC, and an output terminal of the analog-to-digital conversion circuit ATDC is connected to a wiring OL via an output terminal of the circuit ITSa.

[0235] The wiring OL functions as a wiring for outputting the result of the calculation performed in the calculation device CDV as digital data to the outside.

[0236] The circuit RL may be an arithmetic circuit of the above-described function system. The function system may be an activation function used in an artificial neural network model. Examples of the activation function include nonlinear functions such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. The circuit RL may also include a circuit that performs pooling processing instead of an arithmetic circuit of the function system. In the configuration of FIG. 5A, the circuit RL is preferably configured to output a potential from a terminal RTo.

[0237] The circuit RL may also be a current-voltage conversion circuit.

[0238] When the circuit RL is configured as a current-voltage conversion circuit, it is preferable that the circuit RL is configured to generate an analog potential corresponding to the current input to the terminal RTi of the circuit RL from the wiring WCL via the switch SB, and output the analog potential to the terminal RTo of the circuit RL.

[0239] The analog-to-digital converter circuit ATDC preferably converts an analog potential supplied from the terminal RTo of the circuit RL into a digital signal and outputs the digital signal to the wiring OL.

[0240] 5B shows an example of the configuration of the drive circuit ITS when the circuit RL is a current-voltage conversion circuit. The circuit RL shown in FIG. 5B includes, as an example, a load LE and an amplifier circuit OP.

[0241] The amplifier circuit OP has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, an operational amplifier or a differential amplifier circuit can be used as the amplifier circuit OP.

[0242] The inverting input terminal of the amplifier circuit OP is connected to the first terminal of the load LE and the second terminal of the switch SB. The non-inverting input terminal of the amplifier circuit OP is connected to the wiring VRL. The output terminal of the amplifier circuit OP is connected to the second terminal of the load LE and the terminal RTo.

[0243] The wiring VRL functions as a wiring that applies a fixed potential, which may be, for example, a ground potential (GND) or a low-level potential.

[0244] In particular, by setting the fixed potential provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the amplifier circuit OP becomes a virtual ground, and therefore the analog voltage output to the wiring OL can be a voltage based on the ground potential (GND).

[0245] 5B, the drive circuit ITS can output to the terminal RTo an analog voltage corresponding to the amount of current flowing from the wiring WCL through the switch SB to the terminal RTi of the circuit RL. The analog voltage can then be converted into a digital signal by the analog-to-digital converter ATDC and output to the wiring OL.

[0246] Note that, when the drive circuit ITS outputs an analog voltage rather than a digital signal to the wiring OL, the circuit ITSa does not need to include an analog-digital conversion circuit ATDC, as in the drive circuit ITS shown in FIG. 5C . Also, in FIG. 5C , the circuit RL preferably performs a function calculation using a value corresponding to the amount of current flowing through the terminal RTi as an input value, and outputs the result of the calculation as an analog current to the terminal RTo. Furthermore, by passing the analog current resulting from the calculation output from the terminal RTo, for example, through the wiring XCL of another arithmetic unit CDV, another calculation can be performed using the result of the calculation. This corresponds to sending the calculation result to the next fully connected layer in a multilayer perceptron, a type of artificial neural network. By directly using the analog current resulting from the calculation for the next calculation, analog-to-digital conversion and digital-to-analog current conversion are not necessary, and these conversion circuits can be omitted. This reduces the circuit area of ​​the arithmetic unit CDV and the power consumption required for the conversion circuits.

[0247] Next, a configuration example of the circuit RL will be described.

[0248] Next, a specific configuration example of the circuit RL included in the circuit ITSa of FIG. 5A or FIG. 5C will be described.

[0249] FIG. 6 is a circuit diagram showing, as an example, a specific configuration of the circuit RL included in the circuit ITSa of FIG. 5A or FIG. 5C, and the circuit RL shown in FIG. 6 has a function of performing the calculation of the ReLU function.

[0250] The circuit RL in FIG. 6 includes, as an example, transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, MN2o, and a current source CNI.

[0251] 6, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o. A second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o. A third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o. Because the circuit RL includes the first to third current mirror circuits, the circuit RL is sometimes referred to as a three-stage current mirror circuit.

[0252] The drain of transistor MP1i is connected to terminal RTi, and the drain of transistor MP1o is connected to the input terminal of current source CNI and the drain of transistor MN2i. The drain of transistor MN2o is connected to the drain of transistor MP3i. Transistor MP3o is connected to the output terminal of circuit RL. The output terminal of current source CNI is connected to wiring VGE.

[0253] For example, the wiring VGE functions as a wiring that applies a fixed potential. The fixed potential may be, for example, a low-level potential, a negative potential, a ground potential, etc. Depending on the situation, the fixed potential applied by the wiring VGE may be a high-level potential, a positive potential, etc.

[0254] The first current mirror circuit ideally has the function of passing a current between the source and drain of transistor MP2o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of passing a current between the source and drain of transistor MN1o that is equal to the source-drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of passing a current between the source and drain of transistor NP4o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP4i.

[0255] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to DIBL. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to DIBL. Therefore, wiring RSWL1 that applies a desired bias potential is connected to the gates of transistor MP1i and transistor MP1o.

[0256] In the second and third current mirror circuits, the transistors MN2i, MN2o, MP3i, and MP3o also function as clamp transistors to prevent a decrease in the threshold voltage of the transistors connected in series by DIBL. In this case, the wirings RSWL2 and RSWL3 each function as wirings that apply a desired bias potential.

[0257] The bias potentials applied to the wirings RSWL1 to RSWL3 can be made equal to each other, so that the wirings RSWL1 to RSWL3 can be the same wiring.

[0258] Each of the transistors MP1i and MP1o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MP1i and MP1o. Furthermore, by turning off each of the transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing power consumption in the circuit RL.

[0259] Similarly, by making the transistors MN2i and MN2o function as switching transistors, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL2 function as wiring for controlling the switching between the on and off states of the transistors MN2i and MN2o. Similarly, by making the transistors MP3i and MP3o function as switching transistors, it is possible to stop the third current mirror circuit at a desired timing. In this case, it is preferable that the wiring RSWL3 function as wiring for controlling the switching between the on and off states of the transistors MP3i and MP3o.

[0260] Note that the transistors MP1i and MP1o, and the transistors MP3i and MP3o can be simultaneously turned on or off. Therefore, the wiring RSWL1 and the wiring RSWL3 can be the same wiring.

[0261] In the first current mirror circuit, the source of the transistor MP2i and the source of the transistor MP2o are each connected to the wiring VDDL. The first current mirror circuit is configured with p-channel transistors, and therefore also functions as a current source circuit. Therefore, the wiring VDDL functions as a wiring that provides a high-level potential as a high power supply potential for the first current mirror circuit. Similarly, the third current mirror also functions as a current source circuit, and therefore, the high-level potential provided by the wiring VDDL also functions as a high power supply potential for the third current mirror circuit.

[0262] In the second current mirror circuit, the source of the transistor MN1i and the source of the transistor MN1o are connected to the wiring VSSL. The second current mirror circuit is configured with n-channel transistors, and therefore also functions as a current sink circuit. Therefore, the wiring VSSL functions as a wiring that applies a low-level potential as a low power supply potential of the second current mirror circuit.

[0263] The current source CNI is, for example, a quantity I ＩＢ The current flows from the drains of the transistors MP1o and MN2i to the wiring VGE.

[0264] When a high-level potential is applied to the wiring SWLB, the high-level potential is applied to the control terminal of the switch SB, and the switch SB is turned on. At this time, a quantity I corresponding to the value multiplied by the operation cell IM is applied to the wiring WCL. ＩＬ Therefore, a current of the amount I flows from the wiring VDDL to the wiring WCL. ＩＬ Therefore, the amount of the source-drain current of the transistor MP2o is also I ＩＬ This becomes:

[0265] Also, when the current source CNI is operating, I ＩＬ =I ＩＢ +I ＯＬ is established. Note that I ＯＬis the amount of current flowing between the source and drain of the transistor MN1i. Therefore, the amount of source-drain current of the transistor MN1o is also I ＯＬ This becomes:

[0266] The amount of source-drain current of the transistor MN1o is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4i is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4o is also I ＯＬ and the quantity I ＯＬ A current of flows.

[0267] The circuit RL is I ＩＬ Ga I Ｂ If it is greater than , the difference is the amount I ＯＬ A current of I flows through the terminal RTo to the wiring OL. ＩＬ Ga I Ｂ When the following condition is satisfied, the current flowing between the input terminal and the output terminal of the current source CNI is I ＩＬ And also, I ＯＬ = 0. In this case, no current flows from the circuit RL to the wiring OL. That is, the ReLU function can be calculated by the circuit RL shown in FIG.

[0268] <Example of Operation Method of Calculation Device> Next, an example of operation of the calculation device CDV shown in FIG. 1 will be described.

[0269] 7 is a timing chart showing an example of an operation method of the arithmetic device CDV. The timing chart shows changes in the potentials of the wirings SWLA, SWLB, WSL, XCL, the node N, and the node Nd during and around the periods T01 to T08. The timing chart also shows changes in the potentials of the source-drain current I flowing through the transistor M3. Ｍ３ and the source-drain current I flowing through the transistor M3d. Ｍ３ｄ The amount of and the respective variations of are also shown.

[0270] 7, the types of wiring, nodes, etc. are shown on the left side, and the potential levels are shown on the right side. In particular, "High" in the timing chart means a high-level potential on the wiring, and "Low" means a low-level potential on the wiring.

[0271] In this operation example, the driver circuit WCD and driver circuit XCD included in the calculation device CDV of FIG. 1 are respectively described as being applied with the driver circuit WCD of FIG. 2A and the driver circuit XCD of FIG. 2C.

[0272] The potentials applied by the wirings VEL, VINI1, and VINI2 are V Ｎ In addition, V Ｎ is set to ground potential (GND) or negative potential.

[0273] [Before Period T01] Before period T01, a low-level potential is applied to the wirings SWLA, SWLB, WSL, and XCL. The potentials of the node N of the processing cell IM and the node Nd of the driving cell IMD are V Ｎ Also, I Ｍ３ and I Ｍ３ｄ Each of these is set to 0.

[0274] Since the wiring WSL is supplied with a low-level potential, the gates of the transistors M1, M2, M1d, and M2d are supplied with a low-level potential, which turns off these transistors.

[0275] Also, before the period T01, the second data X, which is digital data, has not yet been provided from the outside. The amount of current generated by the circuit XCDa of the drive circuit XCD is 0. Also, the switch SWX is in an on state, and the wiring XCL is connected to the wiring VINI2 through the switch SWX. Ｎ is assumed to be given.

[0276] [Period T01] In the period T01, a high-level potential is applied to the wiring SWLA, and therefore, a high-level potential is applied to the control terminal of the switch SA, turning the switch SA on.

[0277] Also, during the period T01, the first data W, which is digital data, has not yet been provided from the outside. Therefore, the amount of current generated by the circuit WCDa of the drive circuit WCD is 0. Also, the switch SWW is in an on state, and the wiring WCL is connected to the wiring VINI1 through the switch SWW and the switch SA. Ｎ is assumed to be given.

[0278] [Period T02] In the period T02, a high-level potential is applied to the wiring WSL. Therefore, a high-level potential is applied to the gates of the transistors M1, M2, M1d, and M2d, turning these transistors on.

[0279] In the calculation cell IM, the transistor M1 and the transistor M2 are turned on, and thus the potential V Ｎ is applied to the gate of the transistor M3, the first terminal of the capacitor C1 (node ​​N), the first terminal of the capacitor C2, and the terminal Sout (node ​​Nm) of the amplifier circuit SF. At this time, the potential V Ｎ The second terminal of the transistor M3 is supplied with a potential V Ｎ Therefore, no current flows between the source and drain of the transistor M3, and therefore, I Ｍ３ will be 0.

[0280] Similarly, in the driving cell IMD, the transistors M1d and M2d are turned on, and the potential V Ｎ is applied to the gate of the transistor M3d, the first terminal of the capacitor C1d (node ​​Nd), the first terminal of the capacitor C2d, and the terminal Sout (node ​​Nmd) of the amplifier circuit SFd. At this time, the potential V Ｎ The second terminal of the transistor M3d is supplied with a potential V Ｎ Therefore, no current flows between the source and drain of the transistor M3d, and therefore, IＭ３ｄ also becomes 0.

[0281] [Period T03] During period T03, reference data r, which is digital data, is applied from the wiring IXL. Therefore, the amount of current generated by the circuit XCDa of the driver circuit XCD corresponds to r. Here, this amount of current is referred to as rI. Ｘｕｔ In addition, I Ｘｕｔ is the amount of current that flows when r = 1. Also, the switch SWX is in the OFF state, and the amount rI generated by the circuit XCDa Ｘｕｔ A current of flows through the wiring XCL.

[0282] In addition, in the driving cell IMD, the transistors M1d and M2d are in the on state, so the quantity rI Ｘｕｔ The current flows through the source and drain of the transistor M3d to the wiring VEL. At this time, the potentials of the gate of the transistor M3d, the first terminal of the capacitor C1d (node ​​Nd), the first terminal of the capacitor C2d, and the terminal Sout of the amplifier circuit SFd (node ​​Nmd) are each equal to or greater than rI. Ｘｕｔ At this time, the potential is V ｇｍ Let (r).

[0283] In addition, in a period T03, the first data W, which is digital data, is provided from the wiring IWL. Therefore, the amount of current generated in the circuit WCDa of the driving circuit WCD is an amount corresponding to W. Here, this amount of current is expressed as W Ｗｕｔ In addition, I Ｗｕｔ is the amount of current that flows when W=1. Also, assume that the switch SWW is in the OFF state. Since the switch SA is in the ON state, the amount WI generated by the circuit WCDa Ｗｕｔ A current of flows through the wiring WCL.

[0284] In addition, in the operation cell IM, the transistors M1 and M2 are in the on state, so the quantity WI ＷｕｔThe current flows through the source-drain of the transistor M3 to the wiring VEL. At this time, the potentials of the gate of the transistor M3, the first terminal of the capacitor C1 (node ​​N), the first terminal of the capacitor C2, and the terminal Sout of the amplifier circuit SF (node ​​Nm) are each equal to or greater than WI. Ｗｕｔ At this time, the potential is V ｇ Let (W).

[0285] In addition, I Ｘｕｔ I Ｗｕｔ From now on, I Ｘｕｔ and I Ｗｕｔ Each of these is I ０ It will be explained as follows.

[0286] In addition, the amount of current rI generated by the circuit XCDa ０ is the subthreshold current in the transistor M3d, and the gate-source voltage of the transistor M3d is V ｇｍ (r)-V Ｎ Therefore, rI ０ can be expressed as the following equation (1.3).

[0287]

[0288] In addition, V ｔｈ is the threshold voltage of the transistor M3d, and J is a correction coefficient determined by temperature, device structure, etc. ａ is the gate-source voltage of transistor M3 is V ｔｈ is the amount of current that flows when

[0289] In addition, the amount of current WI generated in the circuit WCDa ０ is the subthreshold current in transistor M3, and the gate-source voltage of transistor M3 is V ｇ (W)-V Ｎ Therefore, WI ０ can be expressed as the following equation (1.4).

[0290]

[0291] For the sake of simplicity, Vｔｈ and J and I ａ are the V of the transistor M3d. ｔｈ and J and I ａ The values ​​are equal to each of the following:

[0292] Here, I ０ can be expressed as the following equation (1.5).

[0293]

[0294] Therefore, by using equations (1.4) and (1.5), W can be expressed as in the following equation (1.6).

[0295]

[0296] [Period T04] During the period T04, a low-level potential is applied to the wiring WSL. Therefore, a low-level potential is applied to the gates of the transistors M1, M2, M1d, and M2d. As a result, these transistors are turned off.

[0297] In the processing cell IM, the transistors M1 and M2 are turned off, and the potential V ｇ (W) is held by the capacitance element C1. As a result, the node N is in a floating state. Furthermore, since the potential of the node N is held, the gate-source voltage of the transistor M3 is fixed, and therefore the amount WI continues to flow between the source and drain of the transistor M3. ０ A current of flows.

[0298] Similarly, in the driving cell IMD, the transistors M1d and M2d are turned off, so that the potential V ｇｍ (r) is held by the capacitance element C1d. As a result, the node Nd is in a floating state. Furthermore, since the potential of the node Nd is held, the gate-source voltage of the transistor M3d is fixed, and therefore the quantity rI continues to flow between the source and drain of the transistor M3d. ０ A current of flows.

[0299] As in the above-described transistors M3 and M3d, by passing a current of the amount I between the source and drain and holding a potential corresponding to that current at the gate, it is possible to continue to pass a current of the amount I between the source and drain. In this specification, this type of operation is referred to as "setting (programming) the amount of current flowing between the source and drain of a transistor to I."

[0300] Meanwhile, in the period T04, the transistors M1 and M2 in the processing cell IM are turned off, and the potential V ｇ (W) is also held by the capacitance element C2. The terminal Sin of the amplifier circuit SF is supplied with a potential V ｇ Since (W) is input, the amplifier circuit SF outputs a potential V ｇ As a result, when the transistor M2 is in an off state, even if the potential of the node Nm fluctuates due to a leak current or the like, the amplifier circuit SF can replenish charge at the node Nm. Therefore, the node Nm is at a potential V ｇ At this time, the voltage between the source and drain of the transistor M1 becomes 0 V, so that the leakage current in the transistor M1 can be reduced. Therefore, the node N is at the potential V ｇ (W) can be maintained for a long period of time.

[0301] Similarly, in the driving cell IMD, the transistors M1d and M2d are turned off, so that the potential V ｇｍ (r) is also held by the capacitance element C2d. The terminal Sin of the amplifier circuit SFd is supplied with a potential V ｇｍ Since (r) is input, the amplifier circuit SFd outputs a potential V ｇｍ As a result, when the transistor M2d is in the off state, even if the potential of the node Nmd fluctuates due to a leak current or the like, the amplifier circuit SFd can replenish the charge at the node Nmd. Therefore, the node Nmd is at the potential V ｇｍAt this time, the voltage between the source and drain of the transistor M1 becomes 0 V, so that the leakage current in the transistor M1 can be reduced. Therefore, the node Nd is at the potential V ｇｍ (r) can be maintained for a long period of time.

[0302] [Period T05] In period T05, the circuit XCDa of the driver circuit XCD stops, and the amount of current generated by the circuit XCDa becomes 0. In addition, the switch SWX is turned on, and the potential V Ｎ is given.

[0303] As a result, the potential V Ｎ is applied to the first terminal of the transistor M3d of the driving cell IMD. Furthermore, since the node Nd is in a floating state, the potential of the node Nd fluctuates in accordance with the change in the potential of the wiring XCL due to the capacitive coupling of the capacitance element C1d. For example, the potential of the wiring XCL is V ｇｍ (r) to V Ｎ The changed voltage is V ｇｍ (r)-V Ｎ In addition, from now on, V ｇｍ (r)-V Ｎ = ΔV ｇｍ Furthermore, when the capacitive coupling coefficient of the capacitive element C1d is p, the change in the potential of the node Nd is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ ) Therefore, the potential of the node Nd during the period T05 is V ｇｍ (r)-pΔV ｇｍ (r).

[0304] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r)-pΔV ｇｍ (r)-V Ｎ In this example of operation, the amount of current flowing through the transistor M3d due to this gate-source voltage is assumed to be zero.

[0305] In addition, the potential V Ｎis also applied to the second terminal of the capacitance element C1 of the processing cell IM. In addition, since the node N is also in a floating state, the potential of the node N also fluctuates in accordance with the change in the potential of the wiring XCL due to the capacitive coupling in the capacitance element C1. For example, the change in the potential of the wiring XCL is ΔV ｇｍ (r), and when the capacitive coupling coefficient of the capacitive element C1 is set to p, which is the same as that of the capacitive element C1d, the change in potential of the node N is pΔV ｇｍ (r) = p(V ｇｍ (r)-V Ｎ ) Therefore, the potential of the node N during the period T05 is V ｇ (W)-pΔV ｇｍ (r).

[0306] At this time, the gate-source voltage of the transistor M3 is V ｇ (r)-pΔV ｇｍ (r)-V Ｎ In this operation example, the amount of current flowing through the transistor M3 due to this gate-source voltage is also assumed to be zero.

[0307] During the period T05, the potential of the node N in the processing cell IM is V ｇ (W)-pΔV ｇｍ (r), the potential of the node Nm is also V ｇ (W)-pΔV ｇｍ Similarly, in the driving cell IMD, the potential of the node N is V ｇｍ (r)-pΔV ｇｍ (r), the potential of the node Nm is also V ｇｍ (r)-pΔV ｇｍ (r).

[0308] [Period T06] In the period T06, a low-level potential is applied to the wiring SWLA, whereby the control terminal of the switch SA is supplied with a low-level potential, turning the switch SA off.

[0309] During period T05, the circuit WCDa of the drive circuit WCD stops, and the amount of current generated by the circuit WCDa becomes zero. The switch SWW may be either on or off. In either case, because the switch SA is off, the terminal of the drive circuit WCD connected to the wiring WCL becomes high impedance, and no current or potential is applied from the drive circuit WCD to the wiring WCL.

[0310] [Period T07] In the period T07, a high-level potential is applied to the wiring SWLB, and therefore, a high-level potential is applied to the control terminal of the switch SB, turning the switch SB on.

[0311] At this time, the input terminal of the circuit ITSa is brought into conduction with the first terminal of the transistor M3 of the processing cell IM.

[0312] [Period T08] During period T08, second data X, which is digital data, is provided from the wiring IXL. Therefore, the amount of current generated by the circuit XCDa of the drive circuit XCD is an amount corresponding to X. Here, this amount of current is expressed as XI ０ In addition, the switch SWX is turned off, and the quantity XI generated by the circuit XCDa ０ A current of flows through the wiring XCL.

[0313] Quantity XI ０ The current flows to the wiring VEL via the transistor M3d of the driving cell IMD. At this time, the potential of the wiring XCL is V Ｎ From V ｇｍ Since the node Nd is in a floating state, the potential of the node Nd varies in accordance with the change in the potential of the wiring XCL due to capacitive coupling in the capacitor C1d. For example, the potential of the wiring XCL is V Ｎ From V ｇｍ (X), the changed voltage is V ｇｍ (X)-V Ｎ In addition, from now on, V ｇｍ (X)-V Ｎ = ΔV ｇｍ Since the capacitance coupling coefficient of the capacitance element C1d is p, the change in the potential of the node Nd is pΔVｇｍ (X) = p(V ｇｍ (X)-V Ｎ ) Therefore, the potential of the node Nd during the period T08 is V ｇｍ (r)-pΔV ｇｍ (r) + pΔV ｇｍ (X) = V ｇｍ (r) + p(ΔV ｇｍ (X)-ΔV ｇｍ (r)).

[0314] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r) + p(ΔV ｇｍ (X)-ΔV ｇｍ (r))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M3d Ｍ３ｄ =XI ０ is expressed as the following equation (1.7).

[0315]

[0316] In addition, in the processing cell IM, the node N is also in a floating state, and therefore, due to a change in the potential of the wiring XCL, the potential of the node N fluctuates in accordance with the change in the potential of the wiring XCL due to capacitive coupling in the capacitance element C1. For example, the amount of change in the potential of the wiring XCL is ΔV ｇｍ (X), and since the capacitive coupling coefficient of the capacitive element C1 is p, the change in the potential of the node N is also pΔV ｇｍ (X) = p(V ｇｍ (X)-V Ｎ ) Therefore, the potential of the node N during the period T08 is V ｇ (W)-pΔV ｇｍ (r) + pΔV ｇｍ (X) = V ｇ (W)-p(ΔV ｇｍ (X)-ΔV ｇｍ (r)).

[0317] At this time, the gate-source voltage of the transistor M3 is V ｇ (W)-p(ΔV ｇｍ (X)-ΔV ｇｍ (r))-V ＮAs a result, the amount of current I flowing between the source and drain of the transistor M3 Ｍ３ is expressed as the following equation (1.8).

[0318]

[0319] Here, r and X are defined as in equations (1.9) and (1.10), respectively.

[0320]

[0321] By using equations (1.5), (1.6), (1.9) and (1.10), equation (1.8) becomes the following equation (1.11).

[0322]

[0323] As shown in equation (1.11), the amount of current I flowing between the source and drain of transistor M3 Ｍ３ is proportional to the product of W and X. This means that the amount of current I Ｍ３ Therefore, the multiplication result of the first data, which is W, and the second data, which is X, can be obtained. Therefore, by using the arithmetic unit CDV of FIG. 1, the first data and the second data can be multiplied.

[0324] In particular, when multiplying the first data by the second data, it is preferable that the reference data r is 1. That is, in the periods T03 and T04, the amount of current that the circuit XCDa passes through the wiring XCL is I ０ It is preferable to set the following.

[0325] Furthermore, from the above explanation, in the arithmetic unit CDV of FIG. 1, by setting the reference data r to a positive number other than 1, it is possible to perform division using r as the divisor and WX as the dividend. In other words, it is possible to perform the multiplication of W and X / r. This allows the arithmetic unit CDV to increase the resolution of values ​​that can be input as second data. Furthermore, when considering the multiplication of W / r and X, it can also be said that the arithmetic unit CDV can increase the resolution of values ​​that can be input as first data.

[0326] Since the switch SA is in the OFF state and the switch SB is in the ON state, the amount of current I flowing between the source and drain of the transistor M3 is Ｍ３ The current flows to the input terminal of the circuit ITSa included in the drive circuit ITS.

[0327] The circuit ITSa is the quantity I Ｍ３ By obtaining the current, the quantity I Ｍ３ The circuit ITSa calculates a function in which a value corresponding to I is substituted as a variable, and outputs a voltage or current corresponding to the calculation result from the output terminal. For specific details, please refer to the description of the circuit ITSa above. For example, when the function used in the calculation of the circuit ITSa in which I is substituted as a variable is F(I), and the result of the calculation is Z[j], Z[j] can be expressed as shown in the following formula (1.12).

[0328]

[0329] In addition, during the period T08, the potential of the node N in the processing cell IM is V ｇ (W)-p(ΔV ｇｍ (X)-ΔV ｇｍ (r)), the potential of the node Nm is also V ｇ (W)-p(ΔV ｇｍ (X)-ΔV ｇｍ Similarly, in the driving cell IMD, the potential of the node N is V ｇｍ (r) + p(ΔV ｇｍ (X)-ΔV ｇｍ (r)), the potential of the node Nm is also V ｇｍ (r) + p(ΔV ｇｍ (X)-ΔV ｇｍ (r)).

[0330] <Configuration Example 1 of Arithmetic Circuit> Next, a modification of the arithmetic circuit CC included in the arithmetic device CDV shown in FIG. 1 will be described.

[0331] The arithmetic circuit CC shown in FIG. 8A has a circuit configuration in which the arithmetic cell IM shown in FIG. 1 is provided with a transistor M4, and the driving cell IMD is provided with a transistor M4d.

[0332] Specifically, the transistor M4 is provided between the first terminal of the transistor M3 and the wiring WCL, and the transistor M4d is provided between the first terminal of the transistor M3d and the wiring XCL. The first terminal of the transistor M4 is connected to the first terminal of the transistor M3, and the second terminal of the transistor M4 is connected to the wiring WCL. The first terminal of the transistor M4d is connected to the first terminal of the transistor M3d, and the second terminal of the transistor M4d is connected to the wiring XCL. The gates of the transistors M4 and M4d are connected to the wiring VEB.

[0333] The transistor M4 functions as a clamp transistor to prevent DIBL in the transistor M3, thereby preventing a decrease in the threshold voltage of the transistor M3 due to a high-level potential being applied to the first terminal of the transistor M3. Similarly, the transistor M4d functions as a clamp transistor to prevent DIBL in the transistor M3d, thereby preventing a decrease in the threshold voltage of the transistor M3d due to a high-level potential being applied to the first terminal of the transistor M3d.

[0334] For example, the wiring VEB functions as a wiring that applies a fixed potential. Note that the fixed potential may be, for example, a high-level potential, a positive potential, etc. Note that, depending on the situation, the fixed potential applied by the wiring VEB may be a low-level potential, a ground potential, a negative potential, etc.

[0335] <Configuration Example 2 of Arithmetic Circuit> The arithmetic circuit CC shown in FIG. 8B has a circuit configuration in which each of the amplifier circuit SF and the amplifier circuit SFd is a source follower.

[0336] Specifically, the amplifier circuit SF includes a transistor M5 and a transistor M6, and the amplifier circuit SFd includes a transistor M5d and a transistor M6d. These transistors function as amplifier transistors.

[0337] The gate of the transistor M5 is connected to the terminal Sin of the amplifier circuit SF, the first terminal of the transistor M5 is connected to the first terminal of the transistor M6 and the terminal Sout of the amplifier circuit SF, the second terminal of the transistor M5 is connected to the wiring VED, the second terminal of the transistor M6 is connected to the wiring VES, and the gate of the transistor M6 is connected to the wiring VEI.

[0338] The gate of the transistor M5d is connected to the terminal Sin of the amplifier circuit SFd, the first terminal of the transistor M5d is connected to the first terminal of the transistor M6d and the terminal Sout of the amplifier circuit SFd, the second terminal of the transistor M5d is connected to the wiring VED, the second terminal of the transistor M6d is connected to the wiring VES, and the gate of the transistor M6d is connected to the wiring VEI.

[0339] For example, the wiring VED functions as a wiring that applies a fixed potential. Specifically, the wiring VED functions as a wiring that applies a high-level potential as a high power supply potential to each of the source follower including the transistors M5 and M6 and the source follower including the transistors M5d and M6d. Note that, depending on the situation, the fixed potential applied by the wiring VED may be a low-level potential, a ground potential, a negative potential, or the like, instead of a high-level potential.

[0340] For example, the wiring VES functions as a wiring that applies a fixed potential. Specifically, the wiring VES functions as a wiring that applies a low-level potential as a low power supply potential to each of a source follower including the transistors M5 and M6 and a source follower including the transistors M5d and M6d. Note that, depending on the situation, the fixed potential applied by the wiring VES can be a high-level potential instead of a low power supply potential.

[0341] For example, the wiring VEI functions as a wiring that applies a fixed potential. Specifically, the wiring VEI functions as a wiring that applies the fixed potential to the gates of the transistors M6 and M6d. A low-level potential is applied to the second terminals of the transistors M6 and M6d from the wiring VES, causing the transistors M6 and M6d to function as current sources. The fixed potential may be, for example, a potential higher than 0 V or a potential higher than ground potential.

[0342] Note that the transistors M5 and M6 can each be, for example, a transistor that can be applied to any of the transistors M1 to M3. Similarly, the transistors M5d and M6d can each be, for example, a transistor that can be applied to any of the transistors M1d to M3d.

[0343] In the calculation cell IM, as described above, the transistors M5 and M6 are transistors that constitute a source follower. In particular, it is preferable that the amount of current flowing between the source and drain of the transistors M5 and M6 be large in order to speed up the operation of a source follower that can be applied to the amplifier circuit SFd. Similarly, in the driver cell IMD, as described above, the transistors M5d and M6d are transistors that constitute a source follower. In particular, it is preferable that the amount of current flowing between the source and drain of the transistors M5d and M6d be large in order to speed up the operation of a source follower that can be applied to the amplifier circuit SFd.

[0344] For this reason, it is preferable to use Si transistors for the transistors M5 and M6. Si transistors have a larger on-state current than OS transistors, and therefore can increase the charging speed of nodes, terminals, capacitors, and the like. In the case of the amplifier circuit SF, the amount of current output to the terminal Sout is increased, thereby shortening the time required for the potential of the node Nm to change. Similarly, in the case of the amplifier circuit SFd, the amount of current output to the terminal Sout is increased, thereby shortening the time required for the potential of the node Nmd to change. That is, in each of the amplifier circuits SF and SFd, the response speed from when a potential is input to the terminal Sin until when a potential is output to the terminal Sout can be increased.

[0345] Note that the configurations described in this embodiment can be combined with each other. For example, the configuration of the arithmetic circuit CC shown in FIG. 9 can be one embodiment of the present invention by combining the arithmetic circuits CC shown in FIG. 8A and FIG. 8B.

[0346] The arithmetic circuit CC shown in Fig. 9 has a configuration in which the circuit configurations of the amplifier circuit SF and amplifier circuit SFd shown in Fig. 8B are applied as the amplifier circuit SF and amplifier circuit SFd of the arithmetic circuit CC of Fig. 8 A. Therefore, for the amplifier circuit SF and amplifier circuit SFd in the arithmetic circuit CC of Fig. 9, the description of the amplifier circuit SF and amplifier circuit SFd shown in Fig. 8B can be referred to.

[0347] <Configuration Example 3 of Arithmetic Circuit> The arithmetic circuit CC shown in Fig. 8C is a modified example of the arithmetic circuit CC shown in Fig. 1. The arithmetic circuit CC in Fig. 8C differs from the arithmetic circuit CC in Fig. 1 in that it does not have the capacitive element C2 and the capacitive element C2d.

[0348] 8C does not include capacitance elements for holding the potentials of nodes Nm and Nmd, and therefore, nodes Nm and Nmd of the calculation circuit CC of FIG. 8C cannot hold charge using these capacitance elements. However, when the amount of charge supplied by amplifier circuit SF is greater than the amount of charge released from node Nm, fluctuations in the potential at node Nm can be suppressed. Similarly, when the amount of charge supplied by amplifier circuit SFd is greater than the amount of charge released from node Nmd, fluctuations in the potential at node Nmd can be suppressed. Therefore, in these cases, the calculation circuit CC may be configured without capacitance elements C2 and C2d.

[0349] Furthermore, by configuring the arithmetic circuit CC so that it does not have a capacitive element C2 (capacitive element C2d), the time required for the amplifier circuit SF (amplifier circuit SFd) to accumulate charge at node Nm (node ​​Nmd) can be reduced, thereby increasing the operating speed of the arithmetic circuit CC.

[0350] Furthermore, by configuring the arithmetic circuit CC so that the capacitance element C2 (capacitance element C2d) is not provided, the circuit area of ​​the arithmetic cell IM (driver cell IMD) included in the arithmetic circuit CC can be reduced. Furthermore, since there is no need to provide wiring VEG connected to the capacitance element C2 (capacitance element C2d), the circuit area of ​​the cell array CA can also be reduced. These features enable a reduction in the circuit area of ​​the arithmetic unit CDV. Furthermore, the cell density of the cell array CA can be increased, allowing the arithmetic unit CDV to perform larger-scale operations.

[0351] <Configuration Example 4 of Arithmetic Circuit> The arithmetic circuit CC shown in FIG. 10A is a modified example of the arithmetic circuit CC shown in FIG. 1, and differs from the arithmetic circuit CC in FIG. 1 in that the second terminals of the capacitance elements C2 and C2d are connected to the wiring XCL instead of the wiring VEG.

[0352] By connecting the second terminals of the capacitive elements C2 and C2d to the wiring XCL, in the computation cell IM, not only the node N but also the node Nm is connected to the wiring XCL, and thus the potential of the node Nm also changes due to the capacitive coupling by the capacitive element C2. The potential of the node Nm also changes with a change in the potential of the wiring XCL. Furthermore, since the potentials of the nodes N and Nm are equal during both the write operation and the hold operation, it is preferable that the potentials of the nodes N and Nm are also equal after the capacitive coupling of the capacitive element C2 occurs due to a change in the potential of the wiring XCL. Furthermore, in the drive cell IMD, not only the node Nd but also the node Nmd is connected to the wiring XCL, and thus the potential of the node Nmd also changes due to the capacitive coupling by the capacitive element C2d. The potential of the node Nmd also changes with a change in the potential of the wiring XCL. Furthermore, since the potentials of the nodes Nd and Nmd are equal during both the write operation and the holding operation, it is preferable that the potentials of the nodes Nd and Nmd are also equal after capacitive coupling of the capacitive element C2d occurs due to a change in the potential of the wiring XCL.

[0353] In the processing cell IM, by changing the potential of the wiring XCL, the potential of the node N and the node Nm can be changed, thereby reducing the amount of amplification of the potential of the node Nm by the amplifier circuit SF, and as a result, the amount of charge supplied from the terminal Sout of the amplifier circuit SF can be reduced, thereby reducing the power consumption of the amplifier circuit SF.

[0354] Similarly, in the driving cell IMD, by changing the potential of the wiring XCL, the potential of the node Nd and the node Nmd can be changed, thereby reducing the amount of amplification of the potential of the node Nmd by the amplifier circuit SFd, and as a result, the amount of charge supplied from the terminal Sout of the amplifier circuit SFd can be reduced, thereby reducing the power consumption of the amplifier circuit SFd.

[0355] Furthermore, for example, the configuration of the arithmetic circuit CC shown in FIG. 10B can be one aspect of the present invention by combining the arithmetic circuits CC shown in FIG. 8A and FIG. 10A.

[0356] The calculation circuit CC shown in Fig. 10B has a configuration in which a transistor M4 is provided in the calculation cell IM of Fig. 10A to prevent DIBL of the transistor M3, and a transistor M4d is provided in the driver cell IMD of Fig. 10A to prevent DIBL of the transistor M3d. This makes it possible to prevent a decrease in the threshold voltage of the transistor M3 by the potential of the wiring WCL, or to prevent a decrease in the threshold voltage of the transistor M3d by the potential of the wiring XCL.

[0357] <Configuration Example 5 of Arithmetic Circuit> Fig. 11 shows an arithmetic circuit CC having a configuration different from the arithmetic circuit CC shown in Fig. 1 and Fig. 8 to Fig. 10. The arithmetic circuit CC shown in Fig. 11 is a modified example of the arithmetic circuit CC of Fig. 1, and is an arithmetic circuit that can hold first data in the arithmetic cell IM for a long period of time and can hold reference data in the driving cell IMD for a long period of time.

[0358] The computation cell IM includes a transistor M1, transistors M2[1] to M2[K] (K is an integer equal to or greater than 3), a transistor M3, and capacitors C1 and C2[1] to C2[K]. Note that the transistor M1 in FIG. 11 corresponds to the transistor M1 in FIG. 1, the transistors M2[1] to M2[K] in FIG. 11 correspond to the transistor M2 in FIG. 1, and the transistor M3 in FIG. 11 corresponds to the transistor M3 in FIG. 1. The capacitor C1 in FIG. 11 corresponds to the capacitor C1 in FIG. 1, and the capacitors C2[1] to C2[K] in FIG. 11 correspond to the capacitor C2 in FIG. 1. The amplifier circuits SF[1] to SF[K] in FIG. 11 correspond to the amplifier circuit SF in FIG. 1.

[0359] The driving cell IMD includes a transistor M1d, transistors M2d[1] to M2d[K] (K is an integer of 3 or more), a transistor M3d, a capacitor C1d, and capacitors C2d[1] to C2d[K]. Note that the transistor M1d in FIG. 11 corresponds to the transistor M1d in FIG. 1, the transistors M2d[1] to M2d[K] in FIG. 11 correspond to the transistor M2d in FIG. 1, and the transistor M3d in FIG. 11 corresponds to the transistor M3d in FIG. 1. The capacitor C1 in FIG. 11 corresponds to the capacitor C1d in FIG. 1, and the capacitors C2d[1] to C2d[K] in FIG. 11 correspond to the capacitor C2d in FIG. 1. The amplifier circuits SFd[1] to SFd[K] in FIG. 11 correspond to the amplifier circuit SFd in FIG. 1.

[0360] In the calculation cell IM, the first terminal of the transistor M1 is connected to the gate of the transistor M3, the first terminal of the capacitor C1, and the terminal Sin of each of the amplifier circuits SF[1] to SF[K]. The second terminal of the transistor M1 is connected to the first terminal of the transistor M2[K], the first terminal of the capacitor C2[K], and the terminal Sout of the amplifier circuit SF[K]. The first terminal of the transistor M2[k] (k is an integer greater than or equal to 1 and less than or equal to K-1) is connected to the second terminal of the transistor M2[k+1], the first terminal of the capacitor C2[k], and the terminal Sout of the amplifier circuit SF[k].

[0361] The second terminal of the transistor M2[1] and the first terminal of the transistor M3 are connected to the wiring WCL, and the second terminal of the transistor M3 is connected to the wiring VEL. The second terminal of the capacitor C1 is connected to the wiring XCL, and the second terminals of the capacitors C2[1] to C2[K] are connected to the wiring VEG. The gates of the transistor M1 and the transistors M2[1] to M2[K] are connected to the wiring WSL.

[0362] In the driving cell IMD, the first terminal of the transistor M1d is connected to the gate of the transistor M3d, the first terminal of the capacitor C1d, and the terminals Sin of the amplifier circuits SFd[1] to SFd[K]. The second terminal of the transistor M1d is connected to the first terminal of the transistor M2d[K], the first terminal of the capacitor C2d[K], and the terminal Sout of the amplifier circuit SFd[K]. The first terminal of the transistor M2d[k] (k is an integer between 1 and K-1) is connected to the second terminal of the transistor M2d[k+1], the first terminal of the capacitor C2d[k], and the terminal Sout of the amplifier circuit SFd[k].

[0363] The second terminal of the transistor M2d[1], the first terminal of the transistor M3d, and the second terminal of the capacitor C1d are connected to the wiring XCL, and the second terminal of the transistor M3d is connected to the wiring VEL. The second terminals of the capacitors C2[1] to C2[K] are connected to the wiring VEG. The gates of the transistor M1d and the transistors M2d[1] to M2d[K] are connected to the wiring WSL.

[0364] Note that transistor M2[k], transistor M2[k+1], transistor M2d[k], transistor M2d[k+1], capacitance element C1[k], capacitance element C1d[k], amplifier circuit SF[k], and amplifier circuit SFd[k] are not shown in Figure 11.

[0365] In the operation cell IM, the first terminals of the capacitive element C1 and the capacitive elements C2[1] to C2[K] serve as retention nodes, and the same first data is retained at each retention node.

[0366] In the driving cell IMD, the first terminals of the capacitive element C1d and the capacitive elements C2d[1] to C2d[K] serve as retention nodes, and the same reference data is retained at each retention node.

[0367] 11 , in the calculation cell IM, the transistor M1 and the transistors M2[1] to M2[K] are connected in series, which can be regarded as substantially increasing the channel length of the transistor M1. By increasing the channel length, it is possible to reduce the leakage current flowing between the source and drain of each of the transistors M1 and the transistors M2[1] to M2[K], and it is possible to hold the potential corresponding to the first data in the calculation cell IM for a long period of time.

[0368] Similarly, in the driver cell IMD, the transistor M1d and the transistors M2d[1] to M2d[K] are connected in series, which can be regarded as substantially increasing the channel length of the transistor M1. Increasing the channel length can reduce the leakage current flowing between the source and drain of each of the transistors M1d and M2d[1] to M2d[K], and can hold the potential corresponding to the reference data for the driver cell IMD for a long period of time.

[0369] <Example of Layout of Arithmetic Circuit> Next, an example of the layout of each of the above-mentioned arithmetic cells IM and driving cells IMD will be described.

[0370] FIG. 12 is a schematic plan view showing an example of the layout of the processing cell IM shown in FIG. 9, and FIG. 13 is a schematic plan view showing an example of the layout of the driving cell IMD shown in FIG.

[0371] 12, the calculation cell IM includes, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Similarly, the drive cell IMD includes, as an example, a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Note that, to clearly show the schematic plan views, the insulating layers included in the calculation cell IM and the drive cell IMD are not shown in FIGS. 12 and 13.

[0372] As an example, the semiconductor layer SMC is located below the conductive layers SDM and GEM. Also, as an example, the conductive layer PLG is located above the conductive layers SDM and GEM. Also, as an example, the conductive layer WIR is located above the conductive layer PLG. The order of formation can be as follows: first, the semiconductor layer SMC, second, one of the conductive layers SDM and GEM, third, the other of the conductive layers SDM and GEM, fourth, the conductive layer PLG, and fifth, the conductive layer WIR.

[0373] In the processing cell IM and the driving cell IMD, a portion of the conductive layer GEM functions as, for example, the gates of the transistors M1 to M6 and the transistors M1d to M6d, and a portion of the conductive layer GEM functions as one of a pair of electrodes of the capacitance elements C1, C2, C1d, and C2d, for example.

[0374] 12 and 13, each of the wiring XCL, wiring WSL, wiring VEI, wiring VED, wiring VES, and wiring VEG extending around the periphery of the processing cell IM or the driving cell IMD can be formed as part of the conductive layer GEM.

[0375] For example, parts of the conductive layer SDM function as the sources or drains of the transistors M1 to M6 and the transistors M1d to M6d.

[0376] For example, a part of the conductive layer WIR functions as the other of the pair of electrodes of each of the capacitive elements C1, C2, C1d, and C2d.

[0377] Furthermore, a portion of the conductive layer WIR can be a wiring extending around the periphery of the computation cell IM or the driver cell IMD. For example, in Fig. 12, each of the wiring VEL, wiring WCL, and wiring VEB extending around the periphery of the computation cell IM can be formed as a portion of the conductive layer WIR. For example, in Fig. 13, each of the wiring VEL and wiring VEB extending around the periphery of the driver cell IMD can be formed as a portion of the conductive layer WIR.

[0378] The conductive layer GEM, the conductive layer SDM, the conductive layer WIR, and the semiconductor layer SMC can each be formed using, for example, a lithography method. Specifically, for example, when forming the conductive layer GEM, a conductive material to be the conductive layer GEM can be formed using one or more methods selected from a sputtering method, a CVD (Chemical Vapor Deposition) method, a PLD (Pulsed Laser Deposition) method, and an ALD (Atomic Layer Deposition) method, and then a desired pattern can be formed using a lithography method. In addition, the conductive layer SDM, the conductive layer WIR, the semiconductor layer SMC, and the conductive layer PLG can also be formed using the same method as above.

[0379] Insulating layers may be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDM, and between the conductive layer WIR and the conductive layer GEM. In particular, the insulating layer provided between the semiconductor layer SMC and the conductive layer GEM may function as a gate insulating film (sometimes referred to as a front gate insulating film, etc.). In the region where the capacitive elements C1 and C2 are provided, an insulating layer that functions as a dielectric for each of the capacitive elements C1 and C2 is preferably provided between the conductive layer WIR and the conductive layer GEM. Similarly, in the region where the capacitive elements C1d and C2d are provided, an insulating layer that functions as a dielectric for each of the capacitive elements C1d and C2d is preferably provided between the conductive layer WIR and the conductive layer GEM.

[0380] The capacitance element C1 is preferably provided in a part of the region where the conductive layer GEM extends as the wiring XCL, as shown in Fig. 12. Similarly, the capacitance element C2 is preferably provided in a part of the region where the conductive layer GEM extends as the wiring VEG, as shown in Fig. 12. In this way, by using a part of the extending wiring as one of a pair of electrodes of the capacitance element and using the other of the pair of electrodes of the capacitance element above it, it is possible to easily ensure an area for providing the capacitance element and reduce the circuit area of ​​the calculation cell IM.

[0381] In order to increase the capacitance of the region of the wiring XCL where the capacitor C1 is provided, the width of the region may be made longer than the width of the region of the wiring XCL where the capacitor C1 is not provided. By increasing the capacitance of the capacitor C1 in this manner, the retention time of the potential of the node N shown in FIG. 1 can be increased. Similarly, for the capacitor C2, the width of the region of the wiring VEG where the capacitor C2 is provided can be made longer than the width of the region of the wiring VEG where the capacitor C2 is not provided, thereby increasing the capacitance of the capacitor C2.

[0382] 12, the width d1 of the conductive layer WIR, which functions as the other of the pair of electrodes of the capacitance element C1, is shorter than the width d2 of the conductive layer GEM, which functions as one of the pair of electrodes of the capacitance element C1. When an insulating layer functioning as a dielectric is formed on the conductive layer GEM, the insulating layer may be poorly formed at the edge of the conductive layer GEM or its surrounding area. Specifically, the insulating layer formed at the edge of the conductive layer GEM or its surrounding area may have poor coverage. In this case, if the width d1 of the conductive layer WIR is longer than the width d2 of the conductive layer GEM, the edge of the conductive layer GEM or its surrounding area may be short-circuited with the area of ​​the conductive layer WIR that overlaps it. For this reason, it is preferable that the width d1 of the conductive layer WIR be shorter than the width d2 of the conductive layer GEM.

[0383] Conversely, if the coverage of the insulating layer formed on the edge of the conductive layer GEM or its surrounding area can be increased, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitance element is proportional to the area of ​​the region where one of the pair of electrodes, the dielectric, and the other of the pair of electrodes overlap, if a higher capacitance value is desired, it is preferable to increase the area of ​​that region. Therefore, by making the width d1 longer than the width d2, the width of that region can be increased from d1 to d2. As a result, the conductive layer WIR is formed above the edge of the conductive layer GEM, which increases the area of ​​the other of the pair of electrodes of the capacitance element C1, thereby increasing the capacitance value of the capacitance element C1. The same applies to the capacitance element C2.

[0384] The same can be said about the capacitive elements C1d and C2d of the driving cell IMD in FIG. 13 as about the capacitive elements C1 and C2.

[0385] Furthermore, an opening is provided in the region where a portion of the conductive layer SDM overlaps a portion of the conductive layer WIR, and a conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer SDM and a portion of the conductive layer WIR via the conductive layer PLG. Similarly, an opening is provided in the region where a portion of the conductive layer GEM overlaps a portion of the conductive layer WIR, and another conductive layer PLG is embedded in the opening. This allows charge to move between a portion of the conductive layer GEM and a portion of the conductive layer WIR via the conductive layer PLG.

[0386] Furthermore, in FIG. 1 , because transistors M1 and M2 are connected in series, transistors M1 and M2 can be formed to share an island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 12 . Similarly, because transistors M1 and M2 are connected in series in FIG. 1 , transistors M3 and M4 can be formed to share an island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 12 . Similarly, because transistors M5 and M6 are connected in series in FIG. 1 , transistors M5 and M6 can be formed to share an island-shaped semiconductor layer SMC, as shown in the schematic plan view of the processing cell IM in FIG. 12 . This reduces the area in which the transistors of the processing cell IM are formed, thereby reducing the cell density of the processing cell IM and the circuit area of ​​the processing device CDV. Furthermore, as shown in FIG. 12 , by arranging three island-shaped semiconductor layers SMC side by side, the circuit area of ​​the processing cell IM can be reduced. The same applies to the schematic plan view of the driving cell IMD in FIG.

[0387] 12, by arranging three island-shaped semiconductor layers SMC side by side, it becomes easy to provide wiring (back-gate wiring) functioning as a back gate electrode for each of the transistors M1 to M6 included in the processing cell IM. For example, as shown in FIG. 14, a conductive layer BGM functioning as a wiring BGL1, which is a back-gate wiring, can be extended below the semiconductor layer SMC including the channel formation regions of the transistors M1, M3, and M5. Similarly, a conductive layer BGM functioning as a wiring BGL2, which is a back-gate wiring, can be extended below the semiconductor layer SMC including the channel formation regions of the transistors M2, M4, and M6. This facilitates routing of the wirings BGL1 and BGL2 and shortens the wiring distance, thereby reducing parasitic resistance and power consumption.

[0388] Note that the planar schematic diagram of the arithmetic circuit of one embodiment of the present invention is not limited to FIG. 12 and FIG. 13 . The planar schematic diagram of the arithmetic circuit of one embodiment of the present invention may be appropriately modified as shown in FIG. 12 and FIG. 13 . For example, in FIG. 12 , the transistors M1 and M2 are formed to share an island-shaped semiconductor layer SMC, but each transistor may have a separate island-shaped semiconductor layer SMC. Furthermore, for example, in the circuit diagram shown in FIG. 12 , when the transistors M1, M2, M4, and M3 are focused on, these transistors are connected in series, and therefore these transistors can be formed to share the island-shaped semiconductor layer SMC.

[0389] In addition, in the schematic plan views of Figures 12 and 13, the sizes (including channel length and channel width) of the transistors M1 to M6 are shown to be equal to each other, and the sizes of the transistors M1d to M6d are shown to be equal to each other, but the sizes of the transistors M1 to M6 may be different from each other, and similarly, the sizes of the transistors M1d to M6d may also be different from each other.

[0390] For example, in FIG. 12 , the channel width d3 of each of the transistors M1 and M2 is preferably shorter than the channel width d5 ​​of the transistor M3 and the channel width d7 of each of the transistors M5 and M6. In other words, the channel width of the switching transistor is preferably shorter than the channel width of the amplification transistor. By shortening the channel width d3 of each of the transistors M1 and M2, the off-state current of each of the transistors M1 and M2 can be reduced, thereby enabling the potential applied to the node N of the processing cell IM to be maintained for a long period of time. Furthermore, the channel length d4 of each of the transistors M1 and M2 is preferably longer than the channel length d6 of the transistor M3 and the channel length d7 of each of the transistors M5 and M6. In other words, the channel length of the switching transistor is preferably longer than the channel length of the amplification transistor. By increasing the channel length d4 of each of the transistors M1 and M2, the off-state current of each of the transistors M1 and M2 can also be reduced, enabling the potential applied to the node N of the processing cell IM to be maintained for a long period of time.

[0391] Furthermore, the channel length d6 of transistor M3 is preferably shorter than the channel length d4 of each of transistors M1 and M2. By shortening the channel length d6 of transistor M3, the on-current of transistor M3 can be increased. Furthermore, the channel length d8 of each of transistors M5 and M6 is preferably shorter than the channel length d4 of each of transistors M1 and M2. By shortening the channel length d8 of each of transistors M5 and M6, the on-current of each of transistors M5 and M6 can be increased. In other words, the channel lengths of the amplification transistors (transistors M3, M5, and M6 in the above example) are preferably shorter than the channel lengths of the switching transistors (transistors M1 and M2 in the above example).

[0392] Since the transistor M4 functions as a clamp transistor, it is preferable that the channel length d10 of the transistor M4 be longer than the channel length d6 of the transistor M3. By making the channel length d10 of the transistor M4 longer than the channel length d6 of the transistor M3, DIBL of the transistor M3 can be prevented. Furthermore, even if the channel length d10 of the transistor M4 is equal to or shorter than the channel length d6 of the transistor M3, DIBL of the transistor M3 can be prevented in some cases. Furthermore, since the transistor M4 prevents a decrease in the amount of current flowing between the source and drain of the transistor M3, it is preferable that the channel width d9 of the transistor M4 be longer than the channel width d5 ​​of the transistor M3. Furthermore, even if the channel width d9 of the transistor M4 is equal to or shorter than the channel length d5 ​​of the transistor M3, a decrease in the amount of current flowing between the source and drain of the transistor M3 can be prevented in some cases.

[0393] The same applies to the transistors M1d to M6d of the driving cell IMD.

[0394] In addition, in the plan view schematic diagrams of Figures 12 and 13, each of the capacitance elements C1, C2, C1d, and C2d is a flat-plate type capacitance element, but they can be changed to a capacitance element in which a pair of electrodes and a dielectric are embedded in an opening in an insulating layer, as shown in the cross-sectional view schematic diagram of Figure 34A described later.

[0395] 12 and 13, the wirings XCL, WSL, VEI, VED, VES, and VEG are respectively provided below the wirings WCL, VEL, and VEB, but the vertical relationship of the wirings is not particularly limited. For example, one or more selected from the wirings XCL, WSL, VEI, VED, VES, and VEG can be provided above the wirings WCL, VEL, and VEB, respectively. Furthermore, the selected one or more of the above-mentioned wirings can be provided in a vertical direction (a direction approximately perpendicular to the plan view) rather than in the planar direction shown in the plan view. For example, in FIG. 12 or 13, the above-mentioned wirings can be formed using a conductive layer that can be formed vertically, such as a plug.

[0396] 1 includes one arithmetic circuit CC, but the number of arithmetic circuits CC may be two or more. Also, the arithmetic circuit CC includes one arithmetic cell IM, but the number of arithmetic cells IM may be two or more.

[0397] The arithmetic device CDVA shown in Figure 15 is a modified example of the arithmetic device CDV of Figure 1, and differs from the arithmetic device CDV of Figure 1 in that it includes a cell array CA in which multiple arithmetic circuits CC, each including multiple arithmetic cells IM, are arranged in the column direction.

[0398] 15, the cell array CA has arithmetic circuits CC_1 to CC_m (m is an integer equal to or greater than 1). Each of the arithmetic circuits CC_1 to CC_m has one driving cell IMD and n (n is an integer equal to or greater than 1) processing cells IM. As described above, in the cell array CA, m driving cells IMD are arranged in the column direction, and the processing cells IM are arranged in an m×n matrix.

[0399] 15, when only the calculation cells IM of the cell array CA are focused on, [i, j] is added to the symbol of the calculation cell IM located at the address of row i and column j (i is an integer between 1 and m, and j is an integer between 1 and n). Furthermore, calculation cells IM[1,1] to IM[m,n] have the same circuit configuration as the calculation cell IM shown in FIG. 1, and the description of the calculation cell IM in FIG. 1 can be referred to for the circuit configuration of each of calculation cells IM[1,1] to IM[m,n].

[0400] 15, when only the driver cells IMD of the cell array CA are focused on, the driver cell IMD located at the address of the i-th row is denoted by _i. Driver cells IMD_1 to IMD_m have the same circuit configuration as the driver cells IMD shown in Fig. 1, and the description of the driver cells IMD in Fig. 1 can be referred to for the circuit configuration of each of driver cells IMD_1 to IMD_m.

[0401] 1. The driver circuit WCD in the arithmetic device CDVA in FIG. 15 includes circuits WCDa_1 to WCDa_n corresponding to the circuit WCDa in FIG. 1 and switches SA_1 to SA_n corresponding to the switch SA in FIG.

[0402] 1. The driver circuit XCD in the arithmetic device CDVA in FIG. 15 includes circuits XCDa_1 to XCDa_m corresponding to the circuit XCDa in FIG.

[0403] 15 corresponds to the drive circuit WSD in Fig. 1. Therefore, the drive circuit WSD can transmit a selection signal to each of the processing cells IM and the drive cells IMD arranged in one row selected from the first to m-th rows of the cell array CA, and transmit a non-selection signal to each of the processing cells IM and the drive cells IMD arranged in the remaining rows.

[0404] 1. The driver circuit ITS in the arithmetic device CDVA in FIG. 15 includes circuits ITSa_1 to ITSa_n corresponding to the circuit ITSa in FIG. 1, and switches SB_1 to SB_n corresponding to the switch SB in FIG.

[0405] 15 correspond to the wiring WCL in Fig. 1 and extend in the column direction of the cell array CA. Also, wiring IWL_1 to wiring IWL_n shown in Fig. 15 correspond to the wiring IWL in Fig. 1, and wiring OL_1 to wiring OL_n shown in Fig. 15 correspond to the wiring OL in Fig. 1.

[0406] The wiring IWL_j is connected to the input terminal of the circuit WCDa_j, the output terminal of the circuit WCDa_j is connected to the first terminal of the switch SA_j, and the second terminal of the switch SA_j is connected to the wiring WCL_j. The wiring WCL_j is connected to each of the processing cells IM[1,j] to IM[m,j] arranged in the jth column of the cell array CA and the first terminal of the switch SB_j. The second terminal of the switch SB_j is connected to the input terminal of the circuit ITSa_j, and the output terminal of the circuit ITSa_j is connected to the wiring OL_j. The control terminal of the switch SA_j is connected to the wiring SWLA, and the control terminal of the switch SB_j is connected to the wiring SWLB.

[0407] Wirings XCL_1 to XCL_m shown in Fig. 15 correspond to the wiring XCL in Fig. 1 and extend in the row direction of the cell array CA. Wirings IXL_1 to IXL_m shown in Fig. 15 correspond to the wiring IXL in Fig. 1. Wirings WSL_1 to WSL_m shown in Fig. 15 correspond to the wiring WSL in Fig. 1 and extend in the row direction of the cell array CA.

[0408] The wiring IXL_i is connected to an input terminal of the circuit XCDa_i, and the output terminal of the circuit XCDa_i is connected to a wiring XCL_i, which is connected to the driving cell IMD_i arranged in the i-th row of the cell array CA and each of the calculation cells IM[i,1] to IM[i,n].

[0409] In the driving cell IMD_i (not shown), the gates of the transistors M1d and M2d are connected to the wiring WSL_i, and the second terminal of the capacitance element C1d, the second terminal of the transistor M2d, and the first terminal of the transistor M3d are connected to the wiring XCL_i.

[0410] In the calculation cell IM[i,j] (not shown), the gates of the transistors M1 and M2 are connected to the wiring WSL_i. The second terminal of the capacitance element C1 is connected to the wiring XCL_i. The second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring WCL_j.

[0411] Next, the writing of the first data to the arithmetic unit CDVA in FIG. 15 and the multiplication of the first data and the second data will be described.

[0412] In the calculation device CDVA of Figure 15, when the first data is written to each of the calculation cells IM[1,1] to IM[m,n], currents corresponding to the reference data r[i] flow separately from each of the circuits XCDa_1 to XCDa_m to the driving cells IMD_1 to IMD_m.

[0413] During this time, W[1,1] to W[m,n] are written separately as first data into the arithmetic cells IM[1,1] to IM[m,n], respectively. Specifically, for example, currents corresponding to W[1,1] to W[m,1] generated by the circuit WCDa_1 flow sequentially into the arithmetic cells IM[1,1] to IM[m,1] arranged in the first column, respectively. Similarly, currents corresponding to W[1,n] to W[m,n] generated by the circuit WCDa_n flow sequentially into the arithmetic cells IM[1,n] to IM[m,n] arranged in the nth column, respectively. Note that the description of the arithmetic device CDV in FIG. 1 can be referred to for the write operation.

[0414] After W[1,1] to W[m,n] are written separately as first data into the calculation cells IM[1,1] to IM[m,n], respectively, the circuits XCDa_1 to XCDa_m transmit the second data X[1] to X[m] to the driver cells IMD and calculation cells IM of each row, whereby the first data stored in each calculation cell IM[1,1] to IM[m,n] is multiplied by the transmitted second data. For example, in the calculation cell IM[i,j], W[i,j] is multiplied by X[i].

[0415] In addition, in the j-th column of the cell array CA, a current corresponding to the sum of the results of the multiplications calculated in the respective processing cells IM[1, j] to IM[m, j] flows through the wiring WCL_j. Specifically, the current flowing through the wiring WCL_j is expressed as I Ｓ When [j] is set, I Ｓ [j] can be expressed as in equation (1.13) below.

[0416]

[0417] Therefore, the amount of current flowing through the wiring WCL_j is I Ｓ [j] flows into the circuit ITSa_j, and the circuit ITSa Ｓ A value Z[j] of a function corresponding to [j] is calculated, and Z[j] is output to a wiring OL_j.

[0418] As a result, Z[j] can be expressed as in the following equation (1.14) using each of the above equations (1.13). By arranging the arithmetic cells IM in an m×n matrix in this way, it is possible to perform a multiply-and-accumulate operation between the first data W[1,j] to W[m,j] and the second data X[1] to X[m] in the j-th column of the cell array CA, and to calculate a function according to the result. Furthermore, since the arithmetic cells IM of the arithmetic device CDVA of FIG. 15 are arranged in n columns, it is possible to perform n multiply-and-accumulate operations and to calculate a function according to the result.

[0419]

[0420] Furthermore, Z[j] is output to the outside via a wiring OL_j.

[0421] In particular, the arithmetic unit CDVA is suitable for performing calculations on a fully connected layer neural network. For example, by storing weight coefficients as first data in each arithmetic cell IM of the cell array CA of the arithmetic unit CDVA and inputting the value of an input signal to a neuron as second data to the wiring XCL, a product-sum operation can be performed on the weight coefficients and the input signal to the neuron. Furthermore, by using the circuit ITSa_j as an operation circuit for an activation function applied to the fully connected layer neural network, the value of the activation function can be output using the result of the product-sum operation as an input value. This value can then be input to the next hidden layer, output layer, etc.

[0422] The arithmetic unit CDVA can also suitably perform calculations of a convolutional neural network. In particular, since the arithmetic cell IM of the cell array CA of the arithmetic unit CDVA can hold the first data for a long period of time, it is preferable to use the first data as a filter value used in the convolution process. In the convolution process of the convolutional neural network, the same filter value is multiplied by multiple image data, so it can be said that the arithmetic cell IM of the arithmetic unit CDVA is suitable as a multiplication cell that can hold a filter value for a long period of time.

[0423] <Configuration Example 3 of Arithmetic Device> Next, an arithmetic device according to one embodiment of the present invention, which is different from the arithmetic device CDV and the arithmetic device CDVA, will be described.

[0424] 16 is a circuit diagram showing the circuit configuration of a calculation device CDVB, which is different from the calculation devices CDV and CDVA. The calculation device CDVB is a calculation device that can multiply first data, which is 0, a negative number, or a positive number, by second data, which is 0 or a positive number.

[0425] The cell array CA in Figure 16 shows a driving cell IMD_i located in the i-th row and an operation cell IM[i, j] located at the address of the i-th row and j-th column, but in the description of the operation device CDVB in this specification, unless otherwise specified, they will be referred to as the driving cell IMD and the operation cell IM, respectively.

[0426] In the arithmetic device CDVB, the arithmetic cell IM differs from the arithmetic device CDVA in that it includes transistors M1p, M2p, M3p, capacitive elements C1p, C2p, an amplifier circuit SF, transistors M1n, M2n, M3n, capacitive elements C1n, C2n, and an amplifier circuit SFn. In other words, the arithmetic cell IM in the arithmetic device CDVB differs from the arithmetic device CDV in FIG. 1 in the number of circuit elements included in the arithmetic cell IM.

[0427] The transistors M1p and M1n correspond to the transistor M1 in the arithmetic unit CDV of Fig. 1, the transistors M2p and M2n correspond to the transistor M2 in the arithmetic unit CDV of Fig. 1, and the transistors M3p and M3n correspond to the transistor M3 in the arithmetic unit CDV of Fig. 1. Furthermore, the capacitive elements C1p and C1n correspond to the capacitive element C1 in the arithmetic unit CDV of Fig. 1, and the capacitive elements C2p and C2n correspond to the capacitive element C2 in the arithmetic unit CDV of Fig. 1. Furthermore, the amplifier circuits SFp and SFn correspond to the amplifier circuit SF in the arithmetic unit CDV of Fig. 1.

[0428] For this reason, it can be said that the calculation cell IM in the calculation device CDVB has two calculation cells IM in the calculation device CDV of Fig. 1. Specifically, the transistors M1p, M2p, M3p, the capacitance elements C1p, C2p, and the amplifier circuit SF form one calculation cell IM in the calculation device CDV of Fig. 1, and the transistors M1n, M2n, M3n, the capacitance elements C1n, C2n, and the amplifier circuit SFn form one calculation cell IM in the calculation device CDV of Fig. 1.

[0429] Therefore, the calculation cell IM in the calculation device CDVB can hold two pieces of data.

[0430] Here, the value of the first data held in the calculation cell IM is defined as follows.

[0431] When α is written to the operation cell IM as the value of the positive first data, the amount of current flowing between the source and drain of the transistor M3p of the operation cell IM is |α|×I ０ At this time, the potential between the first terminal of the capacitance element C1p and the gate of the transistor M3p is set to the amount of source-drain current |α|×I ０ The amount of current flowing between the source and drain of the transistor M3n of the processing cell IM is set to 0. ０ is the amount of current that flows when the absolute value of the first data (in this case, α[i, j]) is 1, and is the same as I ０ is.

[0432] Furthermore, when α is written to the calculation cell IM as the negative first data value, the amount of current flowing between the source and drain of the transistor M3n of the calculation cell IM is |α|×I ０ At this time, the potential between the first terminal of the capacitance element C1n and the gate of the transistor M3n is set to the amount of source-drain current |α|×I ０ The amount of current flowing between the source and drain of the transistor M3p of the processing cell IM is set to zero.

[0433] Furthermore, when 0 is written as the first data into the operation cell IM, the amount of current flowing between the source and drain of each of the transistors M3p and M3n of the operation cell IM is set to 0.

[0434] When the amount of current flowing between the source and drain of transistor M3p of the processing cell IM is set to 0, this specification may refer to a case where a current of 0 flows between the source and drain of transistor M3p. Similarly, when the amount of current flowing between the source and drain of transistor M3n of the processing cell IM is set to 0, this specification may refer to a case where a current of 0 flows between the source and drain of transistor M3n.

[0435] As described above, the arithmetic cell IM in the arithmetic device CDVB can store first data of 0, a negative number, or a positive number according to the potentials of the first terminal of the capacitive element C1p and the first terminal of the read-capacitive element C1n by maintaining the respective potentials of the first terminal and the read-capacitive element C1n. Because different potentials must be written to the first terminal of the capacitive element C1p and the first terminal of the read-capacitive element C1n, the arithmetic cell IM requires two wirings for transmitting data (wirings that function as the wirings WCL in the arithmetic device CDV). The arithmetic device CDVB has wirings WCLp and WCLn as these wirings. Note that in FIG. 16 , as wirings extending to the jth column, the wiring WCLp is referred to as wiring WCLp_j, and the wiring WCLn is referred to as wiring WCLn_j.

[0436] The wiring WCLp is connected to the first terminal of the transistor M3p and the second terminal of the transistor M2p, and the wiring WCLn is connected to the first terminal of the transistor M3p and the second terminal of the transistor M2p.

[0437] The drive circuit WCD of the arithmetic unit CDVB has a circuit WCDp and a circuit WCDn corresponding to the circuit WCDa of the arithmetic unit CDV. The circuit SWCA included in the drive circuit WCD has a switch SAp and a switch SAn corresponding to the switch SA of the arithmetic unit CDV. In FIG. 16, the switch SAp is denoted as switch SAp_j and the switch SAn is denoted as switch SAn_j, as switches arranged in the jth column.

[0438] The circuit WCDp has a function of causing an analog current corresponding to digital data input to the wiring IWLp to flow to the wiring VEL via the wiring WCLp and the source-drain of the transistor M3p. Similarly, the circuit WCDn has a function of causing an analog current corresponding to digital data input to the wiring IWLn to flow to the wiring VEL via the wiring WCLn and the source-drain of the transistor M3n. Therefore, when α is a positive number as the first data, digital data with a value of |α| is transmitted to the wiring IWLp, and digital data with a value of 0 is transmitted to the wiring IWLn. Furthermore, when α is a negative number as the first data, digital data with a value of 0 is transmitted to the wiring IWLp, and digital data with a value of |α| is transmitted to the wiring IWLn. Furthermore, when the first data is a number of 0, digital data with a value of 0 is transmitted to both the wiring IWLp and the wiring IWLn.

[0439] When the first data is being written to the calculation cell IM, the switches SAp and SAn are each in the ON state, and the switches SBp and SBn are each in the OFF state, similar to the operation method of the calculation device CDV.

[0440] After the first data is held, a current corresponding to the second data flows through the line XCL, causing the calculation cell IM to multiply the first data by the second data. In the calculation cell IM of the calculation device CDVB, a potential corresponding to the current is input to the second terminal of the capacitance element C1p and the second terminal of the capacitance element C1n. As a result, the amount of current between the source and drain of the transistor M3p is amplified by the capacitive coupling of the capacitance element C1p, and the amount of current between the source and drain of the transistor M3n is amplified by the capacitive coupling of the capacitance element C1n.

[0441] Here, the current according to the second data is βI ０ When the first data α is a positive number, the amount of current Ip flowing between the source and drain of the transistor M3p is expressed as αβI ０and the amount of current In flowing between the source and drain of the transistor M3n becomes 0. At this time, a current of amount Ip flows from a terminal RTip of a circuit ITSpn (described later) to the wiring VEL via the switch SBp and the transistor M3p.

[0442] Furthermore, when the first data α is a negative number, the amount of current Ip flowing between the source and drain of the transistor M3p is 0, and the amount of current In flowing between the source and drain of the transistor M3n is αβI ０ At this time, a current of the amount In flows from a terminal RTin of a circuit ITSpn (described later) to a wiring VEL via a switch SBn and a transistor M3n.

[0443] When the multiplied data is transmitted from the arithmetic cell IM to the drive circuit ITS, the switches SBp and SBn (described later) are in the on state, and the switches SAp and SAn are in the off state, similar to the operation method of the arithmetic device CDV.

[0444] The drive circuit ITS of the arithmetic unit CDVB includes a circuit ITSpn corresponding to the circuit ITSa of the arithmetic unit CDV. The circuit SWCA included in the drive circuit ITS includes switches SBp and SBn corresponding to the switches SB of the arithmetic unit CDV. In FIG. 16, the switches SBp and SBn arranged in the j-th column are denoted as switch SBp_j and switch SBn_j, respectively.

[0445] The circuit ITSpn has terminals RTip, RTin, and RTo, and has the function of obtaining the difference between the amount of current input to terminal RTip and the amount of current input to terminal RTin, and outputting data corresponding to the difference to terminal RTo.

[0446] The terminal RTip is connected to the second terminal of the switch SBp, the terminal RTin is connected to the second terminal of the switch SBn, and the terminal RTo is connected to the line OL.

[0447] Here, when the cell array CA includes m rows of arithmetic circuits CC, a current corresponding to the result of a sum-of-products operation between the first data (positive numbers) and the second data transmitted to each row flows through the terminal RTip of the circuit ITSpn, and a current corresponding to the result of a sum-of-products operation between the first data (negative numbers) and the second data transmitted to each row flows through the terminal RTin of the circuit ITSpn. By calculating the difference between the currents flowing through the wiring WCLp and the wiring WCLn, the circuit ITSpn can obtain a current corresponding to the result of a sum-of-products operation between the first data (0, negative numbers, or positive numbers) and the second data (0 or positive numbers). This allows the circuit ITSpn to convert or generate data according to the current and output it to the terminal RTo.

[0448] <<Circuit ITSpn>> Next, a circuit configuration that can be applied to the circuit ITSpn will be described.

[0449] 17 has a function of obtaining the difference between the currents flowing through the wirings WCLp and WCLn and outputting the difference as an analog current. Note that the circuit ITSpn shown in Fig. 17 is, as an example, a modified version of the circuit RL shown in Fig. 6, and only the parts that differ from the circuit RL in Fig. 6 will be described here.

[0450] Unlike the circuit RL in Fig. 6, the circuit ITSpn in Fig. 17 does not include a current source CNI. Furthermore, the terminal RTip of the circuit ITSpn corresponds to the terminal RTi shown in Fig. 6. Furthermore, the first terminal of the transistor Mp1o, the first terminal of the transistor MN2i, the gate of the transistor MN1i, and the gate of the transistor MN1o are connected to the terminal RTin.

[0451] A current I corresponding to the result of multiplying and accumulating the positive first data and the second data transmitted to each row in the cell array CA flows through the terminal RTip. Ｓｐ The current flows to the wiring WCLp. The terminal RTin receives a current I corresponding to the result of multiplying and accumulating the negative first data and the second data transmitted to each row in the cell array CA. Ｓｎ The current flows to the wiring WCLn.

[0452] Since the transistors MP1i, MP2i, MP1o, and MP2o each constitute a current mirror circuit, the amount of current I flowing through the terminal RTip Ｓｐ Ideally, the amount of current flowing between the source and drain of the transistor MP2o and the transistor MP1o is equal to the amount of current flowing between the source and drain of the transistor MN2i and the transistor MN1i. Ｓｐ -I Ｓｎ (=I Ｓ The current flow is I Ｓｐ Ga I Ｓｎ In the circuit configuration shown in FIG. Ｓ will be 0.

[0453] Since the transistors MN1i, MN2i, MN1o, and MN2o also form a current mirror circuit, the amount of current I flowing between the source and drain of the transistors MN2i and MN1i is Ｓ Ideally, the amount of current I flowing between the source and drain of the transistor MN1o and the transistor MN2o is Ｓ is equal to

[0454] Furthermore, since the transistors MP3i, MP4i, MP3o, and MP4o also form a current mirror circuit, the amount of current I flowing between the source and drain of the transistors MN3i and MN4i is Ｓ Ideally, the amount of current I flowing between the source and drain of the transistor MN3o and the transistor MN4o is Ｓ is equal to

[0455] As a result, the circuit ITSpn in FIG. 17 outputs I Ｓｐ and I Ｓｎ is the differential current I Ｓ This allows the circuit ITSpn to output the result of the product-sum operation by the cell array CA as an analog current.

[0456] Next, a description will be given of an example of the configuration of a circuit that is different from the circuit ITSpn in FIG. 17 and that can be applied to the circuit ITSpn of the arithmetic unit CDV in FIG.

[0457] 18 has a function of obtaining a difference between the currents flowing through the wirings WCLp and WCLn and outputting a value corresponding to the difference as digital data. The circuit ITSpn shown in FIG. 18 is also sometimes called a successive approximation register (SAR) type ADC (analog to digital converter).

[0458] As an example, the circuit ITSpn shown in FIG. 18 includes transistors MP5i, MP6i, MP5o, and MP6o included in a first current mirror circuit, and transistors MP7i, MP8i, MP7o, and MP8o included in a second current mirror circuit.

[0459] 18 includes a first digital potential-analog current converter circuit and a second digital potential-analog current converter circuit. The first digital potential-analog current converter circuit includes transistors Tp1[1] to Tp1[M] (M is an integer of 1 or more) and transistors Tp2[1] to Tp2[M]. The second digital potential-analog current converter circuit includes transistors Tn1[1] to Tn1[M] and transistors Tn2[1] to Tn2[M].

[0460] Note that the transistors Tp1[s] (here, s is an integer between 1 and M) and the transistor Tp2[s] correspond to the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 4 . The transistors Tn1[s] and Tn2[s] also correspond to the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 4 . Therefore, the transistors Tp1[1] to Tp1[M] and the transistors Tn1[1] to Tn1[M] each function as a transistor that passes a constant current according to its channel width. The transistors Tp2[1] to Tp2[M] and the transistors Tn2[1] to Tn2[M] each function as a switching transistor.

[0461] Here, when the channel width of the transistor Tp1[1] and the transistor Tn1[1] is w[1], the channel width of the transistor Tp1[2] and the transistor Tn1[2] is w[2], and the channel width of the transistor Tp1[M] and the transistor Tn1[M] is w[M], the ratio of the respective channel widths is w[1]:w[2]:w[M]=1:2:2. Ｍ−１ Let's say.

[0462] 18 includes a comparator CPR and a logic circuit LGC. The logic circuit LGC includes a terminal LTi, a terminal LFTp, a terminal LFTn, and a terminal LTo.

[0463] A first terminal of the transistor MP5i is connected to the terminal RTip, the gate of the transistor MP6i, the gate of the transistor MP6o, and the first terminals of the transistors Tp2[1] to Tp2[M]. A second terminal of the transistor MP5i is connected to the first terminal of the transistor MP6i, and a gate of the transistor MP5i is connected to the gate of the transistor MP5o and the wiring RSWLp.

[0464] A first terminal of the transistor MP7i is connected to the terminal RTin, the gate of the transistor MP8i, the gate of the transistor MP8o, and the first terminals of the transistors Tn2[1] to Tn2[M]. A second terminal of the transistor MP7i is connected to the first terminal of the transistor MP8i, and a gate of the transistor MP7i is connected to the gate of the transistor MP7o and the wiring RSWLn.

[0465] For the wirings RSWLp and RSWLn, the description of the wirings RSWL1 to RSWL3 shown in FIG. 6 can be referred to.

[0466] A first terminal of the transistor MP5o is connected to a first terminal of the comparator CPR, a second terminal of the transistor MP5o is connected to a first terminal of the transistor MP6o, a first terminal of the transistor MP7o is connected to a second terminal of the comparator CPR, and a second terminal of the transistor MP7o is connected to a first terminal of the transistor MP8o. In addition, second terminals of the transistors MP6i, MP6o, MP8i, and MP8o are connected to the wiring VDDL.

[0467] For the wiring VDDL, the description of the wiring VDDL shown in FIG. 6 can be referred to.

[0468] The second terminal of the transistor Tp2[s] is connected to the first terminal of the transistor Tp1[s]. The gates of the transistors Tp2[1] to Tp2[M] are connected to the terminal LFTp of the logic circuit LGC. The second terminals of the transistors Tp1[1] to Tp1[M] are connected to the wiring VSSL. The gates of the transistors Tp1[1] to Tp1[M] are connected to the wiring VFE.

[0469] The second terminal of the transistor Tn2[s] is connected to the first terminal of the transistor Tn1[s]. The gates of the transistors Tn2[1] to Tn2[M] are connected to the terminal LFTn of the logic circuit LGC. The second terminals of the transistors Tn1[1] to Tn1[M] are connected to the wiring VSSL. The gates of the transistors Tn1[1] to Tn1[M] are connected to the wiring VFE.

[0470] For the wiring VSSL, the description of the wiring VSSL shown in Fig. 6 can be referred to. For the wiring VFE, the description of the wiring BIS shown in Fig. 4 can be referred to.

[0471] The output terminal of the comparator CPR is connected to the terminal LTi of the logic circuit LGC, and the terminal LTo of the logic circuit LGC is connected to the terminal RTo. ＦＳｐ The current I input to the second input terminal is ＦＳｎ When is small, the current I input to the first input terminal ＦＳｐ and the current I input to the second input terminal ＦＳｎ When the values ​​are equal to each other, a high level potential is output to the output terminal, or the current I input to the first input terminal is ＦＳｐ The current I input to the second input terminal is ＦＳｎ is large, it has the function of outputting a low level potential to the output terminal.

[0472] The logic circuit LGC has the function of obtaining the comparison result of the comparator CPR from the terminal LTi, and outputting a digital signal Q to each of the terminals LFTp and LFTn according to the comparison result, and the function of outputting digital data to the terminal LTo according to the comparison result.

[0473] Next, an example of the operation of the circuit ITSpn in FIG. 18 will be described, including the detailed operation of the logic circuit LGC.

[0474] 19 is a timing chart showing an example of the operation of the circuit ITSpn in FIG. 18. The timing chart in FIG. 19 shows the operation of the current I Ｓｐis the current I input to the terminal RTin Ｓｎ This is an example of operation when the current I ＦＳｐ and current I ＦＳｎ , the fluctuation of the potential input to the terminal LTi in the logic circuit LGC, and the fluctuation of the logic of the signal Q output from the terminal LFTp. ＦＳｐ is the amount of current input to the first input terminal of the comparator CPR, and the current I ＦＳｎ is the amount of current input to the second input terminal of the comparator CPR.

[0475] In the timing chart of Fig. 19, the ordinal number M described in the circuit ITSpn of Fig. 18 is set to 8. In this case, the resolution of each of the first digital potential-analog current conversion circuit and the second digital potential-analog current conversion circuit is 8 bits. Furthermore, the amount of current output by each of the first digital potential-analog current conversion circuit and the second digital potential-analog current conversion circuit is, for example, in the range from 0 nA to 255 nA in increments of 1 nA.

[0476] Furthermore, the logic of the b-th bit (b is an integer between 0 and 7) of the digital signal Q output from the logic circuit LGC to each of the terminals LFTp and LFTn is defined as Q[b].

[0477] During the period T0, the logic circuit LGC outputs (00000000) as 8-bit digital signals Qp and Qn to the terminals LFTp and LFTn, respectively. ２ As a result, a low-level potential is input to the gates of the transistors Tp2[1] to Tp2[8] of the first digital potential-analog current conversion circuit, turning these transistors off. Similarly, a low-level potential is input to the gates of the transistors Tn2[1] to Tn2[8] of the second digital potential-analog current conversion circuit, turning these transistors off.

[0478] At this time, the terminal RTip receives the amount I from the cell array CA. ＳｐA current of I flows from the cell array CA to the terminal RTin. Ｓｎ Here, a current of I Ｓｐ = 203 nA, and I Ｓｐ At this time, the first input terminal of the comparator CPR is supplied with a quantity I Ｓｐ A current of the magnitude I flows through the second input terminal of the comparator CPR. Ｓｎ At this time, a current of I ＦＳｐ is I ＦＳｎ , the comparator CPR outputs a high-level potential to the output terminal, which causes the high-level potential to be input to the terminal LTi of the logic circuit LGC.

[0479] During the period T1, the logic circuit LGC outputs (10000000) as an 8-bit digital signal Qp to the terminal LFTp. ２ In other words, the logic of the seventh bit of the digital signal Qp changes from "0" to "1". As a result, a high level potential is input only to the gate of the transistor Tp2[8] of the first digital potential-analog current conversion circuit, and a current of 128 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[8] and the transistor Tp2[8]. As a result, I ＦＳｐ = 203 - 128 = 75 nA, and I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0480] If the potential of the terminal LTi changes from the initial state potential during the period T1, the logic of the seventh bit Q[7] of the digital signal Qp is set to "0" after the period T1. Also, if the potential of the terminal LTi does not change from the initial state potential, the logic of the seventh bit Q[7] of the digital signal Qp is set to "1" after the period T1. In this operation example, the logic of Q[7] is "0" after the period T1.

[0481] During the period T2, the logic circuit LGC outputs (01000000) as an 8-bit digital signal Qp to the terminal LFTp. ２That is, in the digital signal Qp, the logic of the seventh bit changes from "1" to "0", and the logic of the sixth bit changes from "0" to "1". As a result, a high-level potential is input only to the gate of the transistor Tp2[7] of the first digital potential-analog current conversion circuit, and a current of 64 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[7] and the transistor Tp2[7]. As a result, I ＦＳｐ = 203 - 64 = 139 nA, and I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0482] If the potential of the terminal LTi changes from the initial state potential during the period T2, the logic of the sixth bit Q[6] of the digital signal Qp is set to "0" after the period T2. Also, if the potential of the terminal LTi does not change from the initial state potential, the logic of the sixth bit Q[6] of the digital signal Qp is set to "1" after the period T2. In this operation example, the logic of Q[6] is "0" after the period T2.

[0483] During the period T3, the logic circuit LGC outputs (00100000) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the sixth bit changes from "1" to "0", and the logic of the fifth bit changes from "0" to "1". As a result, a high-level potential is input only to the gate of the transistor Tp2[6] of the first digital potential-analog current conversion circuit, and a current of 32 nA flows from the first terminal of the transistor MP5i to the wiring VSSL through the source-drain of the transistor Tp1[6] and the transistor Tp2[6]. As a result, I ＦＳｐ = 203 - 32 = 171 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0484] In the period T3, if the potential of the terminal LTi changes from the potential in the initial state, after the period T3, the digital signal Q ｐ In addition, if the potential of the terminal LTi does not change from the potential in the initial state, after the period T3, the logic of the fifth bit Q[5] of the digital signal Q ｐ The logic of the fifth bit Q[5] is set to "1." In this operation example, the logic of Q[5] is set to "1" after the period T3.

[0485] During the period T4, the logic circuit LGC outputs (00110000) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the fourth bit changes from "0" to "1". As a result, a high level potential is input only to the gates of the transistors Tp2[6] and Tp2[5] of the first digital potential-analog current conversion circuit, and a current of 32+16=48 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 48 = 155 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0486] In the period T4, if the potential of the terminal LTi changes from the potential in the initial state, after the period T4, the digital signal Q ｐ The logic of the fourth bit Q[4] of the digital signal Q is set to "0". Also, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the fourth bit Q[4] of the digital signal Q is set to "1" after the period T4. In this operation example, the logic of Q[4] is "1" after the period T4.

[0487] During the period T5, the logic circuit LGC outputs (00111000) to the terminal LFTp as an 8-bit digital signal Qp. ２That is, in the digital signal Qp, the logic of the third bit changes from "0" to "1". As a result, a high-level potential is input only to the gates of the transistors Tp2[4] to Tp2[6] of the first digital potential-analog current conversion circuit, and a current of 32+16+8=56 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 56 = 147 nA, and I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0488] In the period T5, if the potential of the terminal LTi changes from the potential in the initial state, after the period T5, the digital signal Q ｐ The logic of the third bit Q[3] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the third bit Q[3] of the digital signal Q is set to "1" after the period T5. In this operation example, the logic of Q[3] is "0" after the period T5.

[0489] During the period T6, the logic circuit LGC outputs (00110100) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the third bit changes from "1" to "0", and the logic of the second bit changes from "0" to "1". As a result, a high-level potential is input only to the gates of the transistors Tp2[6], Tp2[5], and Tp2[3] of the first digital potential-analog current conversion circuit, and a current of 32+16+4=52 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 52 = 151 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is input to the terminal LTi of the logic circuit LGC.

[0490] In the period T6, if the potential of the terminal LTi changes from the potential in the initial state, after the period T6, the digital signal Q ｐ The logic of the second bit Q[2] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the second bit Q[2] of the digital signal Q is set to "1" after the period T6. In this operation example, the logic of Q[2] is "1" after the period T6.

[0491] During the period T7, the logic circuit LGC outputs (00110110) to the terminal LFTp as an 8-bit digital signal Qp. ２ That is, in the digital signal Qp, the logic of the first bit changes from "0" to "1". As a result, a high level potential is input only to the gates of the transistors Tp2[6], Tp2[5], Tp2[3], and Tp2[2] of the first digital potential-analog current conversion circuit, and a current of 32+16+4+2=54 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 54 = 149 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a low level potential, which is input to the terminal LTi of the logic circuit LGC.

[0492] In the period T7, if the potential of the terminal LTi changes from the potential in the initial state, after the period T7, the digital signal Q ｐ The logic of the first bit Q[1] of the digital signal Q is set to "0". Also, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the first bit Q[1] of the digital signal Q is set to "1" after the period T7. In this operation example, the logic of Q[1] is "0" after the period T7.

[0493] During the period T8, the logic circuit LGC outputs (00110101) to the terminal LFTp as an 8-bit digital signal Qp. ２That is, in the digital signal Qp, the logic of the 0th bit changes from "0" to "1". As a result, a high level potential is input only to the gates of the transistors Tp2[6], Tp2[5], Tp2[3], and Tp2[1] of the first digital potential-analog current conversion circuit, and a current of 32+16+4+1=53 nA flows from the first terminal of the transistor MP5i to the wiring VSSL. As a result, I ＦＳｐ = 203 - 53 = 150 nA, and I ＦＳｎ =150 nA, the output terminal of the comparator CPR outputs a high-level potential, which is then input to the terminal LTi of the logic circuit LGC.

[0494] In the period T8, if the potential of the terminal LTi changes from the potential in the initial state, after the period T8, the digital signal Q ｐ The logic of the 0th bit Q[0] of the digital signal Q is set to "0". Furthermore, if the potential of the terminal LTi has not changed from the potential in the initial state, the logic of the 0th bit Q[0] of the digital signal Q is set to "1" after the period T8. In this operation example, the logic of Q[0] is "1" after the period T8.

[0495] During the period T9, the logic circuit LGC outputs (00000000) to the terminal LFTp as an 8-bit digital signal Qp. ２ As a result, the current supply from the first digital potential-analog current conversion circuit is stopped, and I ＦＳｐ = 203 nA. Therefore, I ＦＳｎ = 150 nA, the output terminal of the comparator CPR outputs a high level potential.

[0496] During the period T9, the terminal LTo of the logic circuit LGC outputs the digital signal Qp (00110101). ２ This outputs I Ｓｐ = 203 nA and I Ｓｎ The differential current of 53 nA, which is 150 nA, is converted into digital data.

[0497] As described above, by operating the circuit ITSpn of FIG. Ｓｐ and IＳｎ The differential current of can be output as digital data.

[0498] The above is I Ｓｐ Ga I Ｓｎ This is an example of operation assuming that I is larger than Ｓｎ Ga I Ｓｐ If the value is larger than , it can be understood by changing the terms appropriately.

[0499] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0500] Second Embodiment In this embodiment, a convolutional neural network, which is a type of artificial neural network, will be described. Note that by using the arithmetic device described in the above embodiment, it is possible to suitably perform calculations for the convolutional neural network.

[0501] AlexNet will be described as an example of a convolutional neural network. AlexNet is an artificial neural network model shown in Figure 20. AlexNet includes an input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, PL5, and fully connected layers FC6 to FC8. As shown in Figure 20, AlexNet is configured in the following order: input layer INLY, convolutional layer CNV1, pooling layer PL1, convolutional layer CNV2, pooling layer PL2, convolutional layer CNV3, convolutional layer CNV4, convolutional layer CNV5, pooling layer PL5, fully connected layer FC6, fully connected layer FC7, and fully connected layer FC8.

[0502] [Input Layer INLY] As an input to AlexNet, the input layer INLY includes, for example, a 224×224 pixel image P ｉｎIt is assumed that one pixel includes red, green, and blue sub-pixels, and the total number of sub-pixels is 3 colors (red, green, blue) x 224 x 224. ｉｎ The number of channels of the image P is three, namely red, green and blue. ｉｎ The number of image data to the input layer INLY included in is 3×224×224.

[0503] In this example, the image P ｉｎ In this case, the input value in the xth row and yth column included in the zth input channel (where z is an integer between 1 and 3) is expressed as p ｉｎ It is written as [x, y, z]. Note that x is the ｉｎ and y indicates the address of the row of the image P ｉｎ That is, in the input layer INLY, x is an integer between 1 and 224, and y is an integer between 1 and 224.

[0504] [Convolutional Layer CNV1] In the convolutional layer CNV1, image P ｉｎ Specifically, a filter (also called a kernel) used in the convolution process CNV1 and the image P ｉｎ Region A selected from ｉｎ The image data included in is subjected to a multiplication and accumulation operation.

[0505] In the convolution layer CNV1, the filter size (also called kernel size) is 11, the number of output channels (also called kernel number) is 96, and the stride is 4. ｉｎ The convolution process is performed on the region selected from the above. The number of filter values ​​in one kernel is (filter size) ２ × (number of input channels) Image P ｉｎ Since the number of input channels is 3, the number of filter values ​​for one kernel in the convolutional layer CNV1 is 11 × 11 × 3 = 363.

[0506] Here, the sth (here, s is an integer between 1 and 96) kernel in the convolution layer CNV1 is K Ｃ１ （ｓ）Also, kernel K Ｃ１ The filter values ​​contained in Ｃ１ （ｓ） It is written as [p, q, r], where p indicates the row address of the kernel, q indicates the column address of the kernel, and r indicates the ordinal number of the input channel. That is, in the convolution layer CNV1, p is an integer between 1 and 11, q is an integer between 1 and 11, and r is an integer between 1 and 3.

[0507] For example, in FIG. ｉｎ Region A selected from ｉｎ (1) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１ （１） This shows an example of outputting (1). ｉｎ The x in (x) is the image P ｉｎ The data p Ｃ１ （ｓ） The s in (x) indicates the ordinal number of the output channel. Ｃ１ （ｓ） The x in (x) is the area A ｉｎ It corresponds to the ordinal number x in (x).

[0508] Also, since the stride is 4, area A ｉｎ The area shifted four positions in the row direction from (1) is area A. ｉｎ For example, in FIG. ｉｎ Region A selected from ｉｎ (2) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１ （１） An example of outputting (2) is shown.

[0509] In addition, image P ｉｎ If the number of pixels in image P is 224x224 and the stride is 4, ｉｎ The number of regions to be selected is 3025 (=55 ２ ) In this embodiment, the area A ｉｎ (1) to area Aｉｎ It is called (3025).

[0510] As described above, depending on the number of strides, the image P ｉｎ The region selected from is shifted sequentially, and each time the region is shifted, the region and the kernel K Ｃ１ （１） By performing a product-sum operation with K, a matrix of output data with 55 rows and 55 columns is obtained. In addition, the kernel included in the convolution layer CNV1 is the kernel K Ｃ１ （１） Kernel K Ｃ１ （９６） (because the number of kernels in the convolutional layer CNV1 is 96), as a result, the convolutional layer CNV1 outputs 55 × 55 × 96 output data, P Ｃ１ will be output.

[0511] In the convolution process in the convolution layer CNV1, for one kernel, ｉｎ For this reason, the calculation circuit may be configured to, for example, calculate the product of a filter value included in one kernel and the product of a region of the image P ｉｎ It is preferable to simultaneously perform the multiplication of the data included in each of the selected regions from .

[0512] For example, in the configuration of the calculation device CDVA shown in FIG. 15, the kernel K Ｃ１ （１） It is preferable that 11×11×3=363 filter values ​​included in the above are written in the calculation cells IM[1,1] to IM[m,1] (where m is an integer equal to or greater than 11×11×3=363) in the first column of the cell array CA. ｉｎ Region A selected from ｉｎ (1) is preferably input. This allows the kernel K Ｃ１ （１） and area A ｉｎThe circuit ITSa can perform the product-sum operation of (1). Note that, at this time, each of the circuits ITSa_1 to ITSa_n of the driver circuit ITS is preferably configured to perform an identity function operation as an activation function. In other words, the circuit ITSa preferably has a function of outputting to an output terminal a value that is the same as a value input to an input terminal. Furthermore, the circuit ITSa can output the value as a current or a voltage to the output terminal.

[0513] In the above, attention has been focused on the calculation cells IM[1,1] to IM[m,1] in the first column of the cell array CA, but it is possible to write the filter value of another kernel in columns other than the first column. For example, in the configuration of the calculation device CDVB shown in FIG. 15, Ｃ１ （ｊ） (where j is an integer between 1 and 96) is preferably written to each of the calculation cells IM[1,j] to IM[m,j] arranged in the j-th column of the cell array CA. In other words, the calculation device CDVB shown in FIG. 15 can write a different kernel filter value for each column. For this reason, it is preferable that the number of columns n of the cell array CA is 96 or more. As a result, for example, the area A input as the second data ｉｎ (1) and the kernel K held for each column Ｃ１ （１） ~K Ｃ１ （９６） The filter values ​​of and the multiplication and accumulation operations can be performed simultaneously.

[0514] In the arithmetic device CDVA of FIG. 15, each of the circuits XCDa_1 to XCDa_m includes an area A ｉｎ (1) to area A ｉｎ (3025) are input sequentially to obtain the kernel K Ｃ１ （１） ~K Ｃ１ （９６） It is possible to perform a multiply-and-accumulate operation between each of the above and each region.

[0515] For example, consider a cell array CA in which the processing cells IM are arranged in a 363×96 matrix as shown in FIG. 23. The kernel K is assigned to each of the processing cells IM[1,1] to IM[363,1] arranged in the first column of the cell array CA. Ｃ１ （１） As the filter value of Ｃ１ （１） [1,1,1] to k Ｃ１ （１） [11, 11, 3] are written separately. In addition, the kernel K Ｃ１ （９６） As the filter value of Ｃ１ （９６） [1,1,1] to k Ｃ１ （９６） Similarly, the kernel K is written to each of the second to 95th columns of the cell array CA. Ｃ１ （２） ~K Ｃ１ （９６） are written separately.

[0516] Then, the wirings XCL_1 to XCL_363 are respectively connected to the region A ｉｎ As the respective values ​​of (1), a ｉｎ (1) [1, 1, 1] to a ｉｎ (1) By inputting [11, 11, 3] separately, the wiring WCL_1 to the kernel K Ｃ１ （１） and area A ｉｎ p, which is the result of the multiplication and addition operation of (1), ｃ１ （１） (1) is output, and the kernel K Ｃ１ （９６） and area A ｉｎ p, which is the result of the multiplication and addition operation of (1), ｃ１ （９６） (1) is output.

[0517] Next, the region A connected to the wirings XCL_1 to XCL_363 ｉｎ (1) into area A ｉｎSpecifically, as shown in FIG. 24, the wirings XCL_1 to XCL_363 are each provided with a region A ｉｎ (2) As the respective values ​​of area A ｉｎ As the value of (2), a ｉｎ (2) [1, 1, 1] to a ｉｎ (2) [11, 11, 3] are input separately. This allows the wiring WCL_1 to be connected to the kernel K Ｃ１ （１） and area A ｉｎ p, which is the result of the multiplication and addition operation of (2) ｃ１ （１） (2) is output, and the kernel K Ｃ１ （９６） and area A ｉｎ p, which is the result of the multiplication and addition operation of (2) ｃ１ （９６） (2) is output.

[0518] Hereafter, area A ｉｎ (3) to A ｉｎ Similarly, for (3025), by sequentially inputting to the wirings XCL_1 to XCL_363, ｃ１ （１） (3) to p ｃ１ （９６） From the set (3), p ｃ１ （１） (3025) to p ｃ１ （９６） The results of the sum-of-products operation of (3025) sets can be output.

[0519] As described above, by using the arithmetic device according to one embodiment of the present invention, the area A ｉｎ (1) to area A ｉｎ (3025) and kernel K Ｃ１ （１） ~K Ｃ１ （９６） The filter value of and the output data P from the convolution layer CNV1 are input. Ｃ１ can be obtained.

[0520] [Pooling Layer PL1] In the pooling layer PL1, P Ｃ１Pooling is performed on the data. Pooling is a process in which predetermined regions are sequentially selected from the data output from the convolution layer, and predetermined processing is performed on each region to extract features, which are then arranged in a matrix.

[0521] As shown in FIG. 20, in the pooling layer PL1, the kernel size is set to 3, and the data P Ｃ１ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0522] For example, in FIG. 25A, data P Ｃ１ Region A selected from the first input channel of Ｃ１ｉｎ （１） In (1), the maximum pooling process is performed, and the processed data p ｐ１ （１） In this example, the kernel size is 3, so the area A Ｃ１ｉｎ （１） (1) contains 3 x 3 pieces of data.

[0523] In addition, area A Ｃ１ｉｎ （ｓ） s in (a) is the data P Ｃ１ indicates the ordinal number of the input channel of area A Ｃ１ｉｎ （ｓ） a in (a) is data P Ｃ１ indicates the ordinal number of the selected region from the data p ｐ１ （ｓ） In (a), s indicates the ordinal number of the output channel, and data p ｐ１ （ｓ） (a) a is area A Ｃ１ｉｎ （ｓ） This corresponds to the ordinal number a in (a).

[0524] Also, since the stride is 2, area A Ｃ１ｉｎ （１） The area shifted two columns from (1) is area A. Ｃ１ｉｎ （１） For example, in FIG. 25B, data P Ｃ１ Region A selected from Ｃ１ｉｎ（１） In (2), the maximum pooling process is performed, and the processed data p ｐ１ （１） An example of outputting (2) is shown.

[0525] In addition, data P Ｃ１ The number of data is 55 × 55 × 96, and the stride is 2. Ｃ１ The number of regions to be selected is 729 (=27 ２ )

[0526] As described above, the data P Ｃ１ By sequentially performing pooling processing on the regions selected from the data P Ｃ１ The first input channel of the pooling layer PL1 is described above, but the second to 96th input channels are also pooled in the same way. As a result, the pooling layer PL1 outputs 27 x 27 x 96 output data P Ｐ１ will be output.

[0527] [Convolutional Layer CNV2] In the convolutional layer CNV2, the data P output from the pooling layer PL1 is Ｐ１ Specifically, the kernel used in the convolution process CNV2 and P Ｐ１ A multiplication and accumulation operation is performed on the data included in the selected area.

[0528] As shown in Figure 20, in the convolution layer CNV2, the kernel size is set to 5, the number of kernels is set to 256, and P Ｐ１ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0529] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV2, the convolutional layer CNV2 outputs 27 × 27 × 256 output data, P Ｃ２ will be output.

[0530] For the calculation of the convolutional layer CNV2, the calculation device of one embodiment of the present invention can be used, as in the case of the convolutional layer CNV1. For example, 256 kernels of the convolutional layer CNV2 are written to each column of the cell array CA, and P Ｐ１ By inputting each region selected from the above by the driving circuit XCD, P Ｃ２ can be obtained.

[0531] [Pooling Layer PL2] In the pooling layer PL2, P Ｃ２ The pooling process is performed on the

[0532] As shown in FIG. 20, in the pooling layer PL2, the kernel size is set to 3, and the data P Ｃ２ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0533] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL2, the pooling layer PL2 outputs 13×13×256 output data, P Ｐ２ will be output.

[0534] [Convolutional Layer CNV3] In the convolutional layer CNV3, the data P output by the pooling layer PL2 is Ｐ２ Specifically, the kernel used in the convolution process CNV3 and P Ｐ２ A multiplication and accumulation operation is performed on the data included in the selected area.

[0535] As shown in FIG. 20, in the convolution layer CNV3, the kernel size is set to 3 and the number of kernels is set to 384. Ｐ２ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0536] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV3, the convolutional layer CNV3 outputs 13 × 13 × 384 output data, P Ｃ３ will be output.

[0537] For the operation of the arithmetic unit in the convolutional layer CNV3, the description of the operation of the arithmetic unit CDVA in FIG. 15 in the convolutional layer CNV1 can be referred to.

[0538] [Convolutional Layer CNV4] In the convolutional layer CNV4, the data P output by the convolutional layer CNV3 is Ｃ３ Specifically, the kernel used in the convolution process CNV4 and P Ｃ３ A multiplication and accumulation operation is performed on the data included in the selected area.

[0539] As shown in FIG. 20, in the convolution layer CNV4, the kernel size is set to 3 and the number of kernels is set to 384. Ｃ３ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0540] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV4, the convolutional layer CNV4 outputs 13 × 13 × 384 output data, P Ｃ４ will be output.

[0541] Furthermore, for the operation of the arithmetic unit in the convolutional layer CNV4, the description of the operation of the arithmetic unit CDVA in FIG. 15 in the convolutional layer CNV1 can be referred to.

[0542] [Convolutional Layer CNV5] In the convolutional layer CNV5, the data P output from the convolutional layer CNV4 is Ｃ４ Specifically, the kernel used in the convolution process CNV5 and P Ｃ４ A multiplication and accumulation operation is performed on the data included in the selected area.

[0543] As shown in Figure 20, in the convolution layer CNV5, the kernel size is set to 3, the number of kernels is set to 256, and P Ｃ４ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0544] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV5, the convolutional layer CNV5 outputs 13 × 13 × 256 output data, P Ｃ５ will be output.

[0545] For the operation of the arithmetic unit in the convolutional layer CNV5, the description of the operation of the arithmetic unit CDVA in FIG. 15 in the convolutional layer CNV1 can be referred to.

[0546] [Pooling Layer PL5] In the pooling layer PL5, P Ｃ５ The pooling process is performed on the

[0547] As shown in FIG. 20, in the pooling layer PL5, the kernel size is set to 3, and the data P Ｃ５ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0548] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL5, the pooling layer PL5 outputs 6×6×256 output data, P Ｐ５ will be output.

[0549] [Fully Connected Layer FC6] In the fully connected layer FC6, P Ｐ５ The fully connected layer is calculated for

[0550] As shown in Figure 20, the fully connected layer FC6 has 9126 (= 6 x 6 x 256) input channels and 4096 output channels. In the fully connected layer, a multiply-and-accumulate operation is performed on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and the activation function value is calculated using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC6 is 4096 x 9126.

[0551] The data to be the Nth output channel of the fully connected layer FC6 (where N is an integer between 1 and 4096) is zＦＣ６ (N), then z ＦＣ６ (N) can be expressed by the following formula (2.1).

[0552]

[0553] where f is the activation function in the fully connected layer FC6. The activation function may be, for example, an activation function that can be calculated by the circuit RL described in the first embodiment. Specific examples include a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. ＦＣ６ (N) is as shown in the following formula (2.2).

[0554]

[0555] In addition, p ｐ５ （ｓ） (A) is the A-th data of the s-th output channel output in the pooling layer PL5. ＦＣ６（Ｎ） （ｓ） (A) shows the Nth channel of the fully connected layer FC6 and p ｐ５ （ｓ） (A) and the corresponding weighting coefficient (first data).

[0556] By using the above formulas (2.1) and (2.2), z ＦＣ６ (1) to z ＦＣ６ (4096) can be obtained.

[0557] It is preferable that the calculation of the fully connected layer FC6 be performed by, for example, the calculation device CDVA shown in Fig. 15. In this case, when the calculation of the fully connected layer FC6 is performed by the calculation device CDVA shown in Fig. 15, it is preferable that the number of rows m of the cell array CA is set to 9126, which is the number of input channels, and the number of columns n of the cell array CA is set to 4096, which is the number of output channels. As a result, the first data w ＦＣ６（Ｎ） （ｓ） (A) can be written into each of the calculation cells IM[1,1] to IM[9126,4096].

[0558] The second data in the calculation unit CDVA is p ｐ５ （ｓ） Since (A) is used, for example, the input terminals of the circuits XCDa_1 to XCDa_m are connected to ｐ５ （ｓ） It is preferable to input the values ​​of each component of (A). As a result, each of the calculation cells IM[1,1] to IM[m,n] is p ｐ５ （ｓ） The value of each component of (A) and the corresponding weighting coefficient w ＦＣ６（Ｎ） （ｓ） As a result, the arithmetic circuit outputs u from each of the wirings WCL_1 to WCL_4096. ＦＣ６ (1) to u ＦＣ６ (4096) can be output separately.

[0559] In addition, the driving circuit ITS shown in FIG. ＦＣ６ (1) to u ＦＣ６ The activation function is calculated using each of the input values ​​(4096), and z ＦＣ６ (1) to z ＦＣ６ (4096) is obtained. As a result, z ＦＣ６ (1) to z ＦＣ６ An output signal of (4096) is output.

[0560] As a result of the above, the cell array CA stores the first data (weighting coefficient) and the second data (P Ｐ５ ) is multiplied and added, and u ＦＣ６ (1) to u ＦＣ６ (4096) is obtained. Also, the driving circuit ITS ＦＣ６ (1) to u ＦＣ６ (4096) as input values, and the activation function calculation result z ＦＣ６ (1) to z ＦＣ６ (4096) can be obtained.

[0561] [Fully connected layer FC7] In the fully connected layer FC7, z ＦＣ６ (1) to z ＦＣ６ The fully connected layer is calculated for (4096).

[0562] 20 , the fully connected layer FC7 has 4096 input channels and 4096 output channels. As with the fully connected layer FC6, the fully connected layer FC7 performs a product-sum operation on the data of all input channels and corresponding weighting coefficients (first data) as a single output channel, and calculates the value of an activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC7 is 4096 × 4096.

[0563] For the product-sum operation and activation function operation in the fully connected layer FC7, the description of the fully connected layer FC6 can be referred to.

[0564] In the fully connected layer FC7, the data of the output channel from the fully connected layer FC6, z ＦＣ６ (1) to z ＦＣ６ By inputting (4096), the data of the 1st to 4096th output channels of the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ (4096) is output.

[0565] [Fully Connected Layer FC8] In the fully connected layer FC8, z ＦＣ７ (1) to z ＦＣ７ The fully connected layer is calculated for (4096).

[0566] 20 , the fully connected layer FC8 has 4096 input channels and 1000 output channels. As with the fully connected layer FC6, the fully connected layer FC8 performs a product-sum operation on the data of all input channels and corresponding weighting coefficients (first data) as one output channel, and calculates the value of an activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC8 is 1000×4096.

[0567] For the product-sum operation and activation function operation in the fully connected layer FC8, the description of the fully connected layer FC6 can be referred to.

[0568] In the fully connected layer FC8, the data of the output channel from the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ By inputting (4096), the data of the 1st to 1000th output channels of the fully connected layer FC8, z ＦＣ８ (1) to z ＦＣ８ (1000) is output.

[0569] For the fully connected layer FC8, the above description of the operation of the fully connected layer FC7 can be referred to.

[0570] As described above, the calculation of AlexNet shown in FIG. 20 can be performed by using the calculation device of one embodiment of the present invention.

[0571] In this operation example, the operation of the calculation device described in the first embodiment to perform the AlexNet calculation shown in Fig. 20 is described, but the calculation model performed by the calculation device is not limited to AlexNet. For example, in the input layer INLY, an image P ｉｎ is input to the arithmetic unit, but the image size may be determined arbitrarily. The number of kernels used in convolutional layers CNV1 to CNV5 and the filter values ​​included therein may also be determined arbitrarily. A convolutional neural network other than the AlexNet arithmetic model of FIG. 20 may also be operated by the arithmetic unit.

[0572] In this operation example, the pooling process has been described as maximum pooling, but depending on the situation, average pooling, Lp pooling, etc. may also be used.

[0573] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0574] Embodiment Mode 3 In this embodiment mode, a configuration example of the arithmetic device described in the above embodiment mode will be described.

[0575] Fig. 26 is a perspective view schematically illustrating the arithmetic device CDVS described in embodiment 1. The arithmetic device CDVS shown in Fig. 26 includes, as an example, a circuit layer PHRL and an arithmetic layer OMAL. The circuit layer PHRL is located below the arithmetic layer OMAL.

[0576] FIG. 27 is a block diagram showing an example of the configuration of the circuit layer PHRL and the arithmetic layer OMAL shown in FIG.

[0577] 27, the circuit layer PHRL has, for example, the drive circuits WCD, XCD, ITS, and WSD described in embodiment 1. The operation layer OMAL has, for example, the cell array CA described in embodiment 1.

[0578] Note that one or more selected from the driving circuits WCD, XCD, ITS, and WSD described in the first embodiment may be included in the arithmetic layer OMAL.

[0579] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of usable substrates include an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, lamination films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the computing device CDV includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0580] In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0581] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, XCD, ITS, and WSD can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can therefore pass large on-state currents. This makes it possible to increase the drive speed of each of the drive circuits listed above and widen the signal range.

[0582] The stacked structure of the circuit layer PHRL and the arithmetic layer OMAL can be fabricated by forming the arithmetic layer OMAL directly on top of the circuit layer PHRL, or by mounting the arithmetic layer OMAL on top of the circuit layer PHRL as a structure in which circuit elements such as transistors and capacitive elements are provided on a substrate.

[0583] When the arithmetic layer OMAL is formed directly on the circuit layer PHRL, the arithmetic layer OMAL preferably includes an OS transistor. Since OS transistors can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even on a conductive film, an insulating film, or a semiconductor film, they can be easily provided on a semiconductor substrate (on the circuit layer PHRL) on which Si transistors are formed.

[0584] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the arithmetic layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the arithmetic layer OMAL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the arithmetic layer OMAL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper is bonded to each other is called Cu-Cu (copper-copper) direct bonding.

[0585] <Cross-sectional configuration example 1 of arithmetic device> Next, a specific configuration example of the arithmetic device CDVS shown in Fig. 26 and Fig. 27 will be described. Fig. 28 is a schematic cross-sectional view of one example of the arithmetic device CDVS shown in Fig. 26 and Fig. 27.

[0586] Fig. 28 shows a schematic cross-sectional view of the circuit layer PHRL and the arithmetic layer OMAL. Note that the arithmetic device CDV in Fig. 28 shows a configuration in which the arithmetic layer OMAL is formed directly on the circuit layer PHRL.

[0587] 28 illustrates a transistor 400 included in the circuit layer PHRL. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, insulating layers 315 and 317 functioning as gate insulating films, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions including part of the substrate. The transistor 400 can be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal substrate made of silicon.

[0588] Here, in the transistor 400 shown in FIG. 28 , a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0589] Note that the transistor 400 illustrated in FIG. 28 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0590] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0591] For example, an insulating layer 320, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0592] The insulating layer functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method to improve the planarity.

[0593] 28 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0594] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Contact plugs or wiring are preferably embedded in the insulating layer 354 to connect to an upper circuit (for example, a circuit included in the circuit included in the arithmetic layer OMAL).

[0595] 28 also illustrates some of the operation cells included in the operation layer OMAL. Specifically, Fig. 28 illustrates the transistors M1, M2, M3, M5, capacitance elements C1, and C2 included in the operation cell IM of the operation circuit CC shown in Fig. 1.

[0596] In the arithmetic layer OMAL of the arithmetic device CDVS of Fig. 28, the transistors M3 and M5 are formed on the insulating layer STJ1. The transistors M1 and M2 are formed on the insulating layer STJ2. The capacitive elements C1 and C2 are formed on the insulating layer STJ3. The insulating layer STJ2 is located above the insulating layer STJ1, and the insulating layer STJ3 is located above the insulating layer STJ2. Therefore, the capacitive elements C1 and C2 are located above the transistors M1 and M2, and the transistors M1 and M2 are located above the transistors M3 and M5.

[0597] Note that it is preferable that each of the insulating layers STJ1 to STJ3 function as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layers STJ1 to STJ3 can suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be applied to each of the insulating layers STJ1 to STJ3, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0598] A conductive layer functioning as a wiring WCL is connected to one of the source electrode or drain electrode of transistor M3 via a plug, and a conductive layer functioning as a wiring VEL is connected to the other of the source electrode or drain electrode of transistor M3 via a plug. A conductive layer functioning as a wiring VED is connected to one of the source electrode or drain electrode of transistor M5 via a plug. Although not shown, the other of the source electrode or drain electrode of transistor M5 is connected to one of the source electrode or drain electrode of transistor M6, one of the source electrode or drain electrode of transistor M1, one of the source electrode or drain electrode of transistor M2, and one of a pair of electrodes of capacitor C2. The wiring WCL, wiring VEL, and wiring VED are, for example, extended in the channel width direction of transistor M3 or transistor M5.

[0599] A conductive layer that functions as one of a pair of electrodes of a capacitance element C1 is connected to the gate electrode of the transistor M3 via a plug.

[0600] A conductive layer functioning as one of a pair of electrodes of a capacitor C1 is connected to the other of the source electrode or drain electrode of the transistor M1 via a plug, and a conductive layer functioning as one of a pair of electrodes of a capacitor C2 is connected to one of the source electrode or drain electrode of the transistor M1 via a plug. A conductive layer functioning as one of the pair of electrodes of the capacitor C2 is connected to one of the source electrode or drain electrode of the transistor M2 via a plug, and a conductive layer functioning as a wiring WCL is connected to the other of the source electrode or drain electrode of the transistor M2 via a plug.

[0601] A conductive layer functioning as a wiring WSL is connected to the gate electrodes of the transistors M1 and M2, and the conductive layers serving as the gate electrodes of the transistors M1 and M2 extend in the channel width direction.

[0602] An insulating layer functioning as an interlayer film is formed between the transistors M3 and M5 and between the transistors M1 and M2. The insulating layer has openings in regions overlapping the gate electrode of the transistor M3, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping the source or drain electrodes of the transistors M3 and M5, and conductive layers serving as plugs are embedded in the openings.

[0603] An insulating layer functioning as an interlayer film is formed between the transistors M1 and M2 and the capacitors C1 and C2. The insulating layer has openings in regions overlapping the gate electrodes of the transistors M1 and M2, and conductive layers serving as plugs are embedded in the openings. Similarly, openings are also formed in regions overlapping the source or drain electrodes of the transistors M1 and M2, and conductive layers serving as plugs are embedded in the openings.

[0604] The conductive layer serving as one of the pair of electrodes of the capacitance element C1 is formed so as to be embedded in the insulating layer STJ4 on the insulating layer STJ3. Similarly, the conductive layer serving as one of the pair of electrodes of the capacitance element C2 is also formed so as to be embedded in the insulating layer STJ4.

[0605] A conductive layer that functions as the other of the pair of electrodes of the capacitor C1 is provided above one of the pair of electrodes of the capacitor C1 and a part of the insulating layer STJ4, with an insulating layer that functions as a dielectric interposed therebetween. The conductive layer also functions as the wiring XCL.

[0606] Similarly, a conductive layer that functions as the other of the pair of electrodes of the capacitor C2 is provided above one of the pair of electrodes of the capacitor C2 and another part of the insulating layer STJ4, with an insulating layer that functions as a dielectric interposed therebetween. The conductive layer also functions as the wiring VEG.

[0607] By embedding the conductive layer that functions as one of the pair of electrodes of the capacitor C1 in the insulating layer STJ4, the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the insulating layer STJ4 can be made flush with each other. This allows the insulating layer that functions as a dielectric and the conductive layer that functions as the other of the pair of electrodes of the capacitor C1 to be formed with good flatness on the top surfaces of the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the insulating layer STJ4, which already have good flatness. By improving the flatness of both the pair of electrodes of the capacitor C1 and the insulating layer that functions as a dielectric, localized electric field concentration can be suppressed, thereby preventing leakage current between the pair of electrodes of the capacitor C1. Furthermore, one of the pair of electrodes of the capacitor C1 (here, the lower electrode) has a smaller area than the other of the pair of electrodes of the capacitor C1 (here, the upper electrode). This configuration makes it possible to suppress localized electric field concentration that may occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitance element C1, thereby realizing a highly reliable semiconductor device. The same applies to the capacitance element C2.

[0608] For example, in the computation cell IM of FIG. 1 , by configuring the capacitance element C1 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1 that occurs between the node N and the wiring XCL. Therefore, in the computation cell IM, fluctuations in the potential of the node N due to the leakage current can be prevented, and the potential of the node N can be maintained for a long period of time. Similarly, by configuring the capacitance element C2 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C2 that occurs between the node Nm and the wiring VEG. Therefore, in the computation cell IM, fluctuations in the potential of the node Nm due to the leakage current can be prevented, and the potential of the node Nm can be maintained for a long period of time. Furthermore, local electric field concentration can be suppressed in the dielectrics of the capacitance elements C1 and C2, thereby improving the reliability of the computation cell IM.

[0609] Furthermore, for example, in the driver cell IMD of FIG. 1 , by configuring the capacitor C1d as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor C1d that occurs between the node Nd and the wiring XCL. Therefore, in the driver cell IMD, fluctuations in the potential of the node Nd due to the leakage current can be prevented, and the potential of the node Nd can be maintained for a long period of time. Similarly, by configuring the capacitor C2d as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor C2d that occurs between the node Nmd and the wiring VEG. Therefore, in the driver cell IMD, fluctuations in the potential of the node Nmd due to the leakage current can be prevented, and the potential of the node Nmd can be maintained for a long period of time. Furthermore, local electric field concentration can be suppressed in the dielectrics of the capacitors C1d and C2d, thereby improving the reliability of the driver cell IMD. As a result, it is possible to improve the reliability of the calculation circuit CC.

[0610] In addition, in the configuration example of FIG. 28, the conductive layer functioning as the wiring XCL and the conductive layer functioning as the wiring VEG are each extended in the direction of the channel width of each of the transistors M1, M2, M3, and M5.

[0611] 28, a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each of the transistors M1, M2, M3, and M5. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0612] For example, by providing a back gate to each of transistors M1, M2, M3, and M5, the influence of an external electric field can be reduced and the transistors can be stably maintained in an off state. Therefore, data written to capacitive elements C1 and C2 can be stably held. In this way, providing a back gate stabilizes the operation of the computation cell IM and improves the reliability of the computation layer OMAL including the computation cell IM.

[0613] As the semiconductor layers in which the channels of the transistors M1, M2, M3, and M5 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0614] Note that the transistors M1, M2, M3, and M5 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. Since an oxide semiconductor has a band gap of 2 eV or more, its off-state current is significantly small. Therefore, the power consumption of the processing cell can be reduced. Therefore, the power consumption of the processing device CDVS including the processing cell IM can be reduced.

[0615] 28 can store the first data, and therefore also functions as a memory device. Therefore, the calculation cell or the calculation device CDVS in FIG. 28 can be called an "OS memory."

[0616] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0617] Note that when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid formation of parasitic capacitance with the back gate.

[0618] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor having a gate last (GL) structure that can be used for the transistors M1 to M3 and M5 shown in Fig. 28 will be described. A transistor 500 shown in Fig. 29A and Fig. 29B is an example of a transistor having a GL structure that can be used for the transistors M1 to M3 and M5 shown in Fig. 28.

[0619] In particular, FIG. 29A shows a schematic cross-sectional view of the transistor 500 in the channel length direction, and FIG. 29B shows a schematic cross-sectional view of the transistor 500 in the channel width direction.

[0620] 29A and 29B , for example, the transistor 500 includes a semiconductor layer 531a, a semiconductor layer 531b, a conductive layer 505, a conductive layer 542a, a conductive layer 542b, an insulating layer 580, a conductive layer 560, an insulating layer 514, an insulating layer 516, an insulating layer 520, an insulating layer 522, an insulating layer 524, an insulating layer 550, an insulating layer 554, an insulating layer 574, an insulating layer 580, and an insulating layer 581. Note that the transistor 500 does not necessarily include all of the above components. For example, the conductive layer 505 functions as a backgate electrode of the transistor 500, but the transistor 500 may not include the conductive layer 505.

[0621] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0622] The conductive layer 505 (conductive layer 505a and conductive layer 505b) and the insulating layer 516 are disposed above a substrate (not shown). In particular, the conductive layer 505 is preferably provided so as to be embedded in the insulating layer 516. Specifically, the conductive layer 505a is preferably provided in contact with a bottom surface and a sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is preferably provided so as to be embedded in a recess formed in the conductive layer 505a. Note that in the transistor 500 shown in FIGS. 29A and 29B , the height of the top surface of the conductive layer 505b is approximately the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0623] The insulating layer 516 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 320. Therefore, the insulating layer 516 can be made of a material that functions as a planarizing film, similar to the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced.

[0624] For this reason, the insulating layer 516 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 516 can be made of, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating. Alternatively, the insulating layer 516 can be made of, for example, a resin. The material used for the insulating layer 516 may be an appropriate combination of the above-mentioned insulating materials.

[0625] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0626] The semiconductor layer 531 and the conductive layer 560 are disposed in a region overlapping with the conductive layer 505. The semiconductor layer 531b is disposed on the semiconductor layer 531a. The conductive layers 542a and 542b are disposed on the semiconductor layer 531b and spaced apart from each other. The insulating layer 580 is disposed on the conductive layers 542a and 542b. In particular, an opening is formed in the insulating layer 580 in a region between the conductive layers 542a and 542b. The conductive layer 560 is disposed in the opening. The insulating layer 550 is disposed between the semiconductor layer 531b, the conductive layers 542a and 542b, and the insulating layer 580 and the conductive layer 560. Here, as shown in FIGS. 29A and 29B , it is preferable that the top surface of the conductive layer 560 be substantially flush with the top surfaces of the insulating layers 550 and 580. Note that hereinafter, the conductive layers 505a and 505b may be collectively referred to as conductive layers 505. The semiconductor layers 531a and 531b may be collectively referred to as semiconductor layers 531. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0627] 29A , a region 543a may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542a and in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface between the semiconductor layer 531b and the conductive layer 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. Therefore, the region 543a can be one of a source electrode and a drain electrode, and the region 543b can be the other of the source electrode and the drain electrode. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0628] By providing the conductive layer 542a (conductive layer 542b) in contact with the semiconductor layer 531, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductive layer 542a (conductive layer 542b) and a component of the semiconductor layer 531 may be formed in the region 543a (region 543b). Furthermore, the region 543a (region 543b) may have a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In such cases, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region. That is, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0629] On the other hand, the channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0630] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm−３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0631] Note that when the carrier concentration of the semiconductor layer 531 is reduced, the impurity concentration in the semiconductor layer 531 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic. Note that an oxide semiconductor (or a metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0632] In order to stabilize the electrical characteristics of the transistor 500, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 531. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 531, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 531 refer to, for example, elements other than the main components constituting the semiconductor layer 531. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0633] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 531. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0634] In a transistor using an oxide semiconductor for the semiconductor layer 531, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0635] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 500 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0636] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. ＯIt is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. Furthermore, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0637] 29A and 29B , the side surfaces of the conductive layers 542a and 542b facing the conductive layer 560 have a substantially perpendicular shape. Note that the transistor 500 shown in FIGS. 29A and 29B is not limited thereto, and the angle between the side surface and the bottom surface of the conductive layers 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 542a and 542b may have a plurality of surfaces.

[0638] Note that the transistor 500 has a two-layer structure in which the semiconductor layer 531a and the semiconductor layer 531b are stacked in the region where a channel is formed (hereinafter also referred to as the channe...

Claims

A first cell and a second cell, the first cell includes first to third transistors, a first capacitance element, a second capacitance element, and a first amplifier circuit; the second cell includes fourth to sixth transistors, a third capacitance element, a fourth capacitance element, and a second amplifier circuit; a first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplifier circuit, and a first terminal of the first capacitive element; a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplifier circuit, and a first terminal of the second capacitive element; a first terminal of the fourth transistor is electrically connected to a gate of the sixth transistor, an input terminal of the second amplifier circuit, and a first terminal of the third capacitive element; a second terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor, an output terminal of the second amplifier circuit, and a first terminal of the fourth capacitive element; a second terminal of the second transistor and a first terminal of the third transistor are electrically connected to a first wiring; a second terminal of the fifth transistor, a first terminal of the sixth transistor, a second terminal of the first capacitance element, and a second terminal of the third capacitance element are each electrically connected to a second wiring; a gate of the first transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to a third wiring; each of the first amplifier circuit and the second amplifier circuit functions as a buffer circuit that outputs an analog potential; Semiconductor device. 　 In claim 1, each of the first to sixth transistors includes an oxide semiconductor in a channel formation region; a transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit each have the oxide semiconductor or silicon in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Semiconductor device. 　 In claim 2, each of the first transistor, the second transistor, the fourth transistor, and the fifth transistor is a switching transistor; each of the third transistor and the sixth transistor is an amplification transistor; the channel length of the switching transistor is longer than the channel length of the amplifying transistor; a channel width of the amplifying transistor is greater than a channel width of the switching transistor; Semiconductor device. 　 A first cell and a second cell, the first cell includes first to third transistors, a seventh transistor, a first capacitance element, a second capacitance element, and a first amplifier circuit; the second cell includes fourth to sixth transistors, an eighth transistor, a third capacitive element, a fourth capacitive element, and a second amplifier circuit; a first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplifier circuit, and a first terminal of the first capacitive element; a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplifier circuit, and a first terminal of the second capacitive element; a first terminal of the third transistor electrically connected to a first terminal of the seventh transistor; a first terminal of the fourth transistor is electrically connected to a gate of the sixth transistor, an input terminal of the second amplifier circuit, and a first terminal of the third capacitive element; a second terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor, an output terminal of the second amplifier circuit, and a first terminal of the fourth capacitive element; a first terminal of the sixth transistor is electrically connected to a first terminal of the eighth transistor; a second terminal of the second transistor and a second terminal of the seventh transistor are electrically connected to a first wiring; a second terminal of the sixth transistor, a second terminal of the eighth transistor, a second terminal of the first capacitance element, and a second terminal of the third capacitance element are each electrically connected to a second wiring; a gate of the first transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to a third wiring; each of the first amplifier circuit and the second amplifier circuit functions as a buffer circuit that outputs an analog potential; Semiconductor device. In claim 4, each of the first to eighth transistors includes an oxide semiconductor in a channel formation region; a transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit each have the oxide semiconductor or silicon in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Semiconductor device. 　 In claim 5, each of the first transistor, the second transistor, the fourth transistor, and the fifth transistor is a switching transistor; each of the third transistor and the sixth transistor is an amplification transistor; the channel length of the switching transistor is longer than the channel length of the amplifying transistor; a channel width of the amplifying transistor is greater than a channel width of the switching transistor; Semiconductor device. 　 A first cell and a second cell, the first cell includes first to third transistors, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitance element, and a second capacitance element; the second cell includes fourth to sixth transistors, an eighth transistor, an eleventh transistor, a twelfth transistor, a third capacitance element, and a fourth capacitance element; a first terminal of the first transistor is electrically connected to a gate of the third transistor, a gate of the ninth transistor, and a first terminal of the first capacitive element; a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the ninth transistor, a first terminal of the tenth transistor, and a first terminal of the second capacitive element; a first terminal of the third transistor electrically connected to a first terminal of the seventh transistor; a first terminal of the fourth transistor is electrically connected to a gate of the sixth transistor, a gate of the eleventh transistor, and a first terminal of the third capacitive element; a second terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor, a first terminal of the eleventh transistor, a first terminal of the twelfth transistor, and a first terminal of the fourth capacitive element; a first terminal of the sixth transistor is electrically connected to a first terminal of the eighth transistor; a second terminal of the second transistor and a second terminal of the seventh transistor are electrically connected to a first wiring; a second terminal of the fifth transistor, a second terminal of the eighth transistor, a second terminal of the first capacitance element, and a second terminal of the third capacitance element are each electrically connected to a second wiring; a gate of the first transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to a third wiring; Semiconductor device. 　 In claim 7, each of the first to eighth transistors includes an oxide semiconductor in a channel formation region; each of the ninth to twelfth transistors includes the oxide semiconductor or silicon in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Semiconductor device. 　 In claim 8, each of the first transistor, the second transistor, the fourth transistor, and the fifth transistor is a switching transistor; the third transistor, the sixth transistor, and the ninth to twelfth transistors are each an amplification transistor, the channel length of the switching transistor is longer than the channel length of the amplifying transistor; a channel width of the amplifying transistor is greater than a channel width of the switching transistor; Semiconductor device. 　 A first cell and a second cell, the first cell includes first to third transistors, a ninth transistor, a tenth transistor, a first capacitance element, and a second capacitance element; the second cell includes fourth to sixth transistors, an eleventh transistor, a twelfth transistor, a third capacitance element, and a fourth capacitance element; a first terminal of the first transistor is electrically connected to a gate of the third transistor, a gate of the ninth transistor, and a first terminal of the first capacitive element; a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the ninth transistor, a first terminal of the tenth transistor, and a first terminal of the second capacitive element; a first terminal of the fourth transistor is electrically connected to a gate of the sixth transistor, a gate of the eleventh transistor, and a first terminal of the third capacitive element; a second terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor, a first terminal of the eleventh transistor, a first terminal of the twelfth transistor, and a first terminal of the fourth capacitive element; a second terminal of the second transistor and a first terminal of the third transistor are electrically connected to a first wiring; a second terminal of the fifth transistor, a first terminal of the sixth transistor, a second terminal of the first capacitance element, and a second terminal of the third capacitance element are each electrically connected to a second wiring; a gate of the first transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to a third wiring; Semiconductor device. 　 In claim 10, each of the first to sixth transistors includes an oxide semiconductor in a channel formation region; each of the ninth to twelfth transistors includes the oxide semiconductor or silicon in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Semiconductor device. 　 In claim 11, each of the first transistor, the second transistor, the fourth transistor, and the fifth transistor is a switching transistor; the third transistor, the sixth transistor, and the ninth to twelfth transistors are each an amplification transistor, the channel length of the switching transistor is longer than the channel length of the amplifying transistor; a channel width of the amplifying transistor is greater than a channel width of the switching transistor; Semiconductor device. 　 In any one of claims 1 to 12, a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer above the plurality of transistors included in the first cell and the plurality of transistors included in the second cell; the first insulating layer is located on the first conductive layer; the first insulating layer has an opening reaching the first conductive layer; the second conductive layer is located on an upper surface of the first conductive layer in the opening and in a first region on a side surface of the opening; the second insulating layer is located on the top surface of the second conductive layer, in a second region on the side surface of the opening, and on the top surface of the first insulating layer; the third conductive layer is located on the upper surface of the second insulating layer in the opening; the second conductive layer and the third conductive layer function as a pair of electrodes of one or more selected from the first to fourth capacitance elements, the second insulating layer functions as a dielectric for one or more of the first to fourth capacitance elements; Semiconductor device. 　 a semiconductor device comprising: the semiconductor device of claim 13; and first to fourth drive circuits; the first driving circuit and the fourth driving circuit are each electrically connected to the first wiring; the second drive circuit is electrically connected to the second wiring, the third drive circuit is electrically connected to the third wiring, the first driving circuit has a function of generating a first current according to first data and causing the first current to flow through the first wiring; the second driving circuit has a function of generating a second current according to second data and causing the second current to flow through the second wiring; the third driving circuit has a function of applying a high-level potential or a low-level potential to the third wiring, the fourth driving circuit has a function of acquiring, from the first wiring, a third current generated in the first cell and corresponding to the product of the first data and the second data, performing a function calculation using a value corresponding to the third current as an input value, and outputting a result of the calculation; the first current, the second current, and the third current each have a current amount within a range in which the third transistor and the sixth transistor operate in a subthreshold region; Computing device. 　 An electronic device comprising the arithmetic unit of claim 14 and a housing.

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